Lines Matching +full:x1e80100 +full:- +full:mdss
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
8 #include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
9 #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
10 #include <dt-bindings/clock/qcom,x1e80100-gpucc.h>
11 #include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/interconnect/qcom,icc.h>
14 #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/soc/qcom,gpr.h>
21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
22 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
25 interrupt-parent = <&intc>;
27 #address-cells = <2>;
28 #size-cells = <2>;
33 xo_board: xo-board {
34 compatible = "fixed-clock";
35 clock-frequency = <76800000>;
36 #clock-cells = <0>;
39 sleep_clk: sleep-clk {
40 compatible = "fixed-clock";
41 clock-frequency = <32000>;
42 #clock-cells = <0>;
45 bi_tcxo_div2: bi-tcxo-div2-clk {
46 compatible = "fixed-factor-clock";
47 #clock-cells = <0>;
50 clock-mult = <1>;
51 clock-div = <2>;
54 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
55 compatible = "fixed-factor-clock";
56 #clock-cells = <0>;
59 clock-mult = <1>;
60 clock-div = <2>;
65 #address-cells = <2>;
66 #size-cells = <0>;
72 enable-method = "psci";
73 next-level-cache = <&L2_0>;
74 power-domains = <&CPU_PD0>;
75 power-domain-names = "psci";
76 cpu-idle-states = <&CLUSTER_C4>;
78 L2_0: l2-cache {
80 cache-level = <2>;
81 cache-unified;
89 enable-method = "psci";
90 next-level-cache = <&L2_0>;
91 power-domains = <&CPU_PD1>;
92 power-domain-names = "psci";
93 cpu-idle-states = <&CLUSTER_C4>;
100 enable-method = "psci";
101 next-level-cache = <&L2_0>;
102 power-domains = <&CPU_PD2>;
103 power-domain-names = "psci";
104 cpu-idle-states = <&CLUSTER_C4>;
111 enable-method = "psci";
112 next-level-cache = <&L2_0>;
113 power-domains = <&CPU_PD3>;
114 power-domain-names = "psci";
115 cpu-idle-states = <&CLUSTER_C4>;
122 enable-method = "psci";
123 next-level-cache = <&L2_1>;
124 power-domains = <&CPU_PD4>;
125 power-domain-names = "psci";
126 cpu-idle-states = <&CLUSTER_C4>;
128 L2_1: l2-cache {
130 cache-level = <2>;
131 cache-unified;
139 enable-method = "psci";
140 next-level-cache = <&L2_1>;
141 power-domains = <&CPU_PD5>;
142 power-domain-names = "psci";
143 cpu-idle-states = <&CLUSTER_C4>;
150 enable-method = "psci";
151 next-level-cache = <&L2_1>;
152 power-domains = <&CPU_PD6>;
153 power-domain-names = "psci";
154 cpu-idle-states = <&CLUSTER_C4>;
161 enable-method = "psci";
162 next-level-cache = <&L2_1>;
163 power-domains = <&CPU_PD7>;
164 power-domain-names = "psci";
165 cpu-idle-states = <&CLUSTER_C4>;
172 enable-method = "psci";
173 next-level-cache = <&L2_2>;
174 power-domains = <&CPU_PD8>;
175 power-domain-names = "psci";
176 cpu-idle-states = <&CLUSTER_C4>;
178 L2_2: l2-cache {
180 cache-level = <2>;
181 cache-unified;
189 enable-method = "psci";
190 next-level-cache = <&L2_2>;
191 power-domains = <&CPU_PD9>;
192 power-domain-names = "psci";
193 cpu-idle-states = <&CLUSTER_C4>;
200 enable-method = "psci";
201 next-level-cache = <&L2_2>;
202 power-domains = <&CPU_PD10>;
203 power-domain-names = "psci";
204 cpu-idle-states = <&CLUSTER_C4>;
211 enable-method = "psci";
212 next-level-cache = <&L2_2>;
213 power-domains = <&CPU_PD11>;
214 power-domain-names = "psci";
215 cpu-idle-states = <&CLUSTER_C4>;
218 cpu-map {
274 idle-states {
275 entry-method = "psci";
277 CLUSTER_C4: cpu-sleep-0 {
278 compatible = "arm,idle-state";
279 idle-state-name = "ret";
280 arm,psci-suspend-param = <0x00000004>;
281 entry-latency-us = <180>;
282 exit-latency-us = <320>;
283 min-residency-us = <1000>;
287 domain-idle-states {
288 CLUSTER_CL4: cluster-sleep-0 {
289 compatible = "domain-idle-state";
290 idle-state-name = "l2-ret";
291 arm,psci-suspend-param = <0x01000044>;
292 entry-latency-us = <350>;
293 exit-latency-us = <500>;
294 min-residency-us = <2500>;
297 CLUSTER_CL5: cluster-sleep-1 {
298 compatible = "domain-idle-state";
299 idle-state-name = "ret-pll-off";
300 arm,psci-suspend-param = <0x01000054>;
301 entry-latency-us = <2200>;
302 exit-latency-us = <2500>;
303 min-residency-us = <7000>;
310 compatible = "qcom,scm-x1e80100", "qcom,scm";
316 clk_virt: interconnect-0 {
317 compatible = "qcom,x1e80100-clk-virt";
318 #interconnect-cells = <2>;
319 qcom,bcm-voters = <&apps_bcm_voter>;
322 mc_virt: interconnect-1 {
323 compatible = "qcom,x1e80100-mc-virt";
324 #interconnect-cells = <2>;
325 qcom,bcm-voters = <&apps_bcm_voter>;
335 compatible = "arm,armv8-pmuv3";
340 compatible = "arm,psci-1.0";
343 CPU_PD0: power-domain-cpu0 {
344 #power-domain-cells = <0>;
345 power-domains = <&CLUSTER_PD0>;
348 CPU_PD1: power-domain-cpu1 {
349 #power-domain-cells = <0>;
350 power-domains = <&CLUSTER_PD0>;
353 CPU_PD2: power-domain-cpu2 {
354 #power-domain-cells = <0>;
355 power-domains = <&CLUSTER_PD0>;
358 CPU_PD3: power-domain-cpu3 {
359 #power-domain-cells = <0>;
360 power-domains = <&CLUSTER_PD0>;
363 CPU_PD4: power-domain-cpu4 {
364 #power-domain-cells = <0>;
365 power-domains = <&CLUSTER_PD1>;
368 CPU_PD5: power-domain-cpu5 {
369 #power-domain-cells = <0>;
370 power-domains = <&CLUSTER_PD1>;
373 CPU_PD6: power-domain-cpu6 {
374 #power-domain-cells = <0>;
375 power-domains = <&CLUSTER_PD1>;
378 CPU_PD7: power-domain-cpu7 {
379 #power-domain-cells = <0>;
380 power-domains = <&CLUSTER_PD1>;
383 CPU_PD8: power-domain-cpu8 {
384 #power-domain-cells = <0>;
385 power-domains = <&CLUSTER_PD2>;
388 CPU_PD9: power-domain-cpu9 {
389 #power-domain-cells = <0>;
390 power-domains = <&CLUSTER_PD2>;
393 CPU_PD10: power-domain-cpu10 {
394 #power-domain-cells = <0>;
395 power-domains = <&CLUSTER_PD2>;
398 CPU_PD11: power-domain-cpu11 {
399 #power-domain-cells = <0>;
400 power-domains = <&CLUSTER_PD2>;
403 CLUSTER_PD0: power-domain-cpu-cluster0 {
404 #power-domain-cells = <0>;
405 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
406 power-domains = <&SYSTEM_PD>;
409 CLUSTER_PD1: power-domain-cpu-cluster1 {
410 #power-domain-cells = <0>;
411 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
412 power-domains = <&SYSTEM_PD>;
415 CLUSTER_PD2: power-domain-cpu-cluster2 {
416 #power-domain-cells = <0>;
417 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
418 power-domains = <&SYSTEM_PD>;
421 SYSTEM_PD: power-domain-system {
422 #power-domain-cells = <0>;
423 /* TODO: system-wide idle states */
427 reserved-memory {
428 #address-cells = <2>;
429 #size-cells = <2>;
432 gunyah_hyp_mem: gunyah-hyp@80000000 {
434 no-map;
437 hyp_elf_package_mem: hyp-elf-package@80800000 {
439 no-map;
444 no-map;
447 cpucp_log_mem: cpucp-log@80e00000 {
449 no-map;
454 no-map;
457 reserved-region@81380000 {
459 no-map;
462 tags_mem: tags-region@81400000 {
464 no-map;
467 xbl_dtlog_mem: xbl-dtlog@81a00000 {
469 no-map;
472 xbl_ramdump_mem: xbl-ramdump@81a40000 {
474 no-map;
477 aop_image_mem: aop-image@81c00000 {
479 no-map;
482 aop_cmd_db_mem: aop-cmd-db@81c60000 {
483 compatible = "qcom,cmd-db";
485 no-map;
488 aop_config_mem: aop-config@81c80000 {
490 no-map;
493 tme_crash_dump_mem: tme-crash-dump@81ca0000 {
495 no-map;
498 tme_log_mem: tme-log@81ce0000 {
500 no-map;
503 uefi_log_mem: uefi-log@81ce4000 {
505 no-map;
508 secdata_apss_mem: secdata-apss@81cff000 {
510 no-map;
513 pdp_ns_shared_mem: pdp-ns-shared@81e00000 {
515 no-map;
518 gpu_prr_mem: gpu-prr@81f00000 {
520 no-map;
523 tpm_control_mem: tpm-control@81f10000 {
525 no-map;
528 usb_ucsi_shared_mem: usb-ucsi-shared@81f20000 {
530 no-map;
533 pld_pep_mem: pld-pep@81f30000 {
535 no-map;
538 pld_gmu_mem: pld-gmu@81f36000 {
540 no-map;
543 pld_pdp_mem: pld-pdp@81f37000 {
545 no-map;
548 tz_stat_mem: tz-stat@82700000 {
550 no-map;
553 xbl_tmp_buffer_mem: xbl-tmp-buffer@82800000 {
555 no-map;
558 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@84b00000 {
560 no-map;
563 spu_secure_shared_memory_mem: spu-secure-shared-memory@85300000 {
565 no-map;
568 adsp_boot_dtb_mem: adsp-boot-dtb@866c0000 {
570 no-map;
573 spss_region_mem: spss-region@86700000 {
575 no-map;
578 adsp_boot_mem: adsp-boot@86b00000 {
580 no-map;
585 no-map;
590 no-map;
593 q6_adsp_dtb_mem: q6-adsp-dtb@8b800000 {
595 no-map;
600 no-map;
603 q6_cdsp_dtb_mem: q6-cdsp-dtb@8d900000 {
605 no-map;
608 gpu_microcode_mem: gpu-microcode@8d9fe000 {
610 no-map;
615 no-map;
620 no-map;
623 av1_encoder_mem: av1-encoder@8e900000 {
625 no-map;
628 reserved-region@8f000000 {
630 no-map;
635 no-map;
638 q6_wpss_dtb_mem: q6-wpss-dtb@91300000 {
640 no-map;
643 xbl_sc_mem: xbl-sc@d8000000 {
645 no-map;
648 reserved-region@d8040000 {
650 no-map;
655 no-map;
660 no-map;
665 no-map;
668 llcc_lpi_mem: llcc-lpi@ff800000 {
670 no-map;
677 no-map;
681 smp2p-adsp {
684 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
692 qcom,local-pid = <0>;
693 qcom,remote-pid = <2>;
695 smp2p_adsp_out: master-kernel {
696 qcom,entry-name = "master-kernel";
697 #qcom,smem-state-cells = <1>;
700 smp2p_adsp_in: slave-kernel {
701 qcom,entry-name = "slave-kernel";
702 interrupt-controller;
703 #interrupt-cells = <2>;
707 smp2p-cdsp {
710 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
718 qcom,local-pid = <0>;
719 qcom,remote-pid = <5>;
721 smp2p_cdsp_out: master-kernel {
722 qcom,entry-name = "master-kernel";
723 #qcom,smem-state-cells = <1>;
726 smp2p_cdsp_in: slave-kernel {
727 qcom,entry-name = "slave-kernel";
728 interrupt-controller;
729 #interrupt-cells = <2>;
734 compatible = "simple-bus";
736 #address-cells = <2>;
737 #size-cells = <2>;
738 dma-ranges = <0 0 0 0 0x10 0>;
741 gcc: clock-controller@100000 {
742 compatible = "qcom,x1e80100-gcc";
756 power-domains = <&rpmhpd RPMHPD_CX>;
757 #clock-cells = <1>;
758 #reset-cells = <1>;
759 #power-domain-cells = <1>;
763 compatible = "qcom,x1e80100-ipcc", "qcom,ipcc";
767 interrupt-controller;
768 #interrupt-cells = <3>;
770 #mbox-cells = <2>;
773 gpi_dma2: dma-controller@800000 {
774 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
790 dma-channels = <12>;
791 dma-channel-mask = <0x3e>;
792 #dma-cells = <3>;
800 compatible = "qcom,geni-se-qup";
805 clock-names = "m-ahb",
806 "s-ahb";
810 #address-cells = <2>;
811 #size-cells = <2>;
817 compatible = "qcom,geni-i2c";
823 clock-names = "se";
831 interconnect-names = "qup-core",
832 "qup-config",
833 "qup-memory";
837 dma-names = "tx",
840 pinctrl-0 = <&qup_i2c16_data_clk>;
841 pinctrl-names = "default";
843 #address-cells = <1>;
844 #size-cells = <0>;
850 compatible = "qcom,geni-spi";
856 clock-names = "se";
864 interconnect-names = "qup-core",
865 "qup-config",
866 "qup-memory";
870 dma-names = "tx",
873 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
874 pinctrl-names = "default";
876 #address-cells = <1>;
877 #size-cells = <0>;
883 compatible = "qcom,geni-i2c";
889 clock-names = "se";
897 interconnect-names = "qup-core",
898 "qup-config",
899 "qup-memory";
903 dma-names = "tx",
906 pinctrl-0 = <&qup_i2c17_data_clk>;
907 pinctrl-names = "default";
909 #address-cells = <1>;
910 #size-cells = <0>;
916 compatible = "qcom,geni-spi";
922 clock-names = "se";
930 interconnect-names = "qup-core",
931 "qup-config",
932 "qup-memory";
936 dma-names = "tx",
939 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
940 pinctrl-names = "default";
942 #address-cells = <1>;
943 #size-cells = <0>;
949 compatible = "qcom,geni-i2c";
955 clock-names = "se";
963 interconnect-names = "qup-core",
964 "qup-config",
965 "qup-memory";
969 dma-names = "tx",
972 pinctrl-0 = <&qup_i2c18_data_clk>;
973 pinctrl-names = "default";
975 #address-cells = <1>;
976 #size-cells = <0>;
982 compatible = "qcom,geni-spi";
988 clock-names = "se";
996 interconnect-names = "qup-core",
997 "qup-config",
998 "qup-memory";
1002 dma-names = "tx",
1005 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
1006 pinctrl-names = "default";
1008 #address-cells = <1>;
1009 #size-cells = <0>;
1015 compatible = "qcom,geni-i2c";
1021 clock-names = "se";
1029 interconnect-names = "qup-core",
1030 "qup-config",
1031 "qup-memory";
1035 dma-names = "tx",
1038 pinctrl-0 = <&qup_i2c19_data_clk>;
1039 pinctrl-names = "default";
1041 #address-cells = <1>;
1042 #size-cells = <0>;
1048 compatible = "qcom,geni-spi";
1054 clock-names = "se";
1062 interconnect-names = "qup-core",
1063 "qup-config",
1064 "qup-memory";
1068 dma-names = "tx",
1071 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
1072 pinctrl-names = "default";
1074 #address-cells = <1>;
1075 #size-cells = <0>;
1081 compatible = "qcom,geni-i2c";
1087 clock-names = "se";
1095 interconnect-names = "qup-core",
1096 "qup-config",
1097 "qup-memory";
1101 dma-names = "tx",
1104 pinctrl-0 = <&qup_i2c20_data_clk>;
1105 pinctrl-names = "default";
1107 #address-cells = <1>;
1108 #size-cells = <0>;
1114 compatible = "qcom,geni-spi";
1120 clock-names = "se";
1128 interconnect-names = "qup-core",
1129 "qup-config",
1130 "qup-memory";
1134 dma-names = "tx",
1137 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1138 pinctrl-names = "default";
1140 #address-cells = <1>;
1141 #size-cells = <0>;
1147 compatible = "qcom,geni-i2c";
1153 clock-names = "se";
1161 interconnect-names = "qup-core",
1162 "qup-config",
1163 "qup-memory";
1167 dma-names = "tx",
1170 pinctrl-0 = <&qup_i2c21_data_clk>;
1171 pinctrl-names = "default";
1173 #address-cells = <1>;
1174 #size-cells = <0>;
1180 compatible = "qcom,geni-spi";
1186 clock-names = "se";
1194 interconnect-names = "qup-core",
1195 "qup-config",
1196 "qup-memory";
1200 dma-names = "tx",
1203 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1204 pinctrl-names = "default";
1206 #address-cells = <1>;
1207 #size-cells = <0>;
1213 compatible = "qcom,geni-uart";
1219 clock-names = "se";
1225 interconnect-names = "qup-core",
1226 "qup-config";
1228 pinctrl-0 = <&qup_uart21_default>;
1229 pinctrl-names = "default";
1235 compatible = "qcom,geni-i2c";
1241 clock-names = "se";
1249 interconnect-names = "qup-core",
1250 "qup-config",
1251 "qup-memory";
1255 dma-names = "tx",
1258 pinctrl-0 = <&qup_i2c22_data_clk>;
1259 pinctrl-names = "default";
1261 #address-cells = <1>;
1262 #size-cells = <0>;
1268 compatible = "qcom,geni-spi";
1274 clock-names = "se";
1282 interconnect-names = "qup-core",
1283 "qup-config",
1284 "qup-memory";
1288 dma-names = "tx",
1291 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>;
1292 pinctrl-names = "default";
1294 #address-cells = <1>;
1295 #size-cells = <0>;
1301 compatible = "qcom,geni-i2c";
1307 clock-names = "se";
1315 interconnect-names = "qup-core",
1316 "qup-config",
1317 "qup-memory";
1321 dma-names = "tx",
1324 pinctrl-0 = <&qup_i2c23_data_clk>;
1325 pinctrl-names = "default";
1327 #address-cells = <1>;
1328 #size-cells = <0>;
1334 compatible = "qcom,geni-spi";
1340 clock-names = "se";
1348 interconnect-names = "qup-core",
1349 "qup-config",
1350 "qup-memory";
1354 dma-names = "tx",
1357 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>;
1358 pinctrl-names = "default";
1360 #address-cells = <1>;
1361 #size-cells = <0>;
1367 gpi_dma1: dma-controller@a00000 {
1368 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
1384 dma-channels = <12>;
1385 dma-channel-mask = <0x3e>;
1386 #dma-cells = <3>;
1394 compatible = "qcom,geni-se-qup";
1399 clock-names = "m-ahb",
1400 "s-ahb";
1404 #address-cells = <2>;
1405 #size-cells = <2>;
1411 compatible = "qcom,geni-i2c";
1417 clock-names = "se";
1425 interconnect-names = "qup-core",
1426 "qup-config",
1427 "qup-memory";
1431 dma-names = "tx",
1434 pinctrl-0 = <&qup_i2c8_data_clk>;
1435 pinctrl-names = "default";
1437 #address-cells = <1>;
1438 #size-cells = <0>;
1444 compatible = "qcom,geni-spi";
1450 clock-names = "se";
1458 interconnect-names = "qup-core",
1459 "qup-config",
1460 "qup-memory";
1464 dma-names = "tx",
1467 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1468 pinctrl-names = "default";
1470 #address-cells = <1>;
1471 #size-cells = <0>;
1477 compatible = "qcom,geni-i2c";
1483 clock-names = "se";
1491 interconnect-names = "qup-core",
1492 "qup-config",
1493 "qup-memory";
1497 dma-names = "tx",
1500 pinctrl-0 = <&qup_i2c9_data_clk>;
1501 pinctrl-names = "default";
1503 #address-cells = <1>;
1504 #size-cells = <0>;
1510 compatible = "qcom,geni-spi";
1516 clock-names = "se";
1524 interconnect-names = "qup-core",
1525 "qup-config",
1526 "qup-memory";
1530 dma-names = "tx",
1533 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1534 pinctrl-names = "default";
1536 #address-cells = <1>;
1537 #size-cells = <0>;
1543 compatible = "qcom,geni-i2c";
1549 clock-names = "se";
1557 interconnect-names = "qup-core",
1558 "qup-config",
1559 "qup-memory";
1563 dma-names = "tx",
1566 pinctrl-0 = <&qup_i2c10_data_clk>;
1567 pinctrl-names = "default";
1569 #address-cells = <1>;
1570 #size-cells = <0>;
1576 compatible = "qcom,geni-spi";
1582 clock-names = "se";
1590 interconnect-names = "qup-core",
1591 "qup-config",
1592 "qup-memory";
1596 dma-names = "tx",
1599 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1600 pinctrl-names = "default";
1602 #address-cells = <1>;
1603 #size-cells = <0>;
1609 compatible = "qcom,geni-i2c";
1615 clock-names = "se";
1623 interconnect-names = "qup-core",
1624 "qup-config",
1625 "qup-memory";
1629 dma-names = "tx",
1632 pinctrl-0 = <&qup_i2c11_data_clk>;
1633 pinctrl-names = "default";
1635 #address-cells = <1>;
1636 #size-cells = <0>;
1642 compatible = "qcom,geni-spi";
1648 clock-names = "se";
1656 interconnect-names = "qup-core",
1657 "qup-config",
1658 "qup-memory";
1662 dma-names = "tx",
1665 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1666 pinctrl-names = "default";
1668 #address-cells = <1>;
1669 #size-cells = <0>;
1675 compatible = "qcom,geni-i2c";
1681 clock-names = "se";
1689 interconnect-names = "qup-core",
1690 "qup-config",
1691 "qup-memory";
1695 dma-names = "tx",
1698 pinctrl-0 = <&qup_i2c12_data_clk>;
1699 pinctrl-names = "default";
1701 #address-cells = <1>;
1702 #size-cells = <0>;
1708 compatible = "qcom,geni-spi";
1714 clock-names = "se";
1722 interconnect-names = "qup-core",
1723 "qup-config",
1724 "qup-memory";
1728 dma-names = "tx",
1731 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1732 pinctrl-names = "default";
1734 #address-cells = <1>;
1735 #size-cells = <0>;
1741 compatible = "qcom,geni-i2c";
1747 clock-names = "se";
1755 interconnect-names = "qup-core",
1756 "qup-config",
1757 "qup-memory";
1761 dma-names = "tx",
1764 pinctrl-0 = <&qup_i2c13_data_clk>;
1765 pinctrl-names = "default";
1767 #address-cells = <1>;
1768 #size-cells = <0>;
1774 compatible = "qcom,geni-spi";
1780 clock-names = "se";
1788 interconnect-names = "qup-core",
1789 "qup-config",
1790 "qup-memory";
1794 dma-names = "tx",
1797 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1798 pinctrl-names = "default";
1800 #address-cells = <1>;
1801 #size-cells = <0>;
1807 compatible = "qcom,geni-i2c";
1813 clock-names = "se";
1821 interconnect-names = "qup-core",
1822 "qup-config",
1823 "qup-memory";
1827 dma-names = "tx",
1830 pinctrl-0 = <&qup_i2c14_data_clk>;
1831 pinctrl-names = "default";
1833 #address-cells = <1>;
1834 #size-cells = <0>;
1840 compatible = "qcom,geni-spi";
1846 clock-names = "se";
1854 interconnect-names = "qup-core",
1855 "qup-config",
1856 "qup-memory";
1860 dma-names = "tx",
1863 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1864 pinctrl-names = "default";
1866 #address-cells = <1>;
1867 #size-cells = <0>;
1873 compatible = "qcom,geni-i2c";
1879 clock-names = "se";
1887 interconnect-names = "qup-core",
1888 "qup-config",
1889 "qup-memory";
1893 dma-names = "tx",
1896 pinctrl-0 = <&qup_i2c15_data_clk>;
1897 pinctrl-names = "default";
1899 #address-cells = <1>;
1900 #size-cells = <0>;
1906 compatible = "qcom,geni-spi";
1912 clock-names = "se";
1920 interconnect-names = "qup-core",
1921 "qup-config",
1922 "qup-memory";
1926 dma-names = "tx",
1929 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1930 pinctrl-names = "default";
1932 #address-cells = <1>;
1933 #size-cells = <0>;
1939 gpi_dma0: dma-controller@b00000 {
1940 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
1956 dma-channels = <12>;
1957 dma-channel-mask = <0x3e>;
1958 #dma-cells = <3>;
1966 compatible = "qcom,geni-se-qup";
1971 clock-names = "m-ahb",
1972 "s-ahb";
1975 #address-cells = <2>;
1976 #size-cells = <2>;
1982 compatible = "qcom,geni-i2c";
1988 clock-names = "se";
1996 interconnect-names = "qup-core",
1997 "qup-config",
1998 "qup-memory";
2002 dma-names = "tx",
2005 pinctrl-0 = <&qup_i2c0_data_clk>;
2006 pinctrl-names = "default";
2008 #address-cells = <1>;
2009 #size-cells = <0>;
2015 compatible = "qcom,geni-spi";
2021 clock-names = "se";
2029 interconnect-names = "qup-core",
2030 "qup-config",
2031 "qup-memory";
2035 dma-names = "tx",
2038 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
2039 pinctrl-names = "default";
2041 #address-cells = <1>;
2042 #size-cells = <0>;
2048 compatible = "qcom,geni-i2c";
2054 clock-names = "se";
2062 interconnect-names = "qup-core",
2063 "qup-config",
2064 "qup-memory";
2068 dma-names = "tx",
2071 pinctrl-0 = <&qup_i2c1_data_clk>;
2072 pinctrl-names = "default";
2074 #address-cells = <1>;
2075 #size-cells = <0>;
2081 compatible = "qcom,geni-spi";
2087 clock-names = "se";
2095 interconnect-names = "qup-core",
2096 "qup-config",
2097 "qup-memory";
2101 dma-names = "tx",
2104 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
2105 pinctrl-names = "default";
2107 #address-cells = <1>;
2108 #size-cells = <0>;
2114 compatible = "qcom,geni-i2c";
2120 clock-names = "se";
2128 interconnect-names = "qup-core",
2129 "qup-config",
2130 "qup-memory";
2134 dma-names = "tx",
2137 pinctrl-0 = <&qup_i2c2_data_clk>;
2138 pinctrl-names = "default";
2140 #address-cells = <1>;
2141 #size-cells = <0>;
2147 compatible = "qcom,geni-uart";
2153 clock-names = "se";
2159 interconnect-names = "qup-core",
2160 "qup-config";
2162 pinctrl-0 = <&qup_uart2_default>;
2163 pinctrl-names = "default";
2169 compatible = "qcom,geni-spi";
2175 clock-names = "se";
2183 interconnect-names = "qup-core",
2184 "qup-config",
2185 "qup-memory";
2189 dma-names = "tx",
2192 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
2193 pinctrl-names = "default";
2195 #address-cells = <1>;
2196 #size-cells = <0>;
2202 compatible = "qcom,geni-i2c";
2208 clock-names = "se";
2216 interconnect-names = "qup-core",
2217 "qup-config",
2218 "qup-memory";
2222 dma-names = "tx",
2225 pinctrl-0 = <&qup_i2c3_data_clk>;
2226 pinctrl-names = "default";
2228 #address-cells = <1>;
2229 #size-cells = <0>;
2235 compatible = "qcom,geni-spi";
2241 clock-names = "se";
2249 interconnect-names = "qup-core",
2250 "qup-config",
2251 "qup-memory";
2255 dma-names = "tx",
2258 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
2259 pinctrl-names = "default";
2261 #address-cells = <1>;
2262 #size-cells = <0>;
2268 compatible = "qcom,geni-i2c";
2274 clock-names = "se";
2282 interconnect-names = "qup-core",
2283 "qup-config",
2284 "qup-memory";
2288 dma-names = "tx",
2291 pinctrl-0 = <&qup_i2c4_data_clk>;
2292 pinctrl-names = "default";
2294 #address-cells = <1>;
2295 #size-cells = <0>;
2301 compatible = "qcom,geni-spi";
2307 clock-names = "se";
2315 interconnect-names = "qup-core",
2316 "qup-config",
2317 "qup-memory";
2321 dma-names = "tx",
2324 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
2325 pinctrl-names = "default";
2327 #address-cells = <1>;
2328 #size-cells = <0>;
2334 compatible = "qcom,geni-i2c";
2340 clock-names = "se";
2348 interconnect-names = "qup-core",
2349 "qup-config",
2350 "qup-memory";
2354 dma-names = "tx",
2357 pinctrl-0 = <&qup_i2c5_data_clk>;
2358 pinctrl-names = "default";
2360 #address-cells = <1>;
2361 #size-cells = <0>;
2367 compatible = "qcom,geni-spi";
2373 clock-names = "se";
2381 interconnect-names = "qup-core",
2382 "qup-config",
2383 "qup-memory";
2387 dma-names = "tx",
2390 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
2391 pinctrl-names = "default";
2393 #address-cells = <1>;
2394 #size-cells = <0>;
2400 compatible = "qcom,geni-i2c";
2406 clock-names = "se";
2414 interconnect-names = "qup-core",
2415 "qup-config",
2416 "qup-memory";
2420 dma-names = "tx",
2423 pinctrl-0 = <&qup_i2c6_data_clk>;
2424 pinctrl-names = "default";
2426 #address-cells = <1>;
2427 #size-cells = <0>;
2433 compatible = "qcom,geni-spi";
2439 clock-names = "se";
2447 interconnect-names = "qup-core",
2448 "qup-config",
2449 "qup-memory";
2453 dma-names = "tx",
2456 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
2457 pinctrl-names = "default";
2459 #address-cells = <1>;
2460 #size-cells = <0>;
2466 compatible = "qcom,geni-i2c";
2472 clock-names = "se";
2480 interconnect-names = "qup-core",
2481 "qup-config",
2482 "qup-memory";
2486 dma-names = "tx",
2489 pinctrl-0 = <&qup_i2c7_data_clk>;
2490 pinctrl-names = "default";
2492 #address-cells = <1>;
2493 #size-cells = <0>;
2499 compatible = "qcom,geni-spi";
2505 clock-names = "se";
2513 interconnect-names = "qup-core",
2514 "qup-config",
2515 "qup-memory";
2519 dma-names = "tx",
2522 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
2523 pinctrl-names = "default";
2525 #address-cells = <1>;
2526 #size-cells = <0>;
2532 tsens0: thermal-sensor@c271000 {
2533 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2537 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
2539 interrupt-names = "uplow",
2544 #thermal-sensor-cells = <1>;
2547 tsens1: thermal-sensor@c272000 {
2548 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2552 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
2554 interrupt-names = "uplow",
2559 #thermal-sensor-cells = <1>;
2562 tsens2: thermal-sensor@c273000 {
2563 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2567 interrupts-extended = <&pdc 28 IRQ_TYPE_LEVEL_HIGH>,
2569 interrupt-names = "uplow",
2574 #thermal-sensor-cells = <1>;
2577 tsens3: thermal-sensor@c274000 {
2578 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2582 interrupts-extended = <&pdc 29 IRQ_TYPE_LEVEL_HIGH>,
2584 interrupt-names = "uplow",
2589 #thermal-sensor-cells = <1>;
2593 compatible = "qcom,x1e80100-snps-eusb2-phy",
2594 "qcom,sm8550-snps-eusb2-phy";
2596 #phy-cells = <0>;
2599 clock-names = "ref";
2607 compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
2614 clock-names = "aux",
2619 power-domains = <&gcc GCC_USB_0_PHY_GDSC>;
2623 reset-names = "phy",
2626 #clock-cells = <1>;
2627 #phy-cells = <1>;
2629 orientation-switch;
2634 #address-cells = <1>;
2635 #size-cells = <0>;
2648 remote-endpoint = <&usb_1_ss0_dwc3_ss>;
2656 remote-endpoint = <&mdss_dp0_out>;
2663 compatible = "qcom,x1e80100-snps-eusb2-phy",
2664 "qcom,sm8550-snps-eusb2-phy";
2666 #phy-cells = <0>;
2669 clock-names = "ref";
2677 compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
2684 clock-names = "aux",
2689 power-domains = <&gcc GCC_USB_1_PHY_GDSC>;
2693 reset-names = "phy",
2696 #clock-cells = <1>;
2697 #phy-cells = <1>;
2699 orientation-switch;
2704 #address-cells = <1>;
2705 #size-cells = <0>;
2718 remote-endpoint = <&usb_1_ss1_dwc3_ss>;
2726 remote-endpoint = <&mdss_dp1_out>;
2733 compatible = "qcom,x1e80100-snps-eusb2-phy",
2734 "qcom,sm8550-snps-eusb2-phy";
2736 #phy-cells = <0>;
2739 clock-names = "ref";
2747 compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
2754 clock-names = "aux",
2759 power-domains = <&gcc GCC_USB_2_PHY_GDSC>;
2763 reset-names = "phy",
2766 #clock-cells = <1>;
2767 #phy-cells = <1>;
2769 orientation-switch;
2774 #address-cells = <1>;
2775 #size-cells = <0>;
2788 remote-endpoint = <&usb_1_ss2_dwc3_ss>;
2796 remote-endpoint = <&mdss_dp2_out>;
2803 compatible = "qcom,x1e80100-cnoc-main";
2806 qcom,bcm-voters = <&apps_bcm_voter>;
2808 #interconnect-cells = <2>;
2812 compatible = "qcom,x1e80100-cnoc-cfg";
2815 qcom,bcm-voters = <&apps_bcm_voter>;
2817 #interconnect-cells = <2>;
2821 compatible = "qcom,x1e80100-system-noc";
2824 qcom,bcm-voters = <&apps_bcm_voter>;
2826 #interconnect-cells = <2>;
2830 compatible = "qcom,x1e80100-pcie-south-anoc";
2833 qcom,bcm-voters = <&apps_bcm_voter>;
2835 #interconnect-cells = <2>;
2839 compatible = "qcom,x1e80100-pcie-center-anoc";
2842 qcom,bcm-voters = <&apps_bcm_voter>;
2844 #interconnect-cells = <2>;
2848 compatible = "qcom,x1e80100-aggre1-noc";
2851 qcom,bcm-voters = <&apps_bcm_voter>;
2853 #interconnect-cells = <2>;
2857 compatible = "qcom,x1e80100-aggre2-noc";
2860 qcom,bcm-voters = <&apps_bcm_voter>;
2862 #interconnect-cells = <2>;
2866 compatible = "qcom,x1e80100-pcie-north-anoc";
2869 qcom,bcm-voters = <&apps_bcm_voter>;
2871 #interconnect-cells = <2>;
2875 compatible = "qcom,x1e80100-usb-center-anoc";
2878 qcom,bcm-voters = <&apps_bcm_voter>;
2880 #interconnect-cells = <2>;
2884 compatible = "qcom,x1e80100-usb-north-anoc";
2887 qcom,bcm-voters = <&apps_bcm_voter>;
2889 #interconnect-cells = <2>;
2893 compatible = "qcom,x1e80100-usb-south-anoc";
2896 qcom,bcm-voters = <&apps_bcm_voter>;
2898 #interconnect-cells = <2>;
2902 compatible = "qcom,x1e80100-mmss-noc";
2905 qcom,bcm-voters = <&apps_bcm_voter>;
2907 #interconnect-cells = <2>;
2912 compatible = "qcom,pcie-x1e80100";
2919 reg-names = "parf",
2925 #address-cells = <3>;
2926 #size-cells = <2>;
2929 bus-range = <0x00 0xff>;
2931 dma-coherent;
2933 linux,pci-domain = <6>;
2934 num-lanes = <4>;
2944 interrupt-names = "msi0",
2953 #interrupt-cells = <1>;
2954 interrupt-map-mask = <0 0 0 0x7>;
2955 interrupt-map = <0 0 0 1 &intc 0 0 0 843 IRQ_TYPE_LEVEL_HIGH>,
2967 clock-names = "aux",
2975 assigned-clocks = <&gcc GCC_PCIE_6A_AUX_CLK>;
2976 assigned-clock-rates = <19200000>;
2982 interconnect-names = "pcie-mem",
2983 "cpu-pcie";
2987 reset-names = "pci",
2990 power-domains = <&gcc GCC_PCIE_6A_GDSC>;
2991 required-opps = <&rpmhpd_opp_nom>;
2994 phy-names = "pciephy";
3000 compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy";
3010 clock-names = "aux",
3019 reset-names = "phy",
3022 assigned-clocks = <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>;
3023 assigned-clock-rates = <100000000>;
3025 power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>;
3027 qcom,4ln-config-sel = <&tcsr 0x1a000 0>;
3029 #clock-cells = <0>;
3030 clock-output-names = "pcie6a_pipe_clk";
3032 #phy-cells = <0>;
3039 compatible = "qcom,pcie-x1e80100";
3046 reg-names = "parf",
3052 #address-cells = <3>;
3053 #size-cells = <2>;
3056 bus-range = <0x00 0xff>;
3058 dma-coherent;
3060 linux,pci-domain = <5>;
3061 num-lanes = <2>;
3071 interrupt-names = "msi0",
3080 #interrupt-cells = <1>;
3081 interrupt-map-mask = <0 0 0 0x7>;
3082 interrupt-map = <0 0 0 1 &intc 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>,
3094 clock-names = "aux",
3102 assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>;
3103 assigned-clock-rates = <19200000>;
3109 interconnect-names = "pcie-mem",
3110 "cpu-pcie";
3114 reset-names = "pci",
3117 power-domains = <&gcc GCC_PCIE_5_GDSC>;
3118 required-opps = <&rpmhpd_opp_nom>;
3121 phy-names = "pciephy";
3127 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy";
3136 clock-names = "aux",
3144 reset-names = "phy";
3146 assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>;
3147 assigned-clock-rates = <100000000>;
3149 power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>;
3151 #clock-cells = <0>;
3152 clock-output-names = "pcie5_pipe_clk";
3154 #phy-cells = <0>;
3161 compatible = "qcom,pcie-x1e80100";
3168 reg-names = "parf",
3174 #address-cells = <3>;
3175 #size-cells = <2>;
3178 bus-range = <0x00 0xff>;
3180 dma-coherent;
3182 linux,pci-domain = <4>;
3183 num-lanes = <2>;
3193 interrupt-names = "msi0",
3202 #interrupt-cells = <1>;
3203 interrupt-map-mask = <0 0 0 0x7>;
3204 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
3216 clock-names = "aux",
3224 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
3225 assigned-clock-rates = <19200000>;
3231 interconnect-names = "pcie-mem",
3232 "cpu-pcie";
3236 reset-names = "pci",
3239 power-domains = <&gcc GCC_PCIE_4_GDSC>;
3240 required-opps = <&rpmhpd_opp_nom>;
3243 phy-names = "pciephy";
3250 bus-range = <0x01 0xff>;
3252 #address-cells = <3>;
3253 #size-cells = <2>;
3259 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy";
3268 clock-names = "aux",
3276 reset-names = "phy";
3278 assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>;
3279 assigned-clock-rates = <100000000>;
3281 power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>;
3283 #clock-cells = <0>;
3284 clock-output-names = "pcie4_pipe_clk";
3286 #phy-cells = <0>;
3292 compatible = "qcom,tcsr-mutex";
3294 #hwlock-cells = <1>;
3297 tcsr: clock-controller@1fc0000 {
3298 compatible = "qcom,x1e80100-tcsr", "syscon";
3301 #clock-cells = <1>;
3302 #reset-cells = <1>;
3306 compatible = "qcom,adreno-43050c01", "qcom,adreno";
3311 reg-names = "kgsl_3d0_reg_memory",
3320 operating-points-v2 = <&gpu_opp_table>;
3323 #cooling-cells = <2>;
3326 interconnect-names = "gfx-mem";
3330 zap-shader {
3331 memory-region = <&gpu_microcode_mem>;
3334 gpu_opp_table: opp-table {
3335 compatible = "operating-points-v2";
3337 opp-1100000000 {
3338 opp-hz = /bits/ 64 <1100000000>;
3339 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3340 opp-peak-kBps = <16500000>;
3343 opp-1000000000 {
3344 opp-hz = /bits/ 64 <1000000000>;
3345 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3346 opp-peak-kBps = <14398438>;
3349 opp-925000000 {
3350 opp-hz = /bits/ 64 <925000000>;
3351 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3352 opp-peak-kBps = <14398438>;
3355 opp-800000000 {
3356 opp-hz = /bits/ 64 <800000000>;
3357 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3358 opp-peak-kBps = <12449219>;
3361 opp-744000000 {
3362 opp-hz = /bits/ 64 <744000000>;
3363 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
3364 opp-peak-kBps = <10687500>;
3367 opp-687000000 {
3368 opp-hz = /bits/ 64 <687000000>;
3369 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3370 opp-peak-kBps = <8171875>;
3373 opp-550000000 {
3374 opp-hz = /bits/ 64 <550000000>;
3375 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3376 opp-peak-kBps = <6074219>;
3379 opp-390000000 {
3380 opp-hz = /bits/ 64 <390000000>;
3381 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3382 opp-peak-kBps = <3000000>;
3385 opp-300000000 {
3386 opp-hz = /bits/ 64 <300000000>;
3387 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
3388 opp-peak-kBps = <2136719>;
3394 compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu";
3398 reg-names = "gmu", "rscc", "gmu_pdc";
3402 interrupt-names = "hfi", "gmu";
3411 clock-names = "ahb",
3419 power-domains = <&gpucc GPU_CX_GDSC>,
3421 power-domain-names = "cx",
3428 operating-points-v2 = <&gmu_opp_table>;
3430 gmu_opp_table: opp-table {
3431 compatible = "operating-points-v2";
3433 opp-550000000 {
3434 opp-hz = /bits/ 64 <550000000>;
3435 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3438 opp-220000000 {
3439 opp-hz = /bits/ 64 <220000000>;
3440 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3445 gpucc: clock-controller@3d90000 {
3446 compatible = "qcom,x1e80100-gpucc";
3451 #clock-cells = <1>;
3452 #reset-cells = <1>;
3453 #power-domain-cells = <1>;
3457 compatible = "qcom,x1e80100-smmu-500", "qcom,adreno-smmu",
3458 "qcom,smmu-500", "arm,mmu-500";
3460 #iommu-cells = <2>;
3461 #global-interrupts = <1>;
3492 clock-names = "hlos",
3496 power-domains = <&gpucc GPU_CX_GDSC>;
3497 dma-coherent;
3501 compatible = "qcom,x1e80100-gem-noc";
3504 qcom,bcm-voters = <&apps_bcm_voter>;
3506 #interconnect-cells = <2>;
3510 compatible = "qcom,x1e80100-nsp-noc";
3513 qcom,bcm-voters = <&apps_bcm_voter>;
3515 #interconnect-cells = <2>;
3519 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
3525 clock-names = "mclk",
3530 #clock-cells = <0>;
3531 clock-output-names = "wsa2-mclk";
3532 #sound-dai-cells = <1>;
3533 sound-name-prefix = "WSA2";
3537 compatible = "qcom,soundwire-v2.0.0";
3540 clock-names = "iface";
3544 pinctrl-0 = <&wsa2_swr_active>;
3545 pinctrl-names = "default";
3547 reset-names = "swr_audio_cgcr";
3549 qcom,din-ports = <4>;
3550 qcom,dout-ports = <9>;
3552 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x3…
3553 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
3554 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3555 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3556 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3557 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
3558 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
3559 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
3560 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
3562 #address-cells = <2>;
3563 #size-cells = <0>;
3564 #sound-dai-cells = <1>;
3569 compatible = "qcom,x1e80100-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro";
3575 clock-names = "mclk",
3580 #clock-cells = <0>;
3581 clock-output-names = "mclk";
3582 #sound-dai-cells = <1>;
3586 compatible = "qcom,soundwire-v2.0.0";
3589 clock-names = "iface";
3593 pinctrl-0 = <&rx_swr_active>;
3594 pinctrl-names = "default";
3597 reset-names = "swr_audio_cgcr";
3598 qcom,din-ports = <1>;
3599 qcom,dout-ports = <11>;
3601 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3602 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3603 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3604 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3605 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3606 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3607 …qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff…
3608 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
3609 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3611 #address-cells = <2>;
3612 #size-cells = <0>;
3613 #sound-dai-cells = <1>;
3618 compatible = "qcom,x1e80100-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro";
3624 clock-names = "mclk",
3629 #clock-cells = <0>;
3630 clock-output-names = "mclk";
3631 #sound-dai-cells = <1>;
3635 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
3641 clock-names = "mclk",
3646 #clock-cells = <0>;
3647 clock-output-names = "mclk";
3648 #sound-dai-cells = <1>;
3649 sound-name-prefix = "WSA";
3653 compatible = "qcom,soundwire-v2.0.0";
3656 clock-names = "iface";
3660 pinctrl-0 = <&wsa_swr_active>;
3661 pinctrl-names = "default";
3663 reset-names = "swr_audio_cgcr";
3665 qcom,din-ports = <4>;
3666 qcom,dout-ports = <9>;
3668 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x3…
3669 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
3670 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3671 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3672 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3673 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
3674 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
3675 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
3676 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
3678 #address-cells = <2>;
3679 #size-cells = <0>;
3680 #sound-dai-cells = <1>;
3684 lpass_audiocc: clock-controller@6b6c000 {
3685 compatible = "qcom,x1e80100-lpassaudiocc", "qcom,sc8280xp-lpassaudiocc";
3687 #clock-cells = <1>;
3688 #reset-cells = <1>;
3692 compatible = "qcom,soundwire-v2.0.0";
3695 clock-names = "iface";
3698 interrupt-names = "core", "wakeup";
3701 reset-names = "swr_audio_cgcr";
3703 pinctrl-0 = <&tx_swr_active>;
3704 pinctrl-names = "default";
3706 qcom,din-ports = <4>;
3707 qcom,dout-ports = <1>;
3709 qcom,ports-sinterval-low = /bits/ 8 <0x00 0x01 0x03 0x03 0x00>;
3710 qcom,ports-offset1 = /bits/ 8 <0x00 0x01 0x02 0x00 0x00>;
3711 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00 0xff>;
3712 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3713 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3714 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3715 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3716 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3717 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x00 0x01 0xff>;
3719 #address-cells = <2>;
3720 #size-cells = <0>;
3721 #sound-dai-cells = <1>;
3726 compatible = "qcom,x1e80100-lpass-va-macro", "qcom,sm8550-lpass-va-macro";
3731 clock-names = "mclk",
3735 #clock-cells = <0>;
3736 clock-output-names = "fsgen";
3737 #sound-dai-cells = <1>;
3741 compatible = "qcom,x1e80100-lpass-lpi-pinctrl", "qcom,sm8550-lpass-lpi-pinctrl";
3747 clock-names = "core", "audio";
3749 gpio-controller;
3750 #gpio-cells = <2>;
3751 gpio-ranges = <&lpass_tlmm 0 0 23>;
3753 tx_swr_active: tx-swr-active-state {
3754 clk-pins {
3757 drive-strength = <2>;
3758 slew-rate = <1>;
3759 bias-disable;
3762 data-pins {
3765 drive-strength = <2>;
3766 slew-rate = <1>;
3767 bias-bus-hold;
3771 rx_swr_active: rx-swr-active-state {
3772 clk-pins {
3775 drive-strength = <2>;
3776 slew-rate = <1>;
3777 bias-disable;
3780 data-pins {
3783 drive-strength = <2>;
3784 slew-rate = <1>;
3785 bias-bus-hold;
3789 dmic01_default: dmic01-default-state {
3790 clk-pins {
3793 drive-strength = <8>;
3794 output-high;
3797 data-pins {
3800 drive-strength = <8>;
3801 input-enable;
3805 dmic23_default: dmic23-default-state {
3806 clk-pins {
3809 drive-strength = <8>;
3810 output-high;
3813 data-pins {
3816 drive-strength = <8>;
3817 input-enable;
3821 wsa_swr_active: wsa-swr-active-state {
3822 clk-pins {
3825 drive-strength = <2>;
3826 slew-rate = <1>;
3827 bias-disable;
3830 data-pins {
3833 drive-strength = <2>;
3834 slew-rate = <1>;
3835 bias-bus-hold;
3839 wsa2_swr_active: wsa2-swr-active-state {
3840 clk-pins {
3843 drive-strength = <2>;
3844 slew-rate = <1>;
3845 bias-disable;
3848 data-pins {
3851 drive-strength = <2>;
3852 slew-rate = <1>;
3853 bias-bus-hold;
3858 lpasscc: clock-controller@6ea0000 {
3859 compatible = "qcom,x1e80100-lpasscc", "qcom,sc8280xp-lpasscc";
3861 #clock-cells = <1>;
3862 #reset-cells = <1>;
3866 compatible = "qcom,x1e80100-lpass-ag-noc";
3869 qcom,bcm-voters = <&apps_bcm_voter>;
3871 #interconnect-cells = <2>;
3875 compatible = "qcom,x1e80100-lpass-lpiaon-noc";
3878 qcom,bcm-voters = <&apps_bcm_voter>;
3880 #interconnect-cells = <2>;
3884 compatible = "qcom,x1e80100-lpass-lpicx-noc";
3887 qcom,bcm-voters = <&apps_bcm_voter>;
3889 #interconnect-cells = <2>;
3893 compatible = "qcom,x1e80100-snps-eusb2-phy",
3894 "qcom,sm8550-snps-eusb2-phy";
3896 #phy-cells = <0>;
3899 clock-names = "ref";
3907 compatible = "qcom,x1e80100-snps-eusb2-phy",
3908 "qcom,sm8550-snps-eusb2-phy";
3910 #phy-cells = <0>;
3913 clock-names = "ref";
3921 compatible = "qcom,x1e80100-snps-eusb2-phy",
3922 "qcom,sm8550-snps-eusb2-phy";
3924 #phy-cells = <0>;
3927 clock-names = "ref";
3935 compatible = "qcom,x1e80100-qmp-usb3-uni-phy";
3942 clock-names = "aux",
3949 reset-names = "phy",
3952 power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>;
3954 #clock-cells = <0>;
3955 clock-output-names = "usb_mp_phy0_pipe_clk";
3957 #phy-cells = <0>;
3963 compatible = "qcom,x1e80100-qmp-usb3-uni-phy";
3970 clock-names = "aux",
3977 reset-names = "phy",
3980 power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>;
3982 #clock-cells = <0>;
3983 clock-output-names = "usb_mp_phy1_pipe_clk";
3985 #phy-cells = <0>;
3991 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
4003 clock-names = "cfg_noc",
4013 assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>,
4015 assigned-clock-rates = <19200000>,
4018 interrupts-extended = <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
4022 interrupt-names = "pwr_event",
4027 power-domains = <&gcc GCC_USB30_TERT_GDSC>;
4028 required-opps = <&rpmhpd_opp_nom>;
4036 interconnect-names = "usb-ddr",
4037 "apps-usb";
4039 wakeup-source;
4041 #address-cells = <2>;
4042 #size-cells = <2>;
4057 phy-names = "usb2-phy",
4058 "usb3-phy";
4064 dma-coherent;
4067 #address-cells = <1>;
4068 #size-cells = <0>;
4081 remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>;
4089 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
4091 #address-cells = <2>;
4092 #size-cells = <2>;
4104 clock-names = "cfg_noc",
4114 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
4116 assigned-clock-rates = <19200000>, <200000000>;
4118 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4121 interrupt-names = "pwr_event",
4125 power-domains = <&gcc GCC_USB20_PRIM_GDSC>;
4126 required-opps = <&rpmhpd_opp_nom>;
4134 interconnect-names = "usb-ddr",
4135 "apps-usb";
4137 wakeup-source;
4147 phy-names = "usb2-phy";
4148 maximum-speed = "high-speed";
4151 #address-cells = <1>;
4152 #size-cells = <0>;
4165 compatible = "qcom,x1e80100-dwc3-mp", "qcom,dwc3";
4177 clock-names = "cfg_noc",
4187 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
4189 assigned-clock-rates = <19200000>,
4192 interrupts-extended = <&intc GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
4202 interrupt-names = "pwr_event_1", "pwr_event_2",
4208 power-domains = <&gcc GCC_USB30_MP_GDSC>;
4209 required-opps = <&rpmhpd_opp_nom>;
4217 interconnect-names = "usb-ddr",
4218 "apps-usb";
4220 wakeup-source;
4222 #address-cells = <2>;
4223 #size-cells = <2>;
4238 phy-names = "usb2-0", "usb3-0",
4239 "usb2-1", "usb3-1";
4246 dma-coherent;
4251 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
4263 clock-names = "cfg_noc",
4273 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4275 assigned-clock-rates = <19200000>,
4278 interrupts-extended = <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
4282 interrupt-names = "pwr_event",
4287 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
4288 required-opps = <&rpmhpd_opp_nom>;
4292 wakeup-source;
4294 #address-cells = <2>;
4295 #size-cells = <2>;
4310 phy-names = "usb2-phy",
4311 "usb3-phy";
4317 dma-coherent;
4320 #address-cells = <1>;
4321 #size-cells = <0>;
4334 remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>;
4342 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
4354 clock-names = "cfg_noc",
4364 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4366 assigned-clock-rates = <19200000>,
4369 interrupts-extended = <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
4373 interrupt-names = "pwr_event",
4378 power-domains = <&gcc GCC_USB30_SEC_GDSC>;
4379 required-opps = <&rpmhpd_opp_nom>;
4387 interconnect-names = "usb-ddr",
4388 "apps-usb";
4390 wakeup-source;
4392 #address-cells = <2>;
4393 #size-cells = <2>;
4408 phy-names = "usb2-phy",
4409 "usb3-phy";
4415 dma-coherent;
4418 #address-cells = <1>;
4419 #size-cells = <0>;
4432 remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>;
4439 mdss: display-subsystem@ae00000 { label
4440 compatible = "qcom,x1e80100-mdss";
4442 reg-names = "mdss";
4458 interconnect-names = "mdp0-mem",
4459 "mdp1-mem",
4460 "cpu-cfg";
4462 power-domains = <&dispcc MDSS_GDSC>;
4466 interrupt-controller;
4467 #interrupt-cells = <1>;
4469 #address-cells = <2>;
4470 #size-cells = <2>;
4475 mdss_mdp: display-controller@ae01000 {
4476 compatible = "qcom,x1e80100-dpu";
4479 reg-names = "mdp",
4482 interrupts-extended = <&mdss 0>;
4489 clock-names = "nrt_bus",
4495 operating-points-v2 = <&mdp_opp_table>;
4497 power-domains = <&rpmhpd RPMHPD_MMCX>;
4500 #address-cells = <1>;
4501 #size-cells = <0>;
4507 remote-endpoint = <&mdss_dp0_in>;
4515 remote-endpoint = <&mdss_dp1_in>;
4523 remote-endpoint = <&mdss_dp3_in>;
4531 remote-endpoint = <&mdss_dp2_in>;
4536 mdp_opp_table: opp-table {
4537 compatible = "operating-points-v2";
4539 opp-200000000 {
4540 opp-hz = /bits/ 64 <200000000>;
4541 required-opps = <&rpmhpd_opp_low_svs>;
4544 opp-325000000 {
4545 opp-hz = /bits/ 64 <325000000>;
4546 required-opps = <&rpmhpd_opp_svs>;
4549 opp-375000000 {
4550 opp-hz = /bits/ 64 <375000000>;
4551 required-opps = <&rpmhpd_opp_svs_l1>;
4554 opp-514000000 {
4555 opp-hz = /bits/ 64 <514000000>;
4556 required-opps = <&rpmhpd_opp_nom>;
4559 opp-575000000 {
4560 opp-hz = /bits/ 64 <575000000>;
4561 required-opps = <&rpmhpd_opp_nom_l1>;
4566 mdss_dp0: displayport-controller@ae90000 {
4567 compatible = "qcom,x1e80100-dp";
4574 interrupts-extended = <&mdss 12>;
4581 clock-names = "core_iface",
4587 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
4589 assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4592 operating-points-v2 = <&mdss_dp0_opp_table>;
4594 power-domains = <&rpmhpd RPMHPD_MMCX>;
4597 phy-names = "dp";
4599 #sound-dai-cells = <0>;
4604 #address-cells = <1>;
4605 #size-cells = <0>;
4611 remote-endpoint = <&mdss_intf0_out>;
4619 remote-endpoint = <&usb_1_ss0_qmpphy_dp_in>;
4624 mdss_dp0_opp_table: opp-table {
4625 compatible = "operating-points-v2";
4627 opp-160000000 {
4628 opp-hz = /bits/ 64 <160000000>;
4629 required-opps = <&rpmhpd_opp_low_svs>;
4632 opp-270000000 {
4633 opp-hz = /bits/ 64 <270000000>;
4634 required-opps = <&rpmhpd_opp_svs>;
4637 opp-540000000 {
4638 opp-hz = /bits/ 64 <540000000>;
4639 required-opps = <&rpmhpd_opp_svs_l1>;
4642 opp-810000000 {
4643 opp-hz = /bits/ 64 <810000000>;
4644 required-opps = <&rpmhpd_opp_nom>;
4649 mdss_dp1: displayport-controller@ae98000 {
4650 compatible = "qcom,x1e80100-dp";
4657 interrupts-extended = <&mdss 13>;
4664 clock-names = "core_iface",
4670 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
4672 assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4675 operating-points-v2 = <&mdss_dp1_opp_table>;
4677 power-domains = <&rpmhpd RPMHPD_MMCX>;
4680 phy-names = "dp";
4682 #sound-dai-cells = <0>;
4687 #address-cells = <1>;
4688 #size-cells = <0>;
4694 remote-endpoint = <&mdss_intf4_out>;
4702 remote-endpoint = <&usb_1_ss1_qmpphy_dp_in>;
4707 mdss_dp1_opp_table: opp-table {
4708 compatible = "operating-points-v2";
4710 opp-160000000 {
4711 opp-hz = /bits/ 64 <160000000>;
4712 required-opps = <&rpmhpd_opp_low_svs>;
4715 opp-270000000 {
4716 opp-hz = /bits/ 64 <270000000>;
4717 required-opps = <&rpmhpd_opp_svs>;
4720 opp-540000000 {
4721 opp-hz = /bits/ 64 <540000000>;
4722 required-opps = <&rpmhpd_opp_svs_l1>;
4725 opp-810000000 {
4726 opp-hz = /bits/ 64 <810000000>;
4727 required-opps = <&rpmhpd_opp_nom>;
4732 mdss_dp2: displayport-controller@ae9a000 {
4733 compatible = "qcom,x1e80100-dp";
4740 interrupts-extended = <&mdss 14>;
4747 clock-names = "core_iface",
4753 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
4755 assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4758 operating-points-v2 = <&mdss_dp2_opp_table>;
4760 power-domains = <&rpmhpd RPMHPD_MMCX>;
4763 phy-names = "dp";
4765 #sound-dai-cells = <0>;
4770 #address-cells = <1>;
4771 #size-cells = <0>;
4776 remote-endpoint = <&mdss_intf6_out>;
4784 remote-endpoint = <&usb_1_ss2_qmpphy_dp_in>;
4789 mdss_dp2_opp_table: opp-table {
4790 compatible = "operating-points-v2";
4792 opp-160000000 {
4793 opp-hz = /bits/ 64 <160000000>;
4794 required-opps = <&rpmhpd_opp_low_svs>;
4797 opp-270000000 {
4798 opp-hz = /bits/ 64 <270000000>;
4799 required-opps = <&rpmhpd_opp_svs>;
4802 opp-540000000 {
4803 opp-hz = /bits/ 64 <540000000>;
4804 required-opps = <&rpmhpd_opp_svs_l1>;
4807 opp-810000000 {
4808 opp-hz = /bits/ 64 <810000000>;
4809 required-opps = <&rpmhpd_opp_nom>;
4814 mdss_dp3: displayport-controller@aea0000 {
4815 compatible = "qcom,x1e80100-dp";
4822 interrupts-extended = <&mdss 15>;
4829 clock-names = "core_iface",
4835 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
4837 assigned-clock-parents = <&mdss_dp3_phy 0>,
4840 operating-points-v2 = <&mdss_dp3_opp_table>;
4842 power-domains = <&rpmhpd RPMHPD_MMCX>;
4845 phy-names = "dp";
4847 #sound-dai-cells = <0>;
4852 #address-cells = <1>;
4853 #size-cells = <0>;
4859 remote-endpoint = <&mdss_intf5_out>;
4868 mdss_dp3_opp_table: opp-table {
4869 compatible = "operating-points-v2";
4871 opp-160000000 {
4872 opp-hz = /bits/ 64 <160000000>;
4873 required-opps = <&rpmhpd_opp_low_svs>;
4876 opp-270000000 {
4877 opp-hz = /bits/ 64 <270000000>;
4878 required-opps = <&rpmhpd_opp_svs>;
4881 opp-540000000 {
4882 opp-hz = /bits/ 64 <540000000>;
4883 required-opps = <&rpmhpd_opp_svs_l1>;
4886 opp-810000000 {
4887 opp-hz = /bits/ 64 <810000000>;
4888 required-opps = <&rpmhpd_opp_nom>;
4896 compatible = "qcom,x1e80100-dp-phy";
4904 clock-names = "aux",
4907 power-domains = <&rpmhpd RPMHPD_MX>;
4909 #clock-cells = <1>;
4910 #phy-cells = <0>;
4916 compatible = "qcom,x1e80100-dp-phy";
4924 clock-names = "aux",
4927 power-domains = <&rpmhpd RPMHPD_MX>;
4929 #clock-cells = <1>;
4930 #phy-cells = <0>;
4935 dispcc: clock-controller@af00000 {
4936 compatible = "qcom,x1e80100-dispcc";
4954 power-domains = <&rpmhpd RPMHPD_MMCX>;
4955 required-opps = <&rpmhpd_opp_low_svs>;
4956 #clock-cells = <1>;
4957 #reset-cells = <1>;
4958 #power-domain-cells = <1>;
4961 pdc: interrupt-controller@b220000 {
4962 compatible = "qcom,x1e80100-pdc", "qcom,pdc";
4965 qcom,pdc-ranges = <0 480 42>, <42 251 5>,
4968 #interrupt-cells = <2>;
4969 interrupt-parent = <&intc>;
4970 interrupt-controller;
4973 aoss_qmp: power-management@c300000 {
4974 compatible = "qcom,x1e80100-aoss-qmp", "qcom,aoss-qmp";
4976 interrupt-parent = <&ipcc>;
4977 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
4981 #clock-cells = <0>;
4985 compatible = "qcom,rpmh-stats";
4990 compatible = "qcom,x1e80100-spmi-pmic-arb";
4994 reg-names = "core", "chnls", "obsrvr";
4999 #address-cells = <2>;
5000 #size-cells = <2>;
5006 reg-names = "cnfg", "intr";
5008 interrupt-names = "periph_irq";
5009 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5010 interrupt-controller;
5011 #interrupt-cells = <4>;
5013 #address-cells = <2>;
5014 #size-cells = <0>;
5020 reg-names = "cnfg", "intr";
5022 interrupt-names = "periph_irq";
5023 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
5024 interrupt-controller;
5025 #interrupt-cells = <4>;
5027 #address-cells = <2>;
5028 #size-cells = <0>;
5033 compatible = "qcom,x1e80100-tlmm";
5038 gpio-controller;
5039 #gpio-cells = <2>;
5041 interrupt-controller;
5042 #interrupt-cells = <2>;
5044 gpio-ranges = <&tlmm 0 0 239>;
5045 wakeup-parent = <&pdc>;
5047 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
5051 drive-strength = <2>;
5052 bias-pull-up = <2200>;
5055 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
5059 drive-strength = <2>;
5060 bias-pull-up = <2200>;
5063 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
5067 drive-strength = <2>;
5068 bias-pull-up = <2200>;
5071 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
5075 drive-strength = <2>;
5076 bias-pull-up = <2200>;
5079 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
5083 drive-strength = <2>;
5084 bias-pull-up = <2200>;
5087 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
5091 drive-strength = <2>;
5092 bias-pull-up = <2200>;
5095 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
5099 drive-strength = <2>;
5100 bias-pull-up = <2200>;
5103 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
5107 drive-strength = <2>;
5108 bias-pull-up = <2200>;
5111 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
5115 drive-strength = <2>;
5116 bias-pull-up = <2200>;
5119 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
5123 drive-strength = <2>;
5124 bias-pull-up = <2200>;
5127 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
5131 drive-strength = <2>;
5132 bias-pull-up = <2200>;
5135 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
5139 drive-strength = <2>;
5140 bias-pull-up = <2200>;
5143 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
5147 drive-strength = <2>;
5148 bias-pull-up = <2200>;
5151 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
5155 drive-strength = <2>;
5156 bias-pull-up = <2200>;
5159 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
5163 drive-strength = <2>;
5164 bias-pull-up = <2200>;
5167 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
5171 drive-strength = <2>;
5172 bias-pull-up = <2200>;
5175 qup_i2c16_data_clk: qup-i2c16-data-clk-state {
5179 drive-strength = <2>;
5180 bias-pull-up = <2200>;
5183 qup_i2c17_data_clk: qup-i2c17-data-clk-state {
5187 drive-strength = <2>;
5188 bias-pull-up = <2200>;
5191 qup_i2c18_data_clk: qup-i2c18-data-clk-state {
5195 drive-strength = <2>;
5196 bias-pull-up = <2200>;
5199 qup_i2c19_data_clk: qup-i2c19-data-clk-state {
5203 drive-strength = <2>;
5204 bias-pull-up = <2200>;
5207 qup_i2c20_data_clk: qup-i2c20-data-clk-state {
5211 drive-strength = <2>;
5212 bias-pull-up = <2200>;
5215 qup_i2c21_data_clk: qup-i2c21-data-clk-state {
5219 drive-strength = <2>;
5220 bias-pull-up = <2200>;
5223 qup_i2c22_data_clk: qup-i2c22-data-clk-state {
5227 drive-strength = <2>;
5228 bias-pull-up = <2200>;
5231 qup_i2c23_data_clk: qup-i2c23-data-clk-state {
5235 drive-strength = <2>;
5236 bias-pull-up = <2200>;
5239 qup_spi0_cs: qup-spi0-cs-state {
5242 drive-strength = <6>;
5243 bias-disable;
5246 qup_spi0_data_clk: qup-spi0-data-clk-state {
5250 drive-strength = <6>;
5251 bias-disable;
5254 qup_spi1_cs: qup-spi1-cs-state {
5257 drive-strength = <6>;
5258 bias-disable;
5261 qup_spi1_data_clk: qup-spi1-data-clk-state {
5265 drive-strength = <6>;
5266 bias-disable;
5269 qup_spi2_cs: qup-spi2-cs-state {
5272 drive-strength = <6>;
5273 bias-disable;
5276 qup_spi2_data_clk: qup-spi2-data-clk-state {
5280 drive-strength = <6>;
5281 bias-disable;
5284 qup_spi3_cs: qup-spi3-cs-state {
5287 drive-strength = <6>;
5288 bias-disable;
5291 qup_spi3_data_clk: qup-spi3-data-clk-state {
5295 drive-strength = <6>;
5296 bias-disable;
5299 qup_spi4_cs: qup-spi4-cs-state {
5302 drive-strength = <6>;
5303 bias-disable;
5306 qup_spi4_data_clk: qup-spi4-data-clk-state {
5310 drive-strength = <6>;
5311 bias-disable;
5314 qup_spi5_cs: qup-spi5-cs-state {
5317 drive-strength = <6>;
5318 bias-disable;
5321 qup_spi5_data_clk: qup-spi5-data-clk-state {
5325 drive-strength = <6>;
5326 bias-disable;
5329 qup_spi6_cs: qup-spi6-cs-state {
5332 drive-strength = <6>;
5333 bias-disable;
5336 qup_spi6_data_clk: qup-spi6-data-clk-state {
5340 drive-strength = <6>;
5341 bias-disable;
5344 qup_spi7_cs: qup-spi7-cs-state {
5347 drive-strength = <6>;
5348 bias-disable;
5351 qup_spi7_data_clk: qup-spi7-data-clk-state {
5355 drive-strength = <6>;
5356 bias-disable;
5359 qup_spi8_cs: qup-spi8-cs-state {
5362 drive-strength = <6>;
5363 bias-disable;
5366 qup_spi8_data_clk: qup-spi8-data-clk-state {
5370 drive-strength = <6>;
5371 bias-disable;
5374 qup_spi9_cs: qup-spi9-cs-state {
5377 drive-strength = <6>;
5378 bias-disable;
5381 qup_spi9_data_clk: qup-spi9-data-clk-state {
5385 drive-strength = <6>;
5386 bias-disable;
5389 qup_spi10_cs: qup-spi10-cs-state {
5392 drive-strength = <6>;
5393 bias-disable;
5396 qup_spi10_data_clk: qup-spi10-data-clk-state {
5400 drive-strength = <6>;
5401 bias-disable;
5404 qup_spi11_cs: qup-spi11-cs-state {
5407 drive-strength = <6>;
5408 bias-disable;
5411 qup_spi11_data_clk: qup-spi11-data-clk-state {
5415 drive-strength = <6>;
5416 bias-disable;
5419 qup_spi12_cs: qup-spi12-cs-state {
5422 drive-strength = <6>;
5423 bias-disable;
5426 qup_spi12_data_clk: qup-spi12-data-clk-state {
5430 drive-strength = <6>;
5431 bias-disable;
5434 qup_spi13_cs: qup-spi13-cs-state {
5437 drive-strength = <6>;
5438 bias-disable;
5441 qup_spi13_data_clk: qup-spi13-data-clk-state {
5445 drive-strength = <6>;
5446 bias-disable;
5449 qup_spi14_cs: qup-spi14-cs-state {
5452 drive-strength = <6>;
5453 bias-disable;
5456 qup_spi14_data_clk: qup-spi14-data-clk-state {
5460 drive-strength = <6>;
5461 bias-disable;
5464 qup_spi15_cs: qup-spi15-cs-state {
5467 drive-strength = <6>;
5468 bias-disable;
5471 qup_spi15_data_clk: qup-spi15-data-clk-state {
5475 drive-strength = <6>;
5476 bias-disable;
5479 qup_spi16_cs: qup-spi16-cs-state {
5482 drive-strength = <6>;
5483 bias-disable;
5486 qup_spi16_data_clk: qup-spi16-data-clk-state {
5490 drive-strength = <6>;
5491 bias-disable;
5494 qup_spi17_cs: qup-spi17-cs-state {
5497 drive-strength = <6>;
5498 bias-disable;
5501 qup_spi17_data_clk: qup-spi17-data-clk-state {
5505 drive-strength = <6>;
5506 bias-disable;
5509 qup_spi18_cs: qup-spi18-cs-state {
5512 drive-strength = <6>;
5513 bias-disable;
5516 qup_spi18_data_clk: qup-spi18-data-clk-state {
5520 drive-strength = <6>;
5521 bias-disable;
5524 qup_spi19_cs: qup-spi19-cs-state {
5527 drive-strength = <6>;
5528 bias-disable;
5531 qup_spi19_data_clk: qup-spi19-data-clk-state {
5535 drive-strength = <6>;
5536 bias-disable;
5539 qup_spi20_cs: qup-spi20-cs-state {
5542 drive-strength = <6>;
5543 bias-disable;
5546 qup_spi20_data_clk: qup-spi20-data-clk-state {
5550 drive-strength = <6>;
5551 bias-disable;
5554 qup_spi21_cs: qup-spi21-cs-state {
5557 drive-strength = <6>;
5558 bias-disable;
5561 qup_spi21_data_clk: qup-spi21-data-clk-state {
5565 drive-strength = <6>;
5566 bias-disable;
5569 qup_spi22_cs: qup-spi22-cs-state {
5572 drive-strength = <6>;
5573 bias-disable;
5576 qup_spi22_data_clk: qup-spi22-data-clk-state {
5580 drive-strength = <6>;
5581 bias-disable;
5584 qup_spi23_cs: qup-spi23-cs-state {
5587 drive-strength = <6>;
5588 bias-disable;
5591 qup_spi23_data_clk: qup-spi23-data-clk-state {
5595 drive-strength = <6>;
5596 bias-disable;
5599 qup_uart2_default: qup-uart2-default-state {
5600 cts-pins {
5603 drive-strength = <2>;
5604 bias-disable;
5607 rts-pins {
5610 drive-strength = <2>;
5611 bias-disable;
5614 tx-pins {
5617 drive-strength = <2>;
5618 bias-disable;
5621 rx-pins {
5624 drive-strength = <2>;
5625 bias-disable;
5629 qup_uart21_default: qup-uart21-default-state {
5630 tx-pins {
5633 drive-strength = <2>;
5634 bias-disable;
5637 rx-pins {
5640 drive-strength = <2>;
5641 bias-disable;
5647 compatible = "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500";
5748 #iommu-cells = <2>;
5749 #global-interrupts = <1>;
5752 intc: interrupt-controller@17000000 {
5753 compatible = "arm,gic-v3";
5759 #interrupt-cells = <3>;
5760 interrupt-controller;
5762 #redistributor-regions = <1>;
5763 redistributor-stride = <0x0 0x40000>;
5765 #address-cells = <2>;
5766 #size-cells = <2>;
5769 gic_its: msi-controller@17040000 {
5770 compatible = "arm,gic-v3-its";
5773 msi-controller;
5774 #msi-cells = <1>;
5781 compatible = "qcom,rpmh-rsc";
5785 reg-names = "drv-0", "drv-1", "drv-2";
5790 qcom,tcs-offset = <0xd00>;
5791 qcom,drv-id = <2>;
5792 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
5796 power-domains = <&SYSTEM_PD>;
5798 apps_bcm_voter: bcm-voter {
5799 compatible = "qcom,bcm-voter";
5802 rpmhcc: clock-controller {
5803 compatible = "qcom,x1e80100-rpmh-clk";
5806 clock-names = "xo";
5808 #clock-cells = <1>;
5811 rpmhpd: power-controller {
5812 compatible = "qcom,x1e80100-rpmhpd";
5814 operating-points-v2 = <&rpmhpd_opp_table>;
5816 #power-domain-cells = <1>;
5818 rpmhpd_opp_table: opp-table {
5819 compatible = "operating-points-v2";
5821 rpmhpd_opp_ret: opp-16 {
5822 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5825 rpmhpd_opp_min_svs: opp-48 {
5826 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5829 rpmhpd_opp_low_svs_d2: opp-52 {
5830 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
5833 rpmhpd_opp_low_svs_d1: opp-56 {
5834 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
5837 rpmhpd_opp_low_svs_d0: opp-60 {
5838 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
5841 rpmhpd_opp_low_svs: opp-64 {
5842 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5845 rpmhpd_opp_low_svs_l1: opp-80 {
5846 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
5849 rpmhpd_opp_svs: opp-128 {
5850 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5853 rpmhpd_opp_svs_l0: opp-144 {
5854 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
5857 rpmhpd_opp_svs_l1: opp-192 {
5858 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5861 rpmhpd_opp_nom: opp-256 {
5862 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5865 rpmhpd_opp_nom_l1: opp-320 {
5866 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5869 rpmhpd_opp_nom_l2: opp-336 {
5870 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5873 rpmhpd_opp_turbo: opp-384 {
5874 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5877 rpmhpd_opp_turbo_l1: opp-416 {
5878 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5885 compatible = "arm,armv7-timer-mem";
5888 #address-cells = <2>;
5889 #size-cells = <1>;
5899 frame-number = <0>;
5907 frame-number = <1>;
5917 frame-number = <2>;
5927 frame-number = <3>;
5937 frame-number = <4>;
5947 frame-number = <5>;
5957 frame-number = <6>;
5964 compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
5972 operating-points-v2 = <&llcc_bwmon_opp_table>;
5974 llcc_bwmon_opp_table: opp-table {
5975 compatible = "operating-points-v2";
5977 opp-0 {
5978 opp-peak-kBps = <800000>;
5981 opp-1 {
5982 opp-peak-kBps = <2188000>;
5985 opp-2 {
5986 opp-peak-kBps = <3072000>;
5989 opp-3 {
5990 opp-peak-kBps = <6220800>;
5993 opp-4 {
5994 opp-peak-kBps = <6835200>;
5997 opp-5 {
5998 opp-peak-kBps = <8371200>;
6001 opp-6 {
6002 opp-peak-kBps = <10944000>;
6005 opp-7 {
6006 opp-peak-kBps = <12748800>;
6009 opp-8 {
6010 opp-peak-kBps = <14745600>;
6013 opp-9 {
6014 opp-peak-kBps = <16896000>;
6021 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
6029 operating-points-v2 = <&cpu_bwmon_opp_table>;
6031 cpu_bwmon_opp_table: opp-table {
6032 compatible = "operating-points-v2";
6034 opp-0 {
6035 opp-peak-kBps = <4800000>;
6038 opp-1 {
6039 opp-peak-kBps = <7464000>;
6042 opp-2 {
6043 opp-peak-kBps = <9600000>;
6046 opp-3 {
6047 opp-peak-kBps = <12896000>;
6050 opp-4 {
6051 opp-peak-kBps = <14928000>;
6054 opp-5 {
6055 opp-peak-kBps = <17064000>;
6062 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
6070 operating-points-v2 = <&cpu_bwmon_opp_table>;
6075 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
6083 operating-points-v2 = <&cpu_bwmon_opp_table>;
6086 system-cache-controller@25000000 {
6087 compatible = "qcom,x1e80100-llcc";
6098 reg-names = "llcc0_base",
6112 compatible = "qcom,x1e80100-adsp-pas";
6115 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
6120 interrupt-names = "wdog",
6124 "stop-ack";
6127 clock-names = "xo";
6129 power-domains = <&rpmhpd RPMHPD_LCX>,
6131 power-domain-names = "lcx",
6137 memory-region = <&adspslpi_mem>,
6142 qcom,smem-states = <&smp2p_adsp_out 0>;
6143 qcom,smem-state-names = "stop";
6147 glink-edge {
6148 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
6155 qcom,remote-pid = <2>;
6159 qcom,glink-channels = "fastrpcglink-apps-dsp";
6161 qcom,non-secure-domain;
6162 #address-cells = <1>;
6163 #size-cells = <0>;
6165 compute-cb@3 {
6166 compatible = "qcom,fastrpc-compute-cb";
6170 dma-coherent;
6173 compute-cb@4 {
6174 compatible = "qcom,fastrpc-compute-cb";
6178 dma-coherent;
6181 compute-cb@5 {
6182 compatible = "qcom,fastrpc-compute-cb";
6186 dma-coherent;
6189 compute-cb@6 {
6190 compatible = "qcom,fastrpc-compute-cb";
6194 dma-coherent;
6197 compute-cb@7 {
6198 compatible = "qcom,fastrpc-compute-cb";
6202 dma-coherent;
6208 qcom,glink-channels = "adsp_apps";
6211 #address-cells = <1>;
6212 #size-cells = <0>;
6217 #sound-dai-cells = <0>;
6218 qcom,protection-domain = "avs/audio",
6222 compatible = "qcom,q6apm-lpass-dais";
6223 #sound-dai-cells = <1>;
6227 compatible = "qcom,q6apm-dais";
6236 qcom,protection-domain = "avs/audio",
6239 q6prmcc: clock-controller {
6240 compatible = "qcom,q6prm-lpass-clocks";
6241 #clock-cells = <2>;
6249 compatible = "qcom,x1e80100-cdsp-pas";
6252 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
6257 interrupt-names = "wdog",
6261 "stop-ack";
6264 clock-names = "xo";
6266 power-domains = <&rpmhpd RPMHPD_CX>,
6269 power-domain-names = "cx",
6276 memory-region = <&cdsp_mem>,
6281 qcom,smem-states = <&smp2p_cdsp_out 0>;
6282 qcom,smem-state-names = "stop";
6286 glink-edge {
6287 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
6294 qcom,remote-pid = <5>;
6298 qcom,glink-channels = "fastrpcglink-apps-dsp";
6300 qcom,non-secure-domain;
6301 #address-cells = <1>;
6302 #size-cells = <0>;
6304 compute-cb@1 {
6305 compatible = "qcom,fastrpc-compute-cb";
6308 dma-coherent;
6311 compute-cb@2 {
6312 compatible = "qcom,fastrpc-compute-cb";
6315 dma-coherent;
6318 compute-cb@3 {
6319 compatible = "qcom,fastrpc-compute-cb";
6322 dma-coherent;
6325 compute-cb@4 {
6326 compatible = "qcom,fastrpc-compute-cb";
6329 dma-coherent;
6332 compute-cb@5 {
6333 compatible = "qcom,fastrpc-compute-cb";
6336 dma-coherent;
6339 compute-cb@6 {
6340 compatible = "qcom,fastrpc-compute-cb";
6343 dma-coherent;
6346 compute-cb@7 {
6347 compatible = "qcom,fastrpc-compute-cb";
6350 dma-coherent;
6353 compute-cb@8 {
6354 compatible = "qcom,fastrpc-compute-cb";
6357 dma-coherent;
6360 /* note: compute-cb@9 is secure */
6362 compute-cb@10 {
6363 compatible = "qcom,fastrpc-compute-cb";
6366 dma-coherent;
6369 compute-cb@11 {
6370 compatible = "qcom,fastrpc-compute-cb";
6373 dma-coherent;
6376 compute-cb@12 {
6377 compatible = "qcom,fastrpc-compute-cb";
6380 dma-coherent;
6383 compute-cb@13 {
6384 compatible = "qcom,fastrpc-compute-cb";
6387 dma-coherent;
6395 compatible = "arm,armv8-timer";
6403 thermal-zones {
6404 aoss0-thermal {
6405 thermal-sensors = <&tsens0 0>;
6408 trip-point0 {
6414 aoss0-critical {
6422 cpu0-0-top-thermal {
6423 polling-delay-passive = <250>;
6425 thermal-sensors = <&tsens0 1>;
6428 trip-point0 {
6434 trip-point1 {
6440 cpu-critical {
6448 cpu0-0-btm-thermal {
6449 polling-delay-passive = <250>;
6451 thermal-sensors = <&tsens0 2>;
6454 trip-point0 {
6460 trip-point1 {
6466 cpu-critical {
6474 cpu0-1-top-thermal {
6475 polling-delay-passive = <250>;
6477 thermal-sensors = <&tsens0 3>;
6480 trip-point0 {
6486 trip-point1 {
6492 cpu-critical {
6500 cpu0-1-btm-thermal {
6501 polling-delay-passive = <250>;
6503 thermal-sensors = <&tsens0 4>;
6506 trip-point0 {
6512 trip-point1 {
6518 cpu-critical {
6526 cpu0-2-top-thermal {
6527 polling-delay-passive = <250>;
6529 thermal-sensors = <&tsens0 5>;
6532 trip-point0 {
6538 trip-point1 {
6544 cpu-critical {
6552 cpu0-2-btm-thermal {
6553 polling-delay-passive = <250>;
6555 thermal-sensors = <&tsens0 6>;
6558 trip-point0 {
6564 trip-point1 {
6570 cpu-critical {
6578 cpu0-3-top-thermal {
6579 polling-delay-passive = <250>;
6581 thermal-sensors = <&tsens0 7>;
6584 trip-point0 {
6590 trip-point1 {
6596 cpu-critical {
6604 cpu0-3-btm-thermal {
6605 polling-delay-passive = <250>;
6607 thermal-sensors = <&tsens0 8>;
6610 trip-point0 {
6616 trip-point1 {
6622 cpu-critical {
6630 cpuss0-top-thermal {
6631 thermal-sensors = <&tsens0 9>;
6634 trip-point0 {
6640 cpuss2-critical {
6648 cpuss0-btm-thermal {
6649 thermal-sensors = <&tsens0 10>;
6652 trip-point0 {
6658 cpuss2-critical {
6666 mem-thermal {
6667 thermal-sensors = <&tsens0 11>;
6670 trip-point0 {
6676 mem-critical {
6684 video-thermal {
6685 polling-delay-passive = <250>;
6687 thermal-sensors = <&tsens0 12>;
6690 trip-point0 {
6698 aoss1-thermal {
6699 thermal-sensors = <&tsens1 0>;
6702 trip-point0 {
6708 aoss0-critical {
6716 cpu1-0-top-thermal {
6717 polling-delay-passive = <250>;
6719 thermal-sensors = <&tsens1 1>;
6722 trip-point0 {
6728 trip-point1 {
6734 cpu-critical {
6742 cpu1-0-btm-thermal {
6743 polling-delay-passive = <250>;
6745 thermal-sensors = <&tsens1 2>;
6748 trip-point0 {
6754 trip-point1 {
6760 cpu-critical {
6768 cpu1-1-top-thermal {
6769 polling-delay-passive = <250>;
6771 thermal-sensors = <&tsens1 3>;
6774 trip-point0 {
6780 trip-point1 {
6786 cpu-critical {
6794 cpu1-1-btm-thermal {
6795 polling-delay-passive = <250>;
6797 thermal-sensors = <&tsens1 4>;
6800 trip-point0 {
6806 trip-point1 {
6812 cpu-critical {
6820 cpu1-2-top-thermal {
6821 polling-delay-passive = <250>;
6823 thermal-sensors = <&tsens1 5>;
6826 trip-point0 {
6832 trip-point1 {
6838 cpu-critical {
6846 cpu1-2-btm-thermal {
6847 polling-delay-passive = <250>;
6849 thermal-sensors = <&tsens1 6>;
6852 trip-point0 {
6858 trip-point1 {
6864 cpu-critical {
6872 cpu1-3-top-thermal {
6873 polling-delay-passive = <250>;
6875 thermal-sensors = <&tsens1 7>;
6878 trip-point0 {
6884 trip-point1 {
6890 cpu-critical {
6898 cpu1-3-btm-thermal {
6899 polling-delay-passive = <250>;
6901 thermal-sensors = <&tsens1 8>;
6904 trip-point0 {
6910 trip-point1 {
6916 cpu-critical {
6924 cpuss1-top-thermal {
6925 thermal-sensors = <&tsens1 9>;
6928 trip-point0 {
6934 cpuss2-critical {
6942 cpuss1-btm-thermal {
6943 thermal-sensors = <&tsens1 10>;
6946 trip-point0 {
6952 cpuss2-critical {
6960 aoss2-thermal {
6961 thermal-sensors = <&tsens2 0>;
6964 trip-point0 {
6970 aoss0-critical {
6978 cpu2-0-top-thermal {
6979 polling-delay-passive = <250>;
6981 thermal-sensors = <&tsens2 1>;
6984 trip-point0 {
6990 trip-point1 {
6996 cpu-critical {
7004 cpu2-0-btm-thermal {
7005 polling-delay-passive = <250>;
7007 thermal-sensors = <&tsens2 2>;
7010 trip-point0 {
7016 trip-point1 {
7022 cpu-critical {
7030 cpu2-1-top-thermal {
7031 polling-delay-passive = <250>;
7033 thermal-sensors = <&tsens2 3>;
7036 trip-point0 {
7042 trip-point1 {
7048 cpu-critical {
7056 cpu2-1-btm-thermal {
7057 polling-delay-passive = <250>;
7059 thermal-sensors = <&tsens2 4>;
7062 trip-point0 {
7068 trip-point1 {
7074 cpu-critical {
7082 cpu2-2-top-thermal {
7083 polling-delay-passive = <250>;
7085 thermal-sensors = <&tsens2 5>;
7088 trip-point0 {
7094 trip-point1 {
7100 cpu-critical {
7108 cpu2-2-btm-thermal {
7109 polling-delay-passive = <250>;
7111 thermal-sensors = <&tsens2 6>;
7114 trip-point0 {
7120 trip-point1 {
7126 cpu-critical {
7134 cpu2-3-top-thermal {
7135 polling-delay-passive = <250>;
7137 thermal-sensors = <&tsens2 7>;
7140 trip-point0 {
7146 trip-point1 {
7152 cpu-critical {
7160 cpu2-3-btm-thermal {
7161 polling-delay-passive = <250>;
7163 thermal-sensors = <&tsens2 8>;
7166 trip-point0 {
7172 trip-point1 {
7178 cpu-critical {
7186 cpuss2-top-thermal {
7187 thermal-sensors = <&tsens2 9>;
7190 trip-point0 {
7196 cpuss2-critical {
7204 cpuss2-btm-thermal {
7205 thermal-sensors = <&tsens2 10>;
7208 trip-point0 {
7214 cpuss2-critical {
7222 aoss3-thermal {
7223 thermal-sensors = <&tsens3 0>;
7226 trip-point0 {
7232 aoss0-critical {
7240 nsp0-thermal {
7241 thermal-sensors = <&tsens3 1>;
7244 trip-point0 {
7250 nsp0-critical {
7258 nsp1-thermal {
7259 thermal-sensors = <&tsens3 2>;
7262 trip-point0 {
7268 nsp1-critical {
7276 nsp2-thermal {
7277 thermal-sensors = <&tsens3 3>;
7280 trip-point0 {
7286 nsp2-critical {
7294 nsp3-thermal {
7295 thermal-sensors = <&tsens3 4>;
7298 trip-point0 {
7304 nsp3-critical {
7312 gpuss-0-thermal {
7313 polling-delay-passive = <10>;
7315 thermal-sensors = <&tsens3 5>;
7318 trip-point0 {
7324 trip-point1 {
7330 trip-point2 {
7338 gpuss-1-thermal {
7339 polling-delay-passive = <10>;
7341 thermal-sensors = <&tsens3 6>;
7344 trip-point0 {
7350 trip-point1 {
7356 trip-point2 {
7364 gpuss-2-thermal {
7365 polling-delay-passive = <10>;
7367 thermal-sensors = <&tsens3 7>;
7370 trip-point0 {
7376 trip-point1 {
7382 trip-point2 {
7390 gpuss-3-thermal {
7391 polling-delay-passive = <10>;
7393 thermal-sensors = <&tsens3 8>;
7396 trip-point0 {
7402 trip-point1 {
7408 trip-point2 {
7416 gpuss-4-thermal {
7417 polling-delay-passive = <10>;
7419 thermal-sensors = <&tsens3 9>;
7422 trip-point0 {
7428 trip-point1 {
7434 trip-point2 {
7442 gpuss-5-thermal {
7443 polling-delay-passive = <10>;
7445 thermal-sensors = <&tsens3 10>;
7448 trip-point0 {
7454 trip-point1 {
7460 trip-point2 {
7468 gpuss-6-thermal {
7469 polling-delay-passive = <10>;
7471 thermal-sensors = <&tsens3 11>;
7474 trip-point0 {
7480 trip-point1 {
7486 trip-point2 {
7494 gpuss-7-thermal {
7495 polling-delay-passive = <10>;
7497 thermal-sensors = <&tsens3 12>;
7500 trip-point0 {
7506 trip-point1 {
7512 trip-point2 {
7520 camera0-thermal {
7521 thermal-sensors = <&tsens3 13>;
7524 trip-point0 {
7530 camera0-critical {
7538 camera1-thermal {
7539 thermal-sensors = <&tsens3 14>;
7542 trip-point0 {
7548 camera0-critical {