Lines Matching +full:sc7280 +full:- +full:lpassaudiocc
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
8 #include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
9 #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
10 #include <dt-bindings/clock/qcom,x1e80100-gpucc.h>
11 #include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/interconnect/qcom,icc.h>
14 #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/soc/qcom,gpr.h>
21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
22 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
25 interrupt-parent = <&intc>;
27 #address-cells = <2>;
28 #size-cells = <2>;
33 xo_board: xo-board {
34 compatible = "fixed-clock";
35 clock-frequency = <76800000>;
36 #clock-cells = <0>;
39 sleep_clk: sleep-clk {
40 compatible = "fixed-clock";
41 clock-frequency = <32000>;
42 #clock-cells = <0>;
45 bi_tcxo_div2: bi-tcxo-div2-clk {
46 compatible = "fixed-factor-clock";
47 #clock-cells = <0>;
50 clock-mult = <1>;
51 clock-div = <2>;
54 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
55 compatible = "fixed-factor-clock";
56 #clock-cells = <0>;
59 clock-mult = <1>;
60 clock-div = <2>;
65 #address-cells = <2>;
66 #size-cells = <0>;
72 enable-method = "psci";
73 next-level-cache = <&L2_0>;
74 power-domains = <&CPU_PD0>;
75 power-domain-names = "psci";
76 cpu-idle-states = <&CLUSTER_C4>;
78 L2_0: l2-cache {
80 cache-level = <2>;
81 cache-unified;
89 enable-method = "psci";
90 next-level-cache = <&L2_0>;
91 power-domains = <&CPU_PD1>;
92 power-domain-names = "psci";
93 cpu-idle-states = <&CLUSTER_C4>;
100 enable-method = "psci";
101 next-level-cache = <&L2_0>;
102 power-domains = <&CPU_PD2>;
103 power-domain-names = "psci";
104 cpu-idle-states = <&CLUSTER_C4>;
111 enable-method = "psci";
112 next-level-cache = <&L2_0>;
113 power-domains = <&CPU_PD3>;
114 power-domain-names = "psci";
115 cpu-idle-states = <&CLUSTER_C4>;
122 enable-method = "psci";
123 next-level-cache = <&L2_1>;
124 power-domains = <&CPU_PD4>;
125 power-domain-names = "psci";
126 cpu-idle-states = <&CLUSTER_C4>;
128 L2_1: l2-cache {
130 cache-level = <2>;
131 cache-unified;
139 enable-method = "psci";
140 next-level-cache = <&L2_1>;
141 power-domains = <&CPU_PD5>;
142 power-domain-names = "psci";
143 cpu-idle-states = <&CLUSTER_C4>;
150 enable-method = "psci";
151 next-level-cache = <&L2_1>;
152 power-domains = <&CPU_PD6>;
153 power-domain-names = "psci";
154 cpu-idle-states = <&CLUSTER_C4>;
161 enable-method = "psci";
162 next-level-cache = <&L2_1>;
163 power-domains = <&CPU_PD7>;
164 power-domain-names = "psci";
165 cpu-idle-states = <&CLUSTER_C4>;
172 enable-method = "psci";
173 next-level-cache = <&L2_2>;
174 power-domains = <&CPU_PD8>;
175 power-domain-names = "psci";
176 cpu-idle-states = <&CLUSTER_C4>;
178 L2_2: l2-cache {
180 cache-level = <2>;
181 cache-unified;
189 enable-method = "psci";
190 next-level-cache = <&L2_2>;
191 power-domains = <&CPU_PD9>;
192 power-domain-names = "psci";
193 cpu-idle-states = <&CLUSTER_C4>;
200 enable-method = "psci";
201 next-level-cache = <&L2_2>;
202 power-domains = <&CPU_PD10>;
203 power-domain-names = "psci";
204 cpu-idle-states = <&CLUSTER_C4>;
211 enable-method = "psci";
212 next-level-cache = <&L2_2>;
213 power-domains = <&CPU_PD11>;
214 power-domain-names = "psci";
215 cpu-idle-states = <&CLUSTER_C4>;
218 cpu-map {
274 idle-states {
275 entry-method = "psci";
277 CLUSTER_C4: cpu-sleep-0 {
278 compatible = "arm,idle-state";
279 idle-state-name = "ret";
280 arm,psci-suspend-param = <0x00000004>;
281 entry-latency-us = <180>;
282 exit-latency-us = <320>;
283 min-residency-us = <1000>;
287 domain-idle-states {
288 CLUSTER_CL4: cluster-sleep-0 {
289 compatible = "domain-idle-state";
290 idle-state-name = "l2-ret";
291 arm,psci-suspend-param = <0x01000044>;
292 entry-latency-us = <350>;
293 exit-latency-us = <500>;
294 min-residency-us = <2500>;
297 CLUSTER_CL5: cluster-sleep-1 {
298 compatible = "domain-idle-state";
299 idle-state-name = "ret-pll-off";
300 arm,psci-suspend-param = <0x01000054>;
301 entry-latency-us = <2200>;
302 exit-latency-us = <2500>;
303 min-residency-us = <7000>;
310 compatible = "qcom,scm-x1e80100", "qcom,scm";
316 clk_virt: interconnect-0 {
317 compatible = "qcom,x1e80100-clk-virt";
318 #interconnect-cells = <2>;
319 qcom,bcm-voters = <&apps_bcm_voter>;
322 mc_virt: interconnect-1 {
323 compatible = "qcom,x1e80100-mc-virt";
324 #interconnect-cells = <2>;
325 qcom,bcm-voters = <&apps_bcm_voter>;
335 compatible = "arm,armv8-pmuv3";
340 compatible = "arm,psci-1.0";
343 CPU_PD0: power-domain-cpu0 {
344 #power-domain-cells = <0>;
345 power-domains = <&CLUSTER_PD0>;
348 CPU_PD1: power-domain-cpu1 {
349 #power-domain-cells = <0>;
350 power-domains = <&CLUSTER_PD0>;
353 CPU_PD2: power-domain-cpu2 {
354 #power-domain-cells = <0>;
355 power-domains = <&CLUSTER_PD0>;
358 CPU_PD3: power-domain-cpu3 {
359 #power-domain-cells = <0>;
360 power-domains = <&CLUSTER_PD0>;
363 CPU_PD4: power-domain-cpu4 {
364 #power-domain-cells = <0>;
365 power-domains = <&CLUSTER_PD1>;
368 CPU_PD5: power-domain-cpu5 {
369 #power-domain-cells = <0>;
370 power-domains = <&CLUSTER_PD1>;
373 CPU_PD6: power-domain-cpu6 {
374 #power-domain-cells = <0>;
375 power-domains = <&CLUSTER_PD1>;
378 CPU_PD7: power-domain-cpu7 {
379 #power-domain-cells = <0>;
380 power-domains = <&CLUSTER_PD1>;
383 CPU_PD8: power-domain-cpu8 {
384 #power-domain-cells = <0>;
385 power-domains = <&CLUSTER_PD2>;
388 CPU_PD9: power-domain-cpu9 {
389 #power-domain-cells = <0>;
390 power-domains = <&CLUSTER_PD2>;
393 CPU_PD10: power-domain-cpu10 {
394 #power-domain-cells = <0>;
395 power-domains = <&CLUSTER_PD2>;
398 CPU_PD11: power-domain-cpu11 {
399 #power-domain-cells = <0>;
400 power-domains = <&CLUSTER_PD2>;
403 CLUSTER_PD0: power-domain-cpu-cluster0 {
404 #power-domain-cells = <0>;
405 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
406 power-domains = <&SYSTEM_PD>;
409 CLUSTER_PD1: power-domain-cpu-cluster1 {
410 #power-domain-cells = <0>;
411 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
412 power-domains = <&SYSTEM_PD>;
415 CLUSTER_PD2: power-domain-cpu-cluster2 {
416 #power-domain-cells = <0>;
417 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
418 power-domains = <&SYSTEM_PD>;
421 SYSTEM_PD: power-domain-system {
422 #power-domain-cells = <0>;
423 /* TODO: system-wide idle states */
427 reserved-memory {
428 #address-cells = <2>;
429 #size-cells = <2>;
432 gunyah_hyp_mem: gunyah-hyp@80000000 {
434 no-map;
437 hyp_elf_package_mem: hyp-elf-package@80800000 {
439 no-map;
444 no-map;
447 cpucp_log_mem: cpucp-log@80e00000 {
449 no-map;
454 no-map;
457 reserved-region@81380000 {
459 no-map;
462 tags_mem: tags-region@81400000 {
464 no-map;
467 xbl_dtlog_mem: xbl-dtlog@81a00000 {
469 no-map;
472 xbl_ramdump_mem: xbl-ramdump@81a40000 {
474 no-map;
477 aop_image_mem: aop-image@81c00000 {
479 no-map;
482 aop_cmd_db_mem: aop-cmd-db@81c60000 {
483 compatible = "qcom,cmd-db";
485 no-map;
488 aop_config_mem: aop-config@81c80000 {
490 no-map;
493 tme_crash_dump_mem: tme-crash-dump@81ca0000 {
495 no-map;
498 tme_log_mem: tme-log@81ce0000 {
500 no-map;
503 uefi_log_mem: uefi-log@81ce4000 {
505 no-map;
508 secdata_apss_mem: secdata-apss@81cff000 {
510 no-map;
513 pdp_ns_shared_mem: pdp-ns-shared@81e00000 {
515 no-map;
518 gpu_prr_mem: gpu-prr@81f00000 {
520 no-map;
523 tpm_control_mem: tpm-control@81f10000 {
525 no-map;
528 usb_ucsi_shared_mem: usb-ucsi-shared@81f20000 {
530 no-map;
533 pld_pep_mem: pld-pep@81f30000 {
535 no-map;
538 pld_gmu_mem: pld-gmu@81f36000 {
540 no-map;
543 pld_pdp_mem: pld-pdp@81f37000 {
545 no-map;
548 tz_stat_mem: tz-stat@82700000 {
550 no-map;
553 xbl_tmp_buffer_mem: xbl-tmp-buffer@82800000 {
555 no-map;
558 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@84b00000 {
560 no-map;
563 spu_secure_shared_memory_mem: spu-secure-shared-memory@85300000 {
565 no-map;
568 adsp_boot_dtb_mem: adsp-boot-dtb@866c0000 {
570 no-map;
573 spss_region_mem: spss-region@86700000 {
575 no-map;
578 adsp_boot_mem: adsp-boot@86b00000 {
580 no-map;
585 no-map;
590 no-map;
593 q6_adsp_dtb_mem: q6-adsp-dtb@8b800000 {
595 no-map;
600 no-map;
603 q6_cdsp_dtb_mem: q6-cdsp-dtb@8d900000 {
605 no-map;
608 gpu_microcode_mem: gpu-microcode@8d9fe000 {
610 no-map;
615 no-map;
620 no-map;
623 av1_encoder_mem: av1-encoder@8e900000 {
625 no-map;
628 reserved-region@8f000000 {
630 no-map;
635 no-map;
638 q6_wpss_dtb_mem: q6-wpss-dtb@91300000 {
640 no-map;
643 xbl_sc_mem: xbl-sc@d8000000 {
645 no-map;
648 reserved-region@d8040000 {
650 no-map;
655 no-map;
660 no-map;
665 no-map;
668 llcc_lpi_mem: llcc-lpi@ff800000 {
670 no-map;
677 no-map;
681 smp2p-adsp {
684 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
692 qcom,local-pid = <0>;
693 qcom,remote-pid = <2>;
695 smp2p_adsp_out: master-kernel {
696 qcom,entry-name = "master-kernel";
697 #qcom,smem-state-cells = <1>;
700 smp2p_adsp_in: slave-kernel {
701 qcom,entry-name = "slave-kernel";
702 interrupt-controller;
703 #interrupt-cells = <2>;
707 smp2p-cdsp {
710 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
718 qcom,local-pid = <0>;
719 qcom,remote-pid = <5>;
721 smp2p_cdsp_out: master-kernel {
722 qcom,entry-name = "master-kernel";
723 #qcom,smem-state-cells = <1>;
726 smp2p_cdsp_in: slave-kernel {
727 qcom,entry-name = "slave-kernel";
728 interrupt-controller;
729 #interrupt-cells = <2>;
734 compatible = "simple-bus";
736 #address-cells = <2>;
737 #size-cells = <2>;
738 dma-ranges = <0 0 0 0 0x10 0>;
741 gcc: clock-controller@100000 {
742 compatible = "qcom,x1e80100-gcc";
756 power-domains = <&rpmhpd RPMHPD_CX>;
757 #clock-cells = <1>;
758 #reset-cells = <1>;
759 #power-domain-cells = <1>;
763 compatible = "qcom,x1e80100-ipcc", "qcom,ipcc";
767 interrupt-controller;
768 #interrupt-cells = <3>;
770 #mbox-cells = <2>;
773 gpi_dma2: dma-controller@800000 {
774 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
790 dma-channels = <12>;
791 dma-channel-mask = <0x3e>;
792 #dma-cells = <3>;
800 compatible = "qcom,geni-se-qup";
805 clock-names = "m-ahb",
806 "s-ahb";
810 #address-cells = <2>;
811 #size-cells = <2>;
817 compatible = "qcom,geni-i2c";
823 clock-names = "se";
831 interconnect-names = "qup-core",
832 "qup-config",
833 "qup-memory";
837 dma-names = "tx",
840 pinctrl-0 = <&qup_i2c16_data_clk>;
841 pinctrl-names = "default";
843 #address-cells = <1>;
844 #size-cells = <0>;
850 compatible = "qcom,geni-spi";
856 clock-names = "se";
864 interconnect-names = "qup-core",
865 "qup-config",
866 "qup-memory";
870 dma-names = "tx",
873 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
874 pinctrl-names = "default";
876 #address-cells = <1>;
877 #size-cells = <0>;
883 compatible = "qcom,geni-i2c";
889 clock-names = "se";
897 interconnect-names = "qup-core",
898 "qup-config",
899 "qup-memory";
903 dma-names = "tx",
906 pinctrl-0 = <&qup_i2c17_data_clk>;
907 pinctrl-names = "default";
909 #address-cells = <1>;
910 #size-cells = <0>;
916 compatible = "qcom,geni-spi";
922 clock-names = "se";
930 interconnect-names = "qup-core",
931 "qup-config",
932 "qup-memory";
936 dma-names = "tx",
939 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
940 pinctrl-names = "default";
942 #address-cells = <1>;
943 #size-cells = <0>;
949 compatible = "qcom,geni-i2c";
955 clock-names = "se";
963 interconnect-names = "qup-core",
964 "qup-config",
965 "qup-memory";
969 dma-names = "tx",
972 pinctrl-0 = <&qup_i2c18_data_clk>;
973 pinctrl-names = "default";
975 #address-cells = <1>;
976 #size-cells = <0>;
982 compatible = "qcom,geni-spi";
988 clock-names = "se";
996 interconnect-names = "qup-core",
997 "qup-config",
998 "qup-memory";
1002 dma-names = "tx",
1005 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
1006 pinctrl-names = "default";
1008 #address-cells = <1>;
1009 #size-cells = <0>;
1015 compatible = "qcom,geni-i2c";
1021 clock-names = "se";
1029 interconnect-names = "qup-core",
1030 "qup-config",
1031 "qup-memory";
1035 dma-names = "tx",
1038 pinctrl-0 = <&qup_i2c19_data_clk>;
1039 pinctrl-names = "default";
1041 #address-cells = <1>;
1042 #size-cells = <0>;
1048 compatible = "qcom,geni-spi";
1054 clock-names = "se";
1062 interconnect-names = "qup-core",
1063 "qup-config",
1064 "qup-memory";
1068 dma-names = "tx",
1071 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
1072 pinctrl-names = "default";
1074 #address-cells = <1>;
1075 #size-cells = <0>;
1081 compatible = "qcom,geni-i2c";
1087 clock-names = "se";
1095 interconnect-names = "qup-core",
1096 "qup-config",
1097 "qup-memory";
1101 dma-names = "tx",
1104 pinctrl-0 = <&qup_i2c20_data_clk>;
1105 pinctrl-names = "default";
1107 #address-cells = <1>;
1108 #size-cells = <0>;
1114 compatible = "qcom,geni-spi";
1120 clock-names = "se";
1128 interconnect-names = "qup-core",
1129 "qup-config",
1130 "qup-memory";
1134 dma-names = "tx",
1137 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1138 pinctrl-names = "default";
1140 #address-cells = <1>;
1141 #size-cells = <0>;
1147 compatible = "qcom,geni-i2c";
1153 clock-names = "se";
1161 interconnect-names = "qup-core",
1162 "qup-config",
1163 "qup-memory";
1167 dma-names = "tx",
1170 pinctrl-0 = <&qup_i2c21_data_clk>;
1171 pinctrl-names = "default";
1173 #address-cells = <1>;
1174 #size-cells = <0>;
1180 compatible = "qcom,geni-spi";
1186 clock-names = "se";
1194 interconnect-names = "qup-core",
1195 "qup-config",
1196 "qup-memory";
1200 dma-names = "tx",
1203 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1204 pinctrl-names = "default";
1206 #address-cells = <1>;
1207 #size-cells = <0>;
1213 compatible = "qcom,geni-uart";
1219 clock-names = "se";
1225 interconnect-names = "qup-core",
1226 "qup-config";
1228 pinctrl-0 = <&qup_uart21_default>;
1229 pinctrl-names = "default";
1235 compatible = "qcom,geni-i2c";
1241 clock-names = "se";
1249 interconnect-names = "qup-core",
1250 "qup-config",
1251 "qup-memory";
1255 dma-names = "tx",
1258 pinctrl-0 = <&qup_i2c22_data_clk>;
1259 pinctrl-names = "default";
1261 #address-cells = <1>;
1262 #size-cells = <0>;
1268 compatible = "qcom,geni-spi";
1274 clock-names = "se";
1282 interconnect-names = "qup-core",
1283 "qup-config",
1284 "qup-memory";
1288 dma-names = "tx",
1291 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>;
1292 pinctrl-names = "default";
1294 #address-cells = <1>;
1295 #size-cells = <0>;
1301 compatible = "qcom,geni-i2c";
1307 clock-names = "se";
1315 interconnect-names = "qup-core",
1316 "qup-config",
1317 "qup-memory";
1321 dma-names = "tx",
1324 pinctrl-0 = <&qup_i2c23_data_clk>;
1325 pinctrl-names = "default";
1327 #address-cells = <1>;
1328 #size-cells = <0>;
1334 compatible = "qcom,geni-spi";
1340 clock-names = "se";
1348 interconnect-names = "qup-core",
1349 "qup-config",
1350 "qup-memory";
1354 dma-names = "tx",
1357 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>;
1358 pinctrl-names = "default";
1360 #address-cells = <1>;
1361 #size-cells = <0>;
1367 gpi_dma1: dma-controller@a00000 {
1368 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
1384 dma-channels = <12>;
1385 dma-channel-mask = <0x3e>;
1386 #dma-cells = <3>;
1394 compatible = "qcom,geni-se-qup";
1399 clock-names = "m-ahb",
1400 "s-ahb";
1404 #address-cells = <2>;
1405 #size-cells = <2>;
1411 compatible = "qcom,geni-i2c";
1417 clock-names = "se";
1425 interconnect-names = "qup-core",
1426 "qup-config",
1427 "qup-memory";
1431 dma-names = "tx",
1434 pinctrl-0 = <&qup_i2c8_data_clk>;
1435 pinctrl-names = "default";
1437 #address-cells = <1>;
1438 #size-cells = <0>;
1444 compatible = "qcom,geni-spi";
1450 clock-names = "se";
1458 interconnect-names = "qup-core",
1459 "qup-config",
1460 "qup-memory";
1464 dma-names = "tx",
1467 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1468 pinctrl-names = "default";
1470 #address-cells = <1>;
1471 #size-cells = <0>;
1477 compatible = "qcom,geni-i2c";
1483 clock-names = "se";
1491 interconnect-names = "qup-core",
1492 "qup-config",
1493 "qup-memory";
1497 dma-names = "tx",
1500 pinctrl-0 = <&qup_i2c9_data_clk>;
1501 pinctrl-names = "default";
1503 #address-cells = <1>;
1504 #size-cells = <0>;
1510 compatible = "qcom,geni-spi";
1516 clock-names = "se";
1524 interconnect-names = "qup-core",
1525 "qup-config",
1526 "qup-memory";
1530 dma-names = "tx",
1533 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1534 pinctrl-names = "default";
1536 #address-cells = <1>;
1537 #size-cells = <0>;
1543 compatible = "qcom,geni-i2c";
1549 clock-names = "se";
1557 interconnect-names = "qup-core",
1558 "qup-config",
1559 "qup-memory";
1563 dma-names = "tx",
1566 pinctrl-0 = <&qup_i2c10_data_clk>;
1567 pinctrl-names = "default";
1569 #address-cells = <1>;
1570 #size-cells = <0>;
1576 compatible = "qcom,geni-spi";
1582 clock-names = "se";
1590 interconnect-names = "qup-core",
1591 "qup-config",
1592 "qup-memory";
1596 dma-names = "tx",
1599 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1600 pinctrl-names = "default";
1602 #address-cells = <1>;
1603 #size-cells = <0>;
1609 compatible = "qcom,geni-i2c";
1615 clock-names = "se";
1623 interconnect-names = "qup-core",
1624 "qup-config",
1625 "qup-memory";
1629 dma-names = "tx",
1632 pinctrl-0 = <&qup_i2c11_data_clk>;
1633 pinctrl-names = "default";
1635 #address-cells = <1>;
1636 #size-cells = <0>;
1642 compatible = "qcom,geni-spi";
1648 clock-names = "se";
1656 interconnect-names = "qup-core",
1657 "qup-config",
1658 "qup-memory";
1662 dma-names = "tx",
1665 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1666 pinctrl-names = "default";
1668 #address-cells = <1>;
1669 #size-cells = <0>;
1675 compatible = "qcom,geni-i2c";
1681 clock-names = "se";
1689 interconnect-names = "qup-core",
1690 "qup-config",
1691 "qup-memory";
1695 dma-names = "tx",
1698 pinctrl-0 = <&qup_i2c12_data_clk>;
1699 pinctrl-names = "default";
1701 #address-cells = <1>;
1702 #size-cells = <0>;
1708 compatible = "qcom,geni-spi";
1714 clock-names = "se";
1722 interconnect-names = "qup-core",
1723 "qup-config",
1724 "qup-memory";
1728 dma-names = "tx",
1731 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1732 pinctrl-names = "default";
1734 #address-cells = <1>;
1735 #size-cells = <0>;
1741 compatible = "qcom,geni-i2c";
1747 clock-names = "se";
1755 interconnect-names = "qup-core",
1756 "qup-config",
1757 "qup-memory";
1761 dma-names = "tx",
1764 pinctrl-0 = <&qup_i2c13_data_clk>;
1765 pinctrl-names = "default";
1767 #address-cells = <1>;
1768 #size-cells = <0>;
1774 compatible = "qcom,geni-spi";
1780 clock-names = "se";
1788 interconnect-names = "qup-core",
1789 "qup-config",
1790 "qup-memory";
1794 dma-names = "tx",
1797 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1798 pinctrl-names = "default";
1800 #address-cells = <1>;
1801 #size-cells = <0>;
1807 compatible = "qcom,geni-i2c";
1813 clock-names = "se";
1821 interconnect-names = "qup-core",
1822 "qup-config",
1823 "qup-memory";
1827 dma-names = "tx",
1830 pinctrl-0 = <&qup_i2c14_data_clk>;
1831 pinctrl-names = "default";
1833 #address-cells = <1>;
1834 #size-cells = <0>;
1840 compatible = "qcom,geni-spi";
1846 clock-names = "se";
1854 interconnect-names = "qup-core",
1855 "qup-config",
1856 "qup-memory";
1860 dma-names = "tx",
1863 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1864 pinctrl-names = "default";
1866 #address-cells = <1>;
1867 #size-cells = <0>;
1873 compatible = "qcom,geni-i2c";
1879 clock-names = "se";
1887 interconnect-names = "qup-core",
1888 "qup-config",
1889 "qup-memory";
1893 dma-names = "tx",
1896 pinctrl-0 = <&qup_i2c15_data_clk>;
1897 pinctrl-names = "default";
1899 #address-cells = <1>;
1900 #size-cells = <0>;
1906 compatible = "qcom,geni-spi";
1912 clock-names = "se";
1920 interconnect-names = "qup-core",
1921 "qup-config",
1922 "qup-memory";
1926 dma-names = "tx",
1929 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1930 pinctrl-names = "default";
1932 #address-cells = <1>;
1933 #size-cells = <0>;
1939 gpi_dma0: dma-controller@b00000 {
1940 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
1956 dma-channels = <12>;
1957 dma-channel-mask = <0x3e>;
1958 #dma-cells = <3>;
1966 compatible = "qcom,geni-se-qup";
1971 clock-names = "m-ahb",
1972 "s-ahb";
1975 #address-cells = <2>;
1976 #size-cells = <2>;
1982 compatible = "qcom,geni-i2c";
1988 clock-names = "se";
1996 interconnect-names = "qup-core",
1997 "qup-config",
1998 "qup-memory";
2002 dma-names = "tx",
2005 pinctrl-0 = <&qup_i2c0_data_clk>;
2006 pinctrl-names = "default";
2008 #address-cells = <1>;
2009 #size-cells = <0>;
2015 compatible = "qcom,geni-spi";
2021 clock-names = "se";
2029 interconnect-names = "qup-core",
2030 "qup-config",
2031 "qup-memory";
2035 dma-names = "tx",
2038 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
2039 pinctrl-names = "default";
2041 #address-cells = <1>;
2042 #size-cells = <0>;
2048 compatible = "qcom,geni-i2c";
2054 clock-names = "se";
2062 interconnect-names = "qup-core",
2063 "qup-config",
2064 "qup-memory";
2068 dma-names = "tx",
2071 pinctrl-0 = <&qup_i2c1_data_clk>;
2072 pinctrl-names = "default";
2074 #address-cells = <1>;
2075 #size-cells = <0>;
2081 compatible = "qcom,geni-spi";
2087 clock-names = "se";
2095 interconnect-names = "qup-core",
2096 "qup-config",
2097 "qup-memory";
2101 dma-names = "tx",
2104 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
2105 pinctrl-names = "default";
2107 #address-cells = <1>;
2108 #size-cells = <0>;
2114 compatible = "qcom,geni-i2c";
2120 clock-names = "se";
2128 interconnect-names = "qup-core",
2129 "qup-config",
2130 "qup-memory";
2134 dma-names = "tx",
2137 pinctrl-0 = <&qup_i2c2_data_clk>;
2138 pinctrl-names = "default";
2140 #address-cells = <1>;
2141 #size-cells = <0>;
2147 compatible = "qcom,geni-uart";
2153 clock-names = "se";
2159 interconnect-names = "qup-core",
2160 "qup-config";
2162 pinctrl-0 = <&qup_uart2_default>;
2163 pinctrl-names = "default";
2169 compatible = "qcom,geni-spi";
2175 clock-names = "se";
2183 interconnect-names = "qup-core",
2184 "qup-config",
2185 "qup-memory";
2189 dma-names = "tx",
2192 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
2193 pinctrl-names = "default";
2195 #address-cells = <1>;
2196 #size-cells = <0>;
2202 compatible = "qcom,geni-i2c";
2208 clock-names = "se";
2216 interconnect-names = "qup-core",
2217 "qup-config",
2218 "qup-memory";
2222 dma-names = "tx",
2225 pinctrl-0 = <&qup_i2c3_data_clk>;
2226 pinctrl-names = "default";
2228 #address-cells = <1>;
2229 #size-cells = <0>;
2235 compatible = "qcom,geni-spi";
2241 clock-names = "se";
2249 interconnect-names = "qup-core",
2250 "qup-config",
2251 "qup-memory";
2255 dma-names = "tx",
2258 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
2259 pinctrl-names = "default";
2261 #address-cells = <1>;
2262 #size-cells = <0>;
2268 compatible = "qcom,geni-i2c";
2274 clock-names = "se";
2282 interconnect-names = "qup-core",
2283 "qup-config",
2284 "qup-memory";
2288 dma-names = "tx",
2291 pinctrl-0 = <&qup_i2c4_data_clk>;
2292 pinctrl-names = "default";
2294 #address-cells = <1>;
2295 #size-cells = <0>;
2301 compatible = "qcom,geni-spi";
2307 clock-names = "se";
2315 interconnect-names = "qup-core",
2316 "qup-config",
2317 "qup-memory";
2321 dma-names = "tx",
2324 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
2325 pinctrl-names = "default";
2327 #address-cells = <1>;
2328 #size-cells = <0>;
2334 compatible = "qcom,geni-i2c";
2340 clock-names = "se";
2348 interconnect-names = "qup-core",
2349 "qup-config",
2350 "qup-memory";
2354 dma-names = "tx",
2357 pinctrl-0 = <&qup_i2c5_data_clk>;
2358 pinctrl-names = "default";
2360 #address-cells = <1>;
2361 #size-cells = <0>;
2367 compatible = "qcom,geni-spi";
2373 clock-names = "se";
2381 interconnect-names = "qup-core",
2382 "qup-config",
2383 "qup-memory";
2387 dma-names = "tx",
2390 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
2391 pinctrl-names = "default";
2393 #address-cells = <1>;
2394 #size-cells = <0>;
2400 compatible = "qcom,geni-i2c";
2406 clock-names = "se";
2414 interconnect-names = "qup-core",
2415 "qup-config",
2416 "qup-memory";
2420 dma-names = "tx",
2423 pinctrl-0 = <&qup_i2c6_data_clk>;
2424 pinctrl-names = "default";
2426 #address-cells = <1>;
2427 #size-cells = <0>;
2433 compatible = "qcom,geni-spi";
2439 clock-names = "se";
2447 interconnect-names = "qup-core",
2448 "qup-config",
2449 "qup-memory";
2453 dma-names = "tx",
2456 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
2457 pinctrl-names = "default";
2459 #address-cells = <1>;
2460 #size-cells = <0>;
2466 compatible = "qcom,geni-i2c";
2472 clock-names = "se";
2480 interconnect-names = "qup-core",
2481 "qup-config",
2482 "qup-memory";
2486 dma-names = "tx",
2489 pinctrl-0 = <&qup_i2c7_data_clk>;
2490 pinctrl-names = "default";
2492 #address-cells = <1>;
2493 #size-cells = <0>;
2499 compatible = "qcom,geni-spi";
2505 clock-names = "se";
2513 interconnect-names = "qup-core",
2514 "qup-config",
2515 "qup-memory";
2519 dma-names = "tx",
2522 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
2523 pinctrl-names = "default";
2525 #address-cells = <1>;
2526 #size-cells = <0>;
2532 tsens0: thermal-sensor@c271000 {
2533 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2537 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
2539 interrupt-names = "uplow",
2544 #thermal-sensor-cells = <1>;
2547 tsens1: thermal-sensor@c272000 {
2548 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2552 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
2554 interrupt-names = "uplow",
2559 #thermal-sensor-cells = <1>;
2562 tsens2: thermal-sensor@c273000 {
2563 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2567 interrupts-extended = <&pdc 28 IRQ_TYPE_LEVEL_HIGH>,
2569 interrupt-names = "uplow",
2574 #thermal-sensor-cells = <1>;
2577 tsens3: thermal-sensor@c274000 {
2578 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2582 interrupts-extended = <&pdc 29 IRQ_TYPE_LEVEL_HIGH>,
2584 interrupt-names = "uplow",
2589 #thermal-sensor-cells = <1>;
2593 compatible = "qcom,x1e80100-snps-eusb2-phy",
2594 "qcom,sm8550-snps-eusb2-phy";
2596 #phy-cells = <0>;
2599 clock-names = "ref";
2607 compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
2614 clock-names = "aux",
2619 power-domains = <&gcc GCC_USB_0_PHY_GDSC>;
2623 reset-names = "phy",
2626 #clock-cells = <1>;
2627 #phy-cells = <1>;
2629 orientation-switch;
2634 #address-cells = <1>;
2635 #size-cells = <0>;
2648 remote-endpoint = <&usb_1_ss0_dwc3_ss>;
2656 remote-endpoint = <&mdss_dp0_out>;
2663 compatible = "qcom,x1e80100-snps-eusb2-phy",
2664 "qcom,sm8550-snps-eusb2-phy";
2666 #phy-cells = <0>;
2669 clock-names = "ref";
2677 compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
2684 clock-names = "aux",
2689 power-domains = <&gcc GCC_USB_1_PHY_GDSC>;
2693 reset-names = "phy",
2696 #clock-cells = <1>;
2697 #phy-cells = <1>;
2699 orientation-switch;
2704 #address-cells = <1>;
2705 #size-cells = <0>;
2718 remote-endpoint = <&usb_1_ss1_dwc3_ss>;
2726 remote-endpoint = <&mdss_dp1_out>;
2733 compatible = "qcom,x1e80100-snps-eusb2-phy",
2734 "qcom,sm8550-snps-eusb2-phy";
2736 #phy-cells = <0>;
2739 clock-names = "ref";
2747 compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
2754 clock-names = "aux",
2759 power-domains = <&gcc GCC_USB_2_PHY_GDSC>;
2763 reset-names = "phy",
2766 #clock-cells = <1>;
2767 #phy-cells = <1>;
2769 orientation-switch;
2774 #address-cells = <1>;
2775 #size-cells = <0>;
2788 remote-endpoint = <&usb_1_ss2_dwc3_ss>;
2796 remote-endpoint = <&mdss_dp2_out>;
2803 compatible = "qcom,x1e80100-cnoc-main";
2806 qcom,bcm-voters = <&apps_bcm_voter>;
2808 #interconnect-cells = <2>;
2812 compatible = "qcom,x1e80100-cnoc-cfg";
2815 qcom,bcm-voters = <&apps_bcm_voter>;
2817 #interconnect-cells = <2>;
2821 compatible = "qcom,x1e80100-system-noc";
2824 qcom,bcm-voters = <&apps_bcm_voter>;
2826 #interconnect-cells = <2>;
2830 compatible = "qcom,x1e80100-pcie-south-anoc";
2833 qcom,bcm-voters = <&apps_bcm_voter>;
2835 #interconnect-cells = <2>;
2839 compatible = "qcom,x1e80100-pcie-center-anoc";
2842 qcom,bcm-voters = <&apps_bcm_voter>;
2844 #interconnect-cells = <2>;
2848 compatible = "qcom,x1e80100-aggre1-noc";
2851 qcom,bcm-voters = <&apps_bcm_voter>;
2853 #interconnect-cells = <2>;
2857 compatible = "qcom,x1e80100-aggre2-noc";
2860 qcom,bcm-voters = <&apps_bcm_voter>;
2862 #interconnect-cells = <2>;
2866 compatible = "qcom,x1e80100-pcie-north-anoc";
2869 qcom,bcm-voters = <&apps_bcm_voter>;
2871 #interconnect-cells = <2>;
2875 compatible = "qcom,x1e80100-usb-center-anoc";
2878 qcom,bcm-voters = <&apps_bcm_voter>;
2880 #interconnect-cells = <2>;
2884 compatible = "qcom,x1e80100-usb-north-anoc";
2887 qcom,bcm-voters = <&apps_bcm_voter>;
2889 #interconnect-cells = <2>;
2893 compatible = "qcom,x1e80100-usb-south-anoc";
2896 qcom,bcm-voters = <&apps_bcm_voter>;
2898 #interconnect-cells = <2>;
2902 compatible = "qcom,x1e80100-mmss-noc";
2905 qcom,bcm-voters = <&apps_bcm_voter>;
2907 #interconnect-cells = <2>;
2912 compatible = "qcom,pcie-x1e80100";
2919 reg-names = "parf",
2925 #address-cells = <3>;
2926 #size-cells = <2>;
2929 bus-range = <0 0xff>;
2931 dma-coherent;
2933 linux,pci-domain = <6>;
2934 num-lanes = <2>;
2944 interrupt-names = "msi0",
2953 #interrupt-cells = <1>;
2954 interrupt-map-mask = <0 0 0 0x7>;
2955 interrupt-map = <0 0 0 1 &intc 0 0 0 843 IRQ_TYPE_LEVEL_HIGH>,
2967 clock-names = "aux",
2975 assigned-clocks = <&gcc GCC_PCIE_6A_AUX_CLK>;
2976 assigned-clock-rates = <19200000>;
2982 interconnect-names = "pcie-mem",
2983 "cpu-pcie";
2987 reset-names = "pci",
2990 power-domains = <&gcc GCC_PCIE_6A_GDSC>;
2991 required-opps = <&rpmhpd_opp_nom>;
2994 phy-names = "pciephy";
3000 compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy";
3008 clock-names = "aux",
3016 reset-names = "phy",
3019 assigned-clocks = <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>;
3020 assigned-clock-rates = <100000000>;
3022 power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>;
3024 #clock-cells = <0>;
3025 clock-output-names = "pcie6a_pipe_clk";
3027 #phy-cells = <0>;
3034 compatible = "qcom,pcie-x1e80100";
3041 reg-names = "parf",
3047 #address-cells = <3>;
3048 #size-cells = <2>;
3051 bus-range = <0x00 0xff>;
3053 dma-coherent;
3055 linux,pci-domain = <5>;
3056 num-lanes = <2>;
3066 interrupt-names = "msi0",
3075 #interrupt-cells = <1>;
3076 interrupt-map-mask = <0 0 0 0x7>;
3077 interrupt-map = <0 0 0 1 &intc 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>,
3089 clock-names = "aux",
3097 assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>;
3098 assigned-clock-rates = <19200000>;
3104 interconnect-names = "pcie-mem",
3105 "cpu-pcie";
3109 reset-names = "pci",
3112 power-domains = <&gcc GCC_PCIE_5_GDSC>;
3113 required-opps = <&rpmhpd_opp_nom>;
3116 phy-names = "pciephy";
3122 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy";
3130 clock-names = "aux",
3137 reset-names = "phy";
3139 assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>;
3140 assigned-clock-rates = <100000000>;
3142 power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>;
3144 #clock-cells = <0>;
3145 clock-output-names = "pcie5_pipe_clk";
3147 #phy-cells = <0>;
3154 compatible = "qcom,pcie-x1e80100";
3161 reg-names = "parf",
3167 #address-cells = <3>;
3168 #size-cells = <2>;
3171 bus-range = <0x00 0xff>;
3173 dma-coherent;
3175 linux,pci-domain = <4>;
3176 num-lanes = <2>;
3186 interrupt-names = "msi0",
3195 #interrupt-cells = <1>;
3196 interrupt-map-mask = <0 0 0 0x7>;
3197 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
3209 clock-names = "aux",
3217 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
3218 assigned-clock-rates = <19200000>;
3224 interconnect-names = "pcie-mem",
3225 "cpu-pcie";
3229 reset-names = "pci",
3232 power-domains = <&gcc GCC_PCIE_4_GDSC>;
3233 required-opps = <&rpmhpd_opp_nom>;
3236 phy-names = "pciephy";
3243 bus-range = <0x01 0xff>;
3245 #address-cells = <3>;
3246 #size-cells = <2>;
3252 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy";
3260 clock-names = "aux",
3267 reset-names = "phy";
3269 assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>;
3270 assigned-clock-rates = <100000000>;
3272 power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>;
3274 #clock-cells = <0>;
3275 clock-output-names = "pcie4_pipe_clk";
3277 #phy-cells = <0>;
3283 compatible = "qcom,tcsr-mutex";
3285 #hwlock-cells = <1>;
3288 tcsr: clock-controller@1fc0000 {
3289 compatible = "qcom,x1e80100-tcsr", "syscon";
3292 #clock-cells = <1>;
3293 #reset-cells = <1>;
3297 compatible = "qcom,adreno-43050c01", "qcom,adreno";
3302 reg-names = "kgsl_3d0_reg_memory",
3311 operating-points-v2 = <&gpu_opp_table>;
3314 #cooling-cells = <2>;
3317 interconnect-names = "gfx-mem";
3321 zap-shader {
3322 memory-region = <&gpu_microcode_mem>;
3325 gpu_opp_table: opp-table {
3326 compatible = "operating-points-v2";
3328 opp-1100000000 {
3329 opp-hz = /bits/ 64 <1100000000>;
3330 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3331 opp-peak-kBps = <16500000>;
3334 opp-1000000000 {
3335 opp-hz = /bits/ 64 <1000000000>;
3336 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3337 opp-peak-kBps = <14398438>;
3340 opp-925000000 {
3341 opp-hz = /bits/ 64 <925000000>;
3342 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3343 opp-peak-kBps = <14398438>;
3346 opp-800000000 {
3347 opp-hz = /bits/ 64 <800000000>;
3348 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3349 opp-peak-kBps = <12449219>;
3352 opp-744000000 {
3353 opp-hz = /bits/ 64 <744000000>;
3354 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
3355 opp-peak-kBps = <10687500>;
3358 opp-687000000 {
3359 opp-hz = /bits/ 64 <687000000>;
3360 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3361 opp-peak-kBps = <8171875>;
3364 opp-550000000 {
3365 opp-hz = /bits/ 64 <550000000>;
3366 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3367 opp-peak-kBps = <6074219>;
3370 opp-390000000 {
3371 opp-hz = /bits/ 64 <390000000>;
3372 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3373 opp-peak-kBps = <3000000>;
3376 opp-300000000 {
3377 opp-hz = /bits/ 64 <300000000>;
3378 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
3379 opp-peak-kBps = <2136719>;
3385 compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu";
3389 reg-names = "gmu", "rscc", "gmu_pdc";
3393 interrupt-names = "hfi", "gmu";
3402 clock-names = "ahb",
3410 power-domains = <&gpucc GPU_CX_GDSC>,
3412 power-domain-names = "cx",
3419 operating-points-v2 = <&gmu_opp_table>;
3421 gmu_opp_table: opp-table {
3422 compatible = "operating-points-v2";
3424 opp-550000000 {
3425 opp-hz = /bits/ 64 <550000000>;
3426 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3429 opp-220000000 {
3430 opp-hz = /bits/ 64 <220000000>;
3431 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3436 gpucc: clock-controller@3d90000 {
3437 compatible = "qcom,x1e80100-gpucc";
3442 #clock-cells = <1>;
3443 #reset-cells = <1>;
3444 #power-domain-cells = <1>;
3448 compatible = "qcom,x1e80100-smmu-500", "qcom,adreno-smmu",
3449 "qcom,smmu-500", "arm,mmu-500";
3451 #iommu-cells = <2>;
3452 #global-interrupts = <1>;
3483 clock-names = "hlos",
3487 power-domains = <&gpucc GPU_CX_GDSC>;
3488 dma-coherent;
3492 compatible = "qcom,x1e80100-gem-noc";
3495 qcom,bcm-voters = <&apps_bcm_voter>;
3497 #interconnect-cells = <2>;
3501 compatible = "qcom,x1e80100-nsp-noc";
3504 qcom,bcm-voters = <&apps_bcm_voter>;
3506 #interconnect-cells = <2>;
3510 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
3516 clock-names = "mclk",
3521 #clock-cells = <0>;
3522 clock-output-names = "wsa2-mclk";
3523 #sound-dai-cells = <1>;
3524 sound-name-prefix = "WSA2";
3528 compatible = "qcom,soundwire-v2.0.0";
3531 clock-names = "iface";
3535 pinctrl-0 = <&wsa2_swr_active>;
3536 pinctrl-names = "default";
3538 reset-names = "swr_audio_cgcr";
3540 qcom,din-ports = <4>;
3541 qcom,dout-ports = <9>;
3543 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x3…
3544 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
3545 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3546 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3547 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3548 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
3549 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
3550 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
3551 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
3553 #address-cells = <2>;
3554 #size-cells = <0>;
3555 #sound-dai-cells = <1>;
3560 compatible = "qcom,x1e80100-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro";
3566 clock-names = "mclk",
3571 #clock-cells = <0>;
3572 clock-output-names = "mclk";
3573 #sound-dai-cells = <1>;
3577 compatible = "qcom,soundwire-v2.0.0";
3580 clock-names = "iface";
3584 pinctrl-0 = <&rx_swr_active>;
3585 pinctrl-names = "default";
3588 reset-names = "swr_audio_cgcr";
3589 qcom,din-ports = <1>;
3590 qcom,dout-ports = <11>;
3592 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3593 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3594 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3595 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3596 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3597 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3598 …qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff…
3599 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
3600 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3602 #address-cells = <2>;
3603 #size-cells = <0>;
3604 #sound-dai-cells = <1>;
3609 compatible = "qcom,x1e80100-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro";
3615 clock-names = "mclk",
3620 #clock-cells = <0>;
3621 clock-output-names = "mclk";
3622 #sound-dai-cells = <1>;
3626 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
3632 clock-names = "mclk",
3637 #clock-cells = <0>;
3638 clock-output-names = "mclk";
3639 #sound-dai-cells = <1>;
3640 sound-name-prefix = "WSA";
3644 compatible = "qcom,soundwire-v2.0.0";
3647 clock-names = "iface";
3651 pinctrl-0 = <&wsa_swr_active>;
3652 pinctrl-names = "default";
3654 reset-names = "swr_audio_cgcr";
3656 qcom,din-ports = <4>;
3657 qcom,dout-ports = <9>;
3659 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x3…
3660 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
3661 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3662 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3663 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3664 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
3665 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
3666 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
3667 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
3669 #address-cells = <2>;
3670 #size-cells = <0>;
3671 #sound-dai-cells = <1>;
3675 lpass_audiocc: clock-controller@6b6c000 {
3676 compatible = "qcom,x1e80100-lpassaudiocc", "qcom,sc8280xp-lpassaudiocc";
3678 #clock-cells = <1>;
3679 #reset-cells = <1>;
3683 compatible = "qcom,soundwire-v2.0.0";
3686 clock-names = "iface";
3689 interrupt-names = "core", "wakeup";
3692 reset-names = "swr_audio_cgcr";
3694 pinctrl-0 = <&tx_swr_active>;
3695 pinctrl-names = "default";
3697 qcom,din-ports = <4>;
3698 qcom,dout-ports = <1>;
3700 qcom,ports-sinterval-low = /bits/ 8 <0x00 0x01 0x03 0x03 0x00>;
3701 qcom,ports-offset1 = /bits/ 8 <0x00 0x01 0x02 0x00 0x00>;
3702 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00 0xff>;
3703 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3704 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3705 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3706 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3707 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3708 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x00 0x01 0xff>;
3710 #address-cells = <2>;
3711 #size-cells = <0>;
3712 #sound-dai-cells = <1>;
3717 compatible = "qcom,x1e80100-lpass-va-macro", "qcom,sm8550-lpass-va-macro";
3722 clock-names = "mclk",
3726 #clock-cells = <0>;
3727 clock-output-names = "fsgen";
3728 #sound-dai-cells = <1>;
3732 compatible = "qcom,x1e80100-lpass-lpi-pinctrl", "qcom,sm8550-lpass-lpi-pinctrl";
3738 clock-names = "core", "audio";
3740 gpio-controller;
3741 #gpio-cells = <2>;
3742 gpio-ranges = <&lpass_tlmm 0 0 23>;
3744 tx_swr_active: tx-swr-active-state {
3745 clk-pins {
3748 drive-strength = <2>;
3749 slew-rate = <1>;
3750 bias-disable;
3753 data-pins {
3756 drive-strength = <2>;
3757 slew-rate = <1>;
3758 bias-bus-hold;
3762 rx_swr_active: rx-swr-active-state {
3763 clk-pins {
3766 drive-strength = <2>;
3767 slew-rate = <1>;
3768 bias-disable;
3771 data-pins {
3774 drive-strength = <2>;
3775 slew-rate = <1>;
3776 bias-bus-hold;
3780 dmic01_default: dmic01-default-state {
3781 clk-pins {
3784 drive-strength = <8>;
3785 output-high;
3788 data-pins {
3791 drive-strength = <8>;
3792 input-enable;
3796 dmic23_default: dmic23-default-state {
3797 clk-pins {
3800 drive-strength = <8>;
3801 output-high;
3804 data-pins {
3807 drive-strength = <8>;
3808 input-enable;
3812 wsa_swr_active: wsa-swr-active-state {
3813 clk-pins {
3816 drive-strength = <2>;
3817 slew-rate = <1>;
3818 bias-disable;
3821 data-pins {
3824 drive-strength = <2>;
3825 slew-rate = <1>;
3826 bias-bus-hold;
3830 wsa2_swr_active: wsa2-swr-active-state {
3831 clk-pins {
3834 drive-strength = <2>;
3835 slew-rate = <1>;
3836 bias-disable;
3839 data-pins {
3842 drive-strength = <2>;
3843 slew-rate = <1>;
3844 bias-bus-hold;
3849 lpasscc: clock-controller@6ea0000 {
3850 compatible = "qcom,x1e80100-lpasscc", "qcom,sc8280xp-lpasscc";
3852 #clock-cells = <1>;
3853 #reset-cells = <1>;
3857 compatible = "qcom,x1e80100-lpass-ag-noc";
3860 qcom,bcm-voters = <&apps_bcm_voter>;
3862 #interconnect-cells = <2>;
3866 compatible = "qcom,x1e80100-lpass-lpiaon-noc";
3869 qcom,bcm-voters = <&apps_bcm_voter>;
3871 #interconnect-cells = <2>;
3875 compatible = "qcom,x1e80100-lpass-lpicx-noc";
3878 qcom,bcm-voters = <&apps_bcm_voter>;
3880 #interconnect-cells = <2>;
3884 compatible = "qcom,x1e80100-snps-eusb2-phy",
3885 "qcom,sm8550-snps-eusb2-phy";
3887 #phy-cells = <0>;
3890 clock-names = "ref";
3898 compatible = "qcom,x1e80100-snps-eusb2-phy",
3899 "qcom,sm8550-snps-eusb2-phy";
3901 #phy-cells = <0>;
3904 clock-names = "ref";
3912 compatible = "qcom,x1e80100-snps-eusb2-phy",
3913 "qcom,sm8550-snps-eusb2-phy";
3915 #phy-cells = <0>;
3918 clock-names = "ref";
3926 compatible = "qcom,x1e80100-qmp-usb3-uni-phy";
3933 clock-names = "aux",
3940 reset-names = "phy",
3943 power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>;
3945 #clock-cells = <0>;
3946 clock-output-names = "usb_mp_phy0_pipe_clk";
3948 #phy-cells = <0>;
3954 compatible = "qcom,x1e80100-qmp-usb3-uni-phy";
3961 clock-names = "aux",
3968 reset-names = "phy",
3971 power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>;
3973 #clock-cells = <0>;
3974 clock-output-names = "usb_mp_phy1_pipe_clk";
3976 #phy-cells = <0>;
3982 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
3994 clock-names = "cfg_noc",
4004 assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>,
4006 assigned-clock-rates = <19200000>,
4009 interrupts-extended = <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
4013 interrupt-names = "pwr_event",
4018 power-domains = <&gcc GCC_USB30_TERT_GDSC>;
4019 required-opps = <&rpmhpd_opp_nom>;
4027 interconnect-names = "usb-ddr",
4028 "apps-usb";
4030 wakeup-source;
4032 #address-cells = <2>;
4033 #size-cells = <2>;
4048 phy-names = "usb2-phy",
4049 "usb3-phy";
4055 dma-coherent;
4058 #address-cells = <1>;
4059 #size-cells = <0>;
4072 remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>;
4080 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
4082 #address-cells = <2>;
4083 #size-cells = <2>;
4095 clock-names = "cfg_noc",
4105 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
4107 assigned-clock-rates = <19200000>, <200000000>;
4109 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4112 interrupt-names = "pwr_event",
4116 power-domains = <&gcc GCC_USB20_PRIM_GDSC>;
4117 required-opps = <&rpmhpd_opp_nom>;
4125 interconnect-names = "usb-ddr",
4126 "apps-usb";
4128 wakeup-source;
4138 phy-names = "usb2-phy";
4139 maximum-speed = "high-speed";
4142 #address-cells = <1>;
4143 #size-cells = <0>;
4156 compatible = "qcom,x1e80100-dwc3-mp", "qcom,dwc3";
4168 clock-names = "cfg_noc",
4178 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
4180 assigned-clock-rates = <19200000>,
4183 interrupts-extended = <&intc GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
4193 interrupt-names = "pwr_event_1", "pwr_event_2",
4199 power-domains = <&gcc GCC_USB30_MP_GDSC>;
4200 required-opps = <&rpmhpd_opp_nom>;
4208 interconnect-names = "usb-ddr",
4209 "apps-usb";
4211 wakeup-source;
4213 #address-cells = <2>;
4214 #size-cells = <2>;
4229 phy-names = "usb2-0", "usb3-0",
4230 "usb2-1", "usb3-1";
4237 dma-coherent;
4242 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
4254 clock-names = "cfg_noc",
4264 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4266 assigned-clock-rates = <19200000>,
4269 interrupts-extended = <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
4273 interrupt-names = "pwr_event",
4278 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
4279 required-opps = <&rpmhpd_opp_nom>;
4283 wakeup-source;
4285 #address-cells = <2>;
4286 #size-cells = <2>;
4301 phy-names = "usb2-phy",
4302 "usb3-phy";
4308 dma-coherent;
4311 #address-cells = <1>;
4312 #size-cells = <0>;
4325 remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>;
4333 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
4345 clock-names = "cfg_noc",
4355 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4357 assigned-clock-rates = <19200000>,
4360 interrupts-extended = <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
4364 interrupt-names = "pwr_event",
4369 power-domains = <&gcc GCC_USB30_SEC_GDSC>;
4370 required-opps = <&rpmhpd_opp_nom>;
4378 interconnect-names = "usb-ddr",
4379 "apps-usb";
4381 wakeup-source;
4383 #address-cells = <2>;
4384 #size-cells = <2>;
4399 phy-names = "usb2-phy",
4400 "usb3-phy";
4406 dma-coherent;
4409 #address-cells = <1>;
4410 #size-cells = <0>;
4423 remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>;
4430 mdss: display-subsystem@ae00000 {
4431 compatible = "qcom,x1e80100-mdss";
4433 reg-names = "mdss";
4449 interconnect-names = "mdp0-mem",
4450 "mdp1-mem",
4451 "cpu-cfg";
4453 power-domains = <&dispcc MDSS_GDSC>;
4457 interrupt-controller;
4458 #interrupt-cells = <1>;
4460 #address-cells = <2>;
4461 #size-cells = <2>;
4466 mdss_mdp: display-controller@ae01000 {
4467 compatible = "qcom,x1e80100-dpu";
4470 reg-names = "mdp",
4473 interrupts-extended = <&mdss 0>;
4480 clock-names = "nrt_bus",
4486 operating-points-v2 = <&mdp_opp_table>;
4488 power-domains = <&rpmhpd RPMHPD_MMCX>;
4491 #address-cells = <1>;
4492 #size-cells = <0>;
4498 remote-endpoint = <&mdss_dp0_in>;
4506 remote-endpoint = <&mdss_dp1_in>;
4514 remote-endpoint = <&mdss_dp3_in>;
4522 remote-endpoint = <&mdss_dp2_in>;
4527 mdp_opp_table: opp-table {
4528 compatible = "operating-points-v2";
4530 opp-200000000 {
4531 opp-hz = /bits/ 64 <200000000>;
4532 required-opps = <&rpmhpd_opp_low_svs>;
4535 opp-325000000 {
4536 opp-hz = /bits/ 64 <325000000>;
4537 required-opps = <&rpmhpd_opp_svs>;
4540 opp-375000000 {
4541 opp-hz = /bits/ 64 <375000000>;
4542 required-opps = <&rpmhpd_opp_svs_l1>;
4545 opp-514000000 {
4546 opp-hz = /bits/ 64 <514000000>;
4547 required-opps = <&rpmhpd_opp_nom>;
4550 opp-575000000 {
4551 opp-hz = /bits/ 64 <575000000>;
4552 required-opps = <&rpmhpd_opp_nom_l1>;
4557 mdss_dp0: displayport-controller@ae90000 {
4558 compatible = "qcom,x1e80100-dp";
4565 interrupts-extended = <&mdss 12>;
4572 clock-names = "core_iface",
4578 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
4580 assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4583 operating-points-v2 = <&mdss_dp0_opp_table>;
4585 power-domains = <&rpmhpd RPMHPD_MMCX>;
4588 phy-names = "dp";
4590 #sound-dai-cells = <0>;
4595 #address-cells = <1>;
4596 #size-cells = <0>;
4602 remote-endpoint = <&mdss_intf0_out>;
4610 remote-endpoint = <&usb_1_ss0_qmpphy_dp_in>;
4615 mdss_dp0_opp_table: opp-table {
4616 compatible = "operating-points-v2";
4618 opp-160000000 {
4619 opp-hz = /bits/ 64 <160000000>;
4620 required-opps = <&rpmhpd_opp_low_svs>;
4623 opp-270000000 {
4624 opp-hz = /bits/ 64 <270000000>;
4625 required-opps = <&rpmhpd_opp_svs>;
4628 opp-540000000 {
4629 opp-hz = /bits/ 64 <540000000>;
4630 required-opps = <&rpmhpd_opp_svs_l1>;
4633 opp-810000000 {
4634 opp-hz = /bits/ 64 <810000000>;
4635 required-opps = <&rpmhpd_opp_nom>;
4640 mdss_dp1: displayport-controller@ae98000 {
4641 compatible = "qcom,x1e80100-dp";
4648 interrupts-extended = <&mdss 13>;
4655 clock-names = "core_iface",
4661 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
4663 assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4666 operating-points-v2 = <&mdss_dp1_opp_table>;
4668 power-domains = <&rpmhpd RPMHPD_MMCX>;
4671 phy-names = "dp";
4673 #sound-dai-cells = <0>;
4678 #address-cells = <1>;
4679 #size-cells = <0>;
4685 remote-endpoint = <&mdss_intf4_out>;
4693 remote-endpoint = <&usb_1_ss1_qmpphy_dp_in>;
4698 mdss_dp1_opp_table: opp-table {
4699 compatible = "operating-points-v2";
4701 opp-160000000 {
4702 opp-hz = /bits/ 64 <160000000>;
4703 required-opps = <&rpmhpd_opp_low_svs>;
4706 opp-270000000 {
4707 opp-hz = /bits/ 64 <270000000>;
4708 required-opps = <&rpmhpd_opp_svs>;
4711 opp-540000000 {
4712 opp-hz = /bits/ 64 <540000000>;
4713 required-opps = <&rpmhpd_opp_svs_l1>;
4716 opp-810000000 {
4717 opp-hz = /bits/ 64 <810000000>;
4718 required-opps = <&rpmhpd_opp_nom>;
4723 mdss_dp2: displayport-controller@ae9a000 {
4724 compatible = "qcom,x1e80100-dp";
4731 interrupts-extended = <&mdss 14>;
4738 clock-names = "core_iface",
4744 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
4746 assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4749 operating-points-v2 = <&mdss_dp2_opp_table>;
4751 power-domains = <&rpmhpd RPMHPD_MMCX>;
4754 phy-names = "dp";
4756 #sound-dai-cells = <0>;
4761 #address-cells = <1>;
4762 #size-cells = <0>;
4767 remote-endpoint = <&mdss_intf6_out>;
4775 remote-endpoint = <&usb_1_ss2_qmpphy_dp_in>;
4780 mdss_dp2_opp_table: opp-table {
4781 compatible = "operating-points-v2";
4783 opp-160000000 {
4784 opp-hz = /bits/ 64 <160000000>;
4785 required-opps = <&rpmhpd_opp_low_svs>;
4788 opp-270000000 {
4789 opp-hz = /bits/ 64 <270000000>;
4790 required-opps = <&rpmhpd_opp_svs>;
4793 opp-540000000 {
4794 opp-hz = /bits/ 64 <540000000>;
4795 required-opps = <&rpmhpd_opp_svs_l1>;
4798 opp-810000000 {
4799 opp-hz = /bits/ 64 <810000000>;
4800 required-opps = <&rpmhpd_opp_nom>;
4805 mdss_dp3: displayport-controller@aea0000 {
4806 compatible = "qcom,x1e80100-dp";
4813 interrupts-extended = <&mdss 15>;
4820 clock-names = "core_iface",
4826 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
4828 assigned-clock-parents = <&mdss_dp3_phy 0>,
4831 operating-points-v2 = <&mdss_dp3_opp_table>;
4833 power-domains = <&rpmhpd RPMHPD_MMCX>;
4836 phy-names = "dp";
4838 #sound-dai-cells = <0>;
4843 #address-cells = <1>;
4844 #size-cells = <0>;
4850 remote-endpoint = <&mdss_intf5_out>;
4859 mdss_dp3_opp_table: opp-table {
4860 compatible = "operating-points-v2";
4862 opp-160000000 {
4863 opp-hz = /bits/ 64 <160000000>;
4864 required-opps = <&rpmhpd_opp_low_svs>;
4867 opp-270000000 {
4868 opp-hz = /bits/ 64 <270000000>;
4869 required-opps = <&rpmhpd_opp_svs>;
4872 opp-540000000 {
4873 opp-hz = /bits/ 64 <540000000>;
4874 required-opps = <&rpmhpd_opp_svs_l1>;
4877 opp-810000000 {
4878 opp-hz = /bits/ 64 <810000000>;
4879 required-opps = <&rpmhpd_opp_nom>;
4887 compatible = "qcom,x1e80100-dp-phy";
4895 clock-names = "aux",
4898 power-domains = <&rpmhpd RPMHPD_MX>;
4900 #clock-cells = <1>;
4901 #phy-cells = <0>;
4907 compatible = "qcom,x1e80100-dp-phy";
4915 clock-names = "aux",
4918 power-domains = <&rpmhpd RPMHPD_MX>;
4920 #clock-cells = <1>;
4921 #phy-cells = <0>;
4926 dispcc: clock-controller@af00000 {
4927 compatible = "qcom,x1e80100-dispcc";
4945 power-domains = <&rpmhpd RPMHPD_MMCX>;
4946 required-opps = <&rpmhpd_opp_low_svs>;
4947 #clock-cells = <1>;
4948 #reset-cells = <1>;
4949 #power-domain-cells = <1>;
4952 pdc: interrupt-controller@b220000 {
4953 compatible = "qcom,x1e80100-pdc", "qcom,pdc";
4956 qcom,pdc-ranges = <0 480 42>, <42 251 5>,
4959 #interrupt-cells = <2>;
4960 interrupt-parent = <&intc>;
4961 interrupt-controller;
4964 aoss_qmp: power-management@c300000 {
4965 compatible = "qcom,x1e80100-aoss-qmp", "qcom,aoss-qmp";
4967 interrupt-parent = <&ipcc>;
4968 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
4972 #clock-cells = <0>;
4976 compatible = "qcom,rpmh-stats";
4981 compatible = "qcom,x1e80100-spmi-pmic-arb";
4985 reg-names = "core", "chnls", "obsrvr";
4990 #address-cells = <2>;
4991 #size-cells = <2>;
4997 reg-names = "cnfg", "intr";
4999 interrupt-names = "periph_irq";
5000 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5001 interrupt-controller;
5002 #interrupt-cells = <4>;
5004 #address-cells = <2>;
5005 #size-cells = <0>;
5011 reg-names = "cnfg", "intr";
5013 interrupt-names = "periph_irq";
5014 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
5015 interrupt-controller;
5016 #interrupt-cells = <4>;
5018 #address-cells = <2>;
5019 #size-cells = <0>;
5024 compatible = "qcom,x1e80100-tlmm";
5029 gpio-controller;
5030 #gpio-cells = <2>;
5032 interrupt-controller;
5033 #interrupt-cells = <2>;
5035 gpio-ranges = <&tlmm 0 0 239>;
5036 wakeup-parent = <&pdc>;
5038 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
5042 drive-strength = <2>;
5043 bias-pull-up = <2200>;
5046 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
5050 drive-strength = <2>;
5051 bias-pull-up = <2200>;
5054 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
5058 drive-strength = <2>;
5059 bias-pull-up = <2200>;
5062 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
5066 drive-strength = <2>;
5067 bias-pull-up = <2200>;
5070 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
5074 drive-strength = <2>;
5075 bias-pull-up = <2200>;
5078 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
5082 drive-strength = <2>;
5083 bias-pull-up = <2200>;
5086 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
5090 drive-strength = <2>;
5091 bias-pull-up = <2200>;
5094 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
5098 drive-strength = <2>;
5099 bias-pull-up = <2200>;
5102 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
5106 drive-strength = <2>;
5107 bias-pull-up = <2200>;
5110 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
5114 drive-strength = <2>;
5115 bias-pull-up = <2200>;
5118 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
5122 drive-strength = <2>;
5123 bias-pull-up = <2200>;
5126 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
5130 drive-strength = <2>;
5131 bias-pull-up = <2200>;
5134 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
5138 drive-strength = <2>;
5139 bias-pull-up = <2200>;
5142 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
5146 drive-strength = <2>;
5147 bias-pull-up = <2200>;
5150 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
5154 drive-strength = <2>;
5155 bias-pull-up = <2200>;
5158 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
5162 drive-strength = <2>;
5163 bias-pull-up = <2200>;
5166 qup_i2c16_data_clk: qup-i2c16-data-clk-state {
5170 drive-strength = <2>;
5171 bias-pull-up = <2200>;
5174 qup_i2c17_data_clk: qup-i2c17-data-clk-state {
5178 drive-strength = <2>;
5179 bias-pull-up = <2200>;
5182 qup_i2c18_data_clk: qup-i2c18-data-clk-state {
5186 drive-strength = <2>;
5187 bias-pull-up = <2200>;
5190 qup_i2c19_data_clk: qup-i2c19-data-clk-state {
5194 drive-strength = <2>;
5195 bias-pull-up = <2200>;
5198 qup_i2c20_data_clk: qup-i2c20-data-clk-state {
5202 drive-strength = <2>;
5203 bias-pull-up = <2200>;
5206 qup_i2c21_data_clk: qup-i2c21-data-clk-state {
5210 drive-strength = <2>;
5211 bias-pull-up = <2200>;
5214 qup_i2c22_data_clk: qup-i2c22-data-clk-state {
5218 drive-strength = <2>;
5219 bias-pull-up = <2200>;
5222 qup_i2c23_data_clk: qup-i2c23-data-clk-state {
5226 drive-strength = <2>;
5227 bias-pull-up = <2200>;
5230 qup_spi0_cs: qup-spi0-cs-state {
5233 drive-strength = <6>;
5234 bias-disable;
5237 qup_spi0_data_clk: qup-spi0-data-clk-state {
5241 drive-strength = <6>;
5242 bias-disable;
5245 qup_spi1_cs: qup-spi1-cs-state {
5248 drive-strength = <6>;
5249 bias-disable;
5252 qup_spi1_data_clk: qup-spi1-data-clk-state {
5256 drive-strength = <6>;
5257 bias-disable;
5260 qup_spi2_cs: qup-spi2-cs-state {
5263 drive-strength = <6>;
5264 bias-disable;
5267 qup_spi2_data_clk: qup-spi2-data-clk-state {
5271 drive-strength = <6>;
5272 bias-disable;
5275 qup_spi3_cs: qup-spi3-cs-state {
5278 drive-strength = <6>;
5279 bias-disable;
5282 qup_spi3_data_clk: qup-spi3-data-clk-state {
5286 drive-strength = <6>;
5287 bias-disable;
5290 qup_spi4_cs: qup-spi4-cs-state {
5293 drive-strength = <6>;
5294 bias-disable;
5297 qup_spi4_data_clk: qup-spi4-data-clk-state {
5301 drive-strength = <6>;
5302 bias-disable;
5305 qup_spi5_cs: qup-spi5-cs-state {
5308 drive-strength = <6>;
5309 bias-disable;
5312 qup_spi5_data_clk: qup-spi5-data-clk-state {
5316 drive-strength = <6>;
5317 bias-disable;
5320 qup_spi6_cs: qup-spi6-cs-state {
5323 drive-strength = <6>;
5324 bias-disable;
5327 qup_spi6_data_clk: qup-spi6-data-clk-state {
5331 drive-strength = <6>;
5332 bias-disable;
5335 qup_spi7_cs: qup-spi7-cs-state {
5338 drive-strength = <6>;
5339 bias-disable;
5342 qup_spi7_data_clk: qup-spi7-data-clk-state {
5346 drive-strength = <6>;
5347 bias-disable;
5350 qup_spi8_cs: qup-spi8-cs-state {
5353 drive-strength = <6>;
5354 bias-disable;
5357 qup_spi8_data_clk: qup-spi8-data-clk-state {
5361 drive-strength = <6>;
5362 bias-disable;
5365 qup_spi9_cs: qup-spi9-cs-state {
5368 drive-strength = <6>;
5369 bias-disable;
5372 qup_spi9_data_clk: qup-spi9-data-clk-state {
5376 drive-strength = <6>;
5377 bias-disable;
5380 qup_spi10_cs: qup-spi10-cs-state {
5383 drive-strength = <6>;
5384 bias-disable;
5387 qup_spi10_data_clk: qup-spi10-data-clk-state {
5391 drive-strength = <6>;
5392 bias-disable;
5395 qup_spi11_cs: qup-spi11-cs-state {
5398 drive-strength = <6>;
5399 bias-disable;
5402 qup_spi11_data_clk: qup-spi11-data-clk-state {
5406 drive-strength = <6>;
5407 bias-disable;
5410 qup_spi12_cs: qup-spi12-cs-state {
5413 drive-strength = <6>;
5414 bias-disable;
5417 qup_spi12_data_clk: qup-spi12-data-clk-state {
5421 drive-strength = <6>;
5422 bias-disable;
5425 qup_spi13_cs: qup-spi13-cs-state {
5428 drive-strength = <6>;
5429 bias-disable;
5432 qup_spi13_data_clk: qup-spi13-data-clk-state {
5436 drive-strength = <6>;
5437 bias-disable;
5440 qup_spi14_cs: qup-spi14-cs-state {
5443 drive-strength = <6>;
5444 bias-disable;
5447 qup_spi14_data_clk: qup-spi14-data-clk-state {
5451 drive-strength = <6>;
5452 bias-disable;
5455 qup_spi15_cs: qup-spi15-cs-state {
5458 drive-strength = <6>;
5459 bias-disable;
5462 qup_spi15_data_clk: qup-spi15-data-clk-state {
5466 drive-strength = <6>;
5467 bias-disable;
5470 qup_spi16_cs: qup-spi16-cs-state {
5473 drive-strength = <6>;
5474 bias-disable;
5477 qup_spi16_data_clk: qup-spi16-data-clk-state {
5481 drive-strength = <6>;
5482 bias-disable;
5485 qup_spi17_cs: qup-spi17-cs-state {
5488 drive-strength = <6>;
5489 bias-disable;
5492 qup_spi17_data_clk: qup-spi17-data-clk-state {
5496 drive-strength = <6>;
5497 bias-disable;
5500 qup_spi18_cs: qup-spi18-cs-state {
5503 drive-strength = <6>;
5504 bias-disable;
5507 qup_spi18_data_clk: qup-spi18-data-clk-state {
5511 drive-strength = <6>;
5512 bias-disable;
5515 qup_spi19_cs: qup-spi19-cs-state {
5518 drive-strength = <6>;
5519 bias-disable;
5522 qup_spi19_data_clk: qup-spi19-data-clk-state {
5526 drive-strength = <6>;
5527 bias-disable;
5530 qup_spi20_cs: qup-spi20-cs-state {
5533 drive-strength = <6>;
5534 bias-disable;
5537 qup_spi20_data_clk: qup-spi20-data-clk-state {
5541 drive-strength = <6>;
5542 bias-disable;
5545 qup_spi21_cs: qup-spi21-cs-state {
5548 drive-strength = <6>;
5549 bias-disable;
5552 qup_spi21_data_clk: qup-spi21-data-clk-state {
5556 drive-strength = <6>;
5557 bias-disable;
5560 qup_spi22_cs: qup-spi22-cs-state {
5563 drive-strength = <6>;
5564 bias-disable;
5567 qup_spi22_data_clk: qup-spi22-data-clk-state {
5571 drive-strength = <6>;
5572 bias-disable;
5575 qup_spi23_cs: qup-spi23-cs-state {
5578 drive-strength = <6>;
5579 bias-disable;
5582 qup_spi23_data_clk: qup-spi23-data-clk-state {
5586 drive-strength = <6>;
5587 bias-disable;
5590 qup_uart2_default: qup-uart2-default-state {
5591 cts-pins {
5594 drive-strength = <2>;
5595 bias-disable;
5598 rts-pins {
5601 drive-strength = <2>;
5602 bias-disable;
5605 tx-pins {
5608 drive-strength = <2>;
5609 bias-disable;
5612 rx-pins {
5615 drive-strength = <2>;
5616 bias-disable;
5620 qup_uart21_default: qup-uart21-default-state {
5621 tx-pins {
5624 drive-strength = <2>;
5625 bias-disable;
5628 rx-pins {
5631 drive-strength = <2>;
5632 bias-disable;
5638 compatible = "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500";
5739 #iommu-cells = <2>;
5740 #global-interrupts = <1>;
5743 intc: interrupt-controller@17000000 {
5744 compatible = "arm,gic-v3";
5750 #interrupt-cells = <3>;
5751 interrupt-controller;
5753 #redistributor-regions = <1>;
5754 redistributor-stride = <0x0 0x40000>;
5756 #address-cells = <2>;
5757 #size-cells = <2>;
5760 gic_its: msi-controller@17040000 {
5761 compatible = "arm,gic-v3-its";
5764 msi-controller;
5765 #msi-cells = <1>;
5772 compatible = "qcom,rpmh-rsc";
5776 reg-names = "drv-0", "drv-1", "drv-2";
5781 qcom,tcs-offset = <0xd00>;
5782 qcom,drv-id = <2>;
5783 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
5787 power-domains = <&SYSTEM_PD>;
5789 apps_bcm_voter: bcm-voter {
5790 compatible = "qcom,bcm-voter";
5793 rpmhcc: clock-controller {
5794 compatible = "qcom,x1e80100-rpmh-clk";
5797 clock-names = "xo";
5799 #clock-cells = <1>;
5802 rpmhpd: power-controller {
5803 compatible = "qcom,x1e80100-rpmhpd";
5805 operating-points-v2 = <&rpmhpd_opp_table>;
5807 #power-domain-cells = <1>;
5809 rpmhpd_opp_table: opp-table {
5810 compatible = "operating-points-v2";
5812 rpmhpd_opp_ret: opp-16 {
5813 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5816 rpmhpd_opp_min_svs: opp-48 {
5817 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5820 rpmhpd_opp_low_svs_d2: opp-52 {
5821 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
5824 rpmhpd_opp_low_svs_d1: opp-56 {
5825 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
5828 rpmhpd_opp_low_svs_d0: opp-60 {
5829 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
5832 rpmhpd_opp_low_svs: opp-64 {
5833 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5836 rpmhpd_opp_low_svs_l1: opp-80 {
5837 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
5840 rpmhpd_opp_svs: opp-128 {
5841 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5844 rpmhpd_opp_svs_l0: opp-144 {
5845 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
5848 rpmhpd_opp_svs_l1: opp-192 {
5849 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5852 rpmhpd_opp_nom: opp-256 {
5853 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5856 rpmhpd_opp_nom_l1: opp-320 {
5857 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5860 rpmhpd_opp_nom_l2: opp-336 {
5861 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5864 rpmhpd_opp_turbo: opp-384 {
5865 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5868 rpmhpd_opp_turbo_l1: opp-416 {
5869 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5876 compatible = "arm,armv7-timer-mem";
5879 #address-cells = <2>;
5880 #size-cells = <1>;
5890 frame-number = <0>;
5898 frame-number = <1>;
5908 frame-number = <2>;
5918 frame-number = <3>;
5928 frame-number = <4>;
5938 frame-number = <5>;
5948 frame-number = <6>;
5955 compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
5963 operating-points-v2 = <&llcc_bwmon_opp_table>;
5965 llcc_bwmon_opp_table: opp-table {
5966 compatible = "operating-points-v2";
5968 opp-0 {
5969 opp-peak-kBps = <800000>;
5972 opp-1 {
5973 opp-peak-kBps = <2188000>;
5976 opp-2 {
5977 opp-peak-kBps = <3072000>;
5980 opp-3 {
5981 opp-peak-kBps = <6220800>;
5984 opp-4 {
5985 opp-peak-kBps = <6835200>;
5988 opp-5 {
5989 opp-peak-kBps = <8371200>;
5992 opp-6 {
5993 opp-peak-kBps = <10944000>;
5996 opp-7 {
5997 opp-peak-kBps = <12748800>;
6000 opp-8 {
6001 opp-peak-kBps = <14745600>;
6004 opp-9 {
6005 opp-peak-kBps = <16896000>;
6012 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
6020 operating-points-v2 = <&cpu_bwmon_opp_table>;
6022 cpu_bwmon_opp_table: opp-table {
6023 compatible = "operating-points-v2";
6025 opp-0 {
6026 opp-peak-kBps = <4800000>;
6029 opp-1 {
6030 opp-peak-kBps = <7464000>;
6033 opp-2 {
6034 opp-peak-kBps = <9600000>;
6037 opp-3 {
6038 opp-peak-kBps = <12896000>;
6041 opp-4 {
6042 opp-peak-kBps = <14928000>;
6045 opp-5 {
6046 opp-peak-kBps = <17064000>;
6053 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
6061 operating-points-v2 = <&cpu_bwmon_opp_table>;
6066 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
6074 operating-points-v2 = <&cpu_bwmon_opp_table>;
6077 system-cache-controller@25000000 {
6078 compatible = "qcom,x1e80100-llcc";
6088 reg-names = "llcc0_base",
6101 compatible = "qcom,x1e80100-adsp-pas";
6104 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
6109 interrupt-names = "wdog",
6113 "stop-ack";
6116 clock-names = "xo";
6118 power-domains = <&rpmhpd RPMHPD_LCX>,
6120 power-domain-names = "lcx",
6126 memory-region = <&adspslpi_mem>,
6131 qcom,smem-states = <&smp2p_adsp_out 0>;
6132 qcom,smem-state-names = "stop";
6136 glink-edge {
6137 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
6144 qcom,remote-pid = <2>;
6148 qcom,glink-channels = "fastrpcglink-apps-dsp";
6150 qcom,non-secure-domain;
6151 #address-cells = <1>;
6152 #size-cells = <0>;
6154 compute-cb@3 {
6155 compatible = "qcom,fastrpc-compute-cb";
6159 dma-coherent;
6162 compute-cb@4 {
6163 compatible = "qcom,fastrpc-compute-cb";
6167 dma-coherent;
6170 compute-cb@5 {
6171 compatible = "qcom,fastrpc-compute-cb";
6175 dma-coherent;
6178 compute-cb@6 {
6179 compatible = "qcom,fastrpc-compute-cb";
6183 dma-coherent;
6186 compute-cb@7 {
6187 compatible = "qcom,fastrpc-compute-cb";
6191 dma-coherent;
6197 qcom,glink-channels = "adsp_apps";
6200 #address-cells = <1>;
6201 #size-cells = <0>;
6206 #sound-dai-cells = <0>;
6207 qcom,protection-domain = "avs/audio",
6211 compatible = "qcom,q6apm-lpass-dais";
6212 #sound-dai-cells = <1>;
6216 compatible = "qcom,q6apm-dais";
6225 qcom,protection-domain = "avs/audio",
6228 q6prmcc: clock-controller {
6229 compatible = "qcom,q6prm-lpass-clocks";
6230 #clock-cells = <2>;
6238 compatible = "qcom,x1e80100-cdsp-pas";
6241 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
6246 interrupt-names = "wdog",
6250 "stop-ack";
6253 clock-names = "xo";
6255 power-domains = <&rpmhpd RPMHPD_CX>,
6258 power-domain-names = "cx",
6265 memory-region = <&cdsp_mem>,
6270 qcom,smem-states = <&smp2p_cdsp_out 0>;
6271 qcom,smem-state-names = "stop";
6275 glink-edge {
6276 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
6283 qcom,remote-pid = <5>;
6287 qcom,glink-channels = "fastrpcglink-apps-dsp";
6289 qcom,non-secure-domain;
6290 #address-cells = <1>;
6291 #size-cells = <0>;
6293 compute-cb@1 {
6294 compatible = "qcom,fastrpc-compute-cb";
6297 dma-coherent;
6300 compute-cb@2 {
6301 compatible = "qcom,fastrpc-compute-cb";
6304 dma-coherent;
6307 compute-cb@3 {
6308 compatible = "qcom,fastrpc-compute-cb";
6311 dma-coherent;
6314 compute-cb@4 {
6315 compatible = "qcom,fastrpc-compute-cb";
6318 dma-coherent;
6321 compute-cb@5 {
6322 compatible = "qcom,fastrpc-compute-cb";
6325 dma-coherent;
6328 compute-cb@6 {
6329 compatible = "qcom,fastrpc-compute-cb";
6332 dma-coherent;
6335 compute-cb@7 {
6336 compatible = "qcom,fastrpc-compute-cb";
6339 dma-coherent;
6342 compute-cb@8 {
6343 compatible = "qcom,fastrpc-compute-cb";
6346 dma-coherent;
6349 /* note: compute-cb@9 is secure */
6351 compute-cb@10 {
6352 compatible = "qcom,fastrpc-compute-cb";
6355 dma-coherent;
6358 compute-cb@11 {
6359 compatible = "qcom,fastrpc-compute-cb";
6362 dma-coherent;
6365 compute-cb@12 {
6366 compatible = "qcom,fastrpc-compute-cb";
6369 dma-coherent;
6372 compute-cb@13 {
6373 compatible = "qcom,fastrpc-compute-cb";
6376 dma-coherent;
6384 compatible = "arm,armv8-timer";
6392 thermal-zones {
6393 aoss0-thermal {
6394 thermal-sensors = <&tsens0 0>;
6397 trip-point0 {
6403 aoss0-critical {
6411 cpu0-0-top-thermal {
6412 polling-delay-passive = <250>;
6414 thermal-sensors = <&tsens0 1>;
6417 trip-point0 {
6423 trip-point1 {
6429 cpu-critical {
6437 cpu0-0-btm-thermal {
6438 polling-delay-passive = <250>;
6440 thermal-sensors = <&tsens0 2>;
6443 trip-point0 {
6449 trip-point1 {
6455 cpu-critical {
6463 cpu0-1-top-thermal {
6464 polling-delay-passive = <250>;
6466 thermal-sensors = <&tsens0 3>;
6469 trip-point0 {
6475 trip-point1 {
6481 cpu-critical {
6489 cpu0-1-btm-thermal {
6490 polling-delay-passive = <250>;
6492 thermal-sensors = <&tsens0 4>;
6495 trip-point0 {
6501 trip-point1 {
6507 cpu-critical {
6515 cpu0-2-top-thermal {
6516 polling-delay-passive = <250>;
6518 thermal-sensors = <&tsens0 5>;
6521 trip-point0 {
6527 trip-point1 {
6533 cpu-critical {
6541 cpu0-2-btm-thermal {
6542 polling-delay-passive = <250>;
6544 thermal-sensors = <&tsens0 6>;
6547 trip-point0 {
6553 trip-point1 {
6559 cpu-critical {
6567 cpu0-3-top-thermal {
6568 polling-delay-passive = <250>;
6570 thermal-sensors = <&tsens0 7>;
6573 trip-point0 {
6579 trip-point1 {
6585 cpu-critical {
6593 cpu0-3-btm-thermal {
6594 polling-delay-passive = <250>;
6596 thermal-sensors = <&tsens0 8>;
6599 trip-point0 {
6605 trip-point1 {
6611 cpu-critical {
6619 cpuss0-top-thermal {
6620 thermal-sensors = <&tsens0 9>;
6623 trip-point0 {
6629 cpuss2-critical {
6637 cpuss0-btm-thermal {
6638 thermal-sensors = <&tsens0 10>;
6641 trip-point0 {
6647 cpuss2-critical {
6655 mem-thermal {
6656 thermal-sensors = <&tsens0 11>;
6659 trip-point0 {
6665 mem-critical {
6673 video-thermal {
6674 polling-delay-passive = <250>;
6676 thermal-sensors = <&tsens0 12>;
6679 trip-point0 {
6687 aoss1-thermal {
6688 thermal-sensors = <&tsens1 0>;
6691 trip-point0 {
6697 aoss0-critical {
6705 cpu1-0-top-thermal {
6706 polling-delay-passive = <250>;
6708 thermal-sensors = <&tsens1 1>;
6711 trip-point0 {
6717 trip-point1 {
6723 cpu-critical {
6731 cpu1-0-btm-thermal {
6732 polling-delay-passive = <250>;
6734 thermal-sensors = <&tsens1 2>;
6737 trip-point0 {
6743 trip-point1 {
6749 cpu-critical {
6757 cpu1-1-top-thermal {
6758 polling-delay-passive = <250>;
6760 thermal-sensors = <&tsens1 3>;
6763 trip-point0 {
6769 trip-point1 {
6775 cpu-critical {
6783 cpu1-1-btm-thermal {
6784 polling-delay-passive = <250>;
6786 thermal-sensors = <&tsens1 4>;
6789 trip-point0 {
6795 trip-point1 {
6801 cpu-critical {
6809 cpu1-2-top-thermal {
6810 polling-delay-passive = <250>;
6812 thermal-sensors = <&tsens1 5>;
6815 trip-point0 {
6821 trip-point1 {
6827 cpu-critical {
6835 cpu1-2-btm-thermal {
6836 polling-delay-passive = <250>;
6838 thermal-sensors = <&tsens1 6>;
6841 trip-point0 {
6847 trip-point1 {
6853 cpu-critical {
6861 cpu1-3-top-thermal {
6862 polling-delay-passive = <250>;
6864 thermal-sensors = <&tsens1 7>;
6867 trip-point0 {
6873 trip-point1 {
6879 cpu-critical {
6887 cpu1-3-btm-thermal {
6888 polling-delay-passive = <250>;
6890 thermal-sensors = <&tsens1 8>;
6893 trip-point0 {
6899 trip-point1 {
6905 cpu-critical {
6913 cpuss1-top-thermal {
6914 thermal-sensors = <&tsens1 9>;
6917 trip-point0 {
6923 cpuss2-critical {
6931 cpuss1-btm-thermal {
6932 thermal-sensors = <&tsens1 10>;
6935 trip-point0 {
6941 cpuss2-critical {
6949 aoss2-thermal {
6950 thermal-sensors = <&tsens2 0>;
6953 trip-point0 {
6959 aoss0-critical {
6967 cpu2-0-top-thermal {
6968 polling-delay-passive = <250>;
6970 thermal-sensors = <&tsens2 1>;
6973 trip-point0 {
6979 trip-point1 {
6985 cpu-critical {
6993 cpu2-0-btm-thermal {
6994 polling-delay-passive = <250>;
6996 thermal-sensors = <&tsens2 2>;
6999 trip-point0 {
7005 trip-point1 {
7011 cpu-critical {
7019 cpu2-1-top-thermal {
7020 polling-delay-passive = <250>;
7022 thermal-sensors = <&tsens2 3>;
7025 trip-point0 {
7031 trip-point1 {
7037 cpu-critical {
7045 cpu2-1-btm-thermal {
7046 polling-delay-passive = <250>;
7048 thermal-sensors = <&tsens2 4>;
7051 trip-point0 {
7057 trip-point1 {
7063 cpu-critical {
7071 cpu2-2-top-thermal {
7072 polling-delay-passive = <250>;
7074 thermal-sensors = <&tsens2 5>;
7077 trip-point0 {
7083 trip-point1 {
7089 cpu-critical {
7097 cpu2-2-btm-thermal {
7098 polling-delay-passive = <250>;
7100 thermal-sensors = <&tsens2 6>;
7103 trip-point0 {
7109 trip-point1 {
7115 cpu-critical {
7123 cpu2-3-top-thermal {
7124 polling-delay-passive = <250>;
7126 thermal-sensors = <&tsens2 7>;
7129 trip-point0 {
7135 trip-point1 {
7141 cpu-critical {
7149 cpu2-3-btm-thermal {
7150 polling-delay-passive = <250>;
7152 thermal-sensors = <&tsens2 8>;
7155 trip-point0 {
7161 trip-point1 {
7167 cpu-critical {
7175 cpuss2-top-thermal {
7176 thermal-sensors = <&tsens2 9>;
7179 trip-point0 {
7185 cpuss2-critical {
7193 cpuss2-btm-thermal {
7194 thermal-sensors = <&tsens2 10>;
7197 trip-point0 {
7203 cpuss2-critical {
7211 aoss3-thermal {
7212 thermal-sensors = <&tsens3 0>;
7215 trip-point0 {
7221 aoss0-critical {
7229 nsp0-thermal {
7230 thermal-sensors = <&tsens3 1>;
7233 trip-point0 {
7239 nsp0-critical {
7247 nsp1-thermal {
7248 thermal-sensors = <&tsens3 2>;
7251 trip-point0 {
7257 nsp1-critical {
7265 nsp2-thermal {
7266 thermal-sensors = <&tsens3 3>;
7269 trip-point0 {
7275 nsp2-critical {
7283 nsp3-thermal {
7284 thermal-sensors = <&tsens3 4>;
7287 trip-point0 {
7293 nsp3-critical {
7301 gpuss-0-thermal {
7302 polling-delay-passive = <10>;
7304 thermal-sensors = <&tsens3 5>;
7307 trip-point0 {
7313 trip-point1 {
7319 trip-point2 {
7327 gpuss-1-thermal {
7328 polling-delay-passive = <10>;
7330 thermal-sensors = <&tsens3 6>;
7333 trip-point0 {
7339 trip-point1 {
7345 trip-point2 {
7353 gpuss-2-thermal {
7354 polling-delay-passive = <10>;
7356 thermal-sensors = <&tsens3 7>;
7359 trip-point0 {
7365 trip-point1 {
7371 trip-point2 {
7379 gpuss-3-thermal {
7380 polling-delay-passive = <10>;
7382 thermal-sensors = <&tsens3 8>;
7385 trip-point0 {
7391 trip-point1 {
7397 trip-point2 {
7405 gpuss-4-thermal {
7406 polling-delay-passive = <10>;
7408 thermal-sensors = <&tsens3 9>;
7411 trip-point0 {
7417 trip-point1 {
7423 trip-point2 {
7431 gpuss-5-thermal {
7432 polling-delay-passive = <10>;
7434 thermal-sensors = <&tsens3 10>;
7437 trip-point0 {
7443 trip-point1 {
7449 trip-point2 {
7457 gpuss-6-thermal {
7458 polling-delay-passive = <10>;
7460 thermal-sensors = <&tsens3 11>;
7463 trip-point0 {
7469 trip-point1 {
7475 trip-point2 {
7483 gpuss-7-thermal {
7484 polling-delay-passive = <10>;
7486 thermal-sensors = <&tsens3 12>;
7489 trip-point0 {
7495 trip-point1 {
7501 trip-point2 {
7509 camera0-thermal {
7510 thermal-sensors = <&tsens3 13>;
7513 trip-point0 {
7519 camera0-critical {
7527 camera1-thermal {
7528 thermal-sensors = <&tsens3 14>;
7531 trip-point0 {
7537 camera0-critical {