Lines Matching +full:gpi +full:- +full:dma
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
8 #include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
9 #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
10 #include <dt-bindings/clock/qcom,x1e80100-gpucc.h>
11 #include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/interconnect/qcom,icc.h>
14 #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/soc/qcom,gpr.h>
21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
22 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
25 interrupt-parent = <&intc>;
27 #address-cells = <2>;
28 #size-cells = <2>;
33 xo_board: xo-board {
34 compatible = "fixed-clock";
35 clock-frequency = <76800000>;
36 #clock-cells = <0>;
39 sleep_clk: sleep-clk {
40 compatible = "fixed-clock";
41 clock-frequency = <32764>;
42 #clock-cells = <0>;
45 bi_tcxo_div2: bi-tcxo-div2-clk {
46 compatible = "fixed-factor-clock";
47 #clock-cells = <0>;
50 clock-mult = <1>;
51 clock-div = <2>;
54 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
55 compatible = "fixed-factor-clock";
56 #clock-cells = <0>;
59 clock-mult = <1>;
60 clock-div = <2>;
65 #address-cells = <2>;
66 #size-cells = <0>;
72 enable-method = "psci";
73 next-level-cache = <&l2_0>;
74 power-domains = <&cpu_pd0>;
75 power-domain-names = "psci";
76 cpu-idle-states = <&cluster_c4>;
78 l2_0: l2-cache {
80 cache-level = <2>;
81 cache-unified;
89 enable-method = "psci";
90 next-level-cache = <&l2_0>;
91 power-domains = <&cpu_pd1>;
92 power-domain-names = "psci";
93 cpu-idle-states = <&cluster_c4>;
100 enable-method = "psci";
101 next-level-cache = <&l2_0>;
102 power-domains = <&cpu_pd2>;
103 power-domain-names = "psci";
104 cpu-idle-states = <&cluster_c4>;
111 enable-method = "psci";
112 next-level-cache = <&l2_0>;
113 power-domains = <&cpu_pd3>;
114 power-domain-names = "psci";
115 cpu-idle-states = <&cluster_c4>;
122 enable-method = "psci";
123 next-level-cache = <&l2_1>;
124 power-domains = <&cpu_pd4>;
125 power-domain-names = "psci";
126 cpu-idle-states = <&cluster_c4>;
128 l2_1: l2-cache {
130 cache-level = <2>;
131 cache-unified;
139 enable-method = "psci";
140 next-level-cache = <&l2_1>;
141 power-domains = <&cpu_pd5>;
142 power-domain-names = "psci";
143 cpu-idle-states = <&cluster_c4>;
150 enable-method = "psci";
151 next-level-cache = <&l2_1>;
152 power-domains = <&cpu_pd6>;
153 power-domain-names = "psci";
154 cpu-idle-states = <&cluster_c4>;
161 enable-method = "psci";
162 next-level-cache = <&l2_1>;
163 power-domains = <&cpu_pd7>;
164 power-domain-names = "psci";
165 cpu-idle-states = <&cluster_c4>;
172 enable-method = "psci";
173 next-level-cache = <&l2_2>;
174 power-domains = <&cpu_pd8>;
175 power-domain-names = "psci";
176 cpu-idle-states = <&cluster_c4>;
178 l2_2: l2-cache {
180 cache-level = <2>;
181 cache-unified;
189 enable-method = "psci";
190 next-level-cache = <&l2_2>;
191 power-domains = <&cpu_pd9>;
192 power-domain-names = "psci";
193 cpu-idle-states = <&cluster_c4>;
200 enable-method = "psci";
201 next-level-cache = <&l2_2>;
202 power-domains = <&cpu_pd10>;
203 power-domain-names = "psci";
204 cpu-idle-states = <&cluster_c4>;
211 enable-method = "psci";
212 next-level-cache = <&l2_2>;
213 power-domains = <&cpu_pd11>;
214 power-domain-names = "psci";
215 cpu-idle-states = <&cluster_c4>;
218 cpu-map {
274 idle-states {
275 entry-method = "psci";
277 cluster_c4: cpu-sleep-0 {
278 compatible = "arm,idle-state";
279 idle-state-name = "ret";
280 arm,psci-suspend-param = <0x00000004>;
281 entry-latency-us = <180>;
282 exit-latency-us = <500>;
283 min-residency-us = <600>;
287 domain-idle-states {
288 cluster_cl4: cluster-sleep-0 {
289 compatible = "domain-idle-state";
290 arm,psci-suspend-param = <0x01000044>;
291 entry-latency-us = <350>;
292 exit-latency-us = <500>;
293 min-residency-us = <2500>;
296 cluster_cl5: cluster-sleep-1 {
297 compatible = "domain-idle-state";
298 arm,psci-suspend-param = <0x01000054>;
299 entry-latency-us = <2200>;
300 exit-latency-us = <4000>;
301 min-residency-us = <7000>;
306 dummy-sink {
307 compatible = "arm,coresight-dummy-sink";
309 in-ports {
312 remote-endpoint = <&swao_rep_out1>;
320 compatible = "qcom,scm-x1e80100", "qcom,scm";
323 qcom,dload-mode = <&tcsr 0x19000>;
327 clk_virt: interconnect-0 {
328 compatible = "qcom,x1e80100-clk-virt";
329 #interconnect-cells = <2>;
330 qcom,bcm-voters = <&apps_bcm_voter>;
333 mc_virt: interconnect-1 {
334 compatible = "qcom,x1e80100-mc-virt";
335 #interconnect-cells = <2>;
336 qcom,bcm-voters = <&apps_bcm_voter>;
346 compatible = "arm,armv8-pmuv3";
351 compatible = "arm,psci-1.0";
354 cpu_pd0: power-domain-cpu0 {
355 #power-domain-cells = <0>;
356 power-domains = <&cluster_pd0>;
359 cpu_pd1: power-domain-cpu1 {
360 #power-domain-cells = <0>;
361 power-domains = <&cluster_pd0>;
364 cpu_pd2: power-domain-cpu2 {
365 #power-domain-cells = <0>;
366 power-domains = <&cluster_pd0>;
369 cpu_pd3: power-domain-cpu3 {
370 #power-domain-cells = <0>;
371 power-domains = <&cluster_pd0>;
374 cpu_pd4: power-domain-cpu4 {
375 #power-domain-cells = <0>;
376 power-domains = <&cluster_pd1>;
379 cpu_pd5: power-domain-cpu5 {
380 #power-domain-cells = <0>;
381 power-domains = <&cluster_pd1>;
384 cpu_pd6: power-domain-cpu6 {
385 #power-domain-cells = <0>;
386 power-domains = <&cluster_pd1>;
389 cpu_pd7: power-domain-cpu7 {
390 #power-domain-cells = <0>;
391 power-domains = <&cluster_pd1>;
394 cpu_pd8: power-domain-cpu8 {
395 #power-domain-cells = <0>;
396 power-domains = <&cluster_pd2>;
399 cpu_pd9: power-domain-cpu9 {
400 #power-domain-cells = <0>;
401 power-domains = <&cluster_pd2>;
404 cpu_pd10: power-domain-cpu10 {
405 #power-domain-cells = <0>;
406 power-domains = <&cluster_pd2>;
409 cpu_pd11: power-domain-cpu11 {
410 #power-domain-cells = <0>;
411 power-domains = <&cluster_pd2>;
414 cluster_pd0: power-domain-cpu-cluster0 {
415 #power-domain-cells = <0>;
416 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>;
417 power-domains = <&system_pd>;
420 cluster_pd1: power-domain-cpu-cluster1 {
421 #power-domain-cells = <0>;
422 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>;
423 power-domains = <&system_pd>;
426 cluster_pd2: power-domain-cpu-cluster2 {
427 #power-domain-cells = <0>;
428 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>;
429 power-domains = <&system_pd>;
432 system_pd: power-domain-system {
433 #power-domain-cells = <0>;
434 /* TODO: system-wide idle states */
438 reserved-memory {
439 #address-cells = <2>;
440 #size-cells = <2>;
443 gunyah_hyp_mem: gunyah-hyp@80000000 {
445 no-map;
448 hyp_elf_package_mem: hyp-elf-package@80800000 {
450 no-map;
455 no-map;
458 cpucp_log_mem: cpucp-log@80e00000 {
460 no-map;
465 no-map;
468 reserved-region@81380000 {
470 no-map;
473 tags_mem: tags-region@81400000 {
475 no-map;
478 xbl_dtlog_mem: xbl-dtlog@81a00000 {
480 no-map;
483 xbl_ramdump_mem: xbl-ramdump@81a40000 {
485 no-map;
488 aop_image_mem: aop-image@81c00000 {
490 no-map;
493 aop_cmd_db_mem: aop-cmd-db@81c60000 {
494 compatible = "qcom,cmd-db";
496 no-map;
499 aop_config_mem: aop-config@81c80000 {
501 no-map;
504 tme_crash_dump_mem: tme-crash-dump@81ca0000 {
506 no-map;
509 tme_log_mem: tme-log@81ce0000 {
511 no-map;
514 uefi_log_mem: uefi-log@81ce4000 {
516 no-map;
519 secdata_apss_mem: secdata-apss@81cff000 {
521 no-map;
524 pdp_ns_shared_mem: pdp-ns-shared@81e00000 {
526 no-map;
529 gpu_prr_mem: gpu-prr@81f00000 {
531 no-map;
534 tpm_control_mem: tpm-control@81f10000 {
536 no-map;
539 usb_ucsi_shared_mem: usb-ucsi-shared@81f20000 {
541 no-map;
544 pld_pep_mem: pld-pep@81f30000 {
546 no-map;
549 pld_gmu_mem: pld-gmu@81f36000 {
551 no-map;
554 pld_pdp_mem: pld-pdp@81f37000 {
556 no-map;
559 tz_stat_mem: tz-stat@82700000 {
561 no-map;
564 xbl_tmp_buffer_mem: xbl-tmp-buffer@82800000 {
566 no-map;
569 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@84b00000 {
571 no-map;
574 spu_secure_shared_memory_mem: spu-secure-shared-memory@85300000 {
576 no-map;
579 adsp_boot_dtb_mem: adsp-boot-dtb@866c0000 {
581 no-map;
584 spss_region_mem: spss-region@86700000 {
586 no-map;
589 adsp_boot_mem: adsp-boot@86b00000 {
591 no-map;
596 no-map;
601 no-map;
604 q6_adsp_dtb_mem: q6-adsp-dtb@8b800000 {
606 no-map;
611 no-map;
614 q6_cdsp_dtb_mem: q6-cdsp-dtb@8d900000 {
616 no-map;
619 gpu_microcode_mem: gpu-microcode@8d9fe000 {
621 no-map;
626 no-map;
631 no-map;
634 av1_encoder_mem: av1-encoder@8e900000 {
636 no-map;
639 reserved-region@8f000000 {
641 no-map;
646 no-map;
649 q6_wpss_dtb_mem: q6-wpss-dtb@91300000 {
651 no-map;
654 xbl_sc_mem: xbl-sc@d8000000 {
656 no-map;
659 reserved-region@d8040000 {
661 no-map;
666 no-map;
671 no-map;
676 no-map;
679 llcc_lpi_mem: llcc-lpi@ff800000 {
681 no-map;
688 no-map;
692 qup_opp_table_100mhz: opp-table-qup100mhz {
693 compatible = "operating-points-v2";
695 opp-75000000 {
696 opp-hz = /bits/ 64 <75000000>;
697 required-opps = <&rpmhpd_opp_low_svs>;
700 opp-100000000 {
701 opp-hz = /bits/ 64 <100000000>;
702 required-opps = <&rpmhpd_opp_svs>;
706 qup_opp_table_120mhz: opp-table-qup120mhz {
707 compatible = "operating-points-v2";
709 opp-75000000 {
710 opp-hz = /bits/ 64 <75000000>;
711 required-opps = <&rpmhpd_opp_low_svs>;
714 opp-120000000 {
715 opp-hz = /bits/ 64 <120000000>;
716 required-opps = <&rpmhpd_opp_svs>;
720 smp2p-adsp {
723 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
731 qcom,local-pid = <0>;
732 qcom,remote-pid = <2>;
734 smp2p_adsp_out: master-kernel {
735 qcom,entry-name = "master-kernel";
736 #qcom,smem-state-cells = <1>;
739 smp2p_adsp_in: slave-kernel {
740 qcom,entry-name = "slave-kernel";
741 interrupt-controller;
742 #interrupt-cells = <2>;
746 smp2p-cdsp {
749 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
757 qcom,local-pid = <0>;
758 qcom,remote-pid = <5>;
760 smp2p_cdsp_out: master-kernel {
761 qcom,entry-name = "master-kernel";
762 #qcom,smem-state-cells = <1>;
765 smp2p_cdsp_in: slave-kernel {
766 qcom,entry-name = "slave-kernel";
767 interrupt-controller;
768 #interrupt-cells = <2>;
773 compatible = "simple-bus";
775 #address-cells = <2>;
776 #size-cells = <2>;
777 dma-ranges = <0 0 0 0 0x10 0>;
780 gcc: clock-controller@100000 {
781 compatible = "qcom,x1e80100-gcc";
795 power-domains = <&rpmhpd RPMHPD_CX>;
796 #clock-cells = <1>;
797 #reset-cells = <1>;
798 #power-domain-cells = <1>;
802 compatible = "qcom,x1e80100-ipcc", "qcom,ipcc";
806 interrupt-controller;
807 #interrupt-cells = <3>;
809 #mbox-cells = <2>;
812 gpi_dma2: dma-controller@800000 {
813 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
829 dma-channels = <12>;
830 dma-channel-mask = <0x3e>;
831 #dma-cells = <3>;
839 compatible = "qcom,geni-se-qup";
844 clock-names = "m-ahb",
845 "s-ahb";
849 #address-cells = <2>;
850 #size-cells = <2>;
856 compatible = "qcom,geni-i2c";
862 clock-names = "se";
870 interconnect-names = "qup-core",
871 "qup-config",
872 "qup-memory";
874 power-domains = <&rpmhpd RPMHPD_CX>;
875 required-opps = <&rpmhpd_opp_low_svs>;
879 dma-names = "tx",
882 pinctrl-0 = <&qup_i2c16_data_clk>;
883 pinctrl-names = "default";
885 #address-cells = <1>;
886 #size-cells = <0>;
892 compatible = "qcom,geni-spi";
898 clock-names = "se";
906 interconnect-names = "qup-core",
907 "qup-config",
908 "qup-memory";
910 power-domains = <&rpmhpd RPMHPD_CX>;
911 operating-points-v2 = <&qup_opp_table_120mhz>;
915 dma-names = "tx",
918 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
919 pinctrl-names = "default";
921 #address-cells = <1>;
922 #size-cells = <0>;
928 compatible = "qcom,geni-i2c";
934 clock-names = "se";
942 interconnect-names = "qup-core",
943 "qup-config",
944 "qup-memory";
946 power-domains = <&rpmhpd RPMHPD_CX>;
947 required-opps = <&rpmhpd_opp_low_svs>;
951 dma-names = "tx",
954 pinctrl-0 = <&qup_i2c17_data_clk>;
955 pinctrl-names = "default";
957 #address-cells = <1>;
958 #size-cells = <0>;
964 compatible = "qcom,geni-spi";
970 clock-names = "se";
978 interconnect-names = "qup-core",
979 "qup-config",
980 "qup-memory";
982 power-domains = <&rpmhpd RPMHPD_CX>;
983 operating-points-v2 = <&qup_opp_table_120mhz>;
987 dma-names = "tx",
990 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
991 pinctrl-names = "default";
993 #address-cells = <1>;
994 #size-cells = <0>;
1000 compatible = "qcom,geni-i2c";
1006 clock-names = "se";
1014 interconnect-names = "qup-core",
1015 "qup-config",
1016 "qup-memory";
1018 power-domains = <&rpmhpd RPMHPD_CX>;
1019 required-opps = <&rpmhpd_opp_low_svs>;
1023 dma-names = "tx",
1026 pinctrl-0 = <&qup_i2c18_data_clk>;
1027 pinctrl-names = "default";
1029 #address-cells = <1>;
1030 #size-cells = <0>;
1036 compatible = "qcom,geni-spi";
1042 clock-names = "se";
1050 interconnect-names = "qup-core",
1051 "qup-config",
1052 "qup-memory";
1054 power-domains = <&rpmhpd RPMHPD_CX>;
1055 operating-points-v2 = <&qup_opp_table_100mhz>;
1059 dma-names = "tx",
1062 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
1063 pinctrl-names = "default";
1065 #address-cells = <1>;
1066 #size-cells = <0>;
1072 compatible = "qcom,geni-i2c";
1078 clock-names = "se";
1086 interconnect-names = "qup-core",
1087 "qup-config",
1088 "qup-memory";
1090 power-domains = <&rpmhpd RPMHPD_CX>;
1091 required-opps = <&rpmhpd_opp_low_svs>;
1095 dma-names = "tx",
1098 pinctrl-0 = <&qup_i2c19_data_clk>;
1099 pinctrl-names = "default";
1101 #address-cells = <1>;
1102 #size-cells = <0>;
1108 compatible = "qcom,geni-spi";
1114 clock-names = "se";
1122 interconnect-names = "qup-core",
1123 "qup-config",
1124 "qup-memory";
1126 power-domains = <&rpmhpd RPMHPD_CX>;
1127 operating-points-v2 = <&qup_opp_table_100mhz>;
1131 dma-names = "tx",
1134 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
1135 pinctrl-names = "default";
1137 #address-cells = <1>;
1138 #size-cells = <0>;
1144 compatible = "qcom,geni-i2c";
1150 clock-names = "se";
1158 interconnect-names = "qup-core",
1159 "qup-config",
1160 "qup-memory";
1162 power-domains = <&rpmhpd RPMHPD_CX>;
1163 required-opps = <&rpmhpd_opp_low_svs>;
1167 dma-names = "tx",
1170 pinctrl-0 = <&qup_i2c20_data_clk>;
1171 pinctrl-names = "default";
1173 #address-cells = <1>;
1174 #size-cells = <0>;
1180 compatible = "qcom,geni-spi";
1186 clock-names = "se";
1194 interconnect-names = "qup-core",
1195 "qup-config",
1196 "qup-memory";
1198 power-domains = <&rpmhpd RPMHPD_CX>;
1199 operating-points-v2 = <&qup_opp_table_100mhz>;
1203 dma-names = "tx",
1206 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1207 pinctrl-names = "default";
1209 #address-cells = <1>;
1210 #size-cells = <0>;
1216 compatible = "qcom,geni-i2c";
1222 clock-names = "se";
1230 interconnect-names = "qup-core",
1231 "qup-config",
1232 "qup-memory";
1234 power-domains = <&rpmhpd RPMHPD_CX>;
1235 required-opps = <&rpmhpd_opp_low_svs>;
1239 dma-names = "tx",
1242 pinctrl-0 = <&qup_i2c21_data_clk>;
1243 pinctrl-names = "default";
1245 #address-cells = <1>;
1246 #size-cells = <0>;
1252 compatible = "qcom,geni-spi";
1258 clock-names = "se";
1266 interconnect-names = "qup-core",
1267 "qup-config",
1268 "qup-memory";
1270 power-domains = <&rpmhpd RPMHPD_CX>;
1271 operating-points-v2 = <&qup_opp_table_100mhz>;
1275 dma-names = "tx",
1278 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1279 pinctrl-names = "default";
1281 #address-cells = <1>;
1282 #size-cells = <0>;
1288 compatible = "qcom,geni-uart";
1294 clock-names = "se";
1300 interconnect-names = "qup-core",
1301 "qup-config";
1303 power-domains = <&rpmhpd RPMHPD_CX>;
1304 operating-points-v2 = <&qup_opp_table_100mhz>;
1306 pinctrl-0 = <&qup_uart21_default>;
1307 pinctrl-names = "default";
1313 compatible = "qcom,geni-i2c";
1319 clock-names = "se";
1327 interconnect-names = "qup-core",
1328 "qup-config",
1329 "qup-memory";
1331 power-domains = <&rpmhpd RPMHPD_CX>;
1332 required-opps = <&rpmhpd_opp_low_svs>;
1336 dma-names = "tx",
1339 pinctrl-0 = <&qup_i2c22_data_clk>;
1340 pinctrl-names = "default";
1342 #address-cells = <1>;
1343 #size-cells = <0>;
1349 compatible = "qcom,geni-spi";
1355 clock-names = "se";
1363 interconnect-names = "qup-core",
1364 "qup-config",
1365 "qup-memory";
1367 power-domains = <&rpmhpd RPMHPD_CX>;
1368 operating-points-v2 = <&qup_opp_table_100mhz>;
1372 dma-names = "tx",
1375 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>;
1376 pinctrl-names = "default";
1378 #address-cells = <1>;
1379 #size-cells = <0>;
1385 compatible = "qcom,geni-i2c";
1391 clock-names = "se";
1399 interconnect-names = "qup-core",
1400 "qup-config",
1401 "qup-memory";
1403 power-domains = <&rpmhpd RPMHPD_CX>;
1404 required-opps = <&rpmhpd_opp_low_svs>;
1408 dma-names = "tx",
1411 pinctrl-0 = <&qup_i2c23_data_clk>;
1412 pinctrl-names = "default";
1414 #address-cells = <1>;
1415 #size-cells = <0>;
1421 compatible = "qcom,geni-spi";
1427 clock-names = "se";
1435 interconnect-names = "qup-core",
1436 "qup-config",
1437 "qup-memory";
1439 power-domains = <&rpmhpd RPMHPD_CX>;
1440 operating-points-v2 = <&qup_opp_table_100mhz>;
1444 dma-names = "tx",
1447 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>;
1448 pinctrl-names = "default";
1450 #address-cells = <1>;
1451 #size-cells = <0>;
1457 gpi_dma1: dma-controller@a00000 {
1458 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
1474 dma-channels = <12>;
1475 dma-channel-mask = <0x3e>;
1476 #dma-cells = <3>;
1484 compatible = "qcom,geni-se-qup";
1489 clock-names = "m-ahb",
1490 "s-ahb";
1494 #address-cells = <2>;
1495 #size-cells = <2>;
1501 compatible = "qcom,geni-i2c";
1507 clock-names = "se";
1515 interconnect-names = "qup-core",
1516 "qup-config",
1517 "qup-memory";
1519 power-domains = <&rpmhpd RPMHPD_CX>;
1520 required-opps = <&rpmhpd_opp_low_svs>;
1524 dma-names = "tx",
1527 pinctrl-0 = <&qup_i2c8_data_clk>;
1528 pinctrl-names = "default";
1530 #address-cells = <1>;
1531 #size-cells = <0>;
1537 compatible = "qcom,geni-spi";
1543 clock-names = "se";
1551 interconnect-names = "qup-core",
1552 "qup-config",
1553 "qup-memory";
1555 power-domains = <&rpmhpd RPMHPD_CX>;
1556 operating-points-v2 = <&qup_opp_table_120mhz>;
1560 dma-names = "tx",
1563 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1564 pinctrl-names = "default";
1566 #address-cells = <1>;
1567 #size-cells = <0>;
1573 compatible = "qcom,geni-i2c";
1579 clock-names = "se";
1587 interconnect-names = "qup-core",
1588 "qup-config",
1589 "qup-memory";
1591 power-domains = <&rpmhpd RPMHPD_CX>;
1592 required-opps = <&rpmhpd_opp_low_svs>;
1596 dma-names = "tx",
1599 pinctrl-0 = <&qup_i2c9_data_clk>;
1600 pinctrl-names = "default";
1602 #address-cells = <1>;
1603 #size-cells = <0>;
1609 compatible = "qcom,geni-spi";
1615 clock-names = "se";
1623 interconnect-names = "qup-core",
1624 "qup-config",
1625 "qup-memory";
1627 power-domains = <&rpmhpd RPMHPD_CX>;
1628 operating-points-v2 = <&qup_opp_table_120mhz>;
1632 dma-names = "tx",
1635 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1636 pinctrl-names = "default";
1638 #address-cells = <1>;
1639 #size-cells = <0>;
1645 compatible = "qcom,geni-i2c";
1651 clock-names = "se";
1659 interconnect-names = "qup-core",
1660 "qup-config",
1661 "qup-memory";
1663 power-domains = <&rpmhpd RPMHPD_CX>;
1664 required-opps = <&rpmhpd_opp_low_svs>;
1668 dma-names = "tx",
1671 pinctrl-0 = <&qup_i2c10_data_clk>;
1672 pinctrl-names = "default";
1674 #address-cells = <1>;
1675 #size-cells = <0>;
1681 compatible = "qcom,geni-spi";
1687 clock-names = "se";
1695 interconnect-names = "qup-core",
1696 "qup-config",
1697 "qup-memory";
1699 power-domains = <&rpmhpd RPMHPD_CX>;
1700 operating-points-v2 = <&qup_opp_table_100mhz>;
1704 dma-names = "tx",
1707 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1708 pinctrl-names = "default";
1710 #address-cells = <1>;
1711 #size-cells = <0>;
1717 compatible = "qcom,geni-i2c";
1723 clock-names = "se";
1731 interconnect-names = "qup-core",
1732 "qup-config",
1733 "qup-memory";
1735 power-domains = <&rpmhpd RPMHPD_CX>;
1736 required-opps = <&rpmhpd_opp_low_svs>;
1740 dma-names = "tx",
1743 pinctrl-0 = <&qup_i2c11_data_clk>;
1744 pinctrl-names = "default";
1746 #address-cells = <1>;
1747 #size-cells = <0>;
1753 compatible = "qcom,geni-spi";
1759 clock-names = "se";
1767 interconnect-names = "qup-core",
1768 "qup-config",
1769 "qup-memory";
1771 power-domains = <&rpmhpd RPMHPD_CX>;
1772 operating-points-v2 = <&qup_opp_table_100mhz>;
1776 dma-names = "tx",
1779 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1780 pinctrl-names = "default";
1782 #address-cells = <1>;
1783 #size-cells = <0>;
1789 compatible = "qcom,geni-i2c";
1795 clock-names = "se";
1803 interconnect-names = "qup-core",
1804 "qup-config",
1805 "qup-memory";
1807 power-domains = <&rpmhpd RPMHPD_CX>;
1808 required-opps = <&rpmhpd_opp_low_svs>;
1812 dma-names = "tx",
1815 pinctrl-0 = <&qup_i2c12_data_clk>;
1816 pinctrl-names = "default";
1818 #address-cells = <1>;
1819 #size-cells = <0>;
1825 compatible = "qcom,geni-spi";
1831 clock-names = "se";
1839 interconnect-names = "qup-core",
1840 "qup-config",
1841 "qup-memory";
1843 power-domains = <&rpmhpd RPMHPD_CX>;
1844 operating-points-v2 = <&qup_opp_table_100mhz>;
1848 dma-names = "tx",
1851 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1852 pinctrl-names = "default";
1854 #address-cells = <1>;
1855 #size-cells = <0>;
1861 compatible = "qcom,geni-i2c";
1867 clock-names = "se";
1875 interconnect-names = "qup-core",
1876 "qup-config",
1877 "qup-memory";
1879 power-domains = <&rpmhpd RPMHPD_CX>;
1880 required-opps = <&rpmhpd_opp_low_svs>;
1884 dma-names = "tx",
1887 pinctrl-0 = <&qup_i2c13_data_clk>;
1888 pinctrl-names = "default";
1890 #address-cells = <1>;
1891 #size-cells = <0>;
1897 compatible = "qcom,geni-spi";
1903 clock-names = "se";
1911 interconnect-names = "qup-core",
1912 "qup-config",
1913 "qup-memory";
1915 power-domains = <&rpmhpd RPMHPD_CX>;
1916 operating-points-v2 = <&qup_opp_table_100mhz>;
1920 dma-names = "tx",
1923 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1924 pinctrl-names = "default";
1926 #address-cells = <1>;
1927 #size-cells = <0>;
1933 compatible = "qcom,geni-i2c";
1939 clock-names = "se";
1947 interconnect-names = "qup-core",
1948 "qup-config",
1949 "qup-memory";
1951 power-domains = <&rpmhpd RPMHPD_CX>;
1952 required-opps = <&rpmhpd_opp_low_svs>;
1956 dma-names = "tx",
1959 pinctrl-0 = <&qup_i2c14_data_clk>;
1960 pinctrl-names = "default";
1962 #address-cells = <1>;
1963 #size-cells = <0>;
1969 compatible = "qcom,geni-spi";
1975 clock-names = "se";
1983 interconnect-names = "qup-core",
1984 "qup-config",
1985 "qup-memory";
1987 power-domains = <&rpmhpd RPMHPD_CX>;
1988 operating-points-v2 = <&qup_opp_table_100mhz>;
1992 dma-names = "tx",
1995 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1996 pinctrl-names = "default";
1998 #address-cells = <1>;
1999 #size-cells = <0>;
2005 compatible = "qcom,geni-uart";
2011 clock-names = "se";
2017 interconnect-names = "qup-core",
2018 "qup-config";
2020 power-domains = <&rpmhpd RPMHPD_CX>;
2021 operating-points-v2 = <&qup_opp_table_100mhz>;
2023 pinctrl-0 = <&qup_uart14_default>;
2024 pinctrl-names = "default";
2030 compatible = "qcom,geni-i2c";
2036 clock-names = "se";
2044 interconnect-names = "qup-core",
2045 "qup-config",
2046 "qup-memory";
2048 power-domains = <&rpmhpd RPMHPD_CX>;
2049 required-opps = <&rpmhpd_opp_low_svs>;
2053 dma-names = "tx",
2056 pinctrl-0 = <&qup_i2c15_data_clk>;
2057 pinctrl-names = "default";
2059 #address-cells = <1>;
2060 #size-cells = <0>;
2066 compatible = "qcom,geni-spi";
2072 clock-names = "se";
2080 interconnect-names = "qup-core",
2081 "qup-config",
2082 "qup-memory";
2084 power-domains = <&rpmhpd RPMHPD_CX>;
2085 operating-points-v2 = <&qup_opp_table_100mhz>;
2089 dma-names = "tx",
2092 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
2093 pinctrl-names = "default";
2095 #address-cells = <1>;
2096 #size-cells = <0>;
2102 gpi_dma0: dma-controller@b00000 {
2103 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
2119 dma-channels = <12>;
2120 dma-channel-mask = <0x3e>;
2121 #dma-cells = <3>;
2129 compatible = "qcom,geni-se-qup";
2134 clock-names = "m-ahb",
2135 "s-ahb";
2138 #address-cells = <2>;
2139 #size-cells = <2>;
2145 compatible = "qcom,geni-i2c";
2151 clock-names = "se";
2159 interconnect-names = "qup-core",
2160 "qup-config",
2161 "qup-memory";
2163 power-domains = <&rpmhpd RPMHPD_CX>;
2164 required-opps = <&rpmhpd_opp_low_svs>;
2168 dma-names = "tx",
2171 pinctrl-0 = <&qup_i2c0_data_clk>;
2172 pinctrl-names = "default";
2174 #address-cells = <1>;
2175 #size-cells = <0>;
2181 compatible = "qcom,geni-spi";
2187 clock-names = "se";
2195 interconnect-names = "qup-core",
2196 "qup-config",
2197 "qup-memory";
2199 power-domains = <&rpmhpd RPMHPD_CX>;
2200 operating-points-v2 = <&qup_opp_table_120mhz>;
2204 dma-names = "tx",
2207 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
2208 pinctrl-names = "default";
2210 #address-cells = <1>;
2211 #size-cells = <0>;
2217 compatible = "qcom,geni-i2c";
2223 clock-names = "se";
2231 interconnect-names = "qup-core",
2232 "qup-config",
2233 "qup-memory";
2235 power-domains = <&rpmhpd RPMHPD_CX>;
2236 required-opps = <&rpmhpd_opp_low_svs>;
2240 dma-names = "tx",
2243 pinctrl-0 = <&qup_i2c1_data_clk>;
2244 pinctrl-names = "default";
2246 #address-cells = <1>;
2247 #size-cells = <0>;
2253 compatible = "qcom,geni-spi";
2259 clock-names = "se";
2267 interconnect-names = "qup-core",
2268 "qup-config",
2269 "qup-memory";
2271 power-domains = <&rpmhpd RPMHPD_CX>;
2272 operating-points-v2 = <&qup_opp_table_120mhz>;
2276 dma-names = "tx",
2279 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
2280 pinctrl-names = "default";
2282 #address-cells = <1>;
2283 #size-cells = <0>;
2289 compatible = "qcom,geni-i2c";
2295 clock-names = "se";
2303 interconnect-names = "qup-core",
2304 "qup-config",
2305 "qup-memory";
2307 power-domains = <&rpmhpd RPMHPD_CX>;
2308 required-opps = <&rpmhpd_opp_low_svs>;
2312 dma-names = "tx",
2315 pinctrl-0 = <&qup_i2c2_data_clk>;
2316 pinctrl-names = "default";
2318 #address-cells = <1>;
2319 #size-cells = <0>;
2325 compatible = "qcom,geni-uart";
2331 clock-names = "se";
2337 interconnect-names = "qup-core",
2338 "qup-config";
2340 power-domains = <&rpmhpd RPMHPD_CX>;
2341 operating-points-v2 = <&qup_opp_table_100mhz>;
2343 pinctrl-0 = <&qup_uart2_default>;
2344 pinctrl-names = "default";
2350 compatible = "qcom,geni-spi";
2356 clock-names = "se";
2364 interconnect-names = "qup-core",
2365 "qup-config",
2366 "qup-memory";
2368 power-domains = <&rpmhpd RPMHPD_CX>;
2369 operating-points-v2 = <&qup_opp_table_100mhz>;
2373 dma-names = "tx",
2376 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
2377 pinctrl-names = "default";
2379 #address-cells = <1>;
2380 #size-cells = <0>;
2386 compatible = "qcom,geni-i2c";
2392 clock-names = "se";
2400 interconnect-names = "qup-core",
2401 "qup-config",
2402 "qup-memory";
2404 power-domains = <&rpmhpd RPMHPD_CX>;
2405 required-opps = <&rpmhpd_opp_low_svs>;
2409 dma-names = "tx",
2412 pinctrl-0 = <&qup_i2c3_data_clk>;
2413 pinctrl-names = "default";
2415 #address-cells = <1>;
2416 #size-cells = <0>;
2422 compatible = "qcom,geni-spi";
2428 clock-names = "se";
2436 interconnect-names = "qup-core",
2437 "qup-config",
2438 "qup-memory";
2440 power-domains = <&rpmhpd RPMHPD_CX>;
2441 operating-points-v2 = <&qup_opp_table_100mhz>;
2445 dma-names = "tx",
2448 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
2449 pinctrl-names = "default";
2451 #address-cells = <1>;
2452 #size-cells = <0>;
2458 compatible = "qcom,geni-i2c";
2464 clock-names = "se";
2472 interconnect-names = "qup-core",
2473 "qup-config",
2474 "qup-memory";
2476 power-domains = <&rpmhpd RPMHPD_CX>;
2477 required-opps = <&rpmhpd_opp_low_svs>;
2481 dma-names = "tx",
2484 pinctrl-0 = <&qup_i2c4_data_clk>;
2485 pinctrl-names = "default";
2487 #address-cells = <1>;
2488 #size-cells = <0>;
2494 compatible = "qcom,geni-spi";
2500 clock-names = "se";
2508 interconnect-names = "qup-core",
2509 "qup-config",
2510 "qup-memory";
2512 power-domains = <&rpmhpd RPMHPD_CX>;
2513 operating-points-v2 = <&qup_opp_table_100mhz>;
2517 dma-names = "tx",
2520 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
2521 pinctrl-names = "default";
2523 #address-cells = <1>;
2524 #size-cells = <0>;
2530 compatible = "qcom,geni-i2c";
2536 clock-names = "se";
2544 interconnect-names = "qup-core",
2545 "qup-config",
2546 "qup-memory";
2548 power-domains = <&rpmhpd RPMHPD_CX>;
2549 required-opps = <&rpmhpd_opp_low_svs>;
2553 dma-names = "tx",
2556 pinctrl-0 = <&qup_i2c5_data_clk>;
2557 pinctrl-names = "default";
2559 #address-cells = <1>;
2560 #size-cells = <0>;
2566 compatible = "qcom,geni-spi";
2572 clock-names = "se";
2580 interconnect-names = "qup-core",
2581 "qup-config",
2582 "qup-memory";
2584 power-domains = <&rpmhpd RPMHPD_CX>;
2585 operating-points-v2 = <&qup_opp_table_100mhz>;
2589 dma-names = "tx",
2592 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
2593 pinctrl-names = "default";
2595 #address-cells = <1>;
2596 #size-cells = <0>;
2602 compatible = "qcom,geni-i2c";
2608 clock-names = "se";
2616 interconnect-names = "qup-core",
2617 "qup-config",
2618 "qup-memory";
2620 power-domains = <&rpmhpd RPMHPD_CX>;
2621 required-opps = <&rpmhpd_opp_low_svs>;
2625 dma-names = "tx",
2628 pinctrl-0 = <&qup_i2c6_data_clk>;
2629 pinctrl-names = "default";
2631 #address-cells = <1>;
2632 #size-cells = <0>;
2638 compatible = "qcom,geni-spi";
2644 clock-names = "se";
2652 interconnect-names = "qup-core",
2653 "qup-config",
2654 "qup-memory";
2656 power-domains = <&rpmhpd RPMHPD_CX>;
2657 operating-points-v2 = <&qup_opp_table_100mhz>;
2661 dma-names = "tx",
2664 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
2665 pinctrl-names = "default";
2667 #address-cells = <1>;
2668 #size-cells = <0>;
2674 compatible = "qcom,geni-i2c";
2680 clock-names = "se";
2688 interconnect-names = "qup-core",
2689 "qup-config",
2690 "qup-memory";
2692 power-domains = <&rpmhpd RPMHPD_CX>;
2693 required-opps = <&rpmhpd_opp_low_svs>;
2697 dma-names = "tx",
2700 pinctrl-0 = <&qup_i2c7_data_clk>;
2701 pinctrl-names = "default";
2703 #address-cells = <1>;
2704 #size-cells = <0>;
2710 compatible = "qcom,geni-spi";
2716 clock-names = "se";
2724 interconnect-names = "qup-core",
2725 "qup-config",
2726 "qup-memory";
2728 power-domains = <&rpmhpd RPMHPD_CX>;
2729 operating-points-v2 = <&qup_opp_table_100mhz>;
2733 dma-names = "tx",
2736 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
2737 pinctrl-names = "default";
2739 #address-cells = <1>;
2740 #size-cells = <0>;
2746 tsens0: thermal-sensor@c271000 {
2747 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2751 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
2753 interrupt-names = "uplow",
2758 #thermal-sensor-cells = <1>;
2761 tsens1: thermal-sensor@c272000 {
2762 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2766 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
2768 interrupt-names = "uplow",
2773 #thermal-sensor-cells = <1>;
2776 tsens2: thermal-sensor@c273000 {
2777 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2781 interrupts-extended = <&pdc 28 IRQ_TYPE_LEVEL_HIGH>,
2783 interrupt-names = "uplow",
2788 #thermal-sensor-cells = <1>;
2791 tsens3: thermal-sensor@c274000 {
2792 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2796 interrupts-extended = <&pdc 29 IRQ_TYPE_LEVEL_HIGH>,
2798 interrupt-names = "uplow",
2803 #thermal-sensor-cells = <1>;
2807 compatible = "qcom,x1e80100-snps-eusb2-phy",
2808 "qcom,sm8550-snps-eusb2-phy";
2810 #phy-cells = <0>;
2813 clock-names = "ref";
2821 compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
2828 clock-names = "aux",
2833 power-domains = <&gcc GCC_USB_0_PHY_GDSC>;
2837 reset-names = "phy",
2840 #clock-cells = <1>;
2841 #phy-cells = <1>;
2843 orientation-switch;
2848 #address-cells = <1>;
2849 #size-cells = <0>;
2862 remote-endpoint = <&usb_1_ss0_dwc3_ss>;
2870 remote-endpoint = <&mdss_dp0_out>;
2877 compatible = "qcom,x1e80100-snps-eusb2-phy",
2878 "qcom,sm8550-snps-eusb2-phy";
2880 #phy-cells = <0>;
2883 clock-names = "ref";
2891 compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
2898 clock-names = "aux",
2903 power-domains = <&gcc GCC_USB_1_PHY_GDSC>;
2907 reset-names = "phy",
2910 #clock-cells = <1>;
2911 #phy-cells = <1>;
2913 orientation-switch;
2918 #address-cells = <1>;
2919 #size-cells = <0>;
2932 remote-endpoint = <&usb_1_ss1_dwc3_ss>;
2940 remote-endpoint = <&mdss_dp1_out>;
2947 compatible = "qcom,x1e80100-snps-eusb2-phy",
2948 "qcom,sm8550-snps-eusb2-phy";
2950 #phy-cells = <0>;
2953 clock-names = "ref";
2961 compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
2968 clock-names = "aux",
2973 power-domains = <&gcc GCC_USB_2_PHY_GDSC>;
2977 reset-names = "phy",
2980 #clock-cells = <1>;
2981 #phy-cells = <1>;
2983 orientation-switch;
2988 #address-cells = <1>;
2989 #size-cells = <0>;
3002 remote-endpoint = <&usb_1_ss2_dwc3_ss>;
3010 remote-endpoint = <&mdss_dp2_out>;
3017 compatible = "qcom,x1e80100-cnoc-main";
3020 qcom,bcm-voters = <&apps_bcm_voter>;
3022 #interconnect-cells = <2>;
3026 compatible = "qcom,x1e80100-cnoc-cfg";
3029 qcom,bcm-voters = <&apps_bcm_voter>;
3031 #interconnect-cells = <2>;
3035 compatible = "qcom,x1e80100-system-noc";
3038 qcom,bcm-voters = <&apps_bcm_voter>;
3040 #interconnect-cells = <2>;
3044 compatible = "qcom,x1e80100-pcie-south-anoc";
3047 qcom,bcm-voters = <&apps_bcm_voter>;
3049 #interconnect-cells = <2>;
3053 compatible = "qcom,x1e80100-pcie-center-anoc";
3056 qcom,bcm-voters = <&apps_bcm_voter>;
3058 #interconnect-cells = <2>;
3062 compatible = "qcom,x1e80100-aggre1-noc";
3065 qcom,bcm-voters = <&apps_bcm_voter>;
3067 #interconnect-cells = <2>;
3071 compatible = "qcom,x1e80100-aggre2-noc";
3074 qcom,bcm-voters = <&apps_bcm_voter>;
3076 #interconnect-cells = <2>;
3080 compatible = "qcom,x1e80100-pcie-north-anoc";
3083 qcom,bcm-voters = <&apps_bcm_voter>;
3085 #interconnect-cells = <2>;
3089 compatible = "qcom,x1e80100-usb-center-anoc";
3092 qcom,bcm-voters = <&apps_bcm_voter>;
3094 #interconnect-cells = <2>;
3098 compatible = "qcom,x1e80100-usb-north-anoc";
3101 qcom,bcm-voters = <&apps_bcm_voter>;
3103 #interconnect-cells = <2>;
3107 compatible = "qcom,x1e80100-usb-south-anoc";
3110 qcom,bcm-voters = <&apps_bcm_voter>;
3112 #interconnect-cells = <2>;
3116 compatible = "qcom,x1e80100-mmss-noc";
3119 qcom,bcm-voters = <&apps_bcm_voter>;
3121 #interconnect-cells = <2>;
3126 compatible = "qcom,pcie-x1e80100";
3133 reg-names = "parf",
3139 #address-cells = <3>;
3140 #size-cells = <2>;
3144 bus-range = <0x00 0xff>;
3146 dma-coherent;
3148 linux,pci-domain = <3>;
3149 num-lanes = <8>;
3160 interrupt-names = "msi0",
3170 #interrupt-cells = <1>;
3171 interrupt-map-mask = <0 0 0 0x7>;
3172 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
3184 clock-names = "aux",
3192 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
3193 assigned-clock-rates = <19200000>;
3199 interconnect-names = "pcie-mem",
3200 "cpu-pcie";
3204 reset-names = "pci",
3207 power-domains = <&gcc GCC_PCIE_3_GDSC>;
3210 phy-names = "pciephy";
3212 operating-points-v2 = <&pcie3_opp_table>;
3216 pcie3_opp_table: opp-table {
3217 compatible = "operating-points-v2";
3220 opp-2500000 {
3221 opp-hz = /bits/ 64 <2500000>;
3222 required-opps = <&rpmhpd_opp_low_svs>;
3223 opp-peak-kBps = <250000 1>;
3227 opp-5000000 {
3228 opp-hz = /bits/ 64 <5000000>;
3229 required-opps = <&rpmhpd_opp_low_svs>;
3230 opp-peak-kBps = <500000 1>;
3234 opp-10000000 {
3235 opp-hz = /bits/ 64 <10000000>;
3236 required-opps = <&rpmhpd_opp_low_svs>;
3237 opp-peak-kBps = <1000000 1>;
3241 opp-20000000 {
3242 opp-hz = /bits/ 64 <20000000>;
3243 required-opps = <&rpmhpd_opp_low_svs>;
3244 opp-peak-kBps = <2000000 1>;
3248 opp-40000000 {
3249 opp-hz = /bits/ 64 <40000000>;
3250 required-opps = <&rpmhpd_opp_low_svs>;
3251 opp-peak-kBps = <4000000 1>;
3255 opp-8000000 {
3256 opp-hz = /bits/ 64 <8000000>;
3257 required-opps = <&rpmhpd_opp_svs>;
3258 opp-peak-kBps = <984500 1>;
3262 opp-16000000 {
3263 opp-hz = /bits/ 64 <16000000>;
3264 required-opps = <&rpmhpd_opp_svs>;
3265 opp-peak-kBps = <1969000 1>;
3269 opp-32000000 {
3270 opp-hz = /bits/ 64 <32000000>;
3271 required-opps = <&rpmhpd_opp_svs>;
3272 opp-peak-kBps = <3938000 1>;
3276 opp-64000000 {
3277 opp-hz = /bits/ 64 <64000000>;
3278 required-opps = <&rpmhpd_opp_svs>;
3279 opp-peak-kBps = <7876000 1>;
3283 opp-128000000 {
3284 opp-hz = /bits/ 64 <128000000>;
3285 required-opps = <&rpmhpd_opp_svs>;
3286 opp-peak-kBps = <15753000 1>;
3292 compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy";
3301 clock-names = "aux",
3310 reset-names = "phy",
3313 assigned-clocks = <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>;
3314 assigned-clock-rates = <100000000>;
3316 power-domains = <&gcc GCC_PCIE_3_PHY_GDSC>;
3318 #clock-cells = <0>;
3319 clock-output-names = "pcie3_pipe_clk";
3321 #phy-cells = <0>;
3328 compatible = "qcom,pcie-x1e80100";
3335 reg-names = "parf",
3341 #address-cells = <3>;
3342 #size-cells = <2>;
3345 bus-range = <0x00 0xff>;
3347 dma-coherent;
3349 linux,pci-domain = <6>;
3350 num-lanes = <4>;
3352 msi-map = <0x0 &gic_its 0xe0000 0x10000>;
3362 interrupt-names = "msi0",
3371 #interrupt-cells = <1>;
3372 interrupt-map-mask = <0 0 0 0x7>;
3373 interrupt-map = <0 0 0 1 &intc 0 0 0 843 IRQ_TYPE_LEVEL_HIGH>,
3385 clock-names = "aux",
3393 assigned-clocks = <&gcc GCC_PCIE_6A_AUX_CLK>;
3394 assigned-clock-rates = <19200000>;
3400 interconnect-names = "pcie-mem",
3401 "cpu-pcie";
3405 reset-names = "pci",
3408 power-domains = <&gcc GCC_PCIE_6A_GDSC>;
3409 required-opps = <&rpmhpd_opp_nom>;
3412 phy-names = "pciephy";
3418 compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy";
3428 clock-names = "aux",
3437 reset-names = "phy",
3440 assigned-clocks = <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>;
3441 assigned-clock-rates = <100000000>;
3443 power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>;
3445 qcom,4ln-config-sel = <&tcsr 0x1a000 0>;
3447 #clock-cells = <0>;
3448 clock-output-names = "pcie6a_pipe_clk";
3450 #phy-cells = <0>;
3457 compatible = "qcom,pcie-x1e80100";
3464 reg-names = "parf",
3470 #address-cells = <3>;
3471 #size-cells = <2>;
3474 bus-range = <0x00 0xff>;
3476 dma-coherent;
3478 linux,pci-domain = <5>;
3479 num-lanes = <2>;
3489 interrupt-names = "msi0",
3498 #interrupt-cells = <1>;
3499 interrupt-map-mask = <0 0 0 0x7>;
3500 interrupt-map = <0 0 0 1 &intc 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>,
3512 clock-names = "aux",
3520 assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>;
3521 assigned-clock-rates = <19200000>;
3527 interconnect-names = "pcie-mem",
3528 "cpu-pcie";
3532 reset-names = "pci",
3535 power-domains = <&gcc GCC_PCIE_5_GDSC>;
3536 required-opps = <&rpmhpd_opp_nom>;
3539 phy-names = "pciephy";
3545 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy";
3554 clock-names = "aux",
3562 reset-names = "phy";
3564 assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>;
3565 assigned-clock-rates = <100000000>;
3567 power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>;
3569 #clock-cells = <0>;
3570 clock-output-names = "pcie5_pipe_clk";
3572 #phy-cells = <0>;
3579 compatible = "qcom,pcie-x1e80100";
3586 reg-names = "parf",
3592 #address-cells = <3>;
3593 #size-cells = <2>;
3596 bus-range = <0x00 0xff>;
3598 dma-coherent;
3600 linux,pci-domain = <4>;
3601 num-lanes = <2>;
3603 msi-map = <0x0 &gic_its 0xc0000 0x10000>;
3613 interrupt-names = "msi0",
3622 #interrupt-cells = <1>;
3623 interrupt-map-mask = <0 0 0 0x7>;
3624 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
3636 clock-names = "aux",
3644 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
3645 assigned-clock-rates = <19200000>;
3651 interconnect-names = "pcie-mem",
3652 "cpu-pcie";
3656 reset-names = "pci",
3659 power-domains = <&gcc GCC_PCIE_4_GDSC>;
3660 required-opps = <&rpmhpd_opp_nom>;
3663 phy-names = "pciephy";
3670 bus-range = <0x01 0xff>;
3672 #address-cells = <3>;
3673 #size-cells = <2>;
3679 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy";
3688 clock-names = "aux",
3696 reset-names = "phy";
3698 assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>;
3699 assigned-clock-rates = <100000000>;
3701 power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>;
3703 #clock-cells = <0>;
3704 clock-output-names = "pcie4_pipe_clk";
3706 #phy-cells = <0>;
3712 compatible = "qcom,tcsr-mutex";
3714 #hwlock-cells = <1>;
3717 tcsr: clock-controller@1fc0000 {
3718 compatible = "qcom,x1e80100-tcsr", "syscon";
3721 #clock-cells = <1>;
3722 #reset-cells = <1>;
3726 compatible = "qcom,adreno-43050c01", "qcom,adreno";
3731 reg-names = "kgsl_3d0_reg_memory",
3740 operating-points-v2 = <&gpu_opp_table>;
3743 #cooling-cells = <2>;
3746 interconnect-names = "gfx-mem";
3750 zap-shader {
3751 memory-region = <&gpu_microcode_mem>;
3754 gpu_opp_table: opp-table {
3755 compatible = "operating-points-v2";
3757 opp-1100000000 {
3758 opp-hz = /bits/ 64 <1100000000>;
3759 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3760 opp-peak-kBps = <16500000>;
3763 opp-1000000000 {
3764 opp-hz = /bits/ 64 <1000000000>;
3765 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3766 opp-peak-kBps = <14398438>;
3769 opp-925000000 {
3770 opp-hz = /bits/ 64 <925000000>;
3771 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3772 opp-peak-kBps = <14398438>;
3775 opp-800000000 {
3776 opp-hz = /bits/ 64 <800000000>;
3777 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3778 opp-peak-kBps = <12449219>;
3781 opp-744000000 {
3782 opp-hz = /bits/ 64 <744000000>;
3783 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
3784 opp-peak-kBps = <10687500>;
3787 opp-687000000 {
3788 opp-hz = /bits/ 64 <687000000>;
3789 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3790 opp-peak-kBps = <8171875>;
3793 opp-550000000 {
3794 opp-hz = /bits/ 64 <550000000>;
3795 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3796 opp-peak-kBps = <6074219>;
3799 opp-390000000 {
3800 opp-hz = /bits/ 64 <390000000>;
3801 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3802 opp-peak-kBps = <3000000>;
3805 opp-300000000 {
3806 opp-hz = /bits/ 64 <300000000>;
3807 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
3808 opp-peak-kBps = <2136719>;
3814 compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu";
3818 reg-names = "gmu", "rscc", "gmu_pdc";
3822 interrupt-names = "hfi", "gmu";
3831 clock-names = "ahb",
3839 power-domains = <&gpucc GPU_CX_GDSC>,
3841 power-domain-names = "cx",
3848 operating-points-v2 = <&gmu_opp_table>;
3850 gmu_opp_table: opp-table {
3851 compatible = "operating-points-v2";
3853 opp-550000000 {
3854 opp-hz = /bits/ 64 <550000000>;
3855 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3858 opp-220000000 {
3859 opp-hz = /bits/ 64 <220000000>;
3860 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3865 gpucc: clock-controller@3d90000 {
3866 compatible = "qcom,x1e80100-gpucc";
3871 #clock-cells = <1>;
3872 #reset-cells = <1>;
3873 #power-domain-cells = <1>;
3877 compatible = "qcom,x1e80100-smmu-500", "qcom,adreno-smmu",
3878 "qcom,smmu-500", "arm,mmu-500";
3880 #iommu-cells = <2>;
3881 #global-interrupts = <1>;
3912 clock-names = "hlos",
3916 power-domains = <&gpucc GPU_CX_GDSC>;
3917 dma-coherent;
3921 compatible = "qcom,x1e80100-gem-noc";
3924 qcom,bcm-voters = <&apps_bcm_voter>;
3926 #interconnect-cells = <2>;
3930 compatible = "qcom,x1e80100-nsp-noc";
3933 qcom,bcm-voters = <&apps_bcm_voter>;
3935 #interconnect-cells = <2>;
3939 compatible = "qcom,x1e80100-adsp-pas";
3942 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
3947 interrupt-names = "wdog",
3951 "stop-ack";
3954 clock-names = "xo";
3956 power-domains = <&rpmhpd RPMHPD_LCX>,
3958 power-domain-names = "lcx",
3964 memory-region = <&adspslpi_mem>,
3969 qcom,smem-states = <&smp2p_adsp_out 0>;
3970 qcom,smem-state-names = "stop";
3974 glink-edge {
3975 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
3982 qcom,remote-pid = <2>;
3986 qcom,glink-channels = "fastrpcglink-apps-dsp";
3988 qcom,non-secure-domain;
3989 #address-cells = <1>;
3990 #size-cells = <0>;
3992 compute-cb@3 {
3993 compatible = "qcom,fastrpc-compute-cb";
3997 dma-coherent;
4000 compute-cb@4 {
4001 compatible = "qcom,fastrpc-compute-cb";
4005 dma-coherent;
4008 compute-cb@5 {
4009 compatible = "qcom,fastrpc-compute-cb";
4013 dma-coherent;
4016 compute-cb@6 {
4017 compatible = "qcom,fastrpc-compute-cb";
4021 dma-coherent;
4024 compute-cb@7 {
4025 compatible = "qcom,fastrpc-compute-cb";
4029 dma-coherent;
4035 qcom,glink-channels = "adsp_apps";
4038 #address-cells = <1>;
4039 #size-cells = <0>;
4044 #sound-dai-cells = <0>;
4045 qcom,protection-domain = "avs/audio",
4049 compatible = "qcom,q6apm-lpass-dais";
4050 #sound-dai-cells = <1>;
4054 compatible = "qcom,q6apm-dais";
4063 qcom,protection-domain = "avs/audio",
4066 q6prmcc: clock-controller {
4067 compatible = "qcom,q6prm-lpass-clocks";
4068 #clock-cells = <2>;
4076 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
4082 clock-names = "mclk",
4087 #clock-cells = <0>;
4088 clock-output-names = "wsa2-mclk";
4089 #sound-dai-cells = <1>;
4090 sound-name-prefix = "WSA2";
4094 compatible = "qcom,soundwire-v2.0.0";
4097 clock-names = "iface";
4101 pinctrl-0 = <&wsa2_swr_active>;
4102 pinctrl-names = "default";
4104 reset-names = "swr_audio_cgcr";
4106 qcom,din-ports = <4>;
4107 qcom,dout-ports = <9>;
4109 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x3…
4110 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
4111 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4112 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4113 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4114 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
4115 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
4116 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4117 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4119 #address-cells = <2>;
4120 #size-cells = <0>;
4121 #sound-dai-cells = <1>;
4126 compatible = "qcom,x1e80100-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro";
4132 clock-names = "mclk",
4137 #clock-cells = <0>;
4138 clock-output-names = "mclk";
4139 #sound-dai-cells = <1>;
4143 compatible = "qcom,soundwire-v2.0.0";
4146 clock-names = "iface";
4150 pinctrl-0 = <&rx_swr_active>;
4151 pinctrl-names = "default";
4154 reset-names = "swr_audio_cgcr";
4155 qcom,din-ports = <1>;
4156 qcom,dout-ports = <11>;
4158 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4159 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4160 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4161 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4162 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4163 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4164 …qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff…
4165 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4166 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4168 #address-cells = <2>;
4169 #size-cells = <0>;
4170 #sound-dai-cells = <1>;
4175 compatible = "qcom,x1e80100-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro";
4181 clock-names = "mclk",
4186 #clock-cells = <0>;
4187 clock-output-names = "mclk";
4188 #sound-dai-cells = <1>;
4192 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
4198 clock-names = "mclk",
4203 #clock-cells = <0>;
4204 clock-output-names = "mclk";
4205 #sound-dai-cells = <1>;
4206 sound-name-prefix = "WSA";
4210 compatible = "qcom,soundwire-v2.0.0";
4213 clock-names = "iface";
4217 pinctrl-0 = <&wsa_swr_active>;
4218 pinctrl-names = "default";
4220 reset-names = "swr_audio_cgcr";
4222 qcom,din-ports = <4>;
4223 qcom,dout-ports = <9>;
4225 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x3…
4226 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
4227 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4228 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4229 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4230 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
4231 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
4232 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4233 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4235 #address-cells = <2>;
4236 #size-cells = <0>;
4237 #sound-dai-cells = <1>;
4241 lpass_audiocc: clock-controller@6b6c000 {
4242 compatible = "qcom,x1e80100-lpassaudiocc", "qcom,sc8280xp-lpassaudiocc";
4244 #clock-cells = <1>;
4245 #reset-cells = <1>;
4249 compatible = "qcom,soundwire-v2.0.0";
4252 clock-names = "iface";
4255 interrupt-names = "core", "wakeup";
4258 reset-names = "swr_audio_cgcr";
4260 pinctrl-0 = <&tx_swr_active>;
4261 pinctrl-names = "default";
4263 qcom,din-ports = <4>;
4264 qcom,dout-ports = <1>;
4266 qcom,ports-sinterval-low = /bits/ 8 <0x00 0x01 0x03 0x03 0x00>;
4267 qcom,ports-offset1 = /bits/ 8 <0x00 0x01 0x02 0x00 0x00>;
4268 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00 0xff>;
4269 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
4270 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
4271 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
4272 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
4273 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
4274 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x00 0x01 0xff>;
4276 #address-cells = <2>;
4277 #size-cells = <0>;
4278 #sound-dai-cells = <1>;
4283 compatible = "qcom,x1e80100-lpass-va-macro", "qcom,sm8550-lpass-va-macro";
4288 clock-names = "mclk",
4292 #clock-cells = <0>;
4293 clock-output-names = "fsgen";
4294 #sound-dai-cells = <1>;
4298 compatible = "qcom,x1e80100-lpass-lpi-pinctrl", "qcom,sm8550-lpass-lpi-pinctrl";
4304 clock-names = "core", "audio";
4306 gpio-controller;
4307 #gpio-cells = <2>;
4308 gpio-ranges = <&lpass_tlmm 0 0 23>;
4310 tx_swr_active: tx-swr-active-state {
4311 clk-pins {
4314 drive-strength = <2>;
4315 slew-rate = <1>;
4316 bias-disable;
4319 data-pins {
4322 drive-strength = <2>;
4323 slew-rate = <1>;
4324 bias-bus-hold;
4328 rx_swr_active: rx-swr-active-state {
4329 clk-pins {
4332 drive-strength = <2>;
4333 slew-rate = <1>;
4334 bias-disable;
4337 data-pins {
4340 drive-strength = <2>;
4341 slew-rate = <1>;
4342 bias-bus-hold;
4346 dmic01_default: dmic01-default-state {
4347 clk-pins {
4350 drive-strength = <8>;
4351 output-high;
4354 data-pins {
4357 drive-strength = <8>;
4358 input-enable;
4362 dmic23_default: dmic23-default-state {
4363 clk-pins {
4366 drive-strength = <8>;
4367 output-high;
4370 data-pins {
4373 drive-strength = <8>;
4374 input-enable;
4378 wsa_swr_active: wsa-swr-active-state {
4379 clk-pins {
4382 drive-strength = <2>;
4383 slew-rate = <1>;
4384 bias-disable;
4387 data-pins {
4390 drive-strength = <2>;
4391 slew-rate = <1>;
4392 bias-bus-hold;
4396 wsa2_swr_active: wsa2-swr-active-state {
4397 clk-pins {
4400 drive-strength = <2>;
4401 slew-rate = <1>;
4402 bias-disable;
4405 data-pins {
4408 drive-strength = <2>;
4409 slew-rate = <1>;
4410 bias-bus-hold;
4415 lpasscc: clock-controller@6ea0000 {
4416 compatible = "qcom,x1e80100-lpasscc", "qcom,sc8280xp-lpasscc";
4418 #clock-cells = <1>;
4419 #reset-cells = <1>;
4423 compatible = "qcom,x1e80100-lpass-ag-noc";
4426 qcom,bcm-voters = <&apps_bcm_voter>;
4428 #interconnect-cells = <2>;
4432 compatible = "qcom,x1e80100-lpass-lpiaon-noc";
4435 qcom,bcm-voters = <&apps_bcm_voter>;
4437 #interconnect-cells = <2>;
4441 compatible = "qcom,x1e80100-lpass-lpicx-noc";
4444 qcom,bcm-voters = <&apps_bcm_voter>;
4446 #interconnect-cells = <2>;
4450 compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5";
4455 interrupt-names = "hc_irq", "pwr_irq";
4460 clock-names = "iface", "core", "xo";
4462 qcom,dll-config = <0x0007642c>;
4463 qcom,ddr-config = <0x80040868>;
4464 power-domains = <&rpmhpd RPMHPD_CX>;
4465 operating-points-v2 = <&sdhc2_opp_table>;
4471 interconnect-names = "sdhc-ddr", "cpu-sdhc";
4472 bus-width = <4>;
4473 dma-coherent;
4477 sdhc2_opp_table: opp-table {
4478 compatible = "operating-points-v2";
4480 opp-19200000 {
4481 opp-hz = /bits/ 64 <19200000>;
4482 required-opps = <&rpmhpd_opp_min_svs>;
4485 opp-50000000 {
4486 opp-hz = /bits/ 64 <50000000>;
4487 required-opps = <&rpmhpd_opp_low_svs>;
4490 opp-100000000 {
4491 opp-hz = /bits/ 64 <100000000>;
4492 required-opps = <&rpmhpd_opp_svs>;
4495 opp-202000000 {
4496 opp-hz = /bits/ 64 <202000000>;
4497 required-opps = <&rpmhpd_opp_svs_l1>;
4503 compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5";
4508 interrupt-names = "hc_irq", "pwr_irq";
4513 clock-names = "iface", "core", "xo";
4515 qcom,dll-config = <0x0007642c>;
4516 qcom,ddr-config = <0x80040868>;
4517 power-domains = <&rpmhpd RPMHPD_CX>;
4518 operating-points-v2 = <&sdhc4_opp_table>;
4524 interconnect-names = "sdhc-ddr", "cpu-sdhc";
4525 bus-width = <4>;
4526 dma-coherent;
4530 sdhc4_opp_table: opp-table {
4531 compatible = "operating-points-v2";
4533 opp-19200000 {
4534 opp-hz = /bits/ 64 <19200000>;
4535 required-opps = <&rpmhpd_opp_min_svs>;
4538 opp-50000000 {
4539 opp-hz = /bits/ 64 <50000000>;
4540 required-opps = <&rpmhpd_opp_low_svs>;
4543 opp-100000000 {
4544 opp-hz = /bits/ 64 <100000000>;
4545 required-opps = <&rpmhpd_opp_svs>;
4548 opp-202000000 {
4549 opp-hz = /bits/ 64 <202000000>;
4550 required-opps = <&rpmhpd_opp_svs_l1>;
4556 compatible = "qcom,x1e80100-snps-eusb2-phy",
4557 "qcom,sm8550-snps-eusb2-phy";
4559 #phy-cells = <0>;
4562 clock-names = "ref";
4570 compatible = "qcom,x1e80100-snps-eusb2-phy",
4571 "qcom,sm8550-snps-eusb2-phy";
4573 #phy-cells = <0>;
4576 clock-names = "ref";
4584 compatible = "qcom,x1e80100-snps-eusb2-phy",
4585 "qcom,sm8550-snps-eusb2-phy";
4587 #phy-cells = <0>;
4590 clock-names = "ref";
4598 compatible = "qcom,x1e80100-qmp-usb3-uni-phy";
4605 clock-names = "aux",
4612 reset-names = "phy",
4615 power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>;
4617 #clock-cells = <0>;
4618 clock-output-names = "usb_mp_phy0_pipe_clk";
4620 #phy-cells = <0>;
4626 compatible = "qcom,x1e80100-qmp-usb3-uni-phy";
4633 clock-names = "aux",
4640 reset-names = "phy",
4643 power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>;
4645 #clock-cells = <0>;
4646 clock-output-names = "usb_mp_phy1_pipe_clk";
4648 #phy-cells = <0>;
4654 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
4666 clock-names = "cfg_noc",
4676 assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>,
4678 assigned-clock-rates = <19200000>,
4681 interrupts-extended = <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
4685 interrupt-names = "pwr_event",
4690 power-domains = <&gcc GCC_USB30_TERT_GDSC>;
4691 required-opps = <&rpmhpd_opp_nom>;
4699 interconnect-names = "usb-ddr",
4700 "apps-usb";
4702 wakeup-source;
4704 #address-cells = <2>;
4705 #size-cells = <2>;
4720 phy-names = "usb2-phy",
4721 "usb3-phy";
4726 snps,dis-u1-entry-quirk;
4727 snps,dis-u2-entry-quirk;
4729 dma-coherent;
4732 #address-cells = <1>;
4733 #size-cells = <0>;
4746 remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>;
4754 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
4756 #address-cells = <2>;
4757 #size-cells = <2>;
4769 clock-names = "cfg_noc",
4779 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
4781 assigned-clock-rates = <19200000>, <200000000>;
4783 interrupts-extended = <&intc GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
4786 interrupt-names = "pwr_event",
4790 power-domains = <&gcc GCC_USB20_PRIM_GDSC>;
4791 required-opps = <&rpmhpd_opp_nom>;
4799 interconnect-names = "usb-ddr",
4800 "apps-usb";
4802 wakeup-source;
4812 phy-names = "usb2-phy";
4813 maximum-speed = "high-speed";
4814 snps,dis-u1-entry-quirk;
4815 snps,dis-u2-entry-quirk;
4818 #address-cells = <1>;
4819 #size-cells = <0>;
4832 compatible = "qcom,x1e80100-dwc3-mp", "qcom,dwc3";
4844 clock-names = "cfg_noc",
4854 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
4856 assigned-clock-rates = <19200000>,
4859 interrupts-extended = <&intc GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
4869 interrupt-names = "pwr_event_1", "pwr_event_2",
4875 power-domains = <&gcc GCC_USB30_MP_GDSC>;
4876 required-opps = <&rpmhpd_opp_nom>;
4884 interconnect-names = "usb-ddr",
4885 "apps-usb";
4887 wakeup-source;
4889 #address-cells = <2>;
4890 #size-cells = <2>;
4905 phy-names = "usb2-0", "usb3-0",
4906 "usb2-1", "usb3-1";
4912 snps,dis-u1-entry-quirk;
4913 snps,dis-u2-entry-quirk;
4915 dma-coherent;
4920 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
4932 clock-names = "cfg_noc",
4942 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4944 assigned-clock-rates = <19200000>,
4947 interrupts-extended = <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
4951 interrupt-names = "pwr_event",
4956 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
4957 required-opps = <&rpmhpd_opp_nom>;
4961 wakeup-source;
4963 #address-cells = <2>;
4964 #size-cells = <2>;
4979 phy-names = "usb2-phy",
4980 "usb3-phy";
4985 snps,dis-u1-entry-quirk;
4986 snps,dis-u2-entry-quirk;
4988 dma-coherent;
4991 #address-cells = <1>;
4992 #size-cells = <0>;
5005 remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>;
5013 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
5025 clock-names = "cfg_noc",
5035 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
5037 assigned-clock-rates = <19200000>,
5040 interrupts-extended = <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
5044 interrupt-names = "pwr_event",
5049 power-domains = <&gcc GCC_USB30_SEC_GDSC>;
5050 required-opps = <&rpmhpd_opp_nom>;
5058 interconnect-names = "usb-ddr",
5059 "apps-usb";
5061 wakeup-source;
5063 #address-cells = <2>;
5064 #size-cells = <2>;
5079 phy-names = "usb2-phy",
5080 "usb3-phy";
5085 snps,dis-u1-entry-quirk;
5086 snps,dis-u2-entry-quirk;
5088 dma-coherent;
5091 #address-cells = <1>;
5092 #size-cells = <0>;
5105 remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>;
5112 mdss: display-subsystem@ae00000 {
5113 compatible = "qcom,x1e80100-mdss";
5115 reg-names = "mdss";
5131 interconnect-names = "mdp0-mem",
5132 "mdp1-mem",
5133 "cpu-cfg";
5135 power-domains = <&dispcc MDSS_GDSC>;
5139 interrupt-controller;
5140 #interrupt-cells = <1>;
5142 #address-cells = <2>;
5143 #size-cells = <2>;
5148 mdss_mdp: display-controller@ae01000 {
5149 compatible = "qcom,x1e80100-dpu";
5152 reg-names = "mdp",
5155 interrupts-extended = <&mdss 0>;
5162 clock-names = "nrt_bus",
5168 operating-points-v2 = <&mdp_opp_table>;
5170 power-domains = <&rpmhpd RPMHPD_MMCX>;
5173 #address-cells = <1>;
5174 #size-cells = <0>;
5180 remote-endpoint = <&mdss_dp0_in>;
5188 remote-endpoint = <&mdss_dp1_in>;
5196 remote-endpoint = <&mdss_dp3_in>;
5204 remote-endpoint = <&mdss_dp2_in>;
5209 mdp_opp_table: opp-table {
5210 compatible = "operating-points-v2";
5212 opp-200000000 {
5213 opp-hz = /bits/ 64 <200000000>;
5214 required-opps = <&rpmhpd_opp_low_svs>;
5217 opp-325000000 {
5218 opp-hz = /bits/ 64 <325000000>;
5219 required-opps = <&rpmhpd_opp_svs>;
5222 opp-375000000 {
5223 opp-hz = /bits/ 64 <375000000>;
5224 required-opps = <&rpmhpd_opp_svs_l1>;
5227 opp-514000000 {
5228 opp-hz = /bits/ 64 <514000000>;
5229 required-opps = <&rpmhpd_opp_nom>;
5232 opp-575000000 {
5233 opp-hz = /bits/ 64 <575000000>;
5234 required-opps = <&rpmhpd_opp_nom_l1>;
5239 mdss_dp0: displayport-controller@ae90000 {
5240 compatible = "qcom,x1e80100-dp";
5247 interrupts-extended = <&mdss 12>;
5254 clock-names = "core_iface",
5260 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
5262 assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
5265 operating-points-v2 = <&mdss_dp0_opp_table>;
5267 power-domains = <&rpmhpd RPMHPD_MMCX>;
5270 phy-names = "dp";
5272 #sound-dai-cells = <0>;
5277 #address-cells = <1>;
5278 #size-cells = <0>;
5284 remote-endpoint = <&mdss_intf0_out>;
5292 remote-endpoint = <&usb_1_ss0_qmpphy_dp_in>;
5297 mdss_dp0_opp_table: opp-table {
5298 compatible = "operating-points-v2";
5300 opp-160000000 {
5301 opp-hz = /bits/ 64 <160000000>;
5302 required-opps = <&rpmhpd_opp_low_svs>;
5305 opp-270000000 {
5306 opp-hz = /bits/ 64 <270000000>;
5307 required-opps = <&rpmhpd_opp_svs>;
5310 opp-540000000 {
5311 opp-hz = /bits/ 64 <540000000>;
5312 required-opps = <&rpmhpd_opp_svs_l1>;
5315 opp-810000000 {
5316 opp-hz = /bits/ 64 <810000000>;
5317 required-opps = <&rpmhpd_opp_nom>;
5322 mdss_dp1: displayport-controller@ae98000 {
5323 compatible = "qcom,x1e80100-dp";
5330 interrupts-extended = <&mdss 13>;
5337 clock-names = "core_iface",
5343 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
5345 assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
5348 operating-points-v2 = <&mdss_dp1_opp_table>;
5350 power-domains = <&rpmhpd RPMHPD_MMCX>;
5353 phy-names = "dp";
5355 #sound-dai-cells = <0>;
5360 #address-cells = <1>;
5361 #size-cells = <0>;
5367 remote-endpoint = <&mdss_intf4_out>;
5375 remote-endpoint = <&usb_1_ss1_qmpphy_dp_in>;
5380 mdss_dp1_opp_table: opp-table {
5381 compatible = "operating-points-v2";
5383 opp-160000000 {
5384 opp-hz = /bits/ 64 <160000000>;
5385 required-opps = <&rpmhpd_opp_low_svs>;
5388 opp-270000000 {
5389 opp-hz = /bits/ 64 <270000000>;
5390 required-opps = <&rpmhpd_opp_svs>;
5393 opp-540000000 {
5394 opp-hz = /bits/ 64 <540000000>;
5395 required-opps = <&rpmhpd_opp_svs_l1>;
5398 opp-810000000 {
5399 opp-hz = /bits/ 64 <810000000>;
5400 required-opps = <&rpmhpd_opp_nom>;
5405 mdss_dp2: displayport-controller@ae9a000 {
5406 compatible = "qcom,x1e80100-dp";
5413 interrupts-extended = <&mdss 14>;
5420 clock-names = "core_iface",
5426 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
5428 assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>,
5431 operating-points-v2 = <&mdss_dp2_opp_table>;
5433 power-domains = <&rpmhpd RPMHPD_MMCX>;
5436 phy-names = "dp";
5438 #sound-dai-cells = <0>;
5443 #address-cells = <1>;
5444 #size-cells = <0>;
5449 remote-endpoint = <&mdss_intf6_out>;
5457 remote-endpoint = <&usb_1_ss2_qmpphy_dp_in>;
5462 mdss_dp2_opp_table: opp-table {
5463 compatible = "operating-points-v2";
5465 opp-160000000 {
5466 opp-hz = /bits/ 64 <160000000>;
5467 required-opps = <&rpmhpd_opp_low_svs>;
5470 opp-270000000 {
5471 opp-hz = /bits/ 64 <270000000>;
5472 required-opps = <&rpmhpd_opp_svs>;
5475 opp-540000000 {
5476 opp-hz = /bits/ 64 <540000000>;
5477 required-opps = <&rpmhpd_opp_svs_l1>;
5480 opp-810000000 {
5481 opp-hz = /bits/ 64 <810000000>;
5482 required-opps = <&rpmhpd_opp_nom>;
5487 mdss_dp3: displayport-controller@aea0000 {
5488 compatible = "qcom,x1e80100-dp";
5495 interrupts-extended = <&mdss 15>;
5502 clock-names = "core_iface",
5508 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
5510 assigned-clock-parents = <&mdss_dp3_phy 0>,
5513 operating-points-v2 = <&mdss_dp3_opp_table>;
5515 power-domains = <&rpmhpd RPMHPD_MMCX>;
5518 phy-names = "dp";
5520 #sound-dai-cells = <0>;
5525 #address-cells = <1>;
5526 #size-cells = <0>;
5532 remote-endpoint = <&mdss_intf5_out>;
5541 mdss_dp3_opp_table: opp-table {
5542 compatible = "operating-points-v2";
5544 opp-160000000 {
5545 opp-hz = /bits/ 64 <160000000>;
5546 required-opps = <&rpmhpd_opp_low_svs>;
5549 opp-270000000 {
5550 opp-hz = /bits/ 64 <270000000>;
5551 required-opps = <&rpmhpd_opp_svs>;
5554 opp-540000000 {
5555 opp-hz = /bits/ 64 <540000000>;
5556 required-opps = <&rpmhpd_opp_svs_l1>;
5559 opp-810000000 {
5560 opp-hz = /bits/ 64 <810000000>;
5561 required-opps = <&rpmhpd_opp_nom>;
5569 compatible = "qcom,x1e80100-dp-phy";
5577 clock-names = "aux",
5580 power-domains = <&rpmhpd RPMHPD_MX>;
5582 #clock-cells = <1>;
5583 #phy-cells = <0>;
5589 compatible = "qcom,x1e80100-dp-phy";
5597 clock-names = "aux",
5600 power-domains = <&rpmhpd RPMHPD_MX>;
5602 #clock-cells = <1>;
5603 #phy-cells = <0>;
5608 dispcc: clock-controller@af00000 {
5609 compatible = "qcom,x1e80100-dispcc";
5627 power-domains = <&rpmhpd RPMHPD_MMCX>;
5628 required-opps = <&rpmhpd_opp_low_svs>;
5629 #clock-cells = <1>;
5630 #reset-cells = <1>;
5631 #power-domain-cells = <1>;
5634 pdc: interrupt-controller@b220000 {
5635 compatible = "qcom,x1e80100-pdc", "qcom,pdc";
5638 qcom,pdc-ranges = <0 480 42>, <42 251 5>,
5641 #interrupt-cells = <2>;
5642 interrupt-parent = <&intc>;
5643 interrupt-controller;
5646 aoss_qmp: power-management@c300000 {
5647 compatible = "qcom,x1e80100-aoss-qmp", "qcom,aoss-qmp";
5649 interrupt-parent = <&ipcc>;
5650 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
5654 #clock-cells = <0>;
5658 compatible = "qcom,rpmh-stats";
5663 compatible = "qcom,x1e80100-spmi-pmic-arb";
5667 reg-names = "core", "chnls", "obsrvr";
5672 #address-cells = <2>;
5673 #size-cells = <2>;
5679 reg-names = "cnfg", "intr";
5681 interrupt-names = "periph_irq";
5682 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5683 interrupt-controller;
5684 #interrupt-cells = <4>;
5686 #address-cells = <2>;
5687 #size-cells = <0>;
5693 reg-names = "cnfg", "intr";
5695 interrupt-names = "periph_irq";
5696 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
5697 interrupt-controller;
5698 #interrupt-cells = <4>;
5700 #address-cells = <2>;
5701 #size-cells = <0>;
5706 compatible = "qcom,x1e80100-tlmm";
5711 gpio-controller;
5712 #gpio-cells = <2>;
5714 interrupt-controller;
5715 #interrupt-cells = <2>;
5717 gpio-ranges = <&tlmm 0 0 239>;
5718 wakeup-parent = <&pdc>;
5720 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
5724 drive-strength = <2>;
5725 bias-pull-up = <2200>;
5728 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
5732 drive-strength = <2>;
5733 bias-pull-up = <2200>;
5736 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
5740 drive-strength = <2>;
5741 bias-pull-up = <2200>;
5744 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
5748 drive-strength = <2>;
5749 bias-pull-up = <2200>;
5752 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
5756 drive-strength = <2>;
5757 bias-pull-up = <2200>;
5760 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
5764 drive-strength = <2>;
5765 bias-pull-up = <2200>;
5768 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
5772 drive-strength = <2>;
5773 bias-pull-up = <2200>;
5776 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
5780 drive-strength = <2>;
5781 bias-pull-up = <2200>;
5784 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
5788 drive-strength = <2>;
5789 bias-pull-up = <2200>;
5792 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
5796 drive-strength = <2>;
5797 bias-pull-up = <2200>;
5800 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
5804 drive-strength = <2>;
5805 bias-pull-up = <2200>;
5808 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
5812 drive-strength = <2>;
5813 bias-pull-up = <2200>;
5816 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
5820 drive-strength = <2>;
5821 bias-pull-up = <2200>;
5824 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
5828 drive-strength = <2>;
5829 bias-pull-up = <2200>;
5832 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
5836 drive-strength = <2>;
5837 bias-pull-up = <2200>;
5840 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
5844 drive-strength = <2>;
5845 bias-pull-up = <2200>;
5848 qup_i2c16_data_clk: qup-i2c16-data-clk-state {
5852 drive-strength = <2>;
5853 bias-pull-up = <2200>;
5856 qup_i2c17_data_clk: qup-i2c17-data-clk-state {
5860 drive-strength = <2>;
5861 bias-pull-up = <2200>;
5864 qup_i2c18_data_clk: qup-i2c18-data-clk-state {
5868 drive-strength = <2>;
5869 bias-pull-up = <2200>;
5872 qup_i2c19_data_clk: qup-i2c19-data-clk-state {
5876 drive-strength = <2>;
5877 bias-pull-up = <2200>;
5880 qup_i2c20_data_clk: qup-i2c20-data-clk-state {
5884 drive-strength = <2>;
5885 bias-pull-up = <2200>;
5888 qup_i2c21_data_clk: qup-i2c21-data-clk-state {
5892 drive-strength = <2>;
5893 bias-pull-up = <2200>;
5896 qup_i2c22_data_clk: qup-i2c22-data-clk-state {
5900 drive-strength = <2>;
5901 bias-pull-up = <2200>;
5904 qup_i2c23_data_clk: qup-i2c23-data-clk-state {
5908 drive-strength = <2>;
5909 bias-pull-up = <2200>;
5912 qup_spi0_cs: qup-spi0-cs-state {
5915 drive-strength = <6>;
5916 bias-disable;
5919 qup_spi0_data_clk: qup-spi0-data-clk-state {
5923 drive-strength = <6>;
5924 bias-disable;
5927 qup_spi1_cs: qup-spi1-cs-state {
5930 drive-strength = <6>;
5931 bias-disable;
5934 qup_spi1_data_clk: qup-spi1-data-clk-state {
5938 drive-strength = <6>;
5939 bias-disable;
5942 qup_spi2_cs: qup-spi2-cs-state {
5945 drive-strength = <6>;
5946 bias-disable;
5949 qup_spi2_data_clk: qup-spi2-data-clk-state {
5953 drive-strength = <6>;
5954 bias-disable;
5957 qup_spi3_cs: qup-spi3-cs-state {
5960 drive-strength = <6>;
5961 bias-disable;
5964 qup_spi3_data_clk: qup-spi3-data-clk-state {
5968 drive-strength = <6>;
5969 bias-disable;
5972 qup_spi4_cs: qup-spi4-cs-state {
5975 drive-strength = <6>;
5976 bias-disable;
5979 qup_spi4_data_clk: qup-spi4-data-clk-state {
5983 drive-strength = <6>;
5984 bias-disable;
5987 qup_spi5_cs: qup-spi5-cs-state {
5990 drive-strength = <6>;
5991 bias-disable;
5994 qup_spi5_data_clk: qup-spi5-data-clk-state {
5998 drive-strength = <6>;
5999 bias-disable;
6002 qup_spi6_cs: qup-spi6-cs-state {
6005 drive-strength = <6>;
6006 bias-disable;
6009 qup_spi6_data_clk: qup-spi6-data-clk-state {
6013 drive-strength = <6>;
6014 bias-disable;
6017 qup_spi7_cs: qup-spi7-cs-state {
6020 drive-strength = <6>;
6021 bias-disable;
6024 qup_spi7_data_clk: qup-spi7-data-clk-state {
6028 drive-strength = <6>;
6029 bias-disable;
6032 qup_spi8_cs: qup-spi8-cs-state {
6035 drive-strength = <6>;
6036 bias-disable;
6039 qup_spi8_data_clk: qup-spi8-data-clk-state {
6043 drive-strength = <6>;
6044 bias-disable;
6047 qup_spi9_cs: qup-spi9-cs-state {
6050 drive-strength = <6>;
6051 bias-disable;
6054 qup_spi9_data_clk: qup-spi9-data-clk-state {
6058 drive-strength = <6>;
6059 bias-disable;
6062 qup_spi10_cs: qup-spi10-cs-state {
6065 drive-strength = <6>;
6066 bias-disable;
6069 qup_spi10_data_clk: qup-spi10-data-clk-state {
6073 drive-strength = <6>;
6074 bias-disable;
6077 qup_spi11_cs: qup-spi11-cs-state {
6080 drive-strength = <6>;
6081 bias-disable;
6084 qup_spi11_data_clk: qup-spi11-data-clk-state {
6088 drive-strength = <6>;
6089 bias-disable;
6092 qup_spi12_cs: qup-spi12-cs-state {
6095 drive-strength = <6>;
6096 bias-disable;
6099 qup_spi12_data_clk: qup-spi12-data-clk-state {
6103 drive-strength = <6>;
6104 bias-disable;
6107 qup_spi13_cs: qup-spi13-cs-state {
6110 drive-strength = <6>;
6111 bias-disable;
6114 qup_spi13_data_clk: qup-spi13-data-clk-state {
6118 drive-strength = <6>;
6119 bias-disable;
6122 qup_spi14_cs: qup-spi14-cs-state {
6125 drive-strength = <6>;
6126 bias-disable;
6129 qup_spi14_data_clk: qup-spi14-data-clk-state {
6133 drive-strength = <6>;
6134 bias-disable;
6137 qup_spi15_cs: qup-spi15-cs-state {
6140 drive-strength = <6>;
6141 bias-disable;
6144 qup_spi15_data_clk: qup-spi15-data-clk-state {
6148 drive-strength = <6>;
6149 bias-disable;
6152 qup_spi16_cs: qup-spi16-cs-state {
6155 drive-strength = <6>;
6156 bias-disable;
6159 qup_spi16_data_clk: qup-spi16-data-clk-state {
6163 drive-strength = <6>;
6164 bias-disable;
6167 qup_spi17_cs: qup-spi17-cs-state {
6170 drive-strength = <6>;
6171 bias-disable;
6174 qup_spi17_data_clk: qup-spi17-data-clk-state {
6178 drive-strength = <6>;
6179 bias-disable;
6182 qup_spi18_cs: qup-spi18-cs-state {
6185 drive-strength = <6>;
6186 bias-disable;
6189 qup_spi18_data_clk: qup-spi18-data-clk-state {
6193 drive-strength = <6>;
6194 bias-disable;
6197 qup_spi19_cs: qup-spi19-cs-state {
6200 drive-strength = <6>;
6201 bias-disable;
6204 qup_spi19_data_clk: qup-spi19-data-clk-state {
6208 drive-strength = <6>;
6209 bias-disable;
6212 qup_spi20_cs: qup-spi20-cs-state {
6215 drive-strength = <6>;
6216 bias-disable;
6219 qup_spi20_data_clk: qup-spi20-data-clk-state {
6223 drive-strength = <6>;
6224 bias-disable;
6227 qup_spi21_cs: qup-spi21-cs-state {
6230 drive-strength = <6>;
6231 bias-disable;
6234 qup_spi21_data_clk: qup-spi21-data-clk-state {
6238 drive-strength = <6>;
6239 bias-disable;
6242 qup_spi22_cs: qup-spi22-cs-state {
6245 drive-strength = <6>;
6246 bias-disable;
6249 qup_spi22_data_clk: qup-spi22-data-clk-state {
6253 drive-strength = <6>;
6254 bias-disable;
6257 qup_spi23_cs: qup-spi23-cs-state {
6260 drive-strength = <6>;
6261 bias-disable;
6264 qup_spi23_data_clk: qup-spi23-data-clk-state {
6268 drive-strength = <6>;
6269 bias-disable;
6272 qup_uart2_default: qup-uart2-default-state {
6273 cts-pins {
6276 drive-strength = <2>;
6277 bias-disable;
6280 rts-pins {
6283 drive-strength = <2>;
6284 bias-disable;
6287 tx-pins {
6290 drive-strength = <2>;
6291 bias-disable;
6294 rx-pins {
6297 drive-strength = <2>;
6298 bias-disable;
6302 qup_uart14_default: qup-uart14-default-state {
6303 cts-pins {
6306 bias-bus-hold;
6309 rts-pins {
6312 drive-strength = <2>;
6313 bias-disable;
6316 tx-pins {
6319 drive-strength = <2>;
6320 bias-disable;
6323 rx-pins {
6326 bias-pull-up;
6330 qup_uart21_default: qup-uart21-default-state {
6331 tx-pins {
6334 drive-strength = <2>;
6335 bias-disable;
6338 rx-pins {
6341 drive-strength = <2>;
6342 bias-disable;
6346 sdc2_default: sdc2-default-state {
6347 clk-pins {
6349 drive-strength = <16>;
6350 bias-disable;
6353 cmd-pins {
6355 drive-strength = <10>;
6356 bias-pull-up;
6359 data-pins {
6361 drive-strength = <10>;
6362 bias-pull-up;
6366 sdc2_sleep: sdc2-sleep-state {
6367 clk-pins {
6369 drive-strength = <2>;
6370 bias-disable;
6373 cmd-pins {
6375 drive-strength = <2>;
6376 bias-pull-up;
6379 data-pins {
6381 drive-strength = <2>;
6382 bias-pull-up;
6388 compatible = "arm,coresight-stm", "arm,primecell";
6391 reg-names = "stm-base",
6392 "stm-stimulus-base";
6395 clock-names = "apb_pclk";
6397 out-ports {
6400 remote-endpoint = <&funnel0_in7>;
6407 compatible = "qcom,coresight-tpdm", "arm,primecell";
6411 clock-names = "apb_pclk";
6413 qcom,cmb-element-bits = <32>;
6414 qcom,cmb-msrs-num = <32>;
6417 out-ports {
6420 remote-endpoint = <&qdss_tpda_in0>;
6427 compatible = "qcom,coresight-tpda", "arm,primecell";
6431 clock-names = "apb_pclk";
6433 in-ports {
6434 #address-cells = <1>;
6435 #size-cells = <0>;
6441 remote-endpoint = <&dcc_tpdm_out>;
6449 remote-endpoint = <&qdss_tpdm_out>;
6454 out-ports {
6457 remote-endpoint = <&funnel0_in6>;
6464 compatible = "qcom,coresight-tpdm", "arm,primecell";
6468 clock-names = "apb_pclk";
6470 qcom,cmb-element-bits = <32>;
6471 qcom,cmb-msrs-num = <32>;
6473 out-ports {
6476 remote-endpoint = <&qdss_tpda_in1>;
6483 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
6487 clock-names = "apb_pclk";
6489 in-ports {
6490 #address-cells = <1>;
6491 #size-cells = <0>;
6497 remote-endpoint = <&qdss_tpda_out>;
6505 remote-endpoint = <&stm_out>;
6510 out-ports {
6513 remote-endpoint = <&qdss_funnel_in0>;
6520 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
6524 clock-names = "apb_pclk";
6526 in-ports {
6527 #address-cells = <1>;
6528 #size-cells = <0>;
6534 remote-endpoint = <&tmess_funnel_out>;
6542 remote-endpoint = <&dlst_funnel_out>;
6550 remote-endpoint = <&dlct1_funnel_out>;
6555 out-ports {
6558 remote-endpoint = <&qdss_funnel_in1>;
6565 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
6569 clock-names = "apb_pclk";
6571 in-ports {
6572 #address-cells = <1>;
6573 #size-cells = <0>;
6579 remote-endpoint = <&funnel0_out>;
6587 remote-endpoint = <&funnel1_out>;
6592 out-ports {
6595 remote-endpoint = <&aoss_funnel_in7>;
6602 compatible = "qcom,coresight-tpdm", "arm,primecell";
6606 clock-names = "apb_pclk";
6608 qcom,cmb-element-bits = <64>;
6609 qcom,cmb-msrs-num = <32>;
6611 out-ports {
6614 remote-endpoint = <&dlct2_tpda_in15>;
6621 compatible = "qcom,coresight-tpdm", "arm,primecell";
6625 clock-names = "apb_pclk";
6627 qcom,dsb-element-bits = <32>;
6628 qcom,dsb-msrs-num = <32>;
6630 out-ports {
6633 remote-endpoint = <&dlct1_tpda_in21>;
6640 compatible = "qcom,coresight-tpdm", "arm,primecell";
6644 clock-names = "apb_pclk";
6646 qcom,cmb-element-bits = <32>;
6647 qcom,cmb-msrs-num = <32>;
6649 out-ports {
6652 remote-endpoint = <&dlct1_tpda_in19>;
6659 compatible = "qcom,coresight-tpdm", "arm,primecell";
6663 clock-names = "apb_pclk";
6665 qcom,dsb-element-bits = <32>;
6666 qcom,dsb-msrs-num = <32>;
6668 out-ports {
6671 remote-endpoint = <&lpass_cx_funnel_in0>;
6678 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
6682 clock-names = "apb_pclk";
6684 in-ports {
6687 remote-endpoint = <&lpass_cx_tpdm_out>;
6692 out-ports {
6695 remote-endpoint = <&dlct1_tpda_in4>;
6702 compatible = "arm,coresight-cti", "arm,primecell";
6706 clock-names = "apb_pclk";
6710 compatible = "qcom,coresight-tpdm", "arm,primecell";
6714 clock-names = "apb_pclk";
6716 qcom,dsb-element-bits = <32>;
6717 qcom,dsb-msrs-num = <32>;
6720 out-ports {
6723 remote-endpoint = <&dlct1_tpda_in20>;
6730 compatible = "qcom,coresight-tpdm", "arm,primecell";
6734 clock-names = "apb_pclk";
6736 qcom,dsb-element-bits = <32>;
6737 qcom,dsb-msrs-num = <32>;
6740 out-ports {
6743 remote-endpoint = <&dlst_tpda_in8>;
6750 compatible = "qcom,coresight-tpdm", "arm,primecell";
6754 clock-names = "apb_pclk";
6756 qcom,cmb-element-bits = <64>;
6757 qcom,cmb-msrs-num = <32>;
6759 out-ports {
6762 remote-endpoint = <&dlst_tpda_in9>;
6769 compatible = "qcom,coresight-tpda", "arm,primecell";
6773 clock-names = "apb_pclk";
6775 in-ports {
6776 #address-cells = <1>;
6777 #size-cells = <0>;
6783 remote-endpoint = <&dlst_tpdm0_out>;
6791 remote-endpoint = <&dlst_tpdm1_out>;
6796 out-ports {
6799 remote-endpoint = <&dlst_funnel_in0>;
6806 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
6810 clock-names = "apb_pclk";
6812 in-ports {
6815 remote-endpoint = <&dlst_tpda_out>;
6820 out-ports {
6823 remote-endpoint = <&funnel1_in5>;
6830 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
6834 clock-names = "apb_pclk";
6836 in-ports {
6837 #address-cells = <1>;
6838 #size-cells = <0>;
6844 remote-endpoint = <&ddr_lpi_funnel_out>;
6852 remote-endpoint = <&aoss_tpda_out>;
6860 remote-endpoint = <&qdss_funnel_out>;
6865 out-ports {
6868 remote-endpoint = <&etf0_in>;
6875 compatible = "arm,coresight-tmc", "arm,primecell";
6879 clock-names = "apb_pclk";
6881 in-ports {
6884 remote-endpoint = <&aoss_funnel_out>;
6889 out-ports {
6892 remote-endpoint = <&swao_rep_in>;
6899 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
6903 clock-names = "apb_pclk";
6905 in-ports {
6908 remote-endpoint = <&etf0_out>;
6913 out-ports {
6916 remote-endpoint = <&eud_in>;
6923 compatible = "qcom,coresight-tpda", "arm,primecell";
6927 clock-names = "apb_pclk";
6929 in-ports {
6930 #address-cells = <1>;
6931 #size-cells = <0>;
6937 remote-endpoint = <&aoss_tpdm0_out>;
6945 remote-endpoint = <&aoss_tpdm1_out>;
6953 remote-endpoint = <&aoss_tpdm2_out>;
6961 remote-endpoint = <&aoss_tpdm3_out>;
6969 remote-endpoint = <&aoss_tpdm4_out>;
6974 out-ports {
6977 remote-endpoint = <&aoss_funnel_in6>;
6984 compatible = "qcom,coresight-tpdm", "arm,primecell";
6988 clock-names = "apb_pclk";
6990 qcom,cmb-element-bits = <64>;
6991 qcom,cmb-msrs-num = <32>;
6993 out-ports {
6996 remote-endpoint = <&aoss_tpda_in0>;
7003 compatible = "qcom,coresight-tpdm", "arm,primecell";
7007 clock-names = "apb_pclk";
7009 qcom,cmb-element-bits = <64>;
7010 qcom,cmb-msrs-num = <32>;
7012 out-ports {
7015 remote-endpoint = <&aoss_tpda_in1>;
7022 compatible = "qcom,coresight-tpdm", "arm,primecell";
7026 clock-names = "apb_pclk";
7028 qcom,cmb-element-bits = <64>;
7029 qcom,cmb-msrs-num = <32>;
7031 out-ports {
7034 remote-endpoint = <&aoss_tpda_in2>;
7041 compatible = "qcom,coresight-tpdm", "arm,primecell";
7045 clock-names = "apb_pclk";
7047 qcom,cmb-element-bits = <64>;
7048 qcom,cmb-msrs-num = <32>;
7050 out-ports {
7053 remote-endpoint = <&aoss_tpda_in3>;
7060 compatible = "qcom,coresight-tpdm", "arm,primecell";
7064 clock-names = "apb_pclk";
7066 qcom,dsb-element-bits = <32>;
7067 qcom,dsb-msrs-num = <32>;
7069 out-ports {
7072 remote-endpoint = <&aoss_tpda_in4>;
7079 compatible = "qcom,coresight-tpdm", "arm,primecell";
7083 clock-names = "apb_pclk";
7085 qcom,dsb-element-bits = <32>;
7086 qcom,dsb-msrs-num = <32>;
7089 out-ports {
7092 remote-endpoint = <&ddr_lpi_tpda_in>;
7099 compatible = "qcom,coresight-tpda", "arm,primecell";
7103 clock-names = "apb_pclk";
7106 in-ports {
7109 remote-endpoint = <&lpicc_tpdm_out>;
7114 out-ports {
7117 remote-endpoint = <&ddr_lpi_funnel_in0>;
7124 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
7128 clock-names = "apb_pclk";
7131 in-ports {
7134 remote-endpoint = <&ddr_lpi_tpda_out>;
7139 out-ports {
7142 remote-endpoint = <&aoss_funnel_in3>;
7149 compatible = "qcom,coresight-tpdm", "arm,primecell";
7153 clock-names = "apb_pclk";
7155 qcom,dsb-element-bits = <32>;
7156 qcom,dsb-msrs-num = <32>;
7158 out-ports {
7161 remote-endpoint = <&mm_funnel_in4>;
7168 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
7172 clock-names = "apb_pclk";
7174 in-ports {
7175 #address-cells = <1>;
7176 #size-cells = <0>;
7182 remote-endpoint = <&mm_tpdm_out>;
7187 out-ports {
7190 remote-endpoint = <&dlct2_tpda_in4>;
7197 compatible = "qcom,coresight-tpdm", "arm,primecell";
7201 clock-names = "apb_pclk";
7203 qcom,dsb-element-bits = <32>;
7204 qcom,dsb-msrs-num = <32>;
7206 out-ports {
7209 remote-endpoint = <&dlct1_tpda_in26>;
7216 compatible = "qcom,coresight-tpdm", "arm,primecell";
7220 clock-names = "apb_pclk";
7222 qcom,cmb-element-bits = <64>;
7223 qcom,cmb-msrs-num = <32>;
7225 out-ports {
7228 remote-endpoint = <&dlct1_tpda_in27>;
7235 compatible = "qcom,coresight-tpda", "arm,primecell";
7239 clock-names = "apb_pclk";
7241 in-ports {
7242 #address-cells = <1>;
7243 #size-cells = <0>;
7249 remote-endpoint = <&lpass_cx_funnel_out>;
7257 remote-endpoint = <&prng_tpdm_out>;
7265 remote-endpoint = <&qm_tpdm_out>;
7273 remote-endpoint = <&gcc_tpdm_out>;
7281 remote-endpoint = <&dlct1_tpdm_out>;
7289 remote-endpoint = <&ipcc_tpdm_out>;
7294 out-ports {
7297 remote-endpoint = <&dlct1_funnel_in0>;
7304 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
7308 clock-names = "apb_pclk";
7310 in-ports {
7311 #address-cells = <1>;
7312 #size-cells = <0>;
7318 remote-endpoint = <&dlct1_tpda_out>;
7326 remote-endpoint = <&dlct2_funnel_out>;
7334 remote-endpoint = <&ddr_funnel0_out>;
7339 out-ports {
7342 remote-endpoint = <&funnel1_in6>;
7349 compatible = "qcom,coresight-tpdm", "arm,primecell";
7353 clock-names = "apb_pclk";
7355 qcom,cmb-element-bits = <64>;
7356 qcom,cmb-msrs-num = <32>;
7358 out-ports {
7361 remote-endpoint = <&dlct2_tpda_in16>;
7368 compatible = "qcom,coresight-tpdm", "arm,primecell";
7372 clock-names = "apb_pclk";
7374 qcom,cmb-element-bits = <64>;
7375 qcom,cmb-msrs-num = <32>;
7377 out-ports {
7380 remote-endpoint = <&dlct2_tpda_in17>;
7387 compatible = "qcom,coresight-tpda", "arm,primecell";
7391 clock-names = "apb_pclk";
7393 in-ports {
7394 #address-cells = <1>;
7395 #size-cells = <0>;
7401 remote-endpoint = <&mm_funnel_out>;
7409 remote-endpoint = <&mxa_tpdm_out>;
7417 remote-endpoint = <&dlct2_tpdm0_out>;
7425 remote-endpoint = <&dlct2_tpdm1_out>;
7430 out-ports {
7433 remote-endpoint = <&dlct2_funnel_in0>;
7440 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
7444 clock-names = "apb_pclk";
7446 in-ports {
7449 remote-endpoint = <&dlct2_tpda_out>;
7454 out-ports {
7457 remote-endpoint = <&dlct1_funnel_in4>;
7464 compatible = "qcom,coresight-tpdm", "arm,primecell";
7468 clock-names = "apb_pclk";
7470 qcom,cmb-element-bits = <64>;
7471 qcom,cmb-msrs-num = <32>;
7472 qcom,dsb-element-bits = <32>;
7473 qcom,dsb-msrs-num = <32>;
7476 out-ports {
7479 remote-endpoint = <&tmess_tpda_in2>;
7486 compatible = "qcom,coresight-tpda", "arm,primecell";
7490 clock-names = "apb_pclk";
7492 in-ports {
7493 #address-cells = <1>;
7494 #size-cells = <0>;
7500 remote-endpoint = <&tmess_tpdm1_out>;
7505 out-ports {
7508 remote-endpoint = <&tmess_funnel_in0>;
7515 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
7519 clock-names = "apb_pclk";
7521 in-ports {
7524 remote-endpoint = <&tmess_tpda_out>;
7529 out-ports {
7532 remote-endpoint = <&funnel1_in2>;
7539 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
7543 clock-names = "apb_pclk";
7545 in-ports {
7546 #address-cells = <1>;
7547 #size-cells = <0>;
7553 remote-endpoint = <&ddr_funnel1_out>;
7558 out-ports {
7561 remote-endpoint = <&dlct1_funnel_in5>;
7568 compatible = "qcom,coresight-tpdm", "arm,primecell";
7572 clock-names = "apb_pclk";
7574 qcom,cmb-element-bits = <32>;
7575 qcom,cmb-msrs-num = <32>;
7577 out-ports {
7580 remote-endpoint = <&llcc_tpda_in0>;
7587 compatible = "qcom,coresight-tpdm", "arm,primecell";
7591 clock-names = "apb_pclk";
7593 qcom,cmb-element-bits = <32>;
7594 qcom,cmb-msrs-num = <32>;
7596 out-ports {
7599 remote-endpoint = <&llcc_tpda_in1>;
7606 compatible = "qcom,coresight-tpdm", "arm,primecell";
7610 clock-names = "apb_pclk";
7612 qcom,cmb-element-bits = <32>;
7613 qcom,cmb-msrs-num = <32>;
7615 out-ports {
7618 remote-endpoint = <&llcc_tpda_in2>;
7625 compatible = "qcom,coresight-tpdm", "arm,primecell";
7629 clock-names = "apb_pclk";
7631 qcom,cmb-element-bits = <32>;
7632 qcom,cmb-msrs-num = <32>;
7634 out-ports {
7637 remote-endpoint = <&llcc_tpda_in3>;
7644 compatible = "qcom,coresight-tpdm", "arm,primecell";
7648 clock-names = "apb_pclk";
7650 qcom,cmb-element-bits = <32>;
7651 qcom,cmb-msrs-num = <32>;
7653 out-ports {
7656 remote-endpoint = <&llcc_tpda_in4>;
7663 compatible = "qcom,coresight-tpdm", "arm,primecell";
7667 clock-names = "apb_pclk";
7669 qcom,cmb-element-bits = <32>;
7670 qcom,cmb-msrs-num = <32>;
7672 out-ports {
7675 remote-endpoint = <&llcc_tpda_in5>;
7682 compatible = "qcom,coresight-tpdm", "arm,primecell";
7686 clock-names = "apb_pclk";
7688 qcom,cmb-element-bits = <32>;
7689 qcom,cmb-msrs-num = <32>;
7691 out-ports {
7694 remote-endpoint = <&llcc_tpda_in6>;
7701 compatible = "qcom,coresight-tpdm", "arm,primecell";
7705 clock-names = "apb_pclk";
7707 qcom,cmb-element-bits = <32>;
7708 qcom,cmb-msrs-num = <32>;
7710 out-ports {
7713 remote-endpoint = <&llcc_tpda_in7>;
7720 compatible = "qcom,coresight-tpda", "arm,primecell";
7724 clock-names = "apb_pclk";
7726 in-ports {
7727 #address-cells = <1>;
7728 #size-cells = <0>;
7734 remote-endpoint = <&llcc0_tpdm_out>;
7742 remote-endpoint = <&llcc1_tpdm_out>;
7750 remote-endpoint = <&llcc2_tpdm_out>;
7758 remote-endpoint = <&llcc3_tpdm_out>;
7766 remote-endpoint = <&llcc4_tpdm_out>;
7774 remote-endpoint = <&llcc5_tpdm_out>;
7782 remote-endpoint = <&llcc6_tpdm_out>;
7790 remote-endpoint = <&llcc7_tpdm_out>;
7795 out-ports {
7798 remote-endpoint = <&ddr_funnel1_in0>;
7805 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
7809 clock-names = "apb_pclk";
7811 in-ports {
7814 remote-endpoint = <&llcc_tpda_out>;
7819 out-ports {
7822 remote-endpoint = <&ddr_funnel0_in6>;
7829 compatible = "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500";
7930 #iommu-cells = <2>;
7931 #global-interrupts = <1>;
7933 dma-coherent;
7936 intc: interrupt-controller@17000000 {
7937 compatible = "arm,gic-v3";
7943 #interrupt-cells = <3>;
7944 interrupt-controller;
7946 #redistributor-regions = <1>;
7947 redistributor-stride = <0x0 0x40000>;
7949 #address-cells = <2>;
7950 #size-cells = <2>;
7953 gic_its: msi-controller@17040000 {
7954 compatible = "arm,gic-v3-its";
7957 msi-controller;
7958 #msi-cells = <1>;
7963 compatible = "qcom,rpmh-rsc";
7967 reg-names = "drv-0", "drv-1", "drv-2";
7972 qcom,tcs-offset = <0xd00>;
7973 qcom,drv-id = <2>;
7974 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
7978 power-domains = <&system_pd>;
7980 apps_bcm_voter: bcm-voter {
7981 compatible = "qcom,bcm-voter";
7984 rpmhcc: clock-controller {
7985 compatible = "qcom,x1e80100-rpmh-clk";
7988 clock-names = "xo";
7990 #clock-cells = <1>;
7993 rpmhpd: power-controller {
7994 compatible = "qcom,x1e80100-rpmhpd";
7996 operating-points-v2 = <&rpmhpd_opp_table>;
7998 #power-domain-cells = <1>;
8000 rpmhpd_opp_table: opp-table {
8001 compatible = "operating-points-v2";
8003 rpmhpd_opp_ret: opp-16 {
8004 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
8007 rpmhpd_opp_min_svs: opp-48 {
8008 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
8011 rpmhpd_opp_low_svs_d2: opp-52 {
8012 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
8015 rpmhpd_opp_low_svs_d1: opp-56 {
8016 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
8019 rpmhpd_opp_low_svs_d0: opp-60 {
8020 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
8023 rpmhpd_opp_low_svs: opp-64 {
8024 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
8027 rpmhpd_opp_low_svs_l1: opp-80 {
8028 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
8031 rpmhpd_opp_svs: opp-128 {
8032 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
8035 rpmhpd_opp_svs_l0: opp-144 {
8036 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
8039 rpmhpd_opp_svs_l1: opp-192 {
8040 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
8043 rpmhpd_opp_nom: opp-256 {
8044 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
8047 rpmhpd_opp_nom_l1: opp-320 {
8048 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
8051 rpmhpd_opp_nom_l2: opp-336 {
8052 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
8055 rpmhpd_opp_turbo: opp-384 {
8056 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
8059 rpmhpd_opp_turbo_l1: opp-416 {
8060 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
8067 compatible = "arm,armv7-timer-mem";
8070 #address-cells = <2>;
8071 #size-cells = <1>;
8081 frame-number = <0>;
8089 frame-number = <1>;
8099 frame-number = <2>;
8109 frame-number = <3>;
8119 frame-number = <4>;
8129 frame-number = <5>;
8139 frame-number = <6>;
8146 compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
8154 operating-points-v2 = <&llcc_bwmon_opp_table>;
8156 llcc_bwmon_opp_table: opp-table {
8157 compatible = "operating-points-v2";
8159 opp-0 {
8160 opp-peak-kBps = <800000>;
8163 opp-1 {
8164 opp-peak-kBps = <2188000>;
8167 opp-2 {
8168 opp-peak-kBps = <3072000>;
8171 opp-3 {
8172 opp-peak-kBps = <6220800>;
8175 opp-4 {
8176 opp-peak-kBps = <6835200>;
8179 opp-5 {
8180 opp-peak-kBps = <8371200>;
8183 opp-6 {
8184 opp-peak-kBps = <10944000>;
8187 opp-7 {
8188 opp-peak-kBps = <12748800>;
8191 opp-8 {
8192 opp-peak-kBps = <14745600>;
8195 opp-9 {
8196 opp-peak-kBps = <16896000>;
8203 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
8211 operating-points-v2 = <&cpu_bwmon_opp_table>;
8213 cpu_bwmon_opp_table: opp-table {
8214 compatible = "operating-points-v2";
8216 opp-0 {
8217 opp-peak-kBps = <4800000>;
8220 opp-1 {
8221 opp-peak-kBps = <7464000>;
8224 opp-2 {
8225 opp-peak-kBps = <9600000>;
8228 opp-3 {
8229 opp-peak-kBps = <12896000>;
8232 opp-4 {
8233 opp-peak-kBps = <14928000>;
8236 opp-5 {
8237 opp-peak-kBps = <17064000>;
8244 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
8252 operating-points-v2 = <&cpu_bwmon_opp_table>;
8257 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
8265 operating-points-v2 = <&cpu_bwmon_opp_table>;
8268 system-cache-controller@25000000 {
8269 compatible = "qcom,x1e80100-llcc";
8280 reg-names = "llcc0_base",
8294 compatible = "qcom,x1e80100-cdsp-pas";
8297 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
8302 interrupt-names = "wdog",
8306 "stop-ack";
8309 clock-names = "xo";
8311 power-domains = <&rpmhpd RPMHPD_CX>,
8314 power-domain-names = "cx",
8321 memory-region = <&cdsp_mem>,
8326 qcom,smem-states = <&smp2p_cdsp_out 0>;
8327 qcom,smem-state-names = "stop";
8331 glink-edge {
8332 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
8339 qcom,remote-pid = <5>;
8343 qcom,glink-channels = "fastrpcglink-apps-dsp";
8345 qcom,non-secure-domain;
8346 #address-cells = <1>;
8347 #size-cells = <0>;
8349 compute-cb@1 {
8350 compatible = "qcom,fastrpc-compute-cb";
8353 dma-coherent;
8356 compute-cb@2 {
8357 compatible = "qcom,fastrpc-compute-cb";
8360 dma-coherent;
8363 compute-cb@3 {
8364 compatible = "qcom,fastrpc-compute-cb";
8367 dma-coherent;
8370 compute-cb@4 {
8371 compatible = "qcom,fastrpc-compute-cb";
8374 dma-coherent;
8377 compute-cb@5 {
8378 compatible = "qcom,fastrpc-compute-cb";
8381 dma-coherent;
8384 compute-cb@6 {
8385 compatible = "qcom,fastrpc-compute-cb";
8388 dma-coherent;
8391 compute-cb@7 {
8392 compatible = "qcom,fastrpc-compute-cb";
8395 dma-coherent;
8398 compute-cb@8 {
8399 compatible = "qcom,fastrpc-compute-cb";
8402 dma-coherent;
8405 /* note: compute-cb@9 is secure */
8407 compute-cb@10 {
8408 compatible = "qcom,fastrpc-compute-cb";
8411 dma-coherent;
8414 compute-cb@11 {
8415 compatible = "qcom,fastrpc-compute-cb";
8418 dma-coherent;
8421 compute-cb@12 {
8422 compatible = "qcom,fastrpc-compute-cb";
8425 dma-coherent;
8428 compute-cb@13 {
8429 compatible = "qcom,fastrpc-compute-cb";
8432 dma-coherent;
8440 compatible = "arm,armv8-timer";
8448 thermal-zones {
8449 aoss0-thermal {
8450 thermal-sensors = <&tsens0 0>;
8453 trip-point0 {
8459 aoss0-critical {
8467 cpu0-0-top-thermal {
8468 polling-delay-passive = <250>;
8470 thermal-sensors = <&tsens0 1>;
8473 trip-point0 {
8479 trip-point1 {
8485 cpu-critical {
8493 cpu0-0-btm-thermal {
8494 polling-delay-passive = <250>;
8496 thermal-sensors = <&tsens0 2>;
8499 trip-point0 {
8505 trip-point1 {
8511 cpu-critical {
8519 cpu0-1-top-thermal {
8520 polling-delay-passive = <250>;
8522 thermal-sensors = <&tsens0 3>;
8525 trip-point0 {
8531 trip-point1 {
8537 cpu-critical {
8545 cpu0-1-btm-thermal {
8546 polling-delay-passive = <250>;
8548 thermal-sensors = <&tsens0 4>;
8551 trip-point0 {
8557 trip-point1 {
8563 cpu-critical {
8571 cpu0-2-top-thermal {
8572 polling-delay-passive = <250>;
8574 thermal-sensors = <&tsens0 5>;
8577 trip-point0 {
8583 trip-point1 {
8589 cpu-critical {
8597 cpu0-2-btm-thermal {
8598 polling-delay-passive = <250>;
8600 thermal-sensors = <&tsens0 6>;
8603 trip-point0 {
8609 trip-point1 {
8615 cpu-critical {
8623 cpu0-3-top-thermal {
8624 polling-delay-passive = <250>;
8626 thermal-sensors = <&tsens0 7>;
8629 trip-point0 {
8635 trip-point1 {
8641 cpu-critical {
8649 cpu0-3-btm-thermal {
8650 polling-delay-passive = <250>;
8652 thermal-sensors = <&tsens0 8>;
8655 trip-point0 {
8661 trip-point1 {
8667 cpu-critical {
8675 cpuss0-top-thermal {
8676 thermal-sensors = <&tsens0 9>;
8679 trip-point0 {
8685 cpuss2-critical {
8693 cpuss0-btm-thermal {
8694 thermal-sensors = <&tsens0 10>;
8697 trip-point0 {
8703 cpuss2-critical {
8711 mem-thermal {
8712 thermal-sensors = <&tsens0 11>;
8715 trip-point0 {
8721 mem-critical {
8729 video-thermal {
8730 polling-delay-passive = <250>;
8732 thermal-sensors = <&tsens0 12>;
8735 trip-point0 {
8743 aoss1-thermal {
8744 thermal-sensors = <&tsens1 0>;
8747 trip-point0 {
8753 aoss0-critical {
8761 cpu1-0-top-thermal {
8762 polling-delay-passive = <250>;
8764 thermal-sensors = <&tsens1 1>;
8767 trip-point0 {
8773 trip-point1 {
8779 cpu-critical {
8787 cpu1-0-btm-thermal {
8788 polling-delay-passive = <250>;
8790 thermal-sensors = <&tsens1 2>;
8793 trip-point0 {
8799 trip-point1 {
8805 cpu-critical {
8813 cpu1-1-top-thermal {
8814 polling-delay-passive = <250>;
8816 thermal-sensors = <&tsens1 3>;
8819 trip-point0 {
8825 trip-point1 {
8831 cpu-critical {
8839 cpu1-1-btm-thermal {
8840 polling-delay-passive = <250>;
8842 thermal-sensors = <&tsens1 4>;
8845 trip-point0 {
8851 trip-point1 {
8857 cpu-critical {
8865 cpu1-2-top-thermal {
8866 polling-delay-passive = <250>;
8868 thermal-sensors = <&tsens1 5>;
8871 trip-point0 {
8877 trip-point1 {
8883 cpu-critical {
8891 cpu1-2-btm-thermal {
8892 polling-delay-passive = <250>;
8894 thermal-sensors = <&tsens1 6>;
8897 trip-point0 {
8903 trip-point1 {
8909 cpu-critical {
8917 cpu1-3-top-thermal {
8918 polling-delay-passive = <250>;
8920 thermal-sensors = <&tsens1 7>;
8923 trip-point0 {
8929 trip-point1 {
8935 cpu-critical {
8943 cpu1-3-btm-thermal {
8944 polling-delay-passive = <250>;
8946 thermal-sensors = <&tsens1 8>;
8949 trip-point0 {
8955 trip-point1 {
8961 cpu-critical {
8969 cpuss1-top-thermal {
8970 thermal-sensors = <&tsens1 9>;
8973 trip-point0 {
8979 cpuss2-critical {
8987 cpuss1-btm-thermal {
8988 thermal-sensors = <&tsens1 10>;
8991 trip-point0 {
8997 cpuss2-critical {
9005 aoss2-thermal {
9006 thermal-sensors = <&tsens2 0>;
9009 trip-point0 {
9015 aoss0-critical {
9023 cpu2-0-top-thermal {
9024 polling-delay-passive = <250>;
9026 thermal-sensors = <&tsens2 1>;
9029 trip-point0 {
9035 trip-point1 {
9041 cpu-critical {
9049 cpu2-0-btm-thermal {
9050 polling-delay-passive = <250>;
9052 thermal-sensors = <&tsens2 2>;
9055 trip-point0 {
9061 trip-point1 {
9067 cpu-critical {
9075 cpu2-1-top-thermal {
9076 polling-delay-passive = <250>;
9078 thermal-sensors = <&tsens2 3>;
9081 trip-point0 {
9087 trip-point1 {
9093 cpu-critical {
9101 cpu2-1-btm-thermal {
9102 polling-delay-passive = <250>;
9104 thermal-sensors = <&tsens2 4>;
9107 trip-point0 {
9113 trip-point1 {
9119 cpu-critical {
9127 cpu2-2-top-thermal {
9128 polling-delay-passive = <250>;
9130 thermal-sensors = <&tsens2 5>;
9133 trip-point0 {
9139 trip-point1 {
9145 cpu-critical {
9153 cpu2-2-btm-thermal {
9154 polling-delay-passive = <250>;
9156 thermal-sensors = <&tsens2 6>;
9159 trip-point0 {
9165 trip-point1 {
9171 cpu-critical {
9179 cpu2-3-top-thermal {
9180 polling-delay-passive = <250>;
9182 thermal-sensors = <&tsens2 7>;
9185 trip-point0 {
9191 trip-point1 {
9197 cpu-critical {
9205 cpu2-3-btm-thermal {
9206 polling-delay-passive = <250>;
9208 thermal-sensors = <&tsens2 8>;
9211 trip-point0 {
9217 trip-point1 {
9223 cpu-critical {
9231 cpuss2-top-thermal {
9232 thermal-sensors = <&tsens2 9>;
9235 trip-point0 {
9241 cpuss2-critical {
9249 cpuss2-btm-thermal {
9250 thermal-sensors = <&tsens2 10>;
9253 trip-point0 {
9259 cpuss2-critical {
9267 aoss3-thermal {
9268 thermal-sensors = <&tsens3 0>;
9271 trip-point0 {
9277 aoss0-critical {
9285 nsp0-thermal {
9286 thermal-sensors = <&tsens3 1>;
9289 trip-point0 {
9295 nsp0-critical {
9303 nsp1-thermal {
9304 thermal-sensors = <&tsens3 2>;
9307 trip-point0 {
9313 nsp1-critical {
9321 nsp2-thermal {
9322 thermal-sensors = <&tsens3 3>;
9325 trip-point0 {
9331 nsp2-critical {
9339 nsp3-thermal {
9340 thermal-sensors = <&tsens3 4>;
9343 trip-point0 {
9349 nsp3-critical {
9357 gpuss-0-thermal {
9358 polling-delay-passive = <10>;
9360 thermal-sensors = <&tsens3 5>;
9363 trip-point0 {
9369 trip-point1 {
9375 trip-point2 {
9383 gpuss-1-thermal {
9384 polling-delay-passive = <10>;
9386 thermal-sensors = <&tsens3 6>;
9389 trip-point0 {
9395 trip-point1 {
9401 trip-point2 {
9409 gpuss-2-thermal {
9410 polling-delay-passive = <10>;
9412 thermal-sensors = <&tsens3 7>;
9415 trip-point0 {
9421 trip-point1 {
9427 trip-point2 {
9435 gpuss-3-thermal {
9436 polling-delay-passive = <10>;
9438 thermal-sensors = <&tsens3 8>;
9441 trip-point0 {
9447 trip-point1 {
9453 trip-point2 {
9461 gpuss-4-thermal {
9462 polling-delay-passive = <10>;
9464 thermal-sensors = <&tsens3 9>;
9467 trip-point0 {
9473 trip-point1 {
9479 trip-point2 {
9487 gpuss-5-thermal {
9488 polling-delay-passive = <10>;
9490 thermal-sensors = <&tsens3 10>;
9493 trip-point0 {
9499 trip-point1 {
9505 trip-point2 {
9513 gpuss-6-thermal {
9514 polling-delay-passive = <10>;
9516 thermal-sensors = <&tsens3 11>;
9519 trip-point0 {
9525 trip-point1 {
9531 trip-point2 {
9539 gpuss-7-thermal {
9540 polling-delay-passive = <10>;
9542 thermal-sensors = <&tsens3 12>;
9545 trip-point0 {
9551 trip-point1 {
9557 trip-point2 {
9565 camera0-thermal {
9566 thermal-sensors = <&tsens3 13>;
9569 trip-point0 {
9575 camera0-critical {
9583 camera1-thermal {
9584 thermal-sensors = <&tsens3 14>;
9587 trip-point0 {
9593 camera0-critical {