Lines Matching +full:dsp +full:- +full:gpio20
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
8 #include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
9 #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
10 #include <dt-bindings/clock/qcom,x1e80100-gpucc.h>
11 #include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/interconnect/qcom,icc.h>
14 #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/soc/qcom,gpr.h>
21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
22 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
25 interrupt-parent = <&intc>;
27 #address-cells = <2>;
28 #size-cells = <2>;
33 xo_board: xo-board {
34 compatible = "fixed-clock";
35 clock-frequency = <76800000>;
36 #clock-cells = <0>;
39 sleep_clk: sleep-clk {
40 compatible = "fixed-clock";
41 clock-frequency = <32000>;
42 #clock-cells = <0>;
45 bi_tcxo_div2: bi-tcxo-div2-clk {
46 compatible = "fixed-factor-clock";
47 #clock-cells = <0>;
50 clock-mult = <1>;
51 clock-div = <2>;
54 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
55 compatible = "fixed-factor-clock";
56 #clock-cells = <0>;
59 clock-mult = <1>;
60 clock-div = <2>;
65 #address-cells = <2>;
66 #size-cells = <0>;
72 enable-method = "psci";
73 next-level-cache = <&l2_0>;
74 power-domains = <&cpu_pd0>;
75 power-domain-names = "psci";
76 cpu-idle-states = <&cluster_c4>;
78 l2_0: l2-cache {
80 cache-level = <2>;
81 cache-unified;
89 enable-method = "psci";
90 next-level-cache = <&l2_0>;
91 power-domains = <&cpu_pd1>;
92 power-domain-names = "psci";
93 cpu-idle-states = <&cluster_c4>;
100 enable-method = "psci";
101 next-level-cache = <&l2_0>;
102 power-domains = <&cpu_pd2>;
103 power-domain-names = "psci";
104 cpu-idle-states = <&cluster_c4>;
111 enable-method = "psci";
112 next-level-cache = <&l2_0>;
113 power-domains = <&cpu_pd3>;
114 power-domain-names = "psci";
115 cpu-idle-states = <&cluster_c4>;
122 enable-method = "psci";
123 next-level-cache = <&l2_1>;
124 power-domains = <&cpu_pd4>;
125 power-domain-names = "psci";
126 cpu-idle-states = <&cluster_c4>;
128 l2_1: l2-cache {
130 cache-level = <2>;
131 cache-unified;
139 enable-method = "psci";
140 next-level-cache = <&l2_1>;
141 power-domains = <&cpu_pd5>;
142 power-domain-names = "psci";
143 cpu-idle-states = <&cluster_c4>;
150 enable-method = "psci";
151 next-level-cache = <&l2_1>;
152 power-domains = <&cpu_pd6>;
153 power-domain-names = "psci";
154 cpu-idle-states = <&cluster_c4>;
161 enable-method = "psci";
162 next-level-cache = <&l2_1>;
163 power-domains = <&cpu_pd7>;
164 power-domain-names = "psci";
165 cpu-idle-states = <&cluster_c4>;
172 enable-method = "psci";
173 next-level-cache = <&l2_2>;
174 power-domains = <&cpu_pd8>;
175 power-domain-names = "psci";
176 cpu-idle-states = <&cluster_c4>;
178 l2_2: l2-cache {
180 cache-level = <2>;
181 cache-unified;
189 enable-method = "psci";
190 next-level-cache = <&l2_2>;
191 power-domains = <&cpu_pd9>;
192 power-domain-names = "psci";
193 cpu-idle-states = <&cluster_c4>;
200 enable-method = "psci";
201 next-level-cache = <&l2_2>;
202 power-domains = <&cpu_pd10>;
203 power-domain-names = "psci";
204 cpu-idle-states = <&cluster_c4>;
211 enable-method = "psci";
212 next-level-cache = <&l2_2>;
213 power-domains = <&cpu_pd11>;
214 power-domain-names = "psci";
215 cpu-idle-states = <&cluster_c4>;
218 cpu-map {
274 idle-states {
275 entry-method = "psci";
277 cluster_c4: cpu-sleep-0 {
278 compatible = "arm,idle-state";
279 idle-state-name = "ret";
280 arm,psci-suspend-param = <0x00000004>;
281 entry-latency-us = <180>;
282 exit-latency-us = <500>;
283 min-residency-us = <600>;
287 domain-idle-states {
288 cluster_cl4: cluster-sleep-0 {
289 compatible = "domain-idle-state";
290 arm,psci-suspend-param = <0x01000044>;
291 entry-latency-us = <350>;
292 exit-latency-us = <500>;
293 min-residency-us = <2500>;
296 cluster_cl5: cluster-sleep-1 {
297 compatible = "domain-idle-state";
298 arm,psci-suspend-param = <0x01000054>;
299 entry-latency-us = <2200>;
300 exit-latency-us = <4000>;
301 min-residency-us = <7000>;
308 compatible = "qcom,scm-x1e80100", "qcom,scm";
311 qcom,dload-mode = <&tcsr 0x19000>;
315 clk_virt: interconnect-0 {
316 compatible = "qcom,x1e80100-clk-virt";
317 #interconnect-cells = <2>;
318 qcom,bcm-voters = <&apps_bcm_voter>;
321 mc_virt: interconnect-1 {
322 compatible = "qcom,x1e80100-mc-virt";
323 #interconnect-cells = <2>;
324 qcom,bcm-voters = <&apps_bcm_voter>;
334 compatible = "arm,armv8-pmuv3";
339 compatible = "arm,psci-1.0";
342 cpu_pd0: power-domain-cpu0 {
343 #power-domain-cells = <0>;
344 power-domains = <&cluster_pd0>;
347 cpu_pd1: power-domain-cpu1 {
348 #power-domain-cells = <0>;
349 power-domains = <&cluster_pd0>;
352 cpu_pd2: power-domain-cpu2 {
353 #power-domain-cells = <0>;
354 power-domains = <&cluster_pd0>;
357 cpu_pd3: power-domain-cpu3 {
358 #power-domain-cells = <0>;
359 power-domains = <&cluster_pd0>;
362 cpu_pd4: power-domain-cpu4 {
363 #power-domain-cells = <0>;
364 power-domains = <&cluster_pd1>;
367 cpu_pd5: power-domain-cpu5 {
368 #power-domain-cells = <0>;
369 power-domains = <&cluster_pd1>;
372 cpu_pd6: power-domain-cpu6 {
373 #power-domain-cells = <0>;
374 power-domains = <&cluster_pd1>;
377 cpu_pd7: power-domain-cpu7 {
378 #power-domain-cells = <0>;
379 power-domains = <&cluster_pd1>;
382 cpu_pd8: power-domain-cpu8 {
383 #power-domain-cells = <0>;
384 power-domains = <&cluster_pd2>;
387 cpu_pd9: power-domain-cpu9 {
388 #power-domain-cells = <0>;
389 power-domains = <&cluster_pd2>;
392 cpu_pd10: power-domain-cpu10 {
393 #power-domain-cells = <0>;
394 power-domains = <&cluster_pd2>;
397 cpu_pd11: power-domain-cpu11 {
398 #power-domain-cells = <0>;
399 power-domains = <&cluster_pd2>;
402 cluster_pd0: power-domain-cpu-cluster0 {
403 #power-domain-cells = <0>;
404 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>;
405 power-domains = <&system_pd>;
408 cluster_pd1: power-domain-cpu-cluster1 {
409 #power-domain-cells = <0>;
410 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>;
411 power-domains = <&system_pd>;
414 cluster_pd2: power-domain-cpu-cluster2 {
415 #power-domain-cells = <0>;
416 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>;
417 power-domains = <&system_pd>;
420 system_pd: power-domain-system {
421 #power-domain-cells = <0>;
422 /* TODO: system-wide idle states */
426 reserved-memory {
427 #address-cells = <2>;
428 #size-cells = <2>;
431 gunyah_hyp_mem: gunyah-hyp@80000000 {
433 no-map;
436 hyp_elf_package_mem: hyp-elf-package@80800000 {
438 no-map;
443 no-map;
446 cpucp_log_mem: cpucp-log@80e00000 {
448 no-map;
453 no-map;
456 reserved-region@81380000 {
458 no-map;
461 tags_mem: tags-region@81400000 {
463 no-map;
466 xbl_dtlog_mem: xbl-dtlog@81a00000 {
468 no-map;
471 xbl_ramdump_mem: xbl-ramdump@81a40000 {
473 no-map;
476 aop_image_mem: aop-image@81c00000 {
478 no-map;
481 aop_cmd_db_mem: aop-cmd-db@81c60000 {
482 compatible = "qcom,cmd-db";
484 no-map;
487 aop_config_mem: aop-config@81c80000 {
489 no-map;
492 tme_crash_dump_mem: tme-crash-dump@81ca0000 {
494 no-map;
497 tme_log_mem: tme-log@81ce0000 {
499 no-map;
502 uefi_log_mem: uefi-log@81ce4000 {
504 no-map;
507 secdata_apss_mem: secdata-apss@81cff000 {
509 no-map;
512 pdp_ns_shared_mem: pdp-ns-shared@81e00000 {
514 no-map;
517 gpu_prr_mem: gpu-prr@81f00000 {
519 no-map;
522 tpm_control_mem: tpm-control@81f10000 {
524 no-map;
527 usb_ucsi_shared_mem: usb-ucsi-shared@81f20000 {
529 no-map;
532 pld_pep_mem: pld-pep@81f30000 {
534 no-map;
537 pld_gmu_mem: pld-gmu@81f36000 {
539 no-map;
542 pld_pdp_mem: pld-pdp@81f37000 {
544 no-map;
547 tz_stat_mem: tz-stat@82700000 {
549 no-map;
552 xbl_tmp_buffer_mem: xbl-tmp-buffer@82800000 {
554 no-map;
557 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@84b00000 {
559 no-map;
562 spu_secure_shared_memory_mem: spu-secure-shared-memory@85300000 {
564 no-map;
567 adsp_boot_dtb_mem: adsp-boot-dtb@866c0000 {
569 no-map;
572 spss_region_mem: spss-region@86700000 {
574 no-map;
577 adsp_boot_mem: adsp-boot@86b00000 {
579 no-map;
584 no-map;
589 no-map;
592 q6_adsp_dtb_mem: q6-adsp-dtb@8b800000 {
594 no-map;
599 no-map;
602 q6_cdsp_dtb_mem: q6-cdsp-dtb@8d900000 {
604 no-map;
607 gpu_microcode_mem: gpu-microcode@8d9fe000 {
609 no-map;
614 no-map;
619 no-map;
622 av1_encoder_mem: av1-encoder@8e900000 {
624 no-map;
627 reserved-region@8f000000 {
629 no-map;
634 no-map;
637 q6_wpss_dtb_mem: q6-wpss-dtb@91300000 {
639 no-map;
642 xbl_sc_mem: xbl-sc@d8000000 {
644 no-map;
647 reserved-region@d8040000 {
649 no-map;
654 no-map;
659 no-map;
664 no-map;
667 llcc_lpi_mem: llcc-lpi@ff800000 {
669 no-map;
676 no-map;
680 smp2p-adsp {
683 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
691 qcom,local-pid = <0>;
692 qcom,remote-pid = <2>;
694 smp2p_adsp_out: master-kernel {
695 qcom,entry-name = "master-kernel";
696 #qcom,smem-state-cells = <1>;
699 smp2p_adsp_in: slave-kernel {
700 qcom,entry-name = "slave-kernel";
701 interrupt-controller;
702 #interrupt-cells = <2>;
706 smp2p-cdsp {
709 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
717 qcom,local-pid = <0>;
718 qcom,remote-pid = <5>;
720 smp2p_cdsp_out: master-kernel {
721 qcom,entry-name = "master-kernel";
722 #qcom,smem-state-cells = <1>;
725 smp2p_cdsp_in: slave-kernel {
726 qcom,entry-name = "slave-kernel";
727 interrupt-controller;
728 #interrupt-cells = <2>;
733 compatible = "simple-bus";
735 #address-cells = <2>;
736 #size-cells = <2>;
737 dma-ranges = <0 0 0 0 0x10 0>;
740 gcc: clock-controller@100000 {
741 compatible = "qcom,x1e80100-gcc";
755 power-domains = <&rpmhpd RPMHPD_CX>;
756 #clock-cells = <1>;
757 #reset-cells = <1>;
758 #power-domain-cells = <1>;
762 compatible = "qcom,x1e80100-ipcc", "qcom,ipcc";
766 interrupt-controller;
767 #interrupt-cells = <3>;
769 #mbox-cells = <2>;
772 gpi_dma2: dma-controller@800000 {
773 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
789 dma-channels = <12>;
790 dma-channel-mask = <0x3e>;
791 #dma-cells = <3>;
799 compatible = "qcom,geni-se-qup";
804 clock-names = "m-ahb",
805 "s-ahb";
809 #address-cells = <2>;
810 #size-cells = <2>;
816 compatible = "qcom,geni-i2c";
822 clock-names = "se";
830 interconnect-names = "qup-core",
831 "qup-config",
832 "qup-memory";
836 dma-names = "tx",
839 pinctrl-0 = <&qup_i2c16_data_clk>;
840 pinctrl-names = "default";
842 #address-cells = <1>;
843 #size-cells = <0>;
849 compatible = "qcom,geni-spi";
855 clock-names = "se";
863 interconnect-names = "qup-core",
864 "qup-config",
865 "qup-memory";
869 dma-names = "tx",
872 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
873 pinctrl-names = "default";
875 #address-cells = <1>;
876 #size-cells = <0>;
882 compatible = "qcom,geni-i2c";
888 clock-names = "se";
896 interconnect-names = "qup-core",
897 "qup-config",
898 "qup-memory";
902 dma-names = "tx",
905 pinctrl-0 = <&qup_i2c17_data_clk>;
906 pinctrl-names = "default";
908 #address-cells = <1>;
909 #size-cells = <0>;
915 compatible = "qcom,geni-spi";
921 clock-names = "se";
929 interconnect-names = "qup-core",
930 "qup-config",
931 "qup-memory";
935 dma-names = "tx",
938 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
939 pinctrl-names = "default";
941 #address-cells = <1>;
942 #size-cells = <0>;
948 compatible = "qcom,geni-i2c";
954 clock-names = "se";
962 interconnect-names = "qup-core",
963 "qup-config",
964 "qup-memory";
968 dma-names = "tx",
971 pinctrl-0 = <&qup_i2c18_data_clk>;
972 pinctrl-names = "default";
974 #address-cells = <1>;
975 #size-cells = <0>;
981 compatible = "qcom,geni-spi";
987 clock-names = "se";
995 interconnect-names = "qup-core",
996 "qup-config",
997 "qup-memory";
1001 dma-names = "tx",
1004 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
1005 pinctrl-names = "default";
1007 #address-cells = <1>;
1008 #size-cells = <0>;
1014 compatible = "qcom,geni-i2c";
1020 clock-names = "se";
1028 interconnect-names = "qup-core",
1029 "qup-config",
1030 "qup-memory";
1034 dma-names = "tx",
1037 pinctrl-0 = <&qup_i2c19_data_clk>;
1038 pinctrl-names = "default";
1040 #address-cells = <1>;
1041 #size-cells = <0>;
1047 compatible = "qcom,geni-spi";
1053 clock-names = "se";
1061 interconnect-names = "qup-core",
1062 "qup-config",
1063 "qup-memory";
1067 dma-names = "tx",
1070 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
1071 pinctrl-names = "default";
1073 #address-cells = <1>;
1074 #size-cells = <0>;
1080 compatible = "qcom,geni-i2c";
1086 clock-names = "se";
1094 interconnect-names = "qup-core",
1095 "qup-config",
1096 "qup-memory";
1100 dma-names = "tx",
1103 pinctrl-0 = <&qup_i2c20_data_clk>;
1104 pinctrl-names = "default";
1106 #address-cells = <1>;
1107 #size-cells = <0>;
1113 compatible = "qcom,geni-spi";
1119 clock-names = "se";
1127 interconnect-names = "qup-core",
1128 "qup-config",
1129 "qup-memory";
1133 dma-names = "tx",
1136 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1137 pinctrl-names = "default";
1139 #address-cells = <1>;
1140 #size-cells = <0>;
1146 compatible = "qcom,geni-i2c";
1152 clock-names = "se";
1160 interconnect-names = "qup-core",
1161 "qup-config",
1162 "qup-memory";
1166 dma-names = "tx",
1169 pinctrl-0 = <&qup_i2c21_data_clk>;
1170 pinctrl-names = "default";
1172 #address-cells = <1>;
1173 #size-cells = <0>;
1179 compatible = "qcom,geni-spi";
1185 clock-names = "se";
1193 interconnect-names = "qup-core",
1194 "qup-config",
1195 "qup-memory";
1199 dma-names = "tx",
1202 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1203 pinctrl-names = "default";
1205 #address-cells = <1>;
1206 #size-cells = <0>;
1212 compatible = "qcom,geni-uart";
1218 clock-names = "se";
1224 interconnect-names = "qup-core",
1225 "qup-config";
1227 pinctrl-0 = <&qup_uart21_default>;
1228 pinctrl-names = "default";
1234 compatible = "qcom,geni-i2c";
1240 clock-names = "se";
1248 interconnect-names = "qup-core",
1249 "qup-config",
1250 "qup-memory";
1254 dma-names = "tx",
1257 pinctrl-0 = <&qup_i2c22_data_clk>;
1258 pinctrl-names = "default";
1260 #address-cells = <1>;
1261 #size-cells = <0>;
1267 compatible = "qcom,geni-spi";
1273 clock-names = "se";
1281 interconnect-names = "qup-core",
1282 "qup-config",
1283 "qup-memory";
1287 dma-names = "tx",
1290 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>;
1291 pinctrl-names = "default";
1293 #address-cells = <1>;
1294 #size-cells = <0>;
1300 compatible = "qcom,geni-i2c";
1306 clock-names = "se";
1314 interconnect-names = "qup-core",
1315 "qup-config",
1316 "qup-memory";
1320 dma-names = "tx",
1323 pinctrl-0 = <&qup_i2c23_data_clk>;
1324 pinctrl-names = "default";
1326 #address-cells = <1>;
1327 #size-cells = <0>;
1333 compatible = "qcom,geni-spi";
1339 clock-names = "se";
1347 interconnect-names = "qup-core",
1348 "qup-config",
1349 "qup-memory";
1353 dma-names = "tx",
1356 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>;
1357 pinctrl-names = "default";
1359 #address-cells = <1>;
1360 #size-cells = <0>;
1366 gpi_dma1: dma-controller@a00000 {
1367 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
1383 dma-channels = <12>;
1384 dma-channel-mask = <0x3e>;
1385 #dma-cells = <3>;
1393 compatible = "qcom,geni-se-qup";
1398 clock-names = "m-ahb",
1399 "s-ahb";
1403 #address-cells = <2>;
1404 #size-cells = <2>;
1410 compatible = "qcom,geni-i2c";
1416 clock-names = "se";
1424 interconnect-names = "qup-core",
1425 "qup-config",
1426 "qup-memory";
1430 dma-names = "tx",
1433 pinctrl-0 = <&qup_i2c8_data_clk>;
1434 pinctrl-names = "default";
1436 #address-cells = <1>;
1437 #size-cells = <0>;
1443 compatible = "qcom,geni-spi";
1449 clock-names = "se";
1457 interconnect-names = "qup-core",
1458 "qup-config",
1459 "qup-memory";
1463 dma-names = "tx",
1466 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1467 pinctrl-names = "default";
1469 #address-cells = <1>;
1470 #size-cells = <0>;
1476 compatible = "qcom,geni-i2c";
1482 clock-names = "se";
1490 interconnect-names = "qup-core",
1491 "qup-config",
1492 "qup-memory";
1496 dma-names = "tx",
1499 pinctrl-0 = <&qup_i2c9_data_clk>;
1500 pinctrl-names = "default";
1502 #address-cells = <1>;
1503 #size-cells = <0>;
1509 compatible = "qcom,geni-spi";
1515 clock-names = "se";
1523 interconnect-names = "qup-core",
1524 "qup-config",
1525 "qup-memory";
1529 dma-names = "tx",
1532 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1533 pinctrl-names = "default";
1535 #address-cells = <1>;
1536 #size-cells = <0>;
1542 compatible = "qcom,geni-i2c";
1548 clock-names = "se";
1556 interconnect-names = "qup-core",
1557 "qup-config",
1558 "qup-memory";
1562 dma-names = "tx",
1565 pinctrl-0 = <&qup_i2c10_data_clk>;
1566 pinctrl-names = "default";
1568 #address-cells = <1>;
1569 #size-cells = <0>;
1575 compatible = "qcom,geni-spi";
1581 clock-names = "se";
1589 interconnect-names = "qup-core",
1590 "qup-config",
1591 "qup-memory";
1595 dma-names = "tx",
1598 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1599 pinctrl-names = "default";
1601 #address-cells = <1>;
1602 #size-cells = <0>;
1608 compatible = "qcom,geni-i2c";
1614 clock-names = "se";
1622 interconnect-names = "qup-core",
1623 "qup-config",
1624 "qup-memory";
1628 dma-names = "tx",
1631 pinctrl-0 = <&qup_i2c11_data_clk>;
1632 pinctrl-names = "default";
1634 #address-cells = <1>;
1635 #size-cells = <0>;
1641 compatible = "qcom,geni-spi";
1647 clock-names = "se";
1655 interconnect-names = "qup-core",
1656 "qup-config",
1657 "qup-memory";
1661 dma-names = "tx",
1664 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1665 pinctrl-names = "default";
1667 #address-cells = <1>;
1668 #size-cells = <0>;
1674 compatible = "qcom,geni-i2c";
1680 clock-names = "se";
1688 interconnect-names = "qup-core",
1689 "qup-config",
1690 "qup-memory";
1694 dma-names = "tx",
1697 pinctrl-0 = <&qup_i2c12_data_clk>;
1698 pinctrl-names = "default";
1700 #address-cells = <1>;
1701 #size-cells = <0>;
1707 compatible = "qcom,geni-spi";
1713 clock-names = "se";
1721 interconnect-names = "qup-core",
1722 "qup-config",
1723 "qup-memory";
1727 dma-names = "tx",
1730 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1731 pinctrl-names = "default";
1733 #address-cells = <1>;
1734 #size-cells = <0>;
1740 compatible = "qcom,geni-i2c";
1746 clock-names = "se";
1754 interconnect-names = "qup-core",
1755 "qup-config",
1756 "qup-memory";
1760 dma-names = "tx",
1763 pinctrl-0 = <&qup_i2c13_data_clk>;
1764 pinctrl-names = "default";
1766 #address-cells = <1>;
1767 #size-cells = <0>;
1773 compatible = "qcom,geni-spi";
1779 clock-names = "se";
1787 interconnect-names = "qup-core",
1788 "qup-config",
1789 "qup-memory";
1793 dma-names = "tx",
1796 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1797 pinctrl-names = "default";
1799 #address-cells = <1>;
1800 #size-cells = <0>;
1806 compatible = "qcom,geni-i2c";
1812 clock-names = "se";
1820 interconnect-names = "qup-core",
1821 "qup-config",
1822 "qup-memory";
1826 dma-names = "tx",
1829 pinctrl-0 = <&qup_i2c14_data_clk>;
1830 pinctrl-names = "default";
1832 #address-cells = <1>;
1833 #size-cells = <0>;
1839 compatible = "qcom,geni-spi";
1845 clock-names = "se";
1853 interconnect-names = "qup-core",
1854 "qup-config",
1855 "qup-memory";
1859 dma-names = "tx",
1862 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1863 pinctrl-names = "default";
1865 #address-cells = <1>;
1866 #size-cells = <0>;
1872 compatible = "qcom,geni-i2c";
1878 clock-names = "se";
1886 interconnect-names = "qup-core",
1887 "qup-config",
1888 "qup-memory";
1892 dma-names = "tx",
1895 pinctrl-0 = <&qup_i2c15_data_clk>;
1896 pinctrl-names = "default";
1898 #address-cells = <1>;
1899 #size-cells = <0>;
1905 compatible = "qcom,geni-spi";
1911 clock-names = "se";
1919 interconnect-names = "qup-core",
1920 "qup-config",
1921 "qup-memory";
1925 dma-names = "tx",
1928 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1929 pinctrl-names = "default";
1931 #address-cells = <1>;
1932 #size-cells = <0>;
1938 gpi_dma0: dma-controller@b00000 {
1939 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
1955 dma-channels = <12>;
1956 dma-channel-mask = <0x3e>;
1957 #dma-cells = <3>;
1965 compatible = "qcom,geni-se-qup";
1970 clock-names = "m-ahb",
1971 "s-ahb";
1974 #address-cells = <2>;
1975 #size-cells = <2>;
1981 compatible = "qcom,geni-i2c";
1987 clock-names = "se";
1995 interconnect-names = "qup-core",
1996 "qup-config",
1997 "qup-memory";
2001 dma-names = "tx",
2004 pinctrl-0 = <&qup_i2c0_data_clk>;
2005 pinctrl-names = "default";
2007 #address-cells = <1>;
2008 #size-cells = <0>;
2014 compatible = "qcom,geni-spi";
2020 clock-names = "se";
2028 interconnect-names = "qup-core",
2029 "qup-config",
2030 "qup-memory";
2034 dma-names = "tx",
2037 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
2038 pinctrl-names = "default";
2040 #address-cells = <1>;
2041 #size-cells = <0>;
2047 compatible = "qcom,geni-i2c";
2053 clock-names = "se";
2061 interconnect-names = "qup-core",
2062 "qup-config",
2063 "qup-memory";
2067 dma-names = "tx",
2070 pinctrl-0 = <&qup_i2c1_data_clk>;
2071 pinctrl-names = "default";
2073 #address-cells = <1>;
2074 #size-cells = <0>;
2080 compatible = "qcom,geni-spi";
2086 clock-names = "se";
2094 interconnect-names = "qup-core",
2095 "qup-config",
2096 "qup-memory";
2100 dma-names = "tx",
2103 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
2104 pinctrl-names = "default";
2106 #address-cells = <1>;
2107 #size-cells = <0>;
2113 compatible = "qcom,geni-i2c";
2119 clock-names = "se";
2127 interconnect-names = "qup-core",
2128 "qup-config",
2129 "qup-memory";
2133 dma-names = "tx",
2136 pinctrl-0 = <&qup_i2c2_data_clk>;
2137 pinctrl-names = "default";
2139 #address-cells = <1>;
2140 #size-cells = <0>;
2146 compatible = "qcom,geni-uart";
2152 clock-names = "se";
2158 interconnect-names = "qup-core",
2159 "qup-config";
2161 pinctrl-0 = <&qup_uart2_default>;
2162 pinctrl-names = "default";
2168 compatible = "qcom,geni-spi";
2174 clock-names = "se";
2182 interconnect-names = "qup-core",
2183 "qup-config",
2184 "qup-memory";
2188 dma-names = "tx",
2191 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
2192 pinctrl-names = "default";
2194 #address-cells = <1>;
2195 #size-cells = <0>;
2201 compatible = "qcom,geni-i2c";
2207 clock-names = "se";
2215 interconnect-names = "qup-core",
2216 "qup-config",
2217 "qup-memory";
2221 dma-names = "tx",
2224 pinctrl-0 = <&qup_i2c3_data_clk>;
2225 pinctrl-names = "default";
2227 #address-cells = <1>;
2228 #size-cells = <0>;
2234 compatible = "qcom,geni-spi";
2240 clock-names = "se";
2248 interconnect-names = "qup-core",
2249 "qup-config",
2250 "qup-memory";
2254 dma-names = "tx",
2257 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
2258 pinctrl-names = "default";
2260 #address-cells = <1>;
2261 #size-cells = <0>;
2267 compatible = "qcom,geni-i2c";
2273 clock-names = "se";
2281 interconnect-names = "qup-core",
2282 "qup-config",
2283 "qup-memory";
2287 dma-names = "tx",
2290 pinctrl-0 = <&qup_i2c4_data_clk>;
2291 pinctrl-names = "default";
2293 #address-cells = <1>;
2294 #size-cells = <0>;
2300 compatible = "qcom,geni-spi";
2306 clock-names = "se";
2314 interconnect-names = "qup-core",
2315 "qup-config",
2316 "qup-memory";
2320 dma-names = "tx",
2323 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
2324 pinctrl-names = "default";
2326 #address-cells = <1>;
2327 #size-cells = <0>;
2333 compatible = "qcom,geni-i2c";
2339 clock-names = "se";
2347 interconnect-names = "qup-core",
2348 "qup-config",
2349 "qup-memory";
2353 dma-names = "tx",
2356 pinctrl-0 = <&qup_i2c5_data_clk>;
2357 pinctrl-names = "default";
2359 #address-cells = <1>;
2360 #size-cells = <0>;
2366 compatible = "qcom,geni-spi";
2372 clock-names = "se";
2380 interconnect-names = "qup-core",
2381 "qup-config",
2382 "qup-memory";
2386 dma-names = "tx",
2389 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
2390 pinctrl-names = "default";
2392 #address-cells = <1>;
2393 #size-cells = <0>;
2399 compatible = "qcom,geni-i2c";
2405 clock-names = "se";
2413 interconnect-names = "qup-core",
2414 "qup-config",
2415 "qup-memory";
2419 dma-names = "tx",
2422 pinctrl-0 = <&qup_i2c6_data_clk>;
2423 pinctrl-names = "default";
2425 #address-cells = <1>;
2426 #size-cells = <0>;
2432 compatible = "qcom,geni-spi";
2438 clock-names = "se";
2446 interconnect-names = "qup-core",
2447 "qup-config",
2448 "qup-memory";
2452 dma-names = "tx",
2455 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
2456 pinctrl-names = "default";
2458 #address-cells = <1>;
2459 #size-cells = <0>;
2465 compatible = "qcom,geni-i2c";
2471 clock-names = "se";
2479 interconnect-names = "qup-core",
2480 "qup-config",
2481 "qup-memory";
2485 dma-names = "tx",
2488 pinctrl-0 = <&qup_i2c7_data_clk>;
2489 pinctrl-names = "default";
2491 #address-cells = <1>;
2492 #size-cells = <0>;
2498 compatible = "qcom,geni-spi";
2504 clock-names = "se";
2512 interconnect-names = "qup-core",
2513 "qup-config",
2514 "qup-memory";
2518 dma-names = "tx",
2521 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
2522 pinctrl-names = "default";
2524 #address-cells = <1>;
2525 #size-cells = <0>;
2531 tsens0: thermal-sensor@c271000 {
2532 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2536 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
2538 interrupt-names = "uplow",
2543 #thermal-sensor-cells = <1>;
2546 tsens1: thermal-sensor@c272000 {
2547 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2551 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
2553 interrupt-names = "uplow",
2558 #thermal-sensor-cells = <1>;
2561 tsens2: thermal-sensor@c273000 {
2562 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2566 interrupts-extended = <&pdc 28 IRQ_TYPE_LEVEL_HIGH>,
2568 interrupt-names = "uplow",
2573 #thermal-sensor-cells = <1>;
2576 tsens3: thermal-sensor@c274000 {
2577 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2581 interrupts-extended = <&pdc 29 IRQ_TYPE_LEVEL_HIGH>,
2583 interrupt-names = "uplow",
2588 #thermal-sensor-cells = <1>;
2592 compatible = "qcom,x1e80100-snps-eusb2-phy",
2593 "qcom,sm8550-snps-eusb2-phy";
2595 #phy-cells = <0>;
2598 clock-names = "ref";
2606 compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
2613 clock-names = "aux",
2618 power-domains = <&gcc GCC_USB_0_PHY_GDSC>;
2622 reset-names = "phy",
2625 #clock-cells = <1>;
2626 #phy-cells = <1>;
2628 orientation-switch;
2633 #address-cells = <1>;
2634 #size-cells = <0>;
2647 remote-endpoint = <&usb_1_ss0_dwc3_ss>;
2655 remote-endpoint = <&mdss_dp0_out>;
2662 compatible = "qcom,x1e80100-snps-eusb2-phy",
2663 "qcom,sm8550-snps-eusb2-phy";
2665 #phy-cells = <0>;
2668 clock-names = "ref";
2676 compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
2683 clock-names = "aux",
2688 power-domains = <&gcc GCC_USB_1_PHY_GDSC>;
2692 reset-names = "phy",
2695 #clock-cells = <1>;
2696 #phy-cells = <1>;
2698 orientation-switch;
2703 #address-cells = <1>;
2704 #size-cells = <0>;
2717 remote-endpoint = <&usb_1_ss1_dwc3_ss>;
2725 remote-endpoint = <&mdss_dp1_out>;
2732 compatible = "qcom,x1e80100-snps-eusb2-phy",
2733 "qcom,sm8550-snps-eusb2-phy";
2735 #phy-cells = <0>;
2738 clock-names = "ref";
2746 compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
2753 clock-names = "aux",
2758 power-domains = <&gcc GCC_USB_2_PHY_GDSC>;
2762 reset-names = "phy",
2765 #clock-cells = <1>;
2766 #phy-cells = <1>;
2768 orientation-switch;
2773 #address-cells = <1>;
2774 #size-cells = <0>;
2787 remote-endpoint = <&usb_1_ss2_dwc3_ss>;
2795 remote-endpoint = <&mdss_dp2_out>;
2802 compatible = "qcom,x1e80100-cnoc-main";
2805 qcom,bcm-voters = <&apps_bcm_voter>;
2807 #interconnect-cells = <2>;
2811 compatible = "qcom,x1e80100-cnoc-cfg";
2814 qcom,bcm-voters = <&apps_bcm_voter>;
2816 #interconnect-cells = <2>;
2820 compatible = "qcom,x1e80100-system-noc";
2823 qcom,bcm-voters = <&apps_bcm_voter>;
2825 #interconnect-cells = <2>;
2829 compatible = "qcom,x1e80100-pcie-south-anoc";
2832 qcom,bcm-voters = <&apps_bcm_voter>;
2834 #interconnect-cells = <2>;
2838 compatible = "qcom,x1e80100-pcie-center-anoc";
2841 qcom,bcm-voters = <&apps_bcm_voter>;
2843 #interconnect-cells = <2>;
2847 compatible = "qcom,x1e80100-aggre1-noc";
2850 qcom,bcm-voters = <&apps_bcm_voter>;
2852 #interconnect-cells = <2>;
2856 compatible = "qcom,x1e80100-aggre2-noc";
2859 qcom,bcm-voters = <&apps_bcm_voter>;
2861 #interconnect-cells = <2>;
2865 compatible = "qcom,x1e80100-pcie-north-anoc";
2868 qcom,bcm-voters = <&apps_bcm_voter>;
2870 #interconnect-cells = <2>;
2874 compatible = "qcom,x1e80100-usb-center-anoc";
2877 qcom,bcm-voters = <&apps_bcm_voter>;
2879 #interconnect-cells = <2>;
2883 compatible = "qcom,x1e80100-usb-north-anoc";
2886 qcom,bcm-voters = <&apps_bcm_voter>;
2888 #interconnect-cells = <2>;
2892 compatible = "qcom,x1e80100-usb-south-anoc";
2895 qcom,bcm-voters = <&apps_bcm_voter>;
2897 #interconnect-cells = <2>;
2901 compatible = "qcom,x1e80100-mmss-noc";
2904 qcom,bcm-voters = <&apps_bcm_voter>;
2906 #interconnect-cells = <2>;
2911 compatible = "qcom,pcie-x1e80100";
2918 reg-names = "parf",
2924 #address-cells = <3>;
2925 #size-cells = <2>;
2928 bus-range = <0x00 0xff>;
2930 dma-coherent;
2932 linux,pci-domain = <6>;
2933 num-lanes = <4>;
2935 msi-map = <0x0 &gic_its 0xe0000 0x10000>;
2945 interrupt-names = "msi0",
2954 #interrupt-cells = <1>;
2955 interrupt-map-mask = <0 0 0 0x7>;
2956 interrupt-map = <0 0 0 1 &intc 0 0 0 843 IRQ_TYPE_LEVEL_HIGH>,
2968 clock-names = "aux",
2976 assigned-clocks = <&gcc GCC_PCIE_6A_AUX_CLK>;
2977 assigned-clock-rates = <19200000>;
2983 interconnect-names = "pcie-mem",
2984 "cpu-pcie";
2988 reset-names = "pci",
2991 power-domains = <&gcc GCC_PCIE_6A_GDSC>;
2992 required-opps = <&rpmhpd_opp_nom>;
2995 phy-names = "pciephy";
3001 compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy";
3011 clock-names = "aux",
3020 reset-names = "phy",
3023 assigned-clocks = <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>;
3024 assigned-clock-rates = <100000000>;
3026 power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>;
3028 qcom,4ln-config-sel = <&tcsr 0x1a000 0>;
3030 #clock-cells = <0>;
3031 clock-output-names = "pcie6a_pipe_clk";
3033 #phy-cells = <0>;
3040 compatible = "qcom,pcie-x1e80100";
3047 reg-names = "parf",
3053 #address-cells = <3>;
3054 #size-cells = <2>;
3057 bus-range = <0x00 0xff>;
3059 dma-coherent;
3061 linux,pci-domain = <5>;
3062 num-lanes = <2>;
3072 interrupt-names = "msi0",
3081 #interrupt-cells = <1>;
3082 interrupt-map-mask = <0 0 0 0x7>;
3083 interrupt-map = <0 0 0 1 &intc 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>,
3095 clock-names = "aux",
3103 assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>;
3104 assigned-clock-rates = <19200000>;
3110 interconnect-names = "pcie-mem",
3111 "cpu-pcie";
3115 reset-names = "pci",
3118 power-domains = <&gcc GCC_PCIE_5_GDSC>;
3119 required-opps = <&rpmhpd_opp_nom>;
3122 phy-names = "pciephy";
3128 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy";
3137 clock-names = "aux",
3145 reset-names = "phy";
3147 assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>;
3148 assigned-clock-rates = <100000000>;
3150 power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>;
3152 #clock-cells = <0>;
3153 clock-output-names = "pcie5_pipe_clk";
3155 #phy-cells = <0>;
3162 compatible = "qcom,pcie-x1e80100";
3169 reg-names = "parf",
3175 #address-cells = <3>;
3176 #size-cells = <2>;
3179 bus-range = <0x00 0xff>;
3181 dma-coherent;
3183 linux,pci-domain = <4>;
3184 num-lanes = <2>;
3186 msi-map = <0x0 &gic_its 0xc0000 0x10000>;
3196 interrupt-names = "msi0",
3205 #interrupt-cells = <1>;
3206 interrupt-map-mask = <0 0 0 0x7>;
3207 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
3219 clock-names = "aux",
3227 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
3228 assigned-clock-rates = <19200000>;
3234 interconnect-names = "pcie-mem",
3235 "cpu-pcie";
3239 reset-names = "pci",
3242 power-domains = <&gcc GCC_PCIE_4_GDSC>;
3243 required-opps = <&rpmhpd_opp_nom>;
3246 phy-names = "pciephy";
3253 bus-range = <0x01 0xff>;
3255 #address-cells = <3>;
3256 #size-cells = <2>;
3262 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy";
3271 clock-names = "aux",
3279 reset-names = "phy";
3281 assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>;
3282 assigned-clock-rates = <100000000>;
3284 power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>;
3286 #clock-cells = <0>;
3287 clock-output-names = "pcie4_pipe_clk";
3289 #phy-cells = <0>;
3295 compatible = "qcom,tcsr-mutex";
3297 #hwlock-cells = <1>;
3300 tcsr: clock-controller@1fc0000 {
3301 compatible = "qcom,x1e80100-tcsr", "syscon";
3304 #clock-cells = <1>;
3305 #reset-cells = <1>;
3309 compatible = "qcom,adreno-43050c01", "qcom,adreno";
3314 reg-names = "kgsl_3d0_reg_memory",
3323 operating-points-v2 = <&gpu_opp_table>;
3326 #cooling-cells = <2>;
3329 interconnect-names = "gfx-mem";
3333 zap-shader {
3334 memory-region = <&gpu_microcode_mem>;
3337 gpu_opp_table: opp-table {
3338 compatible = "operating-points-v2";
3340 opp-1100000000 {
3341 opp-hz = /bits/ 64 <1100000000>;
3342 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3343 opp-peak-kBps = <16500000>;
3346 opp-1000000000 {
3347 opp-hz = /bits/ 64 <1000000000>;
3348 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3349 opp-peak-kBps = <14398438>;
3352 opp-925000000 {
3353 opp-hz = /bits/ 64 <925000000>;
3354 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3355 opp-peak-kBps = <14398438>;
3358 opp-800000000 {
3359 opp-hz = /bits/ 64 <800000000>;
3360 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3361 opp-peak-kBps = <12449219>;
3364 opp-744000000 {
3365 opp-hz = /bits/ 64 <744000000>;
3366 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
3367 opp-peak-kBps = <10687500>;
3370 opp-687000000 {
3371 opp-hz = /bits/ 64 <687000000>;
3372 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3373 opp-peak-kBps = <8171875>;
3376 opp-550000000 {
3377 opp-hz = /bits/ 64 <550000000>;
3378 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3379 opp-peak-kBps = <6074219>;
3382 opp-390000000 {
3383 opp-hz = /bits/ 64 <390000000>;
3384 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3385 opp-peak-kBps = <3000000>;
3388 opp-300000000 {
3389 opp-hz = /bits/ 64 <300000000>;
3390 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
3391 opp-peak-kBps = <2136719>;
3397 compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu";
3401 reg-names = "gmu", "rscc", "gmu_pdc";
3405 interrupt-names = "hfi", "gmu";
3414 clock-names = "ahb",
3422 power-domains = <&gpucc GPU_CX_GDSC>,
3424 power-domain-names = "cx",
3431 operating-points-v2 = <&gmu_opp_table>;
3433 gmu_opp_table: opp-table {
3434 compatible = "operating-points-v2";
3436 opp-550000000 {
3437 opp-hz = /bits/ 64 <550000000>;
3438 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3441 opp-220000000 {
3442 opp-hz = /bits/ 64 <220000000>;
3443 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3448 gpucc: clock-controller@3d90000 {
3449 compatible = "qcom,x1e80100-gpucc";
3454 #clock-cells = <1>;
3455 #reset-cells = <1>;
3456 #power-domain-cells = <1>;
3460 compatible = "qcom,x1e80100-smmu-500", "qcom,adreno-smmu",
3461 "qcom,smmu-500", "arm,mmu-500";
3463 #iommu-cells = <2>;
3464 #global-interrupts = <1>;
3495 clock-names = "hlos",
3499 power-domains = <&gpucc GPU_CX_GDSC>;
3500 dma-coherent;
3504 compatible = "qcom,x1e80100-gem-noc";
3507 qcom,bcm-voters = <&apps_bcm_voter>;
3509 #interconnect-cells = <2>;
3513 compatible = "qcom,x1e80100-nsp-noc";
3516 qcom,bcm-voters = <&apps_bcm_voter>;
3518 #interconnect-cells = <2>;
3522 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
3528 clock-names = "mclk",
3533 #clock-cells = <0>;
3534 clock-output-names = "wsa2-mclk";
3535 #sound-dai-cells = <1>;
3536 sound-name-prefix = "WSA2";
3540 compatible = "qcom,soundwire-v2.0.0";
3543 clock-names = "iface";
3547 pinctrl-0 = <&wsa2_swr_active>;
3548 pinctrl-names = "default";
3550 reset-names = "swr_audio_cgcr";
3552 qcom,din-ports = <4>;
3553 qcom,dout-ports = <9>;
3555 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x3…
3556 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
3557 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3558 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3559 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3560 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
3561 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
3562 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
3563 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
3565 #address-cells = <2>;
3566 #size-cells = <0>;
3567 #sound-dai-cells = <1>;
3572 compatible = "qcom,x1e80100-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro";
3578 clock-names = "mclk",
3583 #clock-cells = <0>;
3584 clock-output-names = "mclk";
3585 #sound-dai-cells = <1>;
3589 compatible = "qcom,soundwire-v2.0.0";
3592 clock-names = "iface";
3596 pinctrl-0 = <&rx_swr_active>;
3597 pinctrl-names = "default";
3600 reset-names = "swr_audio_cgcr";
3601 qcom,din-ports = <1>;
3602 qcom,dout-ports = <11>;
3604 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3605 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3606 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3607 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3608 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3609 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3610 …qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff…
3611 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
3612 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3614 #address-cells = <2>;
3615 #size-cells = <0>;
3616 #sound-dai-cells = <1>;
3621 compatible = "qcom,x1e80100-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro";
3627 clock-names = "mclk",
3632 #clock-cells = <0>;
3633 clock-output-names = "mclk";
3634 #sound-dai-cells = <1>;
3638 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
3644 clock-names = "mclk",
3649 #clock-cells = <0>;
3650 clock-output-names = "mclk";
3651 #sound-dai-cells = <1>;
3652 sound-name-prefix = "WSA";
3656 compatible = "qcom,soundwire-v2.0.0";
3659 clock-names = "iface";
3663 pinctrl-0 = <&wsa_swr_active>;
3664 pinctrl-names = "default";
3666 reset-names = "swr_audio_cgcr";
3668 qcom,din-ports = <4>;
3669 qcom,dout-ports = <9>;
3671 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x3…
3672 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
3673 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3674 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3675 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3676 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
3677 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
3678 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
3679 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
3681 #address-cells = <2>;
3682 #size-cells = <0>;
3683 #sound-dai-cells = <1>;
3687 lpass_audiocc: clock-controller@6b6c000 {
3688 compatible = "qcom,x1e80100-lpassaudiocc", "qcom,sc8280xp-lpassaudiocc";
3690 #clock-cells = <1>;
3691 #reset-cells = <1>;
3695 compatible = "qcom,soundwire-v2.0.0";
3698 clock-names = "iface";
3701 interrupt-names = "core", "wakeup";
3704 reset-names = "swr_audio_cgcr";
3706 pinctrl-0 = <&tx_swr_active>;
3707 pinctrl-names = "default";
3709 qcom,din-ports = <4>;
3710 qcom,dout-ports = <1>;
3712 qcom,ports-sinterval-low = /bits/ 8 <0x00 0x01 0x03 0x03 0x00>;
3713 qcom,ports-offset1 = /bits/ 8 <0x00 0x01 0x02 0x00 0x00>;
3714 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00 0xff>;
3715 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3716 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3717 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3718 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3719 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3720 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x00 0x01 0xff>;
3722 #address-cells = <2>;
3723 #size-cells = <0>;
3724 #sound-dai-cells = <1>;
3729 compatible = "qcom,x1e80100-lpass-va-macro", "qcom,sm8550-lpass-va-macro";
3734 clock-names = "mclk",
3738 #clock-cells = <0>;
3739 clock-output-names = "fsgen";
3740 #sound-dai-cells = <1>;
3744 compatible = "qcom,x1e80100-lpass-lpi-pinctrl", "qcom,sm8550-lpass-lpi-pinctrl";
3750 clock-names = "core", "audio";
3752 gpio-controller;
3753 #gpio-cells = <2>;
3754 gpio-ranges = <&lpass_tlmm 0 0 23>;
3756 tx_swr_active: tx-swr-active-state {
3757 clk-pins {
3760 drive-strength = <2>;
3761 slew-rate = <1>;
3762 bias-disable;
3765 data-pins {
3768 drive-strength = <2>;
3769 slew-rate = <1>;
3770 bias-bus-hold;
3774 rx_swr_active: rx-swr-active-state {
3775 clk-pins {
3778 drive-strength = <2>;
3779 slew-rate = <1>;
3780 bias-disable;
3783 data-pins {
3786 drive-strength = <2>;
3787 slew-rate = <1>;
3788 bias-bus-hold;
3792 dmic01_default: dmic01-default-state {
3793 clk-pins {
3796 drive-strength = <8>;
3797 output-high;
3800 data-pins {
3803 drive-strength = <8>;
3804 input-enable;
3808 dmic23_default: dmic23-default-state {
3809 clk-pins {
3812 drive-strength = <8>;
3813 output-high;
3816 data-pins {
3819 drive-strength = <8>;
3820 input-enable;
3824 wsa_swr_active: wsa-swr-active-state {
3825 clk-pins {
3828 drive-strength = <2>;
3829 slew-rate = <1>;
3830 bias-disable;
3833 data-pins {
3836 drive-strength = <2>;
3837 slew-rate = <1>;
3838 bias-bus-hold;
3842 wsa2_swr_active: wsa2-swr-active-state {
3843 clk-pins {
3846 drive-strength = <2>;
3847 slew-rate = <1>;
3848 bias-disable;
3851 data-pins {
3854 drive-strength = <2>;
3855 slew-rate = <1>;
3856 bias-bus-hold;
3861 lpasscc: clock-controller@6ea0000 {
3862 compatible = "qcom,x1e80100-lpasscc", "qcom,sc8280xp-lpasscc";
3864 #clock-cells = <1>;
3865 #reset-cells = <1>;
3869 compatible = "qcom,x1e80100-lpass-ag-noc";
3872 qcom,bcm-voters = <&apps_bcm_voter>;
3874 #interconnect-cells = <2>;
3878 compatible = "qcom,x1e80100-lpass-lpiaon-noc";
3881 qcom,bcm-voters = <&apps_bcm_voter>;
3883 #interconnect-cells = <2>;
3887 compatible = "qcom,x1e80100-lpass-lpicx-noc";
3890 qcom,bcm-voters = <&apps_bcm_voter>;
3892 #interconnect-cells = <2>;
3896 compatible = "qcom,x1e80100-snps-eusb2-phy",
3897 "qcom,sm8550-snps-eusb2-phy";
3899 #phy-cells = <0>;
3902 clock-names = "ref";
3910 compatible = "qcom,x1e80100-snps-eusb2-phy",
3911 "qcom,sm8550-snps-eusb2-phy";
3913 #phy-cells = <0>;
3916 clock-names = "ref";
3924 compatible = "qcom,x1e80100-snps-eusb2-phy",
3925 "qcom,sm8550-snps-eusb2-phy";
3927 #phy-cells = <0>;
3930 clock-names = "ref";
3938 compatible = "qcom,x1e80100-qmp-usb3-uni-phy";
3945 clock-names = "aux",
3952 reset-names = "phy",
3955 power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>;
3957 #clock-cells = <0>;
3958 clock-output-names = "usb_mp_phy0_pipe_clk";
3960 #phy-cells = <0>;
3966 compatible = "qcom,x1e80100-qmp-usb3-uni-phy";
3973 clock-names = "aux",
3980 reset-names = "phy",
3983 power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>;
3985 #clock-cells = <0>;
3986 clock-output-names = "usb_mp_phy1_pipe_clk";
3988 #phy-cells = <0>;
3994 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
4006 clock-names = "cfg_noc",
4016 assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>,
4018 assigned-clock-rates = <19200000>,
4021 interrupts-extended = <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
4025 interrupt-names = "pwr_event",
4030 power-domains = <&gcc GCC_USB30_TERT_GDSC>;
4031 required-opps = <&rpmhpd_opp_nom>;
4039 interconnect-names = "usb-ddr",
4040 "apps-usb";
4042 wakeup-source;
4044 #address-cells = <2>;
4045 #size-cells = <2>;
4060 phy-names = "usb2-phy",
4061 "usb3-phy";
4067 dma-coherent;
4069 usb-role-switch;
4072 #address-cells = <1>;
4073 #size-cells = <0>;
4086 remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>;
4094 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
4096 #address-cells = <2>;
4097 #size-cells = <2>;
4109 clock-names = "cfg_noc",
4119 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
4121 assigned-clock-rates = <19200000>, <200000000>;
4123 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4126 interrupt-names = "pwr_event",
4130 power-domains = <&gcc GCC_USB20_PRIM_GDSC>;
4131 required-opps = <&rpmhpd_opp_nom>;
4139 interconnect-names = "usb-ddr",
4140 "apps-usb";
4142 wakeup-source;
4152 phy-names = "usb2-phy";
4153 maximum-speed = "high-speed";
4156 #address-cells = <1>;
4157 #size-cells = <0>;
4170 compatible = "qcom,x1e80100-dwc3-mp", "qcom,dwc3";
4182 clock-names = "cfg_noc",
4192 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
4194 assigned-clock-rates = <19200000>,
4197 interrupts-extended = <&intc GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
4207 interrupt-names = "pwr_event_1", "pwr_event_2",
4213 power-domains = <&gcc GCC_USB30_MP_GDSC>;
4214 required-opps = <&rpmhpd_opp_nom>;
4222 interconnect-names = "usb-ddr",
4223 "apps-usb";
4225 wakeup-source;
4227 #address-cells = <2>;
4228 #size-cells = <2>;
4243 phy-names = "usb2-0", "usb3-0",
4244 "usb2-1", "usb3-1";
4251 dma-coherent;
4256 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
4268 clock-names = "cfg_noc",
4278 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4280 assigned-clock-rates = <19200000>,
4283 interrupts-extended = <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
4287 interrupt-names = "pwr_event",
4292 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
4293 required-opps = <&rpmhpd_opp_nom>;
4297 wakeup-source;
4299 #address-cells = <2>;
4300 #size-cells = <2>;
4315 phy-names = "usb2-phy",
4316 "usb3-phy";
4322 dma-coherent;
4324 usb-role-switch;
4327 #address-cells = <1>;
4328 #size-cells = <0>;
4341 remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>;
4349 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
4361 clock-names = "cfg_noc",
4371 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4373 assigned-clock-rates = <19200000>,
4376 interrupts-extended = <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
4380 interrupt-names = "pwr_event",
4385 power-domains = <&gcc GCC_USB30_SEC_GDSC>;
4386 required-opps = <&rpmhpd_opp_nom>;
4394 interconnect-names = "usb-ddr",
4395 "apps-usb";
4397 wakeup-source;
4399 #address-cells = <2>;
4400 #size-cells = <2>;
4415 phy-names = "usb2-phy",
4416 "usb3-phy";
4422 dma-coherent;
4424 usb-role-switch;
4427 #address-cells = <1>;
4428 #size-cells = <0>;
4441 remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>;
4448 mdss: display-subsystem@ae00000 {
4449 compatible = "qcom,x1e80100-mdss";
4451 reg-names = "mdss";
4467 interconnect-names = "mdp0-mem",
4468 "mdp1-mem",
4469 "cpu-cfg";
4471 power-domains = <&dispcc MDSS_GDSC>;
4475 interrupt-controller;
4476 #interrupt-cells = <1>;
4478 #address-cells = <2>;
4479 #size-cells = <2>;
4484 mdss_mdp: display-controller@ae01000 {
4485 compatible = "qcom,x1e80100-dpu";
4488 reg-names = "mdp",
4491 interrupts-extended = <&mdss 0>;
4498 clock-names = "nrt_bus",
4504 operating-points-v2 = <&mdp_opp_table>;
4506 power-domains = <&rpmhpd RPMHPD_MMCX>;
4509 #address-cells = <1>;
4510 #size-cells = <0>;
4516 remote-endpoint = <&mdss_dp0_in>;
4524 remote-endpoint = <&mdss_dp1_in>;
4532 remote-endpoint = <&mdss_dp3_in>;
4540 remote-endpoint = <&mdss_dp2_in>;
4545 mdp_opp_table: opp-table {
4546 compatible = "operating-points-v2";
4548 opp-200000000 {
4549 opp-hz = /bits/ 64 <200000000>;
4550 required-opps = <&rpmhpd_opp_low_svs>;
4553 opp-325000000 {
4554 opp-hz = /bits/ 64 <325000000>;
4555 required-opps = <&rpmhpd_opp_svs>;
4558 opp-375000000 {
4559 opp-hz = /bits/ 64 <375000000>;
4560 required-opps = <&rpmhpd_opp_svs_l1>;
4563 opp-514000000 {
4564 opp-hz = /bits/ 64 <514000000>;
4565 required-opps = <&rpmhpd_opp_nom>;
4568 opp-575000000 {
4569 opp-hz = /bits/ 64 <575000000>;
4570 required-opps = <&rpmhpd_opp_nom_l1>;
4575 mdss_dp0: displayport-controller@ae90000 {
4576 compatible = "qcom,x1e80100-dp";
4583 interrupts-extended = <&mdss 12>;
4590 clock-names = "core_iface",
4596 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
4598 assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4601 operating-points-v2 = <&mdss_dp0_opp_table>;
4603 power-domains = <&rpmhpd RPMHPD_MMCX>;
4606 phy-names = "dp";
4608 #sound-dai-cells = <0>;
4613 #address-cells = <1>;
4614 #size-cells = <0>;
4620 remote-endpoint = <&mdss_intf0_out>;
4628 remote-endpoint = <&usb_1_ss0_qmpphy_dp_in>;
4633 mdss_dp0_opp_table: opp-table {
4634 compatible = "operating-points-v2";
4636 opp-160000000 {
4637 opp-hz = /bits/ 64 <160000000>;
4638 required-opps = <&rpmhpd_opp_low_svs>;
4641 opp-270000000 {
4642 opp-hz = /bits/ 64 <270000000>;
4643 required-opps = <&rpmhpd_opp_svs>;
4646 opp-540000000 {
4647 opp-hz = /bits/ 64 <540000000>;
4648 required-opps = <&rpmhpd_opp_svs_l1>;
4651 opp-810000000 {
4652 opp-hz = /bits/ 64 <810000000>;
4653 required-opps = <&rpmhpd_opp_nom>;
4658 mdss_dp1: displayport-controller@ae98000 {
4659 compatible = "qcom,x1e80100-dp";
4666 interrupts-extended = <&mdss 13>;
4673 clock-names = "core_iface",
4679 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
4681 assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4684 operating-points-v2 = <&mdss_dp1_opp_table>;
4686 power-domains = <&rpmhpd RPMHPD_MMCX>;
4689 phy-names = "dp";
4691 #sound-dai-cells = <0>;
4696 #address-cells = <1>;
4697 #size-cells = <0>;
4703 remote-endpoint = <&mdss_intf4_out>;
4711 remote-endpoint = <&usb_1_ss1_qmpphy_dp_in>;
4716 mdss_dp1_opp_table: opp-table {
4717 compatible = "operating-points-v2";
4719 opp-160000000 {
4720 opp-hz = /bits/ 64 <160000000>;
4721 required-opps = <&rpmhpd_opp_low_svs>;
4724 opp-270000000 {
4725 opp-hz = /bits/ 64 <270000000>;
4726 required-opps = <&rpmhpd_opp_svs>;
4729 opp-540000000 {
4730 opp-hz = /bits/ 64 <540000000>;
4731 required-opps = <&rpmhpd_opp_svs_l1>;
4734 opp-810000000 {
4735 opp-hz = /bits/ 64 <810000000>;
4736 required-opps = <&rpmhpd_opp_nom>;
4741 mdss_dp2: displayport-controller@ae9a000 {
4742 compatible = "qcom,x1e80100-dp";
4749 interrupts-extended = <&mdss 14>;
4756 clock-names = "core_iface",
4762 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
4764 assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4767 operating-points-v2 = <&mdss_dp2_opp_table>;
4769 power-domains = <&rpmhpd RPMHPD_MMCX>;
4772 phy-names = "dp";
4774 #sound-dai-cells = <0>;
4779 #address-cells = <1>;
4780 #size-cells = <0>;
4785 remote-endpoint = <&mdss_intf6_out>;
4793 remote-endpoint = <&usb_1_ss2_qmpphy_dp_in>;
4798 mdss_dp2_opp_table: opp-table {
4799 compatible = "operating-points-v2";
4801 opp-160000000 {
4802 opp-hz = /bits/ 64 <160000000>;
4803 required-opps = <&rpmhpd_opp_low_svs>;
4806 opp-270000000 {
4807 opp-hz = /bits/ 64 <270000000>;
4808 required-opps = <&rpmhpd_opp_svs>;
4811 opp-540000000 {
4812 opp-hz = /bits/ 64 <540000000>;
4813 required-opps = <&rpmhpd_opp_svs_l1>;
4816 opp-810000000 {
4817 opp-hz = /bits/ 64 <810000000>;
4818 required-opps = <&rpmhpd_opp_nom>;
4823 mdss_dp3: displayport-controller@aea0000 {
4824 compatible = "qcom,x1e80100-dp";
4831 interrupts-extended = <&mdss 15>;
4838 clock-names = "core_iface",
4844 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
4846 assigned-clock-parents = <&mdss_dp3_phy 0>,
4849 operating-points-v2 = <&mdss_dp3_opp_table>;
4851 power-domains = <&rpmhpd RPMHPD_MMCX>;
4854 phy-names = "dp";
4856 #sound-dai-cells = <0>;
4861 #address-cells = <1>;
4862 #size-cells = <0>;
4868 remote-endpoint = <&mdss_intf5_out>;
4877 mdss_dp3_opp_table: opp-table {
4878 compatible = "operating-points-v2";
4880 opp-160000000 {
4881 opp-hz = /bits/ 64 <160000000>;
4882 required-opps = <&rpmhpd_opp_low_svs>;
4885 opp-270000000 {
4886 opp-hz = /bits/ 64 <270000000>;
4887 required-opps = <&rpmhpd_opp_svs>;
4890 opp-540000000 {
4891 opp-hz = /bits/ 64 <540000000>;
4892 required-opps = <&rpmhpd_opp_svs_l1>;
4895 opp-810000000 {
4896 opp-hz = /bits/ 64 <810000000>;
4897 required-opps = <&rpmhpd_opp_nom>;
4905 compatible = "qcom,x1e80100-dp-phy";
4913 clock-names = "aux",
4916 power-domains = <&rpmhpd RPMHPD_MX>;
4918 #clock-cells = <1>;
4919 #phy-cells = <0>;
4925 compatible = "qcom,x1e80100-dp-phy";
4933 clock-names = "aux",
4936 power-domains = <&rpmhpd RPMHPD_MX>;
4938 #clock-cells = <1>;
4939 #phy-cells = <0>;
4944 dispcc: clock-controller@af00000 {
4945 compatible = "qcom,x1e80100-dispcc";
4963 power-domains = <&rpmhpd RPMHPD_MMCX>;
4964 required-opps = <&rpmhpd_opp_low_svs>;
4965 #clock-cells = <1>;
4966 #reset-cells = <1>;
4967 #power-domain-cells = <1>;
4970 pdc: interrupt-controller@b220000 {
4971 compatible = "qcom,x1e80100-pdc", "qcom,pdc";
4974 qcom,pdc-ranges = <0 480 42>, <42 251 5>,
4977 #interrupt-cells = <2>;
4978 interrupt-parent = <&intc>;
4979 interrupt-controller;
4982 aoss_qmp: power-management@c300000 {
4983 compatible = "qcom,x1e80100-aoss-qmp", "qcom,aoss-qmp";
4985 interrupt-parent = <&ipcc>;
4986 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
4990 #clock-cells = <0>;
4994 compatible = "qcom,rpmh-stats";
4999 compatible = "qcom,x1e80100-spmi-pmic-arb";
5003 reg-names = "core", "chnls", "obsrvr";
5008 #address-cells = <2>;
5009 #size-cells = <2>;
5015 reg-names = "cnfg", "intr";
5017 interrupt-names = "periph_irq";
5018 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5019 interrupt-controller;
5020 #interrupt-cells = <4>;
5022 #address-cells = <2>;
5023 #size-cells = <0>;
5029 reg-names = "cnfg", "intr";
5031 interrupt-names = "periph_irq";
5032 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
5033 interrupt-controller;
5034 #interrupt-cells = <4>;
5036 #address-cells = <2>;
5037 #size-cells = <0>;
5042 compatible = "qcom,x1e80100-tlmm";
5047 gpio-controller;
5048 #gpio-cells = <2>;
5050 interrupt-controller;
5051 #interrupt-cells = <2>;
5053 gpio-ranges = <&tlmm 0 0 239>;
5054 wakeup-parent = <&pdc>;
5056 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
5060 drive-strength = <2>;
5061 bias-pull-up = <2200>;
5064 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
5068 drive-strength = <2>;
5069 bias-pull-up = <2200>;
5072 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
5076 drive-strength = <2>;
5077 bias-pull-up = <2200>;
5080 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
5084 drive-strength = <2>;
5085 bias-pull-up = <2200>;
5088 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
5092 drive-strength = <2>;
5093 bias-pull-up = <2200>;
5096 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
5098 pins = "gpio20", "gpio21";
5100 drive-strength = <2>;
5101 bias-pull-up = <2200>;
5104 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
5108 drive-strength = <2>;
5109 bias-pull-up = <2200>;
5112 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
5116 drive-strength = <2>;
5117 bias-pull-up = <2200>;
5120 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
5124 drive-strength = <2>;
5125 bias-pull-up = <2200>;
5128 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
5132 drive-strength = <2>;
5133 bias-pull-up = <2200>;
5136 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
5140 drive-strength = <2>;
5141 bias-pull-up = <2200>;
5144 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
5148 drive-strength = <2>;
5149 bias-pull-up = <2200>;
5152 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
5156 drive-strength = <2>;
5157 bias-pull-up = <2200>;
5160 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
5164 drive-strength = <2>;
5165 bias-pull-up = <2200>;
5168 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
5172 drive-strength = <2>;
5173 bias-pull-up = <2200>;
5176 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
5180 drive-strength = <2>;
5181 bias-pull-up = <2200>;
5184 qup_i2c16_data_clk: qup-i2c16-data-clk-state {
5188 drive-strength = <2>;
5189 bias-pull-up = <2200>;
5192 qup_i2c17_data_clk: qup-i2c17-data-clk-state {
5196 drive-strength = <2>;
5197 bias-pull-up = <2200>;
5200 qup_i2c18_data_clk: qup-i2c18-data-clk-state {
5204 drive-strength = <2>;
5205 bias-pull-up = <2200>;
5208 qup_i2c19_data_clk: qup-i2c19-data-clk-state {
5212 drive-strength = <2>;
5213 bias-pull-up = <2200>;
5216 qup_i2c20_data_clk: qup-i2c20-data-clk-state {
5220 drive-strength = <2>;
5221 bias-pull-up = <2200>;
5224 qup_i2c21_data_clk: qup-i2c21-data-clk-state {
5228 drive-strength = <2>;
5229 bias-pull-up = <2200>;
5232 qup_i2c22_data_clk: qup-i2c22-data-clk-state {
5236 drive-strength = <2>;
5237 bias-pull-up = <2200>;
5240 qup_i2c23_data_clk: qup-i2c23-data-clk-state {
5244 drive-strength = <2>;
5245 bias-pull-up = <2200>;
5248 qup_spi0_cs: qup-spi0-cs-state {
5251 drive-strength = <6>;
5252 bias-disable;
5255 qup_spi0_data_clk: qup-spi0-data-clk-state {
5259 drive-strength = <6>;
5260 bias-disable;
5263 qup_spi1_cs: qup-spi1-cs-state {
5266 drive-strength = <6>;
5267 bias-disable;
5270 qup_spi1_data_clk: qup-spi1-data-clk-state {
5274 drive-strength = <6>;
5275 bias-disable;
5278 qup_spi2_cs: qup-spi2-cs-state {
5281 drive-strength = <6>;
5282 bias-disable;
5285 qup_spi2_data_clk: qup-spi2-data-clk-state {
5289 drive-strength = <6>;
5290 bias-disable;
5293 qup_spi3_cs: qup-spi3-cs-state {
5296 drive-strength = <6>;
5297 bias-disable;
5300 qup_spi3_data_clk: qup-spi3-data-clk-state {
5304 drive-strength = <6>;
5305 bias-disable;
5308 qup_spi4_cs: qup-spi4-cs-state {
5311 drive-strength = <6>;
5312 bias-disable;
5315 qup_spi4_data_clk: qup-spi4-data-clk-state {
5319 drive-strength = <6>;
5320 bias-disable;
5323 qup_spi5_cs: qup-spi5-cs-state {
5326 drive-strength = <6>;
5327 bias-disable;
5330 qup_spi5_data_clk: qup-spi5-data-clk-state {
5332 pins = "gpio20", "gpio21", "gpio22";
5334 drive-strength = <6>;
5335 bias-disable;
5338 qup_spi6_cs: qup-spi6-cs-state {
5341 drive-strength = <6>;
5342 bias-disable;
5345 qup_spi6_data_clk: qup-spi6-data-clk-state {
5349 drive-strength = <6>;
5350 bias-disable;
5353 qup_spi7_cs: qup-spi7-cs-state {
5356 drive-strength = <6>;
5357 bias-disable;
5360 qup_spi7_data_clk: qup-spi7-data-clk-state {
5364 drive-strength = <6>;
5365 bias-disable;
5368 qup_spi8_cs: qup-spi8-cs-state {
5371 drive-strength = <6>;
5372 bias-disable;
5375 qup_spi8_data_clk: qup-spi8-data-clk-state {
5379 drive-strength = <6>;
5380 bias-disable;
5383 qup_spi9_cs: qup-spi9-cs-state {
5386 drive-strength = <6>;
5387 bias-disable;
5390 qup_spi9_data_clk: qup-spi9-data-clk-state {
5394 drive-strength = <6>;
5395 bias-disable;
5398 qup_spi10_cs: qup-spi10-cs-state {
5401 drive-strength = <6>;
5402 bias-disable;
5405 qup_spi10_data_clk: qup-spi10-data-clk-state {
5409 drive-strength = <6>;
5410 bias-disable;
5413 qup_spi11_cs: qup-spi11-cs-state {
5416 drive-strength = <6>;
5417 bias-disable;
5420 qup_spi11_data_clk: qup-spi11-data-clk-state {
5424 drive-strength = <6>;
5425 bias-disable;
5428 qup_spi12_cs: qup-spi12-cs-state {
5431 drive-strength = <6>;
5432 bias-disable;
5435 qup_spi12_data_clk: qup-spi12-data-clk-state {
5439 drive-strength = <6>;
5440 bias-disable;
5443 qup_spi13_cs: qup-spi13-cs-state {
5446 drive-strength = <6>;
5447 bias-disable;
5450 qup_spi13_data_clk: qup-spi13-data-clk-state {
5454 drive-strength = <6>;
5455 bias-disable;
5458 qup_spi14_cs: qup-spi14-cs-state {
5461 drive-strength = <6>;
5462 bias-disable;
5465 qup_spi14_data_clk: qup-spi14-data-clk-state {
5469 drive-strength = <6>;
5470 bias-disable;
5473 qup_spi15_cs: qup-spi15-cs-state {
5476 drive-strength = <6>;
5477 bias-disable;
5480 qup_spi15_data_clk: qup-spi15-data-clk-state {
5484 drive-strength = <6>;
5485 bias-disable;
5488 qup_spi16_cs: qup-spi16-cs-state {
5491 drive-strength = <6>;
5492 bias-disable;
5495 qup_spi16_data_clk: qup-spi16-data-clk-state {
5499 drive-strength = <6>;
5500 bias-disable;
5503 qup_spi17_cs: qup-spi17-cs-state {
5506 drive-strength = <6>;
5507 bias-disable;
5510 qup_spi17_data_clk: qup-spi17-data-clk-state {
5514 drive-strength = <6>;
5515 bias-disable;
5518 qup_spi18_cs: qup-spi18-cs-state {
5521 drive-strength = <6>;
5522 bias-disable;
5525 qup_spi18_data_clk: qup-spi18-data-clk-state {
5529 drive-strength = <6>;
5530 bias-disable;
5533 qup_spi19_cs: qup-spi19-cs-state {
5536 drive-strength = <6>;
5537 bias-disable;
5540 qup_spi19_data_clk: qup-spi19-data-clk-state {
5544 drive-strength = <6>;
5545 bias-disable;
5548 qup_spi20_cs: qup-spi20-cs-state {
5551 drive-strength = <6>;
5552 bias-disable;
5555 qup_spi20_data_clk: qup-spi20-data-clk-state {
5559 drive-strength = <6>;
5560 bias-disable;
5563 qup_spi21_cs: qup-spi21-cs-state {
5566 drive-strength = <6>;
5567 bias-disable;
5570 qup_spi21_data_clk: qup-spi21-data-clk-state {
5574 drive-strength = <6>;
5575 bias-disable;
5578 qup_spi22_cs: qup-spi22-cs-state {
5581 drive-strength = <6>;
5582 bias-disable;
5585 qup_spi22_data_clk: qup-spi22-data-clk-state {
5589 drive-strength = <6>;
5590 bias-disable;
5593 qup_spi23_cs: qup-spi23-cs-state {
5596 drive-strength = <6>;
5597 bias-disable;
5600 qup_spi23_data_clk: qup-spi23-data-clk-state {
5604 drive-strength = <6>;
5605 bias-disable;
5608 qup_uart2_default: qup-uart2-default-state {
5609 cts-pins {
5612 drive-strength = <2>;
5613 bias-disable;
5616 rts-pins {
5619 drive-strength = <2>;
5620 bias-disable;
5623 tx-pins {
5626 drive-strength = <2>;
5627 bias-disable;
5630 rx-pins {
5633 drive-strength = <2>;
5634 bias-disable;
5638 qup_uart21_default: qup-uart21-default-state {
5639 tx-pins {
5642 drive-strength = <2>;
5643 bias-disable;
5646 rx-pins {
5649 drive-strength = <2>;
5650 bias-disable;
5656 compatible = "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500";
5757 #iommu-cells = <2>;
5758 #global-interrupts = <1>;
5760 dma-coherent;
5763 intc: interrupt-controller@17000000 {
5764 compatible = "arm,gic-v3";
5770 #interrupt-cells = <3>;
5771 interrupt-controller;
5773 #redistributor-regions = <1>;
5774 redistributor-stride = <0x0 0x40000>;
5776 #address-cells = <2>;
5777 #size-cells = <2>;
5780 gic_its: msi-controller@17040000 {
5781 compatible = "arm,gic-v3-its";
5784 msi-controller;
5785 #msi-cells = <1>;
5790 compatible = "qcom,rpmh-rsc";
5794 reg-names = "drv-0", "drv-1", "drv-2";
5799 qcom,tcs-offset = <0xd00>;
5800 qcom,drv-id = <2>;
5801 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
5805 power-domains = <&system_pd>;
5807 apps_bcm_voter: bcm-voter {
5808 compatible = "qcom,bcm-voter";
5811 rpmhcc: clock-controller {
5812 compatible = "qcom,x1e80100-rpmh-clk";
5815 clock-names = "xo";
5817 #clock-cells = <1>;
5820 rpmhpd: power-controller {
5821 compatible = "qcom,x1e80100-rpmhpd";
5823 operating-points-v2 = <&rpmhpd_opp_table>;
5825 #power-domain-cells = <1>;
5827 rpmhpd_opp_table: opp-table {
5828 compatible = "operating-points-v2";
5830 rpmhpd_opp_ret: opp-16 {
5831 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5834 rpmhpd_opp_min_svs: opp-48 {
5835 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5838 rpmhpd_opp_low_svs_d2: opp-52 {
5839 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
5842 rpmhpd_opp_low_svs_d1: opp-56 {
5843 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
5846 rpmhpd_opp_low_svs_d0: opp-60 {
5847 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
5850 rpmhpd_opp_low_svs: opp-64 {
5851 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5854 rpmhpd_opp_low_svs_l1: opp-80 {
5855 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
5858 rpmhpd_opp_svs: opp-128 {
5859 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5862 rpmhpd_opp_svs_l0: opp-144 {
5863 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
5866 rpmhpd_opp_svs_l1: opp-192 {
5867 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5870 rpmhpd_opp_nom: opp-256 {
5871 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5874 rpmhpd_opp_nom_l1: opp-320 {
5875 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5878 rpmhpd_opp_nom_l2: opp-336 {
5879 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5882 rpmhpd_opp_turbo: opp-384 {
5883 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5886 rpmhpd_opp_turbo_l1: opp-416 {
5887 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5894 compatible = "arm,armv7-timer-mem";
5897 #address-cells = <2>;
5898 #size-cells = <1>;
5908 frame-number = <0>;
5916 frame-number = <1>;
5926 frame-number = <2>;
5936 frame-number = <3>;
5946 frame-number = <4>;
5956 frame-number = <5>;
5966 frame-number = <6>;
5973 compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
5981 operating-points-v2 = <&llcc_bwmon_opp_table>;
5983 llcc_bwmon_opp_table: opp-table {
5984 compatible = "operating-points-v2";
5986 opp-0 {
5987 opp-peak-kBps = <800000>;
5990 opp-1 {
5991 opp-peak-kBps = <2188000>;
5994 opp-2 {
5995 opp-peak-kBps = <3072000>;
5998 opp-3 {
5999 opp-peak-kBps = <6220800>;
6002 opp-4 {
6003 opp-peak-kBps = <6835200>;
6006 opp-5 {
6007 opp-peak-kBps = <8371200>;
6010 opp-6 {
6011 opp-peak-kBps = <10944000>;
6014 opp-7 {
6015 opp-peak-kBps = <12748800>;
6018 opp-8 {
6019 opp-peak-kBps = <14745600>;
6022 opp-9 {
6023 opp-peak-kBps = <16896000>;
6030 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
6038 operating-points-v2 = <&cpu_bwmon_opp_table>;
6040 cpu_bwmon_opp_table: opp-table {
6041 compatible = "operating-points-v2";
6043 opp-0 {
6044 opp-peak-kBps = <4800000>;
6047 opp-1 {
6048 opp-peak-kBps = <7464000>;
6051 opp-2 {
6052 opp-peak-kBps = <9600000>;
6055 opp-3 {
6056 opp-peak-kBps = <12896000>;
6059 opp-4 {
6060 opp-peak-kBps = <14928000>;
6063 opp-5 {
6064 opp-peak-kBps = <17064000>;
6071 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
6079 operating-points-v2 = <&cpu_bwmon_opp_table>;
6084 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
6092 operating-points-v2 = <&cpu_bwmon_opp_table>;
6095 system-cache-controller@25000000 {
6096 compatible = "qcom,x1e80100-llcc";
6107 reg-names = "llcc0_base",
6121 compatible = "qcom,x1e80100-adsp-pas";
6124 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
6129 interrupt-names = "wdog",
6133 "stop-ack";
6136 clock-names = "xo";
6138 power-domains = <&rpmhpd RPMHPD_LCX>,
6140 power-domain-names = "lcx",
6146 memory-region = <&adspslpi_mem>,
6151 qcom,smem-states = <&smp2p_adsp_out 0>;
6152 qcom,smem-state-names = "stop";
6156 glink-edge {
6157 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
6164 qcom,remote-pid = <2>;
6168 qcom,glink-channels = "fastrpcglink-apps-dsp";
6170 qcom,non-secure-domain;
6171 #address-cells = <1>;
6172 #size-cells = <0>;
6174 compute-cb@3 {
6175 compatible = "qcom,fastrpc-compute-cb";
6179 dma-coherent;
6182 compute-cb@4 {
6183 compatible = "qcom,fastrpc-compute-cb";
6187 dma-coherent;
6190 compute-cb@5 {
6191 compatible = "qcom,fastrpc-compute-cb";
6195 dma-coherent;
6198 compute-cb@6 {
6199 compatible = "qcom,fastrpc-compute-cb";
6203 dma-coherent;
6206 compute-cb@7 {
6207 compatible = "qcom,fastrpc-compute-cb";
6211 dma-coherent;
6217 qcom,glink-channels = "adsp_apps";
6220 #address-cells = <1>;
6221 #size-cells = <0>;
6226 #sound-dai-cells = <0>;
6227 qcom,protection-domain = "avs/audio",
6231 compatible = "qcom,q6apm-lpass-dais";
6232 #sound-dai-cells = <1>;
6236 compatible = "qcom,q6apm-dais";
6245 qcom,protection-domain = "avs/audio",
6248 q6prmcc: clock-controller {
6249 compatible = "qcom,q6prm-lpass-clocks";
6250 #clock-cells = <2>;
6258 compatible = "qcom,x1e80100-cdsp-pas";
6261 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
6266 interrupt-names = "wdog",
6270 "stop-ack";
6273 clock-names = "xo";
6275 power-domains = <&rpmhpd RPMHPD_CX>,
6278 power-domain-names = "cx",
6285 memory-region = <&cdsp_mem>,
6290 qcom,smem-states = <&smp2p_cdsp_out 0>;
6291 qcom,smem-state-names = "stop";
6295 glink-edge {
6296 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
6303 qcom,remote-pid = <5>;
6307 qcom,glink-channels = "fastrpcglink-apps-dsp";
6309 qcom,non-secure-domain;
6310 #address-cells = <1>;
6311 #size-cells = <0>;
6313 compute-cb@1 {
6314 compatible = "qcom,fastrpc-compute-cb";
6317 dma-coherent;
6320 compute-cb@2 {
6321 compatible = "qcom,fastrpc-compute-cb";
6324 dma-coherent;
6327 compute-cb@3 {
6328 compatible = "qcom,fastrpc-compute-cb";
6331 dma-coherent;
6334 compute-cb@4 {
6335 compatible = "qcom,fastrpc-compute-cb";
6338 dma-coherent;
6341 compute-cb@5 {
6342 compatible = "qcom,fastrpc-compute-cb";
6345 dma-coherent;
6348 compute-cb@6 {
6349 compatible = "qcom,fastrpc-compute-cb";
6352 dma-coherent;
6355 compute-cb@7 {
6356 compatible = "qcom,fastrpc-compute-cb";
6359 dma-coherent;
6362 compute-cb@8 {
6363 compatible = "qcom,fastrpc-compute-cb";
6366 dma-coherent;
6369 /* note: compute-cb@9 is secure */
6371 compute-cb@10 {
6372 compatible = "qcom,fastrpc-compute-cb";
6375 dma-coherent;
6378 compute-cb@11 {
6379 compatible = "qcom,fastrpc-compute-cb";
6382 dma-coherent;
6385 compute-cb@12 {
6386 compatible = "qcom,fastrpc-compute-cb";
6389 dma-coherent;
6392 compute-cb@13 {
6393 compatible = "qcom,fastrpc-compute-cb";
6396 dma-coherent;
6404 compatible = "arm,armv8-timer";
6412 thermal-zones {
6413 aoss0-thermal {
6414 thermal-sensors = <&tsens0 0>;
6417 trip-point0 {
6423 aoss0-critical {
6431 cpu0-0-top-thermal {
6432 polling-delay-passive = <250>;
6434 thermal-sensors = <&tsens0 1>;
6437 trip-point0 {
6443 trip-point1 {
6449 cpu-critical {
6457 cpu0-0-btm-thermal {
6458 polling-delay-passive = <250>;
6460 thermal-sensors = <&tsens0 2>;
6463 trip-point0 {
6469 trip-point1 {
6475 cpu-critical {
6483 cpu0-1-top-thermal {
6484 polling-delay-passive = <250>;
6486 thermal-sensors = <&tsens0 3>;
6489 trip-point0 {
6495 trip-point1 {
6501 cpu-critical {
6509 cpu0-1-btm-thermal {
6510 polling-delay-passive = <250>;
6512 thermal-sensors = <&tsens0 4>;
6515 trip-point0 {
6521 trip-point1 {
6527 cpu-critical {
6535 cpu0-2-top-thermal {
6536 polling-delay-passive = <250>;
6538 thermal-sensors = <&tsens0 5>;
6541 trip-point0 {
6547 trip-point1 {
6553 cpu-critical {
6561 cpu0-2-btm-thermal {
6562 polling-delay-passive = <250>;
6564 thermal-sensors = <&tsens0 6>;
6567 trip-point0 {
6573 trip-point1 {
6579 cpu-critical {
6587 cpu0-3-top-thermal {
6588 polling-delay-passive = <250>;
6590 thermal-sensors = <&tsens0 7>;
6593 trip-point0 {
6599 trip-point1 {
6605 cpu-critical {
6613 cpu0-3-btm-thermal {
6614 polling-delay-passive = <250>;
6616 thermal-sensors = <&tsens0 8>;
6619 trip-point0 {
6625 trip-point1 {
6631 cpu-critical {
6639 cpuss0-top-thermal {
6640 thermal-sensors = <&tsens0 9>;
6643 trip-point0 {
6649 cpuss2-critical {
6657 cpuss0-btm-thermal {
6658 thermal-sensors = <&tsens0 10>;
6661 trip-point0 {
6667 cpuss2-critical {
6675 mem-thermal {
6676 thermal-sensors = <&tsens0 11>;
6679 trip-point0 {
6685 mem-critical {
6693 video-thermal {
6694 polling-delay-passive = <250>;
6696 thermal-sensors = <&tsens0 12>;
6699 trip-point0 {
6707 aoss1-thermal {
6708 thermal-sensors = <&tsens1 0>;
6711 trip-point0 {
6717 aoss0-critical {
6725 cpu1-0-top-thermal {
6726 polling-delay-passive = <250>;
6728 thermal-sensors = <&tsens1 1>;
6731 trip-point0 {
6737 trip-point1 {
6743 cpu-critical {
6751 cpu1-0-btm-thermal {
6752 polling-delay-passive = <250>;
6754 thermal-sensors = <&tsens1 2>;
6757 trip-point0 {
6763 trip-point1 {
6769 cpu-critical {
6777 cpu1-1-top-thermal {
6778 polling-delay-passive = <250>;
6780 thermal-sensors = <&tsens1 3>;
6783 trip-point0 {
6789 trip-point1 {
6795 cpu-critical {
6803 cpu1-1-btm-thermal {
6804 polling-delay-passive = <250>;
6806 thermal-sensors = <&tsens1 4>;
6809 trip-point0 {
6815 trip-point1 {
6821 cpu-critical {
6829 cpu1-2-top-thermal {
6830 polling-delay-passive = <250>;
6832 thermal-sensors = <&tsens1 5>;
6835 trip-point0 {
6841 trip-point1 {
6847 cpu-critical {
6855 cpu1-2-btm-thermal {
6856 polling-delay-passive = <250>;
6858 thermal-sensors = <&tsens1 6>;
6861 trip-point0 {
6867 trip-point1 {
6873 cpu-critical {
6881 cpu1-3-top-thermal {
6882 polling-delay-passive = <250>;
6884 thermal-sensors = <&tsens1 7>;
6887 trip-point0 {
6893 trip-point1 {
6899 cpu-critical {
6907 cpu1-3-btm-thermal {
6908 polling-delay-passive = <250>;
6910 thermal-sensors = <&tsens1 8>;
6913 trip-point0 {
6919 trip-point1 {
6925 cpu-critical {
6933 cpuss1-top-thermal {
6934 thermal-sensors = <&tsens1 9>;
6937 trip-point0 {
6943 cpuss2-critical {
6951 cpuss1-btm-thermal {
6952 thermal-sensors = <&tsens1 10>;
6955 trip-point0 {
6961 cpuss2-critical {
6969 aoss2-thermal {
6970 thermal-sensors = <&tsens2 0>;
6973 trip-point0 {
6979 aoss0-critical {
6987 cpu2-0-top-thermal {
6988 polling-delay-passive = <250>;
6990 thermal-sensors = <&tsens2 1>;
6993 trip-point0 {
6999 trip-point1 {
7005 cpu-critical {
7013 cpu2-0-btm-thermal {
7014 polling-delay-passive = <250>;
7016 thermal-sensors = <&tsens2 2>;
7019 trip-point0 {
7025 trip-point1 {
7031 cpu-critical {
7039 cpu2-1-top-thermal {
7040 polling-delay-passive = <250>;
7042 thermal-sensors = <&tsens2 3>;
7045 trip-point0 {
7051 trip-point1 {
7057 cpu-critical {
7065 cpu2-1-btm-thermal {
7066 polling-delay-passive = <250>;
7068 thermal-sensors = <&tsens2 4>;
7071 trip-point0 {
7077 trip-point1 {
7083 cpu-critical {
7091 cpu2-2-top-thermal {
7092 polling-delay-passive = <250>;
7094 thermal-sensors = <&tsens2 5>;
7097 trip-point0 {
7103 trip-point1 {
7109 cpu-critical {
7117 cpu2-2-btm-thermal {
7118 polling-delay-passive = <250>;
7120 thermal-sensors = <&tsens2 6>;
7123 trip-point0 {
7129 trip-point1 {
7135 cpu-critical {
7143 cpu2-3-top-thermal {
7144 polling-delay-passive = <250>;
7146 thermal-sensors = <&tsens2 7>;
7149 trip-point0 {
7155 trip-point1 {
7161 cpu-critical {
7169 cpu2-3-btm-thermal {
7170 polling-delay-passive = <250>;
7172 thermal-sensors = <&tsens2 8>;
7175 trip-point0 {
7181 trip-point1 {
7187 cpu-critical {
7195 cpuss2-top-thermal {
7196 thermal-sensors = <&tsens2 9>;
7199 trip-point0 {
7205 cpuss2-critical {
7213 cpuss2-btm-thermal {
7214 thermal-sensors = <&tsens2 10>;
7217 trip-point0 {
7223 cpuss2-critical {
7231 aoss3-thermal {
7232 thermal-sensors = <&tsens3 0>;
7235 trip-point0 {
7241 aoss0-critical {
7249 nsp0-thermal {
7250 thermal-sensors = <&tsens3 1>;
7253 trip-point0 {
7259 nsp0-critical {
7267 nsp1-thermal {
7268 thermal-sensors = <&tsens3 2>;
7271 trip-point0 {
7277 nsp1-critical {
7285 nsp2-thermal {
7286 thermal-sensors = <&tsens3 3>;
7289 trip-point0 {
7295 nsp2-critical {
7303 nsp3-thermal {
7304 thermal-sensors = <&tsens3 4>;
7307 trip-point0 {
7313 nsp3-critical {
7321 gpuss-0-thermal {
7322 polling-delay-passive = <10>;
7324 thermal-sensors = <&tsens3 5>;
7327 trip-point0 {
7333 trip-point1 {
7339 trip-point2 {
7347 gpuss-1-thermal {
7348 polling-delay-passive = <10>;
7350 thermal-sensors = <&tsens3 6>;
7353 trip-point0 {
7359 trip-point1 {
7365 trip-point2 {
7373 gpuss-2-thermal {
7374 polling-delay-passive = <10>;
7376 thermal-sensors = <&tsens3 7>;
7379 trip-point0 {
7385 trip-point1 {
7391 trip-point2 {
7399 gpuss-3-thermal {
7400 polling-delay-passive = <10>;
7402 thermal-sensors = <&tsens3 8>;
7405 trip-point0 {
7411 trip-point1 {
7417 trip-point2 {
7425 gpuss-4-thermal {
7426 polling-delay-passive = <10>;
7428 thermal-sensors = <&tsens3 9>;
7431 trip-point0 {
7437 trip-point1 {
7443 trip-point2 {
7451 gpuss-5-thermal {
7452 polling-delay-passive = <10>;
7454 thermal-sensors = <&tsens3 10>;
7457 trip-point0 {
7463 trip-point1 {
7469 trip-point2 {
7477 gpuss-6-thermal {
7478 polling-delay-passive = <10>;
7480 thermal-sensors = <&tsens3 11>;
7483 trip-point0 {
7489 trip-point1 {
7495 trip-point2 {
7503 gpuss-7-thermal {
7504 polling-delay-passive = <10>;
7506 thermal-sensors = <&tsens3 12>;
7509 trip-point0 {
7515 trip-point1 {
7521 trip-point2 {
7529 camera0-thermal {
7530 thermal-sensors = <&tsens3 13>;
7533 trip-point0 {
7539 camera0-critical {
7547 camera1-thermal {
7548 thermal-sensors = <&tsens3 14>;
7551 trip-point0 {
7557 camera0-critical {