Lines Matching +full:0 +full:x0c222000
36 #clock-cells = <0>;
42 #clock-cells = <0>;
47 #clock-cells = <0>;
56 #clock-cells = <0>;
66 #size-cells = <0>;
68 cpu0: cpu@0 {
71 reg = <0x0 0x0>;
88 reg = <0x0 0x100>;
99 reg = <0x0 0x200>;
110 reg = <0x0 0x300>;
121 reg = <0x0 0x10000>;
138 reg = <0x0 0x10100>;
149 reg = <0x0 0x10200>;
160 reg = <0x0 0x10300>;
171 reg = <0x0 0x20000>;
188 reg = <0x0 0x20100>;
199 reg = <0x0 0x20200>;
210 reg = <0x0 0x20300>;
277 cluster_c4: cpu-sleep-0 {
280 arm,psci-suspend-param = <0x00000004>;
288 cluster_cl4: cluster-sleep-0 {
290 arm,psci-suspend-param = <0x01000044>;
298 arm,psci-suspend-param = <0x01000054>;
323 qcom,dload-mode = <&tcsr 0x19000>;
327 clk_virt: interconnect-0 {
342 reg = <0 0x80000000 0 0>;
355 #power-domain-cells = <0>;
360 #power-domain-cells = <0>;
365 #power-domain-cells = <0>;
370 #power-domain-cells = <0>;
375 #power-domain-cells = <0>;
380 #power-domain-cells = <0>;
385 #power-domain-cells = <0>;
390 #power-domain-cells = <0>;
395 #power-domain-cells = <0>;
400 #power-domain-cells = <0>;
405 #power-domain-cells = <0>;
410 #power-domain-cells = <0>;
415 #power-domain-cells = <0>;
421 #power-domain-cells = <0>;
427 #power-domain-cells = <0>;
433 #power-domain-cells = <0>;
444 reg = <0x0 0x80000000 0x0 0x800000>;
449 reg = <0x0 0x80800000 0x0 0x200000>;
454 reg = <0x0 0x80a00000 0x0 0x400000>;
459 reg = <0x0 0x80e00000 0x0 0x40000>;
464 reg = <0x0 0x80e40000 0x0 0x540000>;
469 reg = <0x0 0x81380000 0x0 0x80000>;
474 reg = <0x0 0x81400000 0x0 0x1a0000>;
479 reg = <0x0 0x81a00000 0x0 0x40000>;
484 reg = <0x0 0x81a40000 0x0 0x1c0000>;
489 reg = <0x0 0x81c00000 0x0 0x60000>;
495 reg = <0x0 0x81c60000 0x0 0x20000>;
500 reg = <0x0 0x81c80000 0x0 0x20000>;
505 reg = <0x0 0x81ca0000 0x0 0x40000>;
510 reg = <0x0 0x81ce0000 0x0 0x4000>;
515 reg = <0x0 0x81ce4000 0x0 0x10000>;
520 reg = <0x0 0x81cff000 0x0 0x1000>;
525 reg = <0x0 0x81e00000 0x0 0x100000>;
530 reg = <0x0 0x81f00000 0x0 0x10000>;
535 reg = <0x0 0x81f10000 0x0 0x10000>;
540 reg = <0x0 0x81f20000 0x0 0x10000>;
545 reg = <0x0 0x81f30000 0x0 0x6000>;
550 reg = <0x0 0x81f36000 0x0 0x1000>;
555 reg = <0x0 0x81f37000 0x0 0x1000>;
560 reg = <0x0 0x82700000 0x0 0x100000>;
565 reg = <0x0 0x82800000 0x0 0xc00000>;
570 reg = <0x0 0x84b00000 0x0 0x800000>;
575 reg = <0x0 0x85300000 0x0 0x80000>;
580 reg = <0x0 0x866c0000 0x0 0x40000>;
585 reg = <0x0 0x86700000 0x0 0x400000>;
590 reg = <0x0 0x86b00000 0x0 0xc00000>;
595 reg = <0x0 0x87700000 0x0 0x700000>;
600 reg = <0x0 0x87e00000 0x0 0x3a00000>;
605 reg = <0x0 0x8b800000 0x0 0x80000>;
610 reg = <0x0 0x8b900000 0x0 0x2000000>;
615 reg = <0x0 0x8d900000 0x0 0x80000>;
620 reg = <0x0 0x8d9fe000 0x0 0x2000>;
625 reg = <0x0 0x8da00000 0x0 0x700000>;
630 reg = <0x0 0x8e100000 0x0 0x800000>;
635 reg = <0x0 0x8e900000 0x0 0x700000>;
640 reg = <0x0 0x8f000000 0x0 0xa00000>;
645 reg = <0x0 0x8fa00000 0x0 0x1900000>;
650 reg = <0x0 0x91300000 0x0 0x80000>;
655 reg = <0x0 0xd8000000 0x0 0x40000>;
660 reg = <0x0 0xd8040000 0x0 0xa0000>;
665 reg = <0x0 0xd80e0000 0x0 0x520000>;
670 reg = <0x0 0xd8600000 0x0 0x8a00000>;
675 reg = <0x0 0xe1000000 0x0 0x26a0000>;
680 reg = <0x0 0xff800000 0x0 0x600000>;
686 reg = <0x0 0xffe00000 0x0 0x200000>;
731 qcom,local-pid = <0>;
757 qcom,local-pid = <0>;
772 soc: soc@0 {
777 dma-ranges = <0 0 0 0 0x10 0>;
778 ranges = <0 0 0 0 0x10 0>;
782 reg = <0 0x00100000 0 0x200000>;
790 <0>,
803 reg = <0 0x00408000 0 0x1000>;
814 reg = <0 0x00800000 0 0x60000>;
830 dma-channel-mask = <0x3e>;
833 iommus = <&apps_smmu 0x436 0x0>;
840 reg = <0 0x008c0000 0 0x2000>;
847 iommus = <&apps_smmu 0x423 0x0>;
857 reg = <0 0x00880000 0 0x4000>;
877 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
878 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
882 pinctrl-0 = <&qup_i2c16_data_clk>;
886 #size-cells = <0>;
893 reg = <0 0x00880000 0 0x4000>;
913 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
914 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
918 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
922 #size-cells = <0>;
929 reg = <0 0x00884000 0 0x4000>;
949 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
954 pinctrl-0 = <&qup_i2c17_data_clk>;
958 #size-cells = <0>;
965 reg = <0 0x00884000 0 0x4000>;
985 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
990 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
994 #size-cells = <0>;
1001 reg = <0 0x00888000 0 0x4000>;
1021 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1026 pinctrl-0 = <&qup_i2c18_data_clk>;
1030 #size-cells = <0>;
1037 reg = <0 0x00888000 0 0x4000>;
1057 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1062 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
1066 #size-cells = <0>;
1073 reg = <0 0x0088c000 0 0x4000>;
1093 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1098 pinctrl-0 = <&qup_i2c19_data_clk>;
1102 #size-cells = <0>;
1109 reg = <0 0x0088c000 0 0x4000>;
1129 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1134 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
1138 #size-cells = <0>;
1145 reg = <0 0x00890000 0 0x4000>;
1165 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1170 pinctrl-0 = <&qup_i2c20_data_clk>;
1174 #size-cells = <0>;
1181 reg = <0 0x00890000 0 0x4000>;
1201 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1206 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1210 #size-cells = <0>;
1217 reg = <0 0x00894000 0 0x4000>;
1237 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1242 pinctrl-0 = <&qup_i2c21_data_clk>;
1246 #size-cells = <0>;
1253 reg = <0 0x00894000 0 0x4000>;
1273 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1278 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1282 #size-cells = <0>;
1289 reg = <0 0x00894000 0 0x4000>;
1306 pinctrl-0 = <&qup_uart21_default>;
1314 reg = <0 0x00898000 0 0x4000>;
1334 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1339 pinctrl-0 = <&qup_i2c22_data_clk>;
1343 #size-cells = <0>;
1350 reg = <0 0x00898000 0 0x4000>;
1370 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1375 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>;
1379 #size-cells = <0>;
1386 reg = <0 0x0089c000 0 0x4000>;
1406 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
1411 pinctrl-0 = <&qup_i2c23_data_clk>;
1415 #size-cells = <0>;
1422 reg = <0 0x0089c000 0 0x4000>;
1442 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
1447 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>;
1451 #size-cells = <0>;
1459 reg = <0 0x00a00000 0 0x60000>;
1475 dma-channel-mask = <0x3e>;
1478 iommus = <&apps_smmu 0x136 0x0>;
1485 reg = <0 0x00ac0000 0 0x2000>;
1492 iommus = <&apps_smmu 0x123 0x0>;
1502 reg = <0 0x00a80000 0 0x4000>;
1522 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1523 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1527 pinctrl-0 = <&qup_i2c8_data_clk>;
1531 #size-cells = <0>;
1538 reg = <0 0x00a80000 0 0x4000>;
1558 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1559 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1563 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1567 #size-cells = <0>;
1574 reg = <0 0x00a84000 0 0x4000>;
1594 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1599 pinctrl-0 = <&qup_i2c9_data_clk>;
1603 #size-cells = <0>;
1610 reg = <0 0x00a84000 0 0x4000>;
1630 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1635 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1639 #size-cells = <0>;
1646 reg = <0 0x00a88000 0 0x4000>;
1666 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1671 pinctrl-0 = <&qup_i2c10_data_clk>;
1675 #size-cells = <0>;
1682 reg = <0 0x00a88000 0 0x4000>;
1702 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1707 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1711 #size-cells = <0>;
1718 reg = <0 0x00a8c000 0 0x4000>;
1738 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1743 pinctrl-0 = <&qup_i2c11_data_clk>;
1747 #size-cells = <0>;
1754 reg = <0 0x00a8c000 0 0x4000>;
1774 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1779 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1783 #size-cells = <0>;
1790 reg = <0 0x00a90000 0 0x4000>;
1810 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1815 pinctrl-0 = <&qup_i2c12_data_clk>;
1819 #size-cells = <0>;
1826 reg = <0 0x00a90000 0 0x4000>;
1846 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1851 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1855 #size-cells = <0>;
1862 reg = <0 0x00a94000 0 0x4000>;
1882 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1887 pinctrl-0 = <&qup_i2c13_data_clk>;
1891 #size-cells = <0>;
1898 reg = <0 0x00a94000 0 0x4000>;
1918 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1923 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1927 #size-cells = <0>;
1934 reg = <0 0x00a98000 0 0x4000>;
1954 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1959 pinctrl-0 = <&qup_i2c14_data_clk>;
1963 #size-cells = <0>;
1970 reg = <0 0x00a98000 0 0x4000>;
1990 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1995 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1999 #size-cells = <0>;
2006 reg = <0 0x00a98000 0 0x4000>;
2023 pinctrl-0 = <&qup_uart14_default>;
2031 reg = <0 0x00a9c000 0 0x4000>;
2051 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
2056 pinctrl-0 = <&qup_i2c15_data_clk>;
2060 #size-cells = <0>;
2067 reg = <0 0x00a9c000 0 0x4000>;
2087 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
2092 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
2096 #size-cells = <0>;
2104 reg = <0 0x00b00000 0 0x60000>;
2120 dma-channel-mask = <0x3e>;
2123 iommus = <&apps_smmu 0x456 0x0>;
2130 reg = <0 0x00bc0000 0 0x2000>;
2137 iommus = <&apps_smmu 0x443 0x0>;
2146 reg = <0 0x00b80000 0 0x4000>;
2166 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
2167 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
2171 pinctrl-0 = <&qup_i2c0_data_clk>;
2175 #size-cells = <0>;
2182 reg = <0 0x00b80000 0 0x4000>;
2202 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
2203 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
2207 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
2211 #size-cells = <0>;
2218 reg = <0 0x00b84000 0 0x4000>;
2238 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
2243 pinctrl-0 = <&qup_i2c1_data_clk>;
2247 #size-cells = <0>;
2254 reg = <0 0x00b84000 0 0x4000>;
2274 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
2279 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
2283 #size-cells = <0>;
2290 reg = <0 0x00b88000 0 0x4000>;
2310 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
2315 pinctrl-0 = <&qup_i2c2_data_clk>;
2319 #size-cells = <0>;
2326 reg = <0 0x00b88000 0 0x4000>;
2343 pinctrl-0 = <&qup_uart2_default>;
2351 reg = <0 0x00b88000 0 0x4000>;
2371 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
2376 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
2380 #size-cells = <0>;
2387 reg = <0 0x00b8c000 0 0x4000>;
2407 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
2412 pinctrl-0 = <&qup_i2c3_data_clk>;
2416 #size-cells = <0>;
2423 reg = <0 0x00b8c000 0 0x4000>;
2443 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
2448 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
2452 #size-cells = <0>;
2459 reg = <0 0x00b90000 0 0x4000>;
2479 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
2484 pinctrl-0 = <&qup_i2c4_data_clk>;
2488 #size-cells = <0>;
2495 reg = <0 0x00b90000 0 0x4000>;
2515 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
2520 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
2524 #size-cells = <0>;
2531 reg = <0 0x00b94000 0 0x4000>;
2551 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
2556 pinctrl-0 = <&qup_i2c5_data_clk>;
2560 #size-cells = <0>;
2567 reg = <0 0x00b94000 0 0x4000>;
2587 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
2592 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
2596 #size-cells = <0>;
2603 reg = <0 0x00b98000 0 0x4000>;
2623 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
2628 pinctrl-0 = <&qup_i2c6_data_clk>;
2632 #size-cells = <0>;
2639 reg = <0 0x00b98000 0 0x4000>;
2659 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
2664 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
2668 #size-cells = <0>;
2675 reg = <0 0x00b9c000 0 0x4000>;
2695 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
2700 pinctrl-0 = <&qup_i2c7_data_clk>;
2704 #size-cells = <0>;
2711 reg = <0 0x00b9c000 0 0x4000>;
2731 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
2736 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
2740 #size-cells = <0>;
2748 reg = <0 0x0c271000 0 0x1000>,
2749 <0 0x0c222000 0 0x1000>;
2763 reg = <0 0x0c272000 0 0x1000>,
2764 <0 0x0c223000 0 0x1000>;
2778 reg = <0 0x0c273000 0 0x1000>,
2779 <0 0x0c224000 0 0x1000>;
2793 reg = <0 0x0c274000 0 0x1000>,
2794 <0 0x0c225000 0 0x1000>;
2809 reg = <0 0x00fd3000 0 0x154>;
2810 #phy-cells = <0>;
2822 reg = <0 0x00fd5000 0 0x4000>;
2849 #size-cells = <0>;
2851 port@0 {
2852 reg = <0>;
2879 reg = <0 0x00fd9000 0 0x154>;
2880 #phy-cells = <0>;
2892 reg = <0 0x00fda000 0 0x4000>;
2919 #size-cells = <0>;
2921 port@0 {
2922 reg = <0>;
2949 reg = <0 0x00fde000 0 0x154>;
2950 #phy-cells = <0>;
2962 reg = <0 0x00fdf000 0 0x4000>;
2989 #size-cells = <0>;
2991 port@0 {
2992 reg = <0>;
3018 reg = <0 0x01500000 0 0x14400>;
3027 reg = <0 0x01600000 0 0x6600>;
3036 reg = <0 0x01680000 0 0x1c080>;
3045 reg = <0 0x016c0000 0 0xd080>;
3054 reg = <0 0x016d0000 0 0x7000>;
3063 reg = <0 0x016e0000 0 0x14400>;
3072 reg = <0 0x01700000 0 0x1c400>;
3081 reg = <0 0x01740000 0 0x9080>;
3090 reg = <0 0x01750000 0 0x8800>;
3099 reg = <0 0x01760000 0 0x7080>;
3108 reg = <0 0x01770000 0 0xf080>;
3117 reg = <0 0x01780000 0 0x5B800>;
3127 reg = <0x0 0x01bd0000 0x0 0x3000>,
3128 <0x0 0x78000000 0x0 0xf1d>,
3129 <0x0 0x78000f40 0x0 0xa8>,
3130 <0x0 0x78001000 0x0 0x1000>,
3131 <0x0 0x78100000 0x0 0x100000>,
3132 <0x0 0x01bd3000 0x0 0x1000>;
3141 ranges = <0x01000000 0x0 0x00000000 0x0 0x78200000 0x0 0x100000>,
3142 <0x02000000 0x0 0x78300000 0x0 0x78300000 0x0 0x3d00000>,
3143 <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>;
3144 bus-range = <0x00 0xff>;
3171 interrupt-map-mask = <0 0 0 0x7>;
3172 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
3173 <0 0 0 2 &intc 0 0 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
3174 <0 0 0 3 &intc 0 0 GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
3175 <0 0 0 4 &intc 0 0 GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
3293 reg = <0 0x01be0000 0 0x10000>;
3318 #clock-cells = <0>;
3321 #phy-cells = <0>;
3329 reg = <0 0x01bf8000 0 0x3000>,
3330 <0 0x70000000 0 0xf20>,
3331 <0 0x70000f40 0 0xa8>,
3332 <0 0x70001000 0 0x1000>,
3333 <0 0x70100000 0 0x100000>,
3334 <0 0x01bfb000 0 0x1000>;
3343 ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>,
3344 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>;
3345 bus-range = <0x00 0xff>;
3352 msi-map = <0x0 &gic_its 0xe0000 0x10000>;
3372 interrupt-map-mask = <0 0 0 0x7>;
3373 interrupt-map = <0 0 0 1 &intc 0 0 0 843 IRQ_TYPE_LEVEL_HIGH>,
3374 <0 0 0 2 &intc 0 0 0 844 IRQ_TYPE_LEVEL_HIGH>,
3375 <0 0 0 3 &intc 0 0 0 845 IRQ_TYPE_LEVEL_HIGH>,
3376 <0 0 0 4 &intc 0 0 0 772 IRQ_TYPE_LEVEL_HIGH>;
3419 reg = <0 0x01bfc000 0 0x2000>,
3420 <0 0x01bfe000 0 0x2000>;
3445 qcom,4ln-config-sel = <&tcsr 0x1a000 0>;
3447 #clock-cells = <0>;
3450 #phy-cells = <0>;
3458 reg = <0 0x01c00000 0 0x3000>,
3459 <0 0x7e000000 0 0xf1d>,
3460 <0 0x7e000f40 0 0xa8>,
3461 <0 0x7e001000 0 0x1000>,
3462 <0 0x7e100000 0 0x100000>,
3463 <0 0x01c03000 0 0x1000>;
3472 ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>,
3473 <0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>;
3474 bus-range = <0x00 0xff>;
3499 interrupt-map-mask = <0 0 0 0x7>;
3500 interrupt-map = <0 0 0 1 &intc 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>,
3501 <0 0 0 2 &intc 0 0 0 71 IRQ_TYPE_LEVEL_HIGH>,
3502 <0 0 0 3 &intc 0 0 0 72 IRQ_TYPE_LEVEL_HIGH>,
3503 <0 0 0 4 &intc 0 0 0 73 IRQ_TYPE_LEVEL_HIGH>;
3546 reg = <0 0x01c06000 0 0x2000>;
3569 #clock-cells = <0>;
3572 #phy-cells = <0>;
3580 reg = <0 0x01c08000 0 0x3000>,
3581 <0 0x7c000000 0 0xf1d>,
3582 <0 0x7c000f40 0 0xa8>,
3583 <0 0x7c001000 0 0x1000>,
3584 <0 0x7c100000 0 0x100000>,
3585 <0 0x01c0b000 0 0x1000>;
3594 ranges = <0x01000000 0x0 0x00000000 0x0 0x7c200000 0x0 0x100000>,
3595 <0x02000000 0x0 0x7c300000 0x0 0x7c300000 0x0 0x1d00000>;
3596 bus-range = <0x00 0xff>;
3603 msi-map = <0x0 &gic_its 0xc0000 0x10000>;
3623 interrupt-map-mask = <0 0 0 0x7>;
3624 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
3625 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
3626 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
3627 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
3667 pcie4_port0: pcie@0 {
3669 reg = <0x0 0x0 0x0 0x0 0x0>;
3670 bus-range = <0x01 0xff>;
3680 reg = <0 0x01c0e000 0 0x2000>;
3703 #clock-cells = <0>;
3706 #phy-cells = <0>;
3713 reg = <0 0x01f40000 0 0x20000>;
3719 reg = <0 0x01fc0000 0 0x30000>;
3727 reg = <0x0 0x03d00000 0x0 0x40000>,
3728 <0x0 0x03d9e000 0x0 0x1000>,
3729 <0x0 0x03d61000 0x0 0x800>;
3737 iommus = <&adreno_smmu 0 0x0>,
3738 <&adreno_smmu 1 0x0>;
3745 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
3815 reg = <0x0 0x03d6a000 0x0 0x35000>,
3816 <0x0 0x03d50000 0x0 0x10000>,
3817 <0x0 0x0b280000 0x0 0x10000>;
3844 iommus = <&adreno_smmu 5 0x0>;
3867 reg = <0 0x03d90000 0 0xa000>;
3879 reg = <0x0 0x03da0000 0x0 0x40000>;
3922 reg = <0 0x26400000 0 0x311200>;
3931 reg = <0 0x320C0000 0 0xe080>;
3940 reg = <0x0 0x06800000 0x0 0x10000>;
3943 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
3969 qcom,smem-states = <&smp2p_adsp_out 0>;
3990 #size-cells = <0>;
3995 iommus = <&apps_smmu 0x1003 0x80>,
3996 <&apps_smmu 0x1063 0x0>;
4003 iommus = <&apps_smmu 0x1004 0x80>,
4004 <&apps_smmu 0x1064 0x0>;
4011 iommus = <&apps_smmu 0x1005 0x80>,
4012 <&apps_smmu 0x1065 0x0>;
4019 iommus = <&apps_smmu 0x1006 0x80>,
4020 <&apps_smmu 0x1066 0x0>;
4027 iommus = <&apps_smmu 0x1007 0x80>,
4028 <&apps_smmu 0x1067 0x0>;
4039 #size-cells = <0>;
4044 #sound-dai-cells = <0>;
4055 iommus = <&apps_smmu 0x1001 0x80>,
4056 <&apps_smmu 0x1061 0x0>;
4077 reg = <0 0x06aa0000 0 0x1000>;
4087 #clock-cells = <0>;
4095 reg = <0 0x06ab0000 0 0x10000>;
4101 pinctrl-0 = <&wsa2_swr_active>;
4109 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x3…
4110 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
4111 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4112 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4113 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4114 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
4115 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
4116 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4117 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4120 #size-cells = <0>;
4127 reg = <0 0x06ac0000 0 0x1000>;
4137 #clock-cells = <0>;
4144 reg = <0 0x06ad0000 0 0x10000>;
4150 pinctrl-0 = <&rx_swr_active>;
4158 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4159 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4160 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4161 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4162 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4163 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4164 …qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff…
4165 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4166 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4169 #size-cells = <0>;
4176 reg = <0 0x06ae0000 0 0x1000>;
4186 #clock-cells = <0>;
4193 reg = <0 0x06b00000 0 0x1000>;
4203 #clock-cells = <0>;
4211 reg = <0 0x06b10000 0 0x10000>;
4217 pinctrl-0 = <&wsa_swr_active>;
4225 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x3…
4226 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
4227 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4228 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4229 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4230 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
4231 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
4232 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4233 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4236 #size-cells = <0>;
4243 reg = <0 0x06b6c000 0 0x1000>;
4250 reg = <0 0x06d30000 0 0x10000>;
4260 pinctrl-0 = <&tx_swr_active>;
4266 qcom,ports-sinterval-low = /bits/ 8 <0x00 0x01 0x03 0x03 0x00>;
4267 qcom,ports-offset1 = /bits/ 8 <0x00 0x01 0x02 0x00 0x00>;
4268 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00 0xff>;
4269 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
4270 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
4271 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
4272 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
4273 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
4274 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x00 0x01 0xff>;
4277 #size-cells = <0>;
4284 reg = <0 0x06d44000 0 0x1000>;
4292 #clock-cells = <0>;
4299 reg = <0 0x06e80000 0 0x20000>,
4300 <0 0x07250000 0 0x10000>;
4308 gpio-ranges = <&lpass_tlmm 0 0 23>;
4417 reg = <0 0x06ea0000 0 0x12000>;
4424 reg = <0 0x07e40000 0 0xe080>;
4433 reg = <0 0x07400000 0 0x19080>;
4442 reg = <0 0x07430000 0 0x3A200>;
4451 reg = <0 0x08804000 0 0x1000>;
4461 iommus = <&apps_smmu 0x520 0>;
4462 qcom,dll-config = <0x0007642c>;
4463 qcom,ddr-config = <0x80040868>;
4504 reg = <0 0x08844000 0 0x1000>;
4514 iommus = <&apps_smmu 0x160 0>;
4515 qcom,dll-config = <0x0007642c>;
4516 qcom,ddr-config = <0x80040868>;
4558 reg = <0 0x088e0000 0 0x154>;
4559 #phy-cells = <0>;
4572 reg = <0 0x088e1000 0 0x154>;
4573 #phy-cells = <0>;
4586 reg = <0 0x088e2000 0 0x154>;
4587 #phy-cells = <0>;
4599 reg = <0 0x088e3000 0 0x2000>;
4617 #clock-cells = <0>;
4620 #phy-cells = <0>;
4627 reg = <0 0x088e5000 0 0x2000>;
4645 #clock-cells = <0>;
4648 #phy-cells = <0>;
4655 reg = <0 0x0a0f8800 0 0x400>;
4712 reg = <0 0x0a000000 0 0xcd00>;
4716 iommus = <&apps_smmu 0x14a0 0x0>;
4733 #size-cells = <0>;
4735 port@0 {
4736 reg = <0>;
4755 reg = <0 0x0a2f8800 0 0x400>;
4808 reg = <0 0x0a200000 0 0xcd00>;
4810 iommus = <&apps_smmu 0x14e0 0x0>;
4819 #size-cells = <0>;
4821 port@0 {
4822 reg = <0>;
4833 reg = <0 0x0a4f8800 0 0x400>;
4897 reg = <0 0x0a400000 0 0xcd00>;
4901 iommus = <&apps_smmu 0x1400 0x0>;
4905 phy-names = "usb2-0", "usb3-0",
4921 reg = <0 0x0a6f8800 0 0x400>;
4971 reg = <0 0x0a600000 0 0xcd00>;
4975 iommus = <&apps_smmu 0x1420 0x0>;
4992 #size-cells = <0>;
4994 port@0 {
4995 reg = <0>;
5014 reg = <0 0x0a8f8800 0 0x400>;
5071 reg = <0 0x0a800000 0 0xcd00>;
5075 iommus = <&apps_smmu 0x1460 0x0>;
5092 #size-cells = <0>;
5094 port@0 {
5095 reg = <0>;
5114 reg = <0 0x0ae00000 0 0x1000>;
5137 iommus = <&apps_smmu 0x1c00 0x2>;
5150 reg = <0 0x0ae01000 0 0x8f000>,
5151 <0 0x0aeb0000 0 0x2008>;
5155 interrupts-extended = <&mdss 0>;
5174 #size-cells = <0>;
5176 port@0 {
5177 reg = <0>;
5241 reg = <0 0x0ae90000 0 0x200>,
5242 <0 0x0ae90200 0 0x200>,
5243 <0 0x0ae90400 0 0x600>,
5244 <0 0x0ae91000 0 0x400>,
5245 <0 0x0ae91400 0 0x400>;
5272 #sound-dai-cells = <0>;
5278 #size-cells = <0>;
5280 port@0 {
5281 reg = <0>;
5324 reg = <0 0x0ae98000 0 0x200>,
5325 <0 0x0ae98200 0 0x200>,
5326 <0 0x0ae98400 0 0x600>,
5327 <0 0x0ae99000 0 0x400>,
5328 <0 0x0ae99400 0 0x400>;
5355 #sound-dai-cells = <0>;
5361 #size-cells = <0>;
5363 port@0 {
5364 reg = <0>;
5407 reg = <0 0x0ae9a000 0 0x200>,
5408 <0 0x0ae9a200 0 0x200>,
5409 <0 0x0ae9a400 0 0x600>,
5410 <0 0x0ae9b000 0 0x400>,
5411 <0 0x0ae9b400 0 0x400>;
5438 #sound-dai-cells = <0>;
5444 #size-cells = <0>;
5446 port@0 {
5447 reg = <0>;
5489 reg = <0 0x0aea0000 0 0x200>,
5490 <0 0x0aea0200 0 0x200>,
5491 <0 0x0aea0400 0 0x600>,
5492 <0 0x0aea1000 0 0x400>,
5493 <0 0x0aea1400 0 0x400>;
5510 assigned-clock-parents = <&mdss_dp3_phy 0>,
5520 #sound-dai-cells = <0>;
5526 #size-cells = <0>;
5528 port@0 {
5529 reg = <0>;
5570 reg = <0 0x0aec2a00 0 0x19c>,
5571 <0 0x0aec2200 0 0xec>,
5572 <0 0x0aec2600 0 0xec>,
5573 <0 0x0aec2000 0 0x1c8>;
5583 #phy-cells = <0>;
5590 reg = <0 0x0aec5a00 0 0x19c>,
5591 <0 0x0aec5200 0 0xec>,
5592 <0 0x0aec5600 0 0xec>,
5593 <0 0x0aec5000 0 0x1c8>;
5603 #phy-cells = <0>;
5610 reg = <0 0x0af00000 0 0x20000>;
5615 <0>, /* dsi0 */
5616 <0>,
5617 <0>, /* dsi1 */
5618 <0>,
5625 <&mdss_dp3_phy 0>, /* dp3 */
5636 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
5638 qcom,pdc-ranges = <0 480 42>, <42 251 5>,
5648 reg = <0 0x0c300000 0 0x400>;
5654 #clock-cells = <0>;
5659 reg = <0 0x0c3f0000 0 0x400>;
5664 reg = <0 0x0c400000 0 0x3000>,
5665 <0 0x0c500000 0 0x400000>,
5666 <0 0x0c440000 0 0x80000>;
5669 qcom,ee = <0>;
5670 qcom,channel = <0>;
5677 reg = <0 0x0c42d000 0 0x4000>,
5678 <0 0x0c4c0000 0 0x10000>;
5687 #size-cells = <0>;
5691 reg = <0 0x0c432000 0 0x4000>,
5692 <0 0x0c4d0000 0 0x10000>;
5701 #size-cells = <0>;
5707 reg = <0 0x0f100000 0 0xf00000>;
5717 gpio-ranges = <&tlmm 0 0 239>;
6389 reg = <0x0 0x10002000 0x0 0x1000>,
6390 <0x0 0x16280000 0x0 0x180000>;
6408 reg = <0x0 0x10003000 0x0 0x1000>;
6428 reg = <0x0 0x10004000 0x0 0x1000>;
6435 #size-cells = <0>;
6437 port@0 {
6438 reg = <0>;
6465 reg = <0x0 0x1000f000 0x0 0x1000>;
6484 reg = <0x0 0x10041000 0x0 0x1000>;
6491 #size-cells = <0>;
6521 reg = <0x0 0x10042000 0x0 0x1000>;
6528 #size-cells = <0>;
6566 reg = <0x0 0x10045000 0x0 0x1000>;
6573 #size-cells = <0>;
6575 port@0 {
6576 reg = <0>;
6603 reg = <0x0 0x10800000 0x0 0x1000>;
6622 reg = <0x0 0x1082c000 0x0 0x1000>;
6641 reg = <0x0 0x10841000 0x0 0x1000>;
6660 reg = <0x0 0x10844000 0x0 0x1000>;
6679 reg = <0x0 0x10846000 0x0 0x1000>;
6703 reg = <0x0 0x1098b000 0x0 0x1000>;
6711 reg = <0x0 0x109d0000 0x0 0x1000>;
6731 reg = <0x0 0x10ac0000 0x0 0x1000>;
6751 reg = <0x0 0x10ac1000 0x0 0x1000>;
6770 reg = <0x0 0x10ac4000 0x0 0x1000>;
6777 #size-cells = <0>;
6807 reg = <0x0 0x10ac5000 0x0 0x1000>;
6831 reg = <0x0 0x10b04000 0x0 0x1000>;
6838 #size-cells = <0>;
6876 reg = <0x0 0x10b05000 0x0 0x1000>;
6900 reg = <0x0 0x10b06000 0x0 0x1000>;
6924 reg = <0x0 0x10b08000 0x0 0x1000>;
6931 #size-cells = <0>;
6933 port@0 {
6934 reg = <0>;
6985 reg = <0x0 0x10b09000 0x0 0x1000>;
7004 reg = <0x0 0x10b0a000 0x0 0x1000>;
7023 reg = <0x0 0x10b0b000 0x0 0x1000>;
7042 reg = <0x0 0x10b0c000 0x0 0x1000>;
7061 reg = <0x0 0x10b0d000 0x0 0x1000>;
7080 reg = <0x0 0x10b20000 0x0 0x1000>;
7100 reg = <0x0 0x10b23000 0x0 0x1000>;
7125 reg = <0x0 0x10b24000 0x0 0x1000>;
7150 reg = <0x0 0x10c08000 0x0 0x1000>;
7169 reg = <0x0 0x10c0b000 0x0 0x1000>;
7176 #size-cells = <0>;
7198 reg = <0x0 0x10c28000 0x0 0x1000>;
7217 reg = <0x0 0x10c29000 0x0 0x1000>;
7236 reg = <0x0 0x10c2b000 0x0 0x1000>;
7243 #size-cells = <0>;
7305 reg = <0x0 0x10c2c000 0x0 0x1000>;
7312 #size-cells = <0>;
7314 port@0 {
7315 reg = <0>;
7350 reg = <0x0 0x10c38000 0x0 0x1000>;
7369 reg = <0x0 0x10c39000 0x0 0x1000>;
7388 reg = <0x0 0x10c3c000 0x0 0x1000>;
7395 #size-cells = <0>;
7441 reg = <0x0 0x10c3d000 0x0 0x1000>;
7465 reg = <0x0 0x10cc1000 0x0 0x1000>;
7487 reg = <0x0 0x10cc4000 0x0 0x1000>;
7494 #size-cells = <0>;
7516 reg = <0x0 0x10cc5000 0x0 0x1000>;
7540 reg = <0x0 0x10d04000 0x0 0x1000>;
7547 #size-cells = <0>;
7569 reg = <0x0 0x10d08000 0x0 0x1000>;
7588 reg = <0x0 0x10d09000 0x0 0x1000>;
7607 reg = <0x0 0x10d0a000 0x0 0x1000>;
7626 reg = <0x0 0x10d0b000 0x0 0x1000>;
7645 reg = <0x0 0x10d0c000 0x0 0x1000>;
7664 reg = <0x0 0x10d0d000 0x0 0x1000>;
7683 reg = <0x0 0x10d0e000 0x0 0x1000>;
7702 reg = <0x0 0x10d0f000 0x0 0x1000>;
7721 reg = <0x0 0x10d12000 0x0 0x1000>;
7728 #size-cells = <0>;
7730 port@0 {
7731 reg = <0>;
7806 reg = <0x0 0x10d13000 0x0 0x1000>;
7830 reg = <0 0x15000000 0 0x100000>;
7938 reg = <0 0x17000000 0 0x10000>, /* GICD */
7939 <0 0x17080000 0 0x300000>; /* GICR * 12 */
7947 redistributor-stride = <0x0 0x40000>;
7955 reg = <0 0x17040000 0 0x40000>;
7964 reg = <0 0x17500000 0 0x10000>,
7965 <0 0x17510000 0 0x10000>,
7966 <0 0x17520000 0 0x10000>;
7967 reg-names = "drv-0", "drv-1", "drv-2";
7972 qcom,tcs-offset = <0xd00>;
7975 <WAKE_TCS 2>, <CONTROL_TCS 0>;
8068 reg = <0 0x17800000 0 0x1000>;
8072 ranges = <0 0 0 0 0x20000000>;
8075 reg = <0 0x17801000 0x1000>,
8076 <0 0x17802000 0x1000>;
8081 frame-number = <0>;
8085 reg = <0 0x17803000 0x1000>;
8095 reg = <0 0x17805000 0x1000>;
8105 reg = <0 0x17807000 0x1000>;
8115 reg = <0 0x17809000 0x1000>;
8125 reg = <0 0x1780b000 0x1000>;
8135 reg = <0 0x1780d000 0x1000>;
8147 reg = <0 0x24091000 0 0x1000>;
8159 opp-0 {
8204 reg = <0 0x240b3400 0 0x600>;
8216 opp-0 {
8245 reg = <0 0x240b5400 0 0x600>;
8258 reg = <0 0x240b6400 0 0x600>;
8270 reg = <0 0x25000000 0 0x200000>,
8271 <0 0x25200000 0 0x200000>,
8272 <0 0x25400000 0 0x200000>,
8273 <0 0x25600000 0 0x200000>,
8274 <0 0x25800000 0 0x200000>,
8275 <0 0x25a00000 0 0x200000>,
8276 <0 0x25c00000 0 0x200000>,
8277 <0 0x25e00000 0 0x200000>,
8278 <0 0x26000000 0 0x200000>,
8279 <0 0x26200000 0 0x200000>;
8295 reg = <0x0 0x32300000 0x0 0x10000>;
8298 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
8326 qcom,smem-states = <&smp2p_cdsp_out 0>;
8347 #size-cells = <0>;
8352 iommus = <&apps_smmu 0x0c01 0x20>;
8359 iommus = <&apps_smmu 0x0c02 0x20>;
8366 iommus = <&apps_smmu 0x0c03 0x20>;
8373 iommus = <&apps_smmu 0x0c04 0x20>;
8380 iommus = <&apps_smmu 0x0c05 0x20>;
8387 iommus = <&apps_smmu 0x0c06 0x20>;
8394 iommus = <&apps_smmu 0x0c07 0x20>;
8401 iommus = <&apps_smmu 0x0c08 0x20>;
8410 iommus = <&apps_smmu 0x0c0c 0x20>;
8417 iommus = <&apps_smmu 0x0c0d 0x20>;
8424 iommus = <&apps_smmu 0x0c0e 0x20>;
8431 iommus = <&apps_smmu 0x0c0f 0x20>;
8450 thermal-sensors = <&tsens0 0>;
8461 hysteresis = <0>;
8467 cpu0-0-top-thermal {
8493 cpu0-0-btm-thermal {
8687 hysteresis = <0>;
8705 hysteresis = <0>;
8723 hysteresis = <0>;
8744 thermal-sensors = <&tsens1 0>;
8755 hysteresis = <0>;
8761 cpu1-0-top-thermal {
8787 cpu1-0-btm-thermal {
8981 hysteresis = <0>;
8999 hysteresis = <0>;
9006 thermal-sensors = <&tsens2 0>;
9017 hysteresis = <0>;
9023 cpu2-0-top-thermal {
9049 cpu2-0-btm-thermal {
9243 hysteresis = <0>;
9261 hysteresis = <0>;
9268 thermal-sensors = <&tsens3 0>;
9279 hysteresis = <0>;
9297 hysteresis = <0>;
9315 hysteresis = <0>;
9333 hysteresis = <0>;
9351 hysteresis = <0>;
9357 gpuss-0-thermal {
9577 hysteresis = <0>;
9595 hysteresis = <0>;