Lines Matching +full:0 +full:x088e2000
36 #clock-cells = <0>;
42 #clock-cells = <0>;
47 #clock-cells = <0>;
56 #clock-cells = <0>;
66 #size-cells = <0>;
68 cpu0: cpu@0 {
71 reg = <0x0 0x0>;
88 reg = <0x0 0x100>;
99 reg = <0x0 0x200>;
110 reg = <0x0 0x300>;
121 reg = <0x0 0x10000>;
138 reg = <0x0 0x10100>;
149 reg = <0x0 0x10200>;
160 reg = <0x0 0x10300>;
171 reg = <0x0 0x20000>;
188 reg = <0x0 0x20100>;
199 reg = <0x0 0x20200>;
210 reg = <0x0 0x20300>;
277 cluster_c4: cpu-sleep-0 {
280 arm,psci-suspend-param = <0x00000004>;
288 cluster_cl4: cluster-sleep-0 {
290 arm,psci-suspend-param = <0x01000044>;
298 arm,psci-suspend-param = <0x01000054>;
311 qcom,dload-mode = <&tcsr 0x19000>;
315 clk_virt: interconnect-0 {
330 reg = <0 0x80000000 0 0>;
343 #power-domain-cells = <0>;
348 #power-domain-cells = <0>;
353 #power-domain-cells = <0>;
358 #power-domain-cells = <0>;
363 #power-domain-cells = <0>;
368 #power-domain-cells = <0>;
373 #power-domain-cells = <0>;
378 #power-domain-cells = <0>;
383 #power-domain-cells = <0>;
388 #power-domain-cells = <0>;
393 #power-domain-cells = <0>;
398 #power-domain-cells = <0>;
403 #power-domain-cells = <0>;
409 #power-domain-cells = <0>;
415 #power-domain-cells = <0>;
421 #power-domain-cells = <0>;
432 reg = <0x0 0x80000000 0x0 0x800000>;
437 reg = <0x0 0x80800000 0x0 0x200000>;
442 reg = <0x0 0x80a00000 0x0 0x400000>;
447 reg = <0x0 0x80e00000 0x0 0x40000>;
452 reg = <0x0 0x80e40000 0x0 0x540000>;
457 reg = <0x0 0x81380000 0x0 0x80000>;
462 reg = <0x0 0x81400000 0x0 0x1a0000>;
467 reg = <0x0 0x81a00000 0x0 0x40000>;
472 reg = <0x0 0x81a40000 0x0 0x1c0000>;
477 reg = <0x0 0x81c00000 0x0 0x60000>;
483 reg = <0x0 0x81c60000 0x0 0x20000>;
488 reg = <0x0 0x81c80000 0x0 0x20000>;
493 reg = <0x0 0x81ca0000 0x0 0x40000>;
498 reg = <0x0 0x81ce0000 0x0 0x4000>;
503 reg = <0x0 0x81ce4000 0x0 0x10000>;
508 reg = <0x0 0x81cff000 0x0 0x1000>;
513 reg = <0x0 0x81e00000 0x0 0x100000>;
518 reg = <0x0 0x81f00000 0x0 0x10000>;
523 reg = <0x0 0x81f10000 0x0 0x10000>;
528 reg = <0x0 0x81f20000 0x0 0x10000>;
533 reg = <0x0 0x81f30000 0x0 0x6000>;
538 reg = <0x0 0x81f36000 0x0 0x1000>;
543 reg = <0x0 0x81f37000 0x0 0x1000>;
548 reg = <0x0 0x82700000 0x0 0x100000>;
553 reg = <0x0 0x82800000 0x0 0xc00000>;
558 reg = <0x0 0x84b00000 0x0 0x800000>;
563 reg = <0x0 0x85300000 0x0 0x80000>;
568 reg = <0x0 0x866c0000 0x0 0x40000>;
573 reg = <0x0 0x86700000 0x0 0x400000>;
578 reg = <0x0 0x86b00000 0x0 0xc00000>;
583 reg = <0x0 0x87700000 0x0 0x700000>;
588 reg = <0x0 0x87e00000 0x0 0x3a00000>;
593 reg = <0x0 0x8b800000 0x0 0x80000>;
598 reg = <0x0 0x8b900000 0x0 0x2000000>;
603 reg = <0x0 0x8d900000 0x0 0x80000>;
608 reg = <0x0 0x8d9fe000 0x0 0x2000>;
613 reg = <0x0 0x8da00000 0x0 0x700000>;
618 reg = <0x0 0x8e100000 0x0 0x800000>;
623 reg = <0x0 0x8e900000 0x0 0x700000>;
628 reg = <0x0 0x8f000000 0x0 0xa00000>;
633 reg = <0x0 0x8fa00000 0x0 0x1900000>;
638 reg = <0x0 0x91300000 0x0 0x80000>;
643 reg = <0x0 0xd8000000 0x0 0x40000>;
648 reg = <0x0 0xd8040000 0x0 0xa0000>;
653 reg = <0x0 0xd80e0000 0x0 0x520000>;
658 reg = <0x0 0xd8600000 0x0 0x8a00000>;
663 reg = <0x0 0xe1000000 0x0 0x26a0000>;
668 reg = <0x0 0xff800000 0x0 0x600000>;
674 reg = <0x0 0xffe00000 0x0 0x200000>;
691 qcom,local-pid = <0>;
717 qcom,local-pid = <0>;
732 soc: soc@0 {
737 dma-ranges = <0 0 0 0 0x10 0>;
738 ranges = <0 0 0 0 0x10 0>;
742 reg = <0 0x00100000 0 0x200000>;
746 <0>,
750 <0>,
763 reg = <0 0x00408000 0 0x1000>;
774 reg = <0 0x00800000 0 0x60000>;
790 dma-channel-mask = <0x3e>;
793 iommus = <&apps_smmu 0x436 0x0>;
800 reg = <0 0x008c0000 0 0x2000>;
807 iommus = <&apps_smmu 0x423 0x0>;
817 reg = <0 0x00880000 0 0x4000>;
834 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
835 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
839 pinctrl-0 = <&qup_i2c16_data_clk>;
843 #size-cells = <0>;
850 reg = <0 0x00880000 0 0x4000>;
867 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
868 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
872 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
876 #size-cells = <0>;
883 reg = <0 0x00884000 0 0x4000>;
900 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
905 pinctrl-0 = <&qup_i2c17_data_clk>;
909 #size-cells = <0>;
916 reg = <0 0x00884000 0 0x4000>;
933 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
938 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
942 #size-cells = <0>;
949 reg = <0 0x00888000 0 0x4000>;
966 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
971 pinctrl-0 = <&qup_i2c18_data_clk>;
975 #size-cells = <0>;
982 reg = <0 0x00888000 0 0x4000>;
999 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1004 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
1008 #size-cells = <0>;
1015 reg = <0 0x0088c000 0 0x4000>;
1032 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1037 pinctrl-0 = <&qup_i2c19_data_clk>;
1041 #size-cells = <0>;
1048 reg = <0 0x0088c000 0 0x4000>;
1065 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1070 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
1074 #size-cells = <0>;
1081 reg = <0 0x00890000 0 0x4000>;
1098 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1103 pinctrl-0 = <&qup_i2c20_data_clk>;
1107 #size-cells = <0>;
1114 reg = <0 0x00890000 0 0x4000>;
1131 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1136 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1140 #size-cells = <0>;
1147 reg = <0 0x00894000 0 0x4000>;
1164 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1169 pinctrl-0 = <&qup_i2c21_data_clk>;
1173 #size-cells = <0>;
1180 reg = <0 0x00894000 0 0x4000>;
1197 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1202 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1206 #size-cells = <0>;
1213 reg = <0 0x00894000 0 0x4000>;
1227 pinctrl-0 = <&qup_uart21_default>;
1235 reg = <0 0x00898000 0 0x4000>;
1252 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1257 pinctrl-0 = <&qup_i2c22_data_clk>;
1261 #size-cells = <0>;
1268 reg = <0 0x00898000 0 0x4000>;
1285 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1290 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>;
1294 #size-cells = <0>;
1301 reg = <0 0x0089c000 0 0x4000>;
1318 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
1323 pinctrl-0 = <&qup_i2c23_data_clk>;
1327 #size-cells = <0>;
1334 reg = <0 0x0089c000 0 0x4000>;
1351 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
1356 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>;
1360 #size-cells = <0>;
1368 reg = <0 0x00a00000 0 0x60000>;
1384 dma-channel-mask = <0x3e>;
1387 iommus = <&apps_smmu 0x136 0x0>;
1394 reg = <0 0x00ac0000 0 0x2000>;
1401 iommus = <&apps_smmu 0x123 0x0>;
1411 reg = <0 0x00a80000 0 0x4000>;
1428 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1429 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1433 pinctrl-0 = <&qup_i2c8_data_clk>;
1437 #size-cells = <0>;
1444 reg = <0 0x00a80000 0 0x4000>;
1461 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1462 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1466 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1470 #size-cells = <0>;
1477 reg = <0 0x00a84000 0 0x4000>;
1494 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1499 pinctrl-0 = <&qup_i2c9_data_clk>;
1503 #size-cells = <0>;
1510 reg = <0 0x00a84000 0 0x4000>;
1527 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1532 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1536 #size-cells = <0>;
1543 reg = <0 0x00a88000 0 0x4000>;
1560 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1565 pinctrl-0 = <&qup_i2c10_data_clk>;
1569 #size-cells = <0>;
1576 reg = <0 0x00a88000 0 0x4000>;
1593 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1598 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1602 #size-cells = <0>;
1609 reg = <0 0x00a8c000 0 0x4000>;
1626 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1631 pinctrl-0 = <&qup_i2c11_data_clk>;
1635 #size-cells = <0>;
1642 reg = <0 0x00a8c000 0 0x4000>;
1659 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1664 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1668 #size-cells = <0>;
1675 reg = <0 0x00a90000 0 0x4000>;
1692 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1697 pinctrl-0 = <&qup_i2c12_data_clk>;
1701 #size-cells = <0>;
1708 reg = <0 0x00a90000 0 0x4000>;
1725 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1730 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1734 #size-cells = <0>;
1741 reg = <0 0x00a94000 0 0x4000>;
1758 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1763 pinctrl-0 = <&qup_i2c13_data_clk>;
1767 #size-cells = <0>;
1774 reg = <0 0x00a94000 0 0x4000>;
1791 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1796 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1800 #size-cells = <0>;
1807 reg = <0 0x00a98000 0 0x4000>;
1824 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1829 pinctrl-0 = <&qup_i2c14_data_clk>;
1833 #size-cells = <0>;
1840 reg = <0 0x00a98000 0 0x4000>;
1857 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1862 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1866 #size-cells = <0>;
1873 reg = <0 0x00a9c000 0 0x4000>;
1890 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
1895 pinctrl-0 = <&qup_i2c15_data_clk>;
1899 #size-cells = <0>;
1906 reg = <0 0x00a9c000 0 0x4000>;
1923 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
1928 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1932 #size-cells = <0>;
1940 reg = <0 0x00b00000 0 0x60000>;
1956 dma-channel-mask = <0x3e>;
1959 iommus = <&apps_smmu 0x456 0x0>;
1966 reg = <0 0x00bc0000 0 0x2000>;
1973 iommus = <&apps_smmu 0x443 0x0>;
1982 reg = <0 0x00b80000 0 0x4000>;
1999 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
2000 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
2004 pinctrl-0 = <&qup_i2c0_data_clk>;
2008 #size-cells = <0>;
2015 reg = <0 0x00b80000 0 0x4000>;
2032 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
2033 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
2037 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
2041 #size-cells = <0>;
2048 reg = <0 0x00b84000 0 0x4000>;
2065 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
2070 pinctrl-0 = <&qup_i2c1_data_clk>;
2074 #size-cells = <0>;
2081 reg = <0 0x00b84000 0 0x4000>;
2098 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
2103 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
2107 #size-cells = <0>;
2114 reg = <0 0x00b88000 0 0x4000>;
2131 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
2136 pinctrl-0 = <&qup_i2c2_data_clk>;
2140 #size-cells = <0>;
2147 reg = <0 0x00b88000 0 0x4000>;
2161 pinctrl-0 = <&qup_uart2_default>;
2169 reg = <0 0x00b88000 0 0x4000>;
2186 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
2191 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
2195 #size-cells = <0>;
2202 reg = <0 0x00b8c000 0 0x4000>;
2219 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
2224 pinctrl-0 = <&qup_i2c3_data_clk>;
2228 #size-cells = <0>;
2235 reg = <0 0x00b8c000 0 0x4000>;
2252 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
2257 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
2261 #size-cells = <0>;
2268 reg = <0 0x00b90000 0 0x4000>;
2285 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
2290 pinctrl-0 = <&qup_i2c4_data_clk>;
2294 #size-cells = <0>;
2301 reg = <0 0x00b90000 0 0x4000>;
2318 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
2323 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
2327 #size-cells = <0>;
2334 reg = <0 0x00b94000 0 0x4000>;
2351 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
2356 pinctrl-0 = <&qup_i2c5_data_clk>;
2360 #size-cells = <0>;
2367 reg = <0 0x00b94000 0 0x4000>;
2384 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
2389 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
2393 #size-cells = <0>;
2400 reg = <0 0x00b98000 0 0x4000>;
2417 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
2422 pinctrl-0 = <&qup_i2c6_data_clk>;
2426 #size-cells = <0>;
2433 reg = <0 0x00b98000 0 0x4000>;
2450 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
2455 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
2459 #size-cells = <0>;
2466 reg = <0 0x00b9c000 0 0x4000>;
2483 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
2488 pinctrl-0 = <&qup_i2c7_data_clk>;
2492 #size-cells = <0>;
2499 reg = <0 0x00b9c000 0 0x4000>;
2516 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
2521 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
2525 #size-cells = <0>;
2533 reg = <0 0x0c271000 0 0x1000>,
2534 <0 0x0c222000 0 0x1000>;
2548 reg = <0 0x0c272000 0 0x1000>,
2549 <0 0x0c223000 0 0x1000>;
2563 reg = <0 0x0c273000 0 0x1000>,
2564 <0 0x0c224000 0 0x1000>;
2578 reg = <0 0x0c274000 0 0x1000>,
2579 <0 0x0c225000 0 0x1000>;
2594 reg = <0 0x00fd3000 0 0x154>;
2595 #phy-cells = <0>;
2607 reg = <0 0x00fd5000 0 0x4000>;
2634 #size-cells = <0>;
2636 port@0 {
2637 reg = <0>;
2664 reg = <0 0x00fd9000 0 0x154>;
2665 #phy-cells = <0>;
2677 reg = <0 0x00fda000 0 0x4000>;
2704 #size-cells = <0>;
2706 port@0 {
2707 reg = <0>;
2734 reg = <0 0x00fde000 0 0x154>;
2735 #phy-cells = <0>;
2747 reg = <0 0x00fdf000 0 0x4000>;
2774 #size-cells = <0>;
2776 port@0 {
2777 reg = <0>;
2803 reg = <0 0x01500000 0 0x14400>;
2812 reg = <0 0x01600000 0 0x6600>;
2821 reg = <0 0x01680000 0 0x1c080>;
2830 reg = <0 0x016c0000 0 0xd080>;
2839 reg = <0 0x016d0000 0 0x7000>;
2848 reg = <0 0x016e0000 0 0x14400>;
2857 reg = <0 0x01700000 0 0x1c400>;
2866 reg = <0 0x01740000 0 0x9080>;
2875 reg = <0 0x01750000 0 0x8800>;
2884 reg = <0 0x01760000 0 0x7080>;
2893 reg = <0 0x01770000 0 0xf080>;
2902 reg = <0 0x01780000 0 0x5B800>;
2912 reg = <0 0x01bf8000 0 0x3000>,
2913 <0 0x70000000 0 0xf20>,
2914 <0 0x70000f40 0 0xa8>,
2915 <0 0x70001000 0 0x1000>,
2916 <0 0x70100000 0 0x100000>,
2917 <0 0x01bfb000 0 0x1000>;
2926 ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>,
2927 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x1d00000>;
2928 bus-range = <0x00 0xff>;
2935 msi-map = <0x0 &gic_its 0xe0000 0x10000>;
2955 interrupt-map-mask = <0 0 0 0x7>;
2956 interrupt-map = <0 0 0 1 &intc 0 0 0 843 IRQ_TYPE_LEVEL_HIGH>,
2957 <0 0 0 2 &intc 0 0 0 844 IRQ_TYPE_LEVEL_HIGH>,
2958 <0 0 0 3 &intc 0 0 0 845 IRQ_TYPE_LEVEL_HIGH>,
2959 <0 0 0 4 &intc 0 0 0 772 IRQ_TYPE_LEVEL_HIGH>;
3002 reg = <0 0x01bfc000 0 0x2000>,
3003 <0 0x01bfe000 0 0x2000>;
3028 qcom,4ln-config-sel = <&tcsr 0x1a000 0>;
3030 #clock-cells = <0>;
3033 #phy-cells = <0>;
3041 reg = <0 0x01c00000 0 0x3000>,
3042 <0 0x7e000000 0 0xf1d>,
3043 <0 0x7e000f40 0 0xa8>,
3044 <0 0x7e001000 0 0x1000>,
3045 <0 0x7e100000 0 0x100000>,
3046 <0 0x01c03000 0 0x1000>;
3055 ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>,
3056 <0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>;
3057 bus-range = <0x00 0xff>;
3082 interrupt-map-mask = <0 0 0 0x7>;
3083 interrupt-map = <0 0 0 1 &intc 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>,
3084 <0 0 0 2 &intc 0 0 0 71 IRQ_TYPE_LEVEL_HIGH>,
3085 <0 0 0 3 &intc 0 0 0 72 IRQ_TYPE_LEVEL_HIGH>,
3086 <0 0 0 4 &intc 0 0 0 73 IRQ_TYPE_LEVEL_HIGH>;
3129 reg = <0 0x01c06000 0 0x2000>;
3152 #clock-cells = <0>;
3155 #phy-cells = <0>;
3163 reg = <0 0x01c08000 0 0x3000>,
3164 <0 0x7c000000 0 0xf1d>,
3165 <0 0x7c000f40 0 0xa8>,
3166 <0 0x7c001000 0 0x1000>,
3167 <0 0x7c100000 0 0x100000>,
3168 <0 0x01c0b000 0 0x1000>;
3177 ranges = <0x01000000 0x0 0x00000000 0x0 0x7c200000 0x0 0x100000>,
3178 <0x02000000 0x0 0x7c300000 0x0 0x7c300000 0x0 0x1d00000>;
3179 bus-range = <0x00 0xff>;
3186 msi-map = <0x0 &gic_its 0xc0000 0x10000>;
3206 interrupt-map-mask = <0 0 0 0x7>;
3207 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
3208 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
3209 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
3210 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
3250 pcie4_port0: pcie@0 {
3252 reg = <0x0 0x0 0x0 0x0 0x0>;
3253 bus-range = <0x01 0xff>;
3263 reg = <0 0x01c0e000 0 0x2000>;
3286 #clock-cells = <0>;
3289 #phy-cells = <0>;
3296 reg = <0 0x01f40000 0 0x20000>;
3302 reg = <0 0x01fc0000 0 0x30000>;
3310 reg = <0x0 0x03d00000 0x0 0x40000>,
3311 <0x0 0x03d9e000 0x0 0x1000>,
3312 <0x0 0x03d61000 0x0 0x800>;
3320 iommus = <&adreno_smmu 0 0x0>,
3321 <&adreno_smmu 1 0x0>;
3328 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
3398 reg = <0x0 0x03d6a000 0x0 0x35000>,
3399 <0x0 0x03d50000 0x0 0x10000>,
3400 <0x0 0x0b280000 0x0 0x10000>;
3427 iommus = <&adreno_smmu 5 0x0>;
3450 reg = <0 0x03d90000 0 0xa000>;
3462 reg = <0x0 0x03da0000 0x0 0x40000>;
3505 reg = <0 0x26400000 0 0x311200>;
3514 reg = <0 0x320C0000 0 0xe080>;
3523 reg = <0 0x06aa0000 0 0x1000>;
3533 #clock-cells = <0>;
3541 reg = <0 0x06ab0000 0 0x10000>;
3547 pinctrl-0 = <&wsa2_swr_active>;
3555 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x3…
3556 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
3557 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3558 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3559 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3560 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
3561 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
3562 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
3563 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
3566 #size-cells = <0>;
3573 reg = <0 0x06ac0000 0 0x1000>;
3583 #clock-cells = <0>;
3590 reg = <0 0x06ad0000 0 0x10000>;
3596 pinctrl-0 = <&rx_swr_active>;
3604 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3605 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3606 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3607 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3608 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3609 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3610 …qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff…
3611 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
3612 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3615 #size-cells = <0>;
3622 reg = <0 0x06ae0000 0 0x1000>;
3632 #clock-cells = <0>;
3639 reg = <0 0x06b00000 0 0x1000>;
3649 #clock-cells = <0>;
3657 reg = <0 0x06b10000 0 0x10000>;
3663 pinctrl-0 = <&wsa_swr_active>;
3671 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x3…
3672 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
3673 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3674 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3675 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3676 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
3677 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
3678 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
3679 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
3682 #size-cells = <0>;
3689 reg = <0 0x06b6c000 0 0x1000>;
3696 reg = <0 0x06d30000 0 0x10000>;
3706 pinctrl-0 = <&tx_swr_active>;
3712 qcom,ports-sinterval-low = /bits/ 8 <0x00 0x01 0x03 0x03 0x00>;
3713 qcom,ports-offset1 = /bits/ 8 <0x00 0x01 0x02 0x00 0x00>;
3714 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00 0xff>;
3715 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3716 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3717 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3718 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3719 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3720 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x00 0x01 0xff>;
3723 #size-cells = <0>;
3730 reg = <0 0x06d44000 0 0x1000>;
3738 #clock-cells = <0>;
3745 reg = <0 0x06e80000 0 0x20000>,
3746 <0 0x07250000 0 0x10000>;
3754 gpio-ranges = <&lpass_tlmm 0 0 23>;
3863 reg = <0 0x06ea0000 0 0x12000>;
3870 reg = <0 0x07e40000 0 0xe080>;
3879 reg = <0 0x07400000 0 0x19080>;
3888 reg = <0 0x07430000 0 0x3A200>;
3898 reg = <0 0x088e0000 0 0x154>;
3899 #phy-cells = <0>;
3912 reg = <0 0x088e1000 0 0x154>;
3913 #phy-cells = <0>;
3926 reg = <0 0x088e2000 0 0x154>;
3927 #phy-cells = <0>;
3939 reg = <0 0x088e3000 0 0x2000>;
3957 #clock-cells = <0>;
3960 #phy-cells = <0>;
3967 reg = <0 0x088e5000 0 0x2000>;
3985 #clock-cells = <0>;
3988 #phy-cells = <0>;
3995 reg = <0 0x0a0f8800 0 0x400>;
4052 reg = <0 0x0a000000 0 0xcd00>;
4056 iommus = <&apps_smmu 0x14a0 0x0>;
4073 #size-cells = <0>;
4075 port@0 {
4076 reg = <0>;
4095 reg = <0 0x0a2f8800 0 0x400>;
4148 reg = <0 0x0a200000 0 0xcd00>;
4150 iommus = <&apps_smmu 0x14e0 0x0>;
4157 #size-cells = <0>;
4159 port@0 {
4160 reg = <0>;
4171 reg = <0 0x0a4f8800 0 0x400>;
4235 reg = <0 0x0a400000 0 0xcd00>;
4239 iommus = <&apps_smmu 0x1400 0x0>;
4243 phy-names = "usb2-0", "usb3-0",
4257 reg = <0 0x0a6f8800 0 0x400>;
4307 reg = <0 0x0a600000 0 0xcd00>;
4311 iommus = <&apps_smmu 0x1420 0x0>;
4328 #size-cells = <0>;
4330 port@0 {
4331 reg = <0>;
4350 reg = <0 0x0a8f8800 0 0x400>;
4407 reg = <0 0x0a800000 0 0xcd00>;
4411 iommus = <&apps_smmu 0x1460 0x0>;
4428 #size-cells = <0>;
4430 port@0 {
4431 reg = <0>;
4450 reg = <0 0x0ae00000 0 0x1000>;
4473 iommus = <&apps_smmu 0x1c00 0x2>;
4486 reg = <0 0x0ae01000 0 0x8f000>,
4487 <0 0x0aeb0000 0 0x2008>;
4491 interrupts-extended = <&mdss 0>;
4510 #size-cells = <0>;
4512 port@0 {
4513 reg = <0>;
4577 reg = <0 0x0ae90000 0 0x200>,
4578 <0 0x0ae90200 0 0x200>,
4579 <0 0x0ae90400 0 0x600>,
4580 <0 0x0ae91000 0 0x400>,
4581 <0 0x0ae91400 0 0x400>;
4608 #sound-dai-cells = <0>;
4614 #size-cells = <0>;
4616 port@0 {
4617 reg = <0>;
4660 reg = <0 0x0ae98000 0 0x200>,
4661 <0 0x0ae98200 0 0x200>,
4662 <0 0x0ae98400 0 0x600>,
4663 <0 0x0ae99000 0 0x400>,
4664 <0 0x0ae99400 0 0x400>;
4691 #sound-dai-cells = <0>;
4697 #size-cells = <0>;
4699 port@0 {
4700 reg = <0>;
4743 reg = <0 0x0ae9a000 0 0x200>,
4744 <0 0x0ae9a200 0 0x200>,
4745 <0 0x0ae9a400 0 0x600>,
4746 <0 0x0ae9b000 0 0x400>,
4747 <0 0x0ae9b400 0 0x400>;
4774 #sound-dai-cells = <0>;
4780 #size-cells = <0>;
4782 port@0 {
4783 reg = <0>;
4825 reg = <0 0x0aea0000 0 0x200>,
4826 <0 0x0aea0200 0 0x200>,
4827 <0 0x0aea0400 0 0x600>,
4828 <0 0x0aea1000 0 0x400>,
4829 <0 0x0aea1400 0 0x400>;
4846 assigned-clock-parents = <&mdss_dp3_phy 0>,
4856 #sound-dai-cells = <0>;
4862 #size-cells = <0>;
4864 port@0 {
4865 reg = <0>;
4906 reg = <0 0x0aec2a00 0 0x19c>,
4907 <0 0x0aec2200 0 0xec>,
4908 <0 0x0aec2600 0 0xec>,
4909 <0 0x0aec2000 0 0x1c8>;
4919 #phy-cells = <0>;
4926 reg = <0 0x0aec5a00 0 0x19c>,
4927 <0 0x0aec5200 0 0xec>,
4928 <0 0x0aec5600 0 0xec>,
4929 <0 0x0aec5000 0 0x1c8>;
4939 #phy-cells = <0>;
4946 reg = <0 0x0af00000 0 0x20000>;
4951 <0>, /* dsi0 */
4952 <0>,
4953 <0>, /* dsi1 */
4954 <0>,
4961 <&mdss_dp3_phy 0>, /* dp3 */
4972 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
4974 qcom,pdc-ranges = <0 480 42>, <42 251 5>,
4984 reg = <0 0x0c300000 0 0x400>;
4990 #clock-cells = <0>;
4995 reg = <0 0x0c3f0000 0 0x400>;
5000 reg = <0 0x0c400000 0 0x3000>,
5001 <0 0x0c500000 0 0x400000>,
5002 <0 0x0c440000 0 0x80000>;
5005 qcom,ee = <0>;
5006 qcom,channel = <0>;
5013 reg = <0 0x0c42d000 0 0x4000>,
5014 <0 0x0c4c0000 0 0x10000>;
5023 #size-cells = <0>;
5027 reg = <0 0x0c432000 0 0x4000>,
5028 <0 0x0c4d0000 0 0x10000>;
5037 #size-cells = <0>;
5043 reg = <0 0x0f100000 0 0xf00000>;
5053 gpio-ranges = <&tlmm 0 0 239>;
5657 reg = <0 0x15000000 0 0x100000>;
5765 reg = <0 0x17000000 0 0x10000>, /* GICD */
5766 <0 0x17080000 0 0x300000>; /* GICR * 12 */
5774 redistributor-stride = <0x0 0x40000>;
5782 reg = <0 0x17040000 0 0x40000>;
5791 reg = <0 0x17500000 0 0x10000>,
5792 <0 0x17510000 0 0x10000>,
5793 <0 0x17520000 0 0x10000>;
5794 reg-names = "drv-0", "drv-1", "drv-2";
5799 qcom,tcs-offset = <0xd00>;
5802 <WAKE_TCS 2>, <CONTROL_TCS 0>;
5895 reg = <0 0x17800000 0 0x1000>;
5899 ranges = <0 0 0 0 0x20000000>;
5902 reg = <0 0x17801000 0x1000>,
5903 <0 0x17802000 0x1000>;
5908 frame-number = <0>;
5912 reg = <0 0x17803000 0x1000>;
5922 reg = <0 0x17805000 0x1000>;
5932 reg = <0 0x17807000 0x1000>;
5942 reg = <0 0x17809000 0x1000>;
5952 reg = <0 0x1780b000 0x1000>;
5962 reg = <0 0x1780d000 0x1000>;
5974 reg = <0 0x24091000 0 0x1000>;
5986 opp-0 {
6031 reg = <0 0x240b3400 0 0x600>;
6043 opp-0 {
6072 reg = <0 0x240b5400 0 0x600>;
6085 reg = <0 0x240b6400 0 0x600>;
6097 reg = <0 0x25000000 0 0x200000>,
6098 <0 0x25200000 0 0x200000>,
6099 <0 0x25400000 0 0x200000>,
6100 <0 0x25600000 0 0x200000>,
6101 <0 0x25800000 0 0x200000>,
6102 <0 0x25a00000 0 0x200000>,
6103 <0 0x25c00000 0 0x200000>,
6104 <0 0x25e00000 0 0x200000>,
6105 <0 0x26000000 0 0x200000>,
6106 <0 0x26200000 0 0x200000>;
6122 reg = <0 0x30000000 0 0x100>;
6125 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
6151 qcom,smem-states = <&smp2p_adsp_out 0>;
6172 #size-cells = <0>;
6177 iommus = <&apps_smmu 0x1003 0x80>,
6178 <&apps_smmu 0x1063 0x0>;
6185 iommus = <&apps_smmu 0x1004 0x80>,
6186 <&apps_smmu 0x1064 0x0>;
6193 iommus = <&apps_smmu 0x1005 0x80>,
6194 <&apps_smmu 0x1065 0x0>;
6201 iommus = <&apps_smmu 0x1006 0x80>,
6202 <&apps_smmu 0x1066 0x0>;
6209 iommus = <&apps_smmu 0x1007 0x80>,
6210 <&apps_smmu 0x1067 0x0>;
6221 #size-cells = <0>;
6226 #sound-dai-cells = <0>;
6237 iommus = <&apps_smmu 0x1001 0x80>,
6238 <&apps_smmu 0x1061 0x0>;
6259 reg = <0 0x32300000 0 0x1400000>;
6262 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
6290 qcom,smem-states = <&smp2p_cdsp_out 0>;
6311 #size-cells = <0>;
6316 iommus = <&apps_smmu 0x0c01 0x20>;
6323 iommus = <&apps_smmu 0x0c02 0x20>;
6330 iommus = <&apps_smmu 0x0c03 0x20>;
6337 iommus = <&apps_smmu 0x0c04 0x20>;
6344 iommus = <&apps_smmu 0x0c05 0x20>;
6351 iommus = <&apps_smmu 0x0c06 0x20>;
6358 iommus = <&apps_smmu 0x0c07 0x20>;
6365 iommus = <&apps_smmu 0x0c08 0x20>;
6374 iommus = <&apps_smmu 0x0c0c 0x20>;
6381 iommus = <&apps_smmu 0x0c0d 0x20>;
6388 iommus = <&apps_smmu 0x0c0e 0x20>;
6395 iommus = <&apps_smmu 0x0c0f 0x20>;
6414 thermal-sensors = <&tsens0 0>;
6425 hysteresis = <0>;
6431 cpu0-0-top-thermal {
6457 cpu0-0-btm-thermal {
6651 hysteresis = <0>;
6669 hysteresis = <0>;
6687 hysteresis = <0>;
6708 thermal-sensors = <&tsens1 0>;
6719 hysteresis = <0>;
6725 cpu1-0-top-thermal {
6751 cpu1-0-btm-thermal {
6945 hysteresis = <0>;
6963 hysteresis = <0>;
6970 thermal-sensors = <&tsens2 0>;
6981 hysteresis = <0>;
6987 cpu2-0-top-thermal {
7013 cpu2-0-btm-thermal {
7207 hysteresis = <0>;
7225 hysteresis = <0>;
7232 thermal-sensors = <&tsens3 0>;
7243 hysteresis = <0>;
7261 hysteresis = <0>;
7279 hysteresis = <0>;
7297 hysteresis = <0>;
7315 hysteresis = <0>;
7321 gpuss-0-thermal {
7541 hysteresis = <0>;
7559 hysteresis = <0>;