Lines Matching +full:0 +full:x01700000
37 #clock-cells = <0>;
43 #clock-cells = <0>;
48 #clock-cells = <0>;
57 #clock-cells = <0>;
67 #size-cells = <0>;
69 cpu0: cpu@0 {
72 reg = <0x0 0x0>;
75 power-domains = <&cpu_pd0>, <&scmi_dvfs 0>;
89 reg = <0x0 0x100>;
92 power-domains = <&cpu_pd1>, <&scmi_dvfs 0>;
100 reg = <0x0 0x200>;
103 power-domains = <&cpu_pd2>, <&scmi_dvfs 0>;
111 reg = <0x0 0x300>;
114 power-domains = <&cpu_pd3>, <&scmi_dvfs 0>;
122 reg = <0x0 0x10000>;
139 reg = <0x0 0x10100>;
150 reg = <0x0 0x10200>;
161 reg = <0x0 0x10300>;
172 reg = <0x0 0x20000>;
189 reg = <0x0 0x20100>;
200 reg = <0x0 0x20200>;
211 reg = <0x0 0x20300>;
278 cluster_c4: cpu-sleep-0 {
281 arm,psci-suspend-param = <0x00000004>;
289 cluster_cl4: cluster-sleep-0 {
291 arm,psci-suspend-param = <0x01000044>;
299 arm,psci-suspend-param = <0x01000054>;
324 qcom,dload-mode = <&tcsr 0x19000>;
329 mboxes = <&cpucp_mbox 0>, <&cpucp_mbox 2>;
334 #size-cells = <0>;
337 reg = <0x13>;
343 clk_virt: interconnect-0 {
358 reg = <0 0x80000000 0 0>;
371 #power-domain-cells = <0>;
376 #power-domain-cells = <0>;
381 #power-domain-cells = <0>;
386 #power-domain-cells = <0>;
391 #power-domain-cells = <0>;
396 #power-domain-cells = <0>;
401 #power-domain-cells = <0>;
406 #power-domain-cells = <0>;
411 #power-domain-cells = <0>;
416 #power-domain-cells = <0>;
421 #power-domain-cells = <0>;
426 #power-domain-cells = <0>;
431 #power-domain-cells = <0>;
437 #power-domain-cells = <0>;
443 #power-domain-cells = <0>;
449 #power-domain-cells = <0>;
460 reg = <0x0 0x80000000 0x0 0x800000>;
465 reg = <0x0 0x80800000 0x0 0x200000>;
470 reg = <0x0 0x80a00000 0x0 0x400000>;
475 reg = <0x0 0x80e00000 0x0 0x40000>;
480 reg = <0x0 0x80e40000 0x0 0x540000>;
485 reg = <0x0 0x81380000 0x0 0x80000>;
490 reg = <0x0 0x81400000 0x0 0x1a0000>;
495 reg = <0x0 0x81a00000 0x0 0x40000>;
500 reg = <0x0 0x81a40000 0x0 0x1c0000>;
505 reg = <0x0 0x81c00000 0x0 0x60000>;
511 reg = <0x0 0x81c60000 0x0 0x20000>;
516 reg = <0x0 0x81c80000 0x0 0x20000>;
521 reg = <0x0 0x81ca0000 0x0 0x40000>;
526 reg = <0x0 0x81ce0000 0x0 0x4000>;
531 reg = <0x0 0x81ce4000 0x0 0x10000>;
536 reg = <0x0 0x81cff000 0x0 0x1000>;
541 reg = <0x0 0x81e00000 0x0 0x100000>;
546 reg = <0x0 0x81f00000 0x0 0x10000>;
551 reg = <0x0 0x81f10000 0x0 0x10000>;
556 reg = <0x0 0x81f20000 0x0 0x10000>;
561 reg = <0x0 0x81f30000 0x0 0x6000>;
566 reg = <0x0 0x81f36000 0x0 0x1000>;
571 reg = <0x0 0x81f37000 0x0 0x1000>;
576 reg = <0x0 0x82700000 0x0 0x100000>;
581 reg = <0x0 0x82800000 0x0 0xc00000>;
586 reg = <0x0 0x84b00000 0x0 0x800000>;
591 reg = <0x0 0x85300000 0x0 0x80000>;
596 reg = <0x0 0x866c0000 0x0 0x40000>;
601 reg = <0x0 0x86700000 0x0 0x400000>;
606 reg = <0x0 0x86b00000 0x0 0xc00000>;
611 reg = <0x0 0x87700000 0x0 0x700000>;
616 reg = <0x0 0x87e00000 0x0 0x3a00000>;
621 reg = <0x0 0x8b800000 0x0 0x80000>;
626 reg = <0x0 0x8b900000 0x0 0x2000000>;
631 reg = <0x0 0x8d900000 0x0 0x80000>;
636 reg = <0x0 0x8d9fe000 0x0 0x2000>;
641 reg = <0x0 0x8da00000 0x0 0x700000>;
646 reg = <0x0 0x8e100000 0x0 0x800000>;
651 reg = <0x0 0x8e900000 0x0 0x700000>;
656 reg = <0x0 0x8f000000 0x0 0xa00000>;
661 reg = <0x0 0x8fa00000 0x0 0x1900000>;
666 reg = <0x0 0x91300000 0x0 0x80000>;
671 reg = <0x0 0xd8000000 0x0 0x40000>;
676 reg = <0x0 0xd8040000 0x0 0xa0000>;
681 reg = <0x0 0xd80e0000 0x0 0x520000>;
686 reg = <0x0 0xd8600000 0x0 0x8a00000>;
691 reg = <0x0 0xe1000000 0x0 0x26a0000>;
696 reg = <0x0 0xff800000 0x0 0x600000>;
702 reg = <0x0 0xffe00000 0x0 0x200000>;
747 qcom,local-pid = <0>;
773 qcom,local-pid = <0>;
788 soc: soc@0 {
793 dma-ranges = <0 0 0 0 0x10 0>;
794 ranges = <0 0 0 0 0x10 0>;
798 reg = <0 0x00100000 0 0x200000>;
806 <0>,
819 reg = <0 0x00408000 0 0x1000>;
830 reg = <0 0x00800000 0 0x60000>;
846 dma-channel-mask = <0x3e>;
849 iommus = <&apps_smmu 0x436 0x0>;
856 reg = <0 0x008c0000 0 0x2000>;
863 iommus = <&apps_smmu 0x423 0x0>;
873 reg = <0 0x00880000 0 0x4000>;
893 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
894 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
898 pinctrl-0 = <&qup_i2c16_data_clk>;
902 #size-cells = <0>;
909 reg = <0 0x00880000 0 0x4000>;
929 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
930 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
934 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
938 #size-cells = <0>;
945 reg = <0 0x00884000 0 0x4000>;
965 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
970 pinctrl-0 = <&qup_i2c17_data_clk>;
974 #size-cells = <0>;
981 reg = <0 0x00884000 0 0x4000>;
1001 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1006 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
1010 #size-cells = <0>;
1017 reg = <0 0x00888000 0 0x4000>;
1037 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1042 pinctrl-0 = <&qup_i2c18_data_clk>;
1046 #size-cells = <0>;
1053 reg = <0 0x00888000 0 0x4000>;
1073 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1078 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
1082 #size-cells = <0>;
1089 reg = <0 0x0088c000 0 0x4000>;
1109 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1114 pinctrl-0 = <&qup_i2c19_data_clk>;
1118 #size-cells = <0>;
1125 reg = <0 0x0088c000 0 0x4000>;
1145 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1150 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
1154 #size-cells = <0>;
1161 reg = <0 0x00890000 0 0x4000>;
1181 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1186 pinctrl-0 = <&qup_i2c20_data_clk>;
1190 #size-cells = <0>;
1197 reg = <0 0x00890000 0 0x4000>;
1217 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1222 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1226 #size-cells = <0>;
1233 reg = <0 0x00894000 0 0x4000>;
1253 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1258 pinctrl-0 = <&qup_i2c21_data_clk>;
1262 #size-cells = <0>;
1269 reg = <0 0x00894000 0 0x4000>;
1289 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1294 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1298 #size-cells = <0>;
1305 reg = <0 0x00894000 0 0x4000>;
1322 pinctrl-0 = <&qup_uart21_default>;
1330 reg = <0 0x00898000 0 0x4000>;
1350 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1355 pinctrl-0 = <&qup_i2c22_data_clk>;
1359 #size-cells = <0>;
1366 reg = <0 0x00898000 0 0x4000>;
1386 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1391 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>;
1395 #size-cells = <0>;
1402 reg = <0 0x0089c000 0 0x4000>;
1422 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
1427 pinctrl-0 = <&qup_i2c23_data_clk>;
1431 #size-cells = <0>;
1438 reg = <0 0x0089c000 0 0x4000>;
1458 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
1463 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>;
1467 #size-cells = <0>;
1475 reg = <0 0x00a00000 0 0x60000>;
1491 dma-channel-mask = <0x3e>;
1494 iommus = <&apps_smmu 0x136 0x0>;
1501 reg = <0 0x00ac0000 0 0x2000>;
1508 iommus = <&apps_smmu 0x123 0x0>;
1518 reg = <0 0x00a80000 0 0x4000>;
1538 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1539 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1543 pinctrl-0 = <&qup_i2c8_data_clk>;
1547 #size-cells = <0>;
1554 reg = <0 0x00a80000 0 0x4000>;
1574 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1575 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1579 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1583 #size-cells = <0>;
1590 reg = <0 0x00a84000 0 0x4000>;
1610 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1615 pinctrl-0 = <&qup_i2c9_data_clk>;
1619 #size-cells = <0>;
1626 reg = <0 0x00a84000 0 0x4000>;
1646 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1651 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1655 #size-cells = <0>;
1662 reg = <0 0x00a88000 0 0x4000>;
1682 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1687 pinctrl-0 = <&qup_i2c10_data_clk>;
1691 #size-cells = <0>;
1698 reg = <0 0x00a88000 0 0x4000>;
1718 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1723 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1727 #size-cells = <0>;
1734 reg = <0 0x00a8c000 0 0x4000>;
1754 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1759 pinctrl-0 = <&qup_i2c11_data_clk>;
1763 #size-cells = <0>;
1770 reg = <0 0x00a8c000 0 0x4000>;
1790 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1795 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1799 #size-cells = <0>;
1806 reg = <0 0x00a90000 0 0x4000>;
1826 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1831 pinctrl-0 = <&qup_i2c12_data_clk>;
1835 #size-cells = <0>;
1842 reg = <0 0x00a90000 0 0x4000>;
1862 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1867 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1871 #size-cells = <0>;
1878 reg = <0 0x00a94000 0 0x4000>;
1898 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1903 pinctrl-0 = <&qup_i2c13_data_clk>;
1907 #size-cells = <0>;
1914 reg = <0 0x00a94000 0 0x4000>;
1934 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1939 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1943 #size-cells = <0>;
1950 reg = <0 0x00a98000 0 0x4000>;
1970 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1975 pinctrl-0 = <&qup_i2c14_data_clk>;
1979 #size-cells = <0>;
1986 reg = <0 0x00a98000 0 0x4000>;
2006 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
2011 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
2015 #size-cells = <0>;
2022 reg = <0 0x00a98000 0 0x4000>;
2039 pinctrl-0 = <&qup_uart14_default>;
2047 reg = <0 0x00a9c000 0 0x4000>;
2067 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
2072 pinctrl-0 = <&qup_i2c15_data_clk>;
2076 #size-cells = <0>;
2083 reg = <0 0x00a9c000 0 0x4000>;
2103 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
2108 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
2112 #size-cells = <0>;
2120 reg = <0 0x00b00000 0 0x60000>;
2136 dma-channel-mask = <0x3e>;
2139 iommus = <&apps_smmu 0x456 0x0>;
2146 reg = <0 0x00bc0000 0 0x2000>;
2153 iommus = <&apps_smmu 0x443 0x0>;
2162 reg = <0 0x00b80000 0 0x4000>;
2182 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
2183 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
2187 pinctrl-0 = <&qup_i2c0_data_clk>;
2191 #size-cells = <0>;
2198 reg = <0 0x00b80000 0 0x4000>;
2218 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
2219 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
2223 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
2227 #size-cells = <0>;
2234 reg = <0 0x00b84000 0 0x4000>;
2254 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
2259 pinctrl-0 = <&qup_i2c1_data_clk>;
2263 #size-cells = <0>;
2270 reg = <0 0x00b84000 0 0x4000>;
2290 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
2295 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
2299 #size-cells = <0>;
2306 reg = <0 0x00b88000 0 0x4000>;
2326 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
2331 pinctrl-0 = <&qup_i2c2_data_clk>;
2335 #size-cells = <0>;
2342 reg = <0 0x00b88000 0 0x4000>;
2359 pinctrl-0 = <&qup_uart2_default>;
2367 reg = <0 0x00b88000 0 0x4000>;
2387 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
2392 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
2396 #size-cells = <0>;
2403 reg = <0 0x00b8c000 0 0x4000>;
2423 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
2428 pinctrl-0 = <&qup_i2c3_data_clk>;
2432 #size-cells = <0>;
2439 reg = <0 0x00b8c000 0 0x4000>;
2459 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
2464 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
2468 #size-cells = <0>;
2475 reg = <0 0x00b90000 0 0x4000>;
2495 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
2500 pinctrl-0 = <&qup_i2c4_data_clk>;
2504 #size-cells = <0>;
2511 reg = <0 0x00b90000 0 0x4000>;
2531 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
2536 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
2540 #size-cells = <0>;
2547 reg = <0 0x00b94000 0 0x4000>;
2567 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
2572 pinctrl-0 = <&qup_i2c5_data_clk>;
2576 #size-cells = <0>;
2583 reg = <0 0x00b94000 0 0x4000>;
2603 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
2608 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
2612 #size-cells = <0>;
2619 reg = <0 0x00b98000 0 0x4000>;
2639 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
2644 pinctrl-0 = <&qup_i2c6_data_clk>;
2648 #size-cells = <0>;
2655 reg = <0 0x00b98000 0 0x4000>;
2675 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
2680 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
2684 #size-cells = <0>;
2691 reg = <0 0x00b9c000 0 0x4000>;
2711 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
2716 pinctrl-0 = <&qup_i2c7_data_clk>;
2720 #size-cells = <0>;
2727 reg = <0 0x00b9c000 0 0x4000>;
2747 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
2752 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
2756 #size-cells = <0>;
2764 reg = <0 0x0c271000 0 0x1000>,
2765 <0 0x0c222000 0 0x1000>;
2779 reg = <0 0x0c272000 0 0x1000>,
2780 <0 0x0c223000 0 0x1000>;
2794 reg = <0 0x0c273000 0 0x1000>,
2795 <0 0x0c224000 0 0x1000>;
2809 reg = <0 0x0c274000 0 0x1000>,
2810 <0 0x0c225000 0 0x1000>;
2825 reg = <0 0x00fd3000 0 0x154>;
2826 #phy-cells = <0>;
2838 reg = <0 0x00fd5000 0 0x4000>;
2865 #size-cells = <0>;
2867 port@0 {
2868 reg = <0>;
2895 reg = <0 0x00fd9000 0 0x154>;
2896 #phy-cells = <0>;
2908 reg = <0 0x00fda000 0 0x4000>;
2935 #size-cells = <0>;
2937 port@0 {
2938 reg = <0>;
2965 reg = <0 0x00fde000 0 0x154>;
2966 #phy-cells = <0>;
2978 reg = <0 0x00fdf000 0 0x4000>;
3005 #size-cells = <0>;
3007 port@0 {
3008 reg = <0>;
3034 reg = <0 0x01500000 0 0x14400>;
3043 reg = <0 0x01600000 0 0x6600>;
3052 reg = <0 0x01680000 0 0x1c080>;
3061 reg = <0 0x016c0000 0 0xd080>;
3070 reg = <0 0x016d0000 0 0x7000>;
3079 reg = <0 0x016e0000 0 0x14400>;
3088 reg = <0 0x01700000 0 0x1c400>;
3097 reg = <0 0x01740000 0 0x9080>;
3106 reg = <0 0x01750000 0 0x8800>;
3115 reg = <0 0x01760000 0 0x7080>;
3124 reg = <0 0x01770000 0 0xf080>;
3133 reg = <0 0x01780000 0 0x5B800>;
3143 reg = <0x0 0x01bd0000 0x0 0x3000>,
3144 <0x0 0x78000000 0x0 0xf20>,
3145 <0x0 0x78000f40 0x0 0xa8>,
3146 <0x0 0x78001000 0x0 0x1000>,
3147 <0x0 0x78100000 0x0 0x100000>,
3148 <0x0 0x01bd3000 0x0 0x1000>;
3157 ranges = <0x01000000 0x0 0x00000000 0x0 0x78200000 0x0 0x100000>,
3158 <0x02000000 0x0 0x78300000 0x0 0x78300000 0x0 0x3d00000>,
3159 <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>;
3160 bus-range = <0x00 0xff>;
3187 interrupt-map-mask = <0 0 0 0x7>;
3188 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
3189 <0 0 0 2 &intc 0 0 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
3190 <0 0 0 3 &intc 0 0 GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
3191 <0 0 0 4 &intc 0 0 GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
3228 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555
3229 0x5555 0x5555 0x5555 0x5555>;
3230 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>;
3313 reg = <0 0x01be0000 0 0x10000>;
3338 #clock-cells = <0>;
3341 #phy-cells = <0>;
3349 reg = <0 0x01bf8000 0 0x3000>,
3350 <0 0x70000000 0 0xf20>,
3351 <0 0x70000f40 0 0xa8>,
3352 <0 0x70001000 0 0x1000>,
3353 <0 0x70100000 0 0x100000>,
3354 <0 0x01bfb000 0 0x1000>;
3363 ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>,
3364 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>;
3365 bus-range = <0x00 0xff>;
3372 msi-map = <0x0 &gic_its 0xe0000 0x10000>;
3394 interrupt-map-mask = <0 0 0 0x7>;
3395 interrupt-map = <0 0 0 1 &intc 0 0 0 843 IRQ_TYPE_LEVEL_HIGH>,
3396 <0 0 0 2 &intc 0 0 0 844 IRQ_TYPE_LEVEL_HIGH>,
3397 <0 0 0 3 &intc 0 0 0 845 IRQ_TYPE_LEVEL_HIGH>,
3398 <0 0 0 4 &intc 0 0 0 772 IRQ_TYPE_LEVEL_HIGH>;
3436 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>;
3437 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>;
3444 reg = <0 0x01bfc000 0 0x2000>,
3445 <0 0x01bfe000 0 0x2000>;
3470 qcom,4ln-config-sel = <&tcsr 0x1a000 0>;
3472 #clock-cells = <0>;
3475 #phy-cells = <0>;
3483 reg = <0 0x01c00000 0 0x3000>,
3484 <0 0x7e000000 0 0xf1d>,
3485 <0 0x7e000f40 0 0xa8>,
3486 <0 0x7e001000 0 0x1000>,
3487 <0 0x7e100000 0 0x100000>,
3488 <0 0x01c03000 0 0x1000>;
3497 ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>,
3498 <0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>;
3499 bus-range = <0x00 0xff>;
3526 interrupt-map-mask = <0 0 0 0x7>;
3527 interrupt-map = <0 0 0 1 &intc 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>,
3528 <0 0 0 2 &intc 0 0 0 71 IRQ_TYPE_LEVEL_HIGH>,
3529 <0 0 0 3 &intc 0 0 0 72 IRQ_TYPE_LEVEL_HIGH>,
3530 <0 0 0 4 &intc 0 0 0 73 IRQ_TYPE_LEVEL_HIGH>;
3568 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
3575 reg = <0 0x01c06000 0 0x2000>;
3600 #clock-cells = <0>;
3603 #phy-cells = <0>;
3611 reg = <0 0x01c08000 0 0x3000>,
3612 <0 0x7c000000 0 0xf1d>,
3613 <0 0x7c000f40 0 0xa8>,
3614 <0 0x7c001000 0 0x1000>,
3615 <0 0x7c100000 0 0x100000>,
3616 <0 0x01c0b000 0 0x1000>;
3625 ranges = <0x01000000 0x0 0x00000000 0x0 0x7c200000 0x0 0x100000>,
3626 <0x02000000 0x0 0x7c300000 0x0 0x7c300000 0x0 0x1d00000>;
3627 bus-range = <0x00 0xff>;
3634 msi-map = <0x0 &gic_its 0xc0000 0x10000>;
3656 interrupt-map-mask = <0 0 0 0x7>;
3657 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
3658 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
3659 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
3660 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
3698 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
3702 pcie4_port0: pcie@0 {
3704 reg = <0x0 0x0 0x0 0x0 0x0>;
3705 bus-range = <0x01 0xff>;
3715 reg = <0 0x01c0e000 0 0x2000>;
3740 #clock-cells = <0>;
3743 #phy-cells = <0>;
3750 reg = <0 0x01f40000 0 0x20000>;
3756 reg = <0 0x01fc0000 0 0x30000>;
3764 reg = <0x0 0x03d00000 0x0 0x40000>,
3765 <0x0 0x03d9e000 0x0 0x1000>,
3766 <0x0 0x03d61000 0x0 0x800>;
3774 iommus = <&adreno_smmu 0 0x0>,
3775 <&adreno_smmu 1 0x0>;
3782 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
3798 qcom,opp-acd-level = <0xa82a5ffd>;
3805 qcom,opp-acd-level = <0xa82a5ffd>;
3812 qcom,opp-acd-level = <0xa82a5ffd>;
3819 qcom,opp-acd-level = <0xa82b5ffd>;
3826 qcom,opp-acd-level = <0xa82b5ffd>;
3833 qcom,opp-acd-level = <0xa82c5ffd>;
3840 qcom,opp-acd-level = <0x882e5ffd>;
3847 qcom,opp-acd-level = <0x882e5ffd>;
3854 qcom,opp-acd-level = <0xc0285ffd>;
3861 qcom,opp-acd-level = <0xc0285ffd>;
3868 qcom,opp-acd-level = <0xc02b5ffd>;
3875 reg = <0x0 0x03d6a000 0x0 0x35000>,
3876 <0x0 0x03d50000 0x0 0x10000>,
3877 <0x0 0x0b280000 0x0 0x10000>;
3904 iommus = <&adreno_smmu 5 0x0>;
3927 reg = <0 0x03d90000 0 0xa000>;
3939 reg = <0x0 0x03da0000 0x0 0x40000>;
3982 reg = <0 0x26400000 0 0x311200>;
3991 reg = <0 0x320C0000 0 0xe080>;
4000 reg = <0x0 0x06800000 0x0 0x10000>;
4003 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
4029 qcom,smem-states = <&smp2p_adsp_out 0>;
4050 #size-cells = <0>;
4055 iommus = <&apps_smmu 0x1003 0x80>,
4056 <&apps_smmu 0x1063 0x0>;
4063 iommus = <&apps_smmu 0x1004 0x80>,
4064 <&apps_smmu 0x1064 0x0>;
4071 iommus = <&apps_smmu 0x1005 0x80>,
4072 <&apps_smmu 0x1065 0x0>;
4079 iommus = <&apps_smmu 0x1006 0x80>,
4080 <&apps_smmu 0x1066 0x0>;
4087 iommus = <&apps_smmu 0x1007 0x80>,
4088 <&apps_smmu 0x1067 0x0>;
4099 #size-cells = <0>;
4104 #sound-dai-cells = <0>;
4115 iommus = <&apps_smmu 0x1001 0x80>,
4116 <&apps_smmu 0x1061 0x0>;
4137 reg = <0 0x06aa0000 0 0x1000>;
4147 #clock-cells = <0>;
4155 reg = <0 0x06ab0000 0 0x10000>;
4161 pinctrl-0 = <&wsa2_swr_active>;
4169 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x3…
4170 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
4171 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4172 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4173 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4174 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
4175 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
4176 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4177 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4180 #size-cells = <0>;
4187 reg = <0 0x06ac0000 0 0x1000>;
4197 #clock-cells = <0>;
4204 reg = <0 0x06ad0000 0 0x10000>;
4210 pinctrl-0 = <&rx_swr_active>;
4218 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4219 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4220 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4221 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4222 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4223 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4224 …qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff…
4225 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4226 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4229 #size-cells = <0>;
4236 reg = <0 0x06ae0000 0 0x1000>;
4246 #clock-cells = <0>;
4253 reg = <0 0x06b00000 0 0x1000>;
4263 #clock-cells = <0>;
4271 reg = <0 0x06b10000 0 0x10000>;
4277 pinctrl-0 = <&wsa_swr_active>;
4285 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x3…
4286 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
4287 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4288 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4289 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4290 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
4291 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
4292 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4293 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4296 #size-cells = <0>;
4303 reg = <0 0x06b6c000 0 0x1000>;
4310 reg = <0 0x06d30000 0 0x10000>;
4320 pinctrl-0 = <&tx_swr_active>;
4326 qcom,ports-sinterval-low = /bits/ 8 <0x00 0x01 0x03 0x03 0x00>;
4327 qcom,ports-offset1 = /bits/ 8 <0x00 0x01 0x02 0x00 0x00>;
4328 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00 0xff>;
4329 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
4330 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
4331 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
4332 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
4333 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
4334 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x00 0x01 0xff>;
4337 #size-cells = <0>;
4344 reg = <0 0x06d44000 0 0x1000>;
4352 #clock-cells = <0>;
4359 reg = <0 0x06e80000 0 0x20000>,
4360 <0 0x07250000 0 0x10000>;
4368 gpio-ranges = <&lpass_tlmm 0 0 23>;
4477 reg = <0 0x06ea0000 0 0x12000>;
4484 reg = <0 0x07e40000 0 0xe080>;
4493 reg = <0 0x07400000 0 0x19080>;
4502 reg = <0 0x07430000 0 0x3A200>;
4511 reg = <0 0x08804000 0 0x1000>;
4521 iommus = <&apps_smmu 0x520 0>;
4522 qcom,dll-config = <0x0007642c>;
4523 qcom,ddr-config = <0x80040868>;
4564 reg = <0 0x08844000 0 0x1000>;
4574 iommus = <&apps_smmu 0x160 0>;
4575 qcom,dll-config = <0x0007642c>;
4576 qcom,ddr-config = <0x80040868>;
4618 reg = <0 0x088e0000 0 0x154>;
4619 #phy-cells = <0>;
4632 reg = <0 0x088e1000 0 0x154>;
4633 #phy-cells = <0>;
4646 reg = <0 0x088e2000 0 0x154>;
4647 #phy-cells = <0>;
4659 reg = <0 0x088e3000 0 0x2000>;
4677 #clock-cells = <0>;
4680 #phy-cells = <0>;
4687 reg = <0 0x088e5000 0 0x2000>;
4705 #clock-cells = <0>;
4708 #phy-cells = <0>;
4715 reg = <0 0x0a0f8800 0 0x400>;
4772 reg = <0 0x0a000000 0 0xcd00>;
4776 iommus = <&apps_smmu 0x14a0 0x0>;
4793 #size-cells = <0>;
4795 port@0 {
4796 reg = <0>;
4815 reg = <0 0x0a2f8800 0 0x400>;
4868 reg = <0 0x0a200000 0 0xcd00>;
4870 iommus = <&apps_smmu 0x14e0 0x0>;
4881 #size-cells = <0>;
4883 port@0 {
4884 reg = <0>;
4895 reg = <0 0x0a4f8800 0 0x400>;
4959 reg = <0 0x0a400000 0 0xcd00>;
4963 iommus = <&apps_smmu 0x1400 0x0>;
4967 phy-names = "usb2-0", "usb3-0",
4983 reg = <0 0x0a6f8800 0 0x400>;
5033 reg = <0 0x0a600000 0 0xcd00>;
5037 iommus = <&apps_smmu 0x1420 0x0>;
5054 #size-cells = <0>;
5056 port@0 {
5057 reg = <0>;
5076 reg = <0 0x0a8f8800 0 0x400>;
5133 reg = <0 0x0a800000 0 0xcd00>;
5137 iommus = <&apps_smmu 0x1460 0x0>;
5154 #size-cells = <0>;
5156 port@0 {
5157 reg = <0>;
5176 reg = <0 0x0ae00000 0 0x1000>;
5199 iommus = <&apps_smmu 0x1c00 0x2>;
5212 reg = <0 0x0ae01000 0 0x8f000>,
5213 <0 0x0aeb0000 0 0x2008>;
5217 interrupts-extended = <&mdss 0>;
5236 #size-cells = <0>;
5238 port@0 {
5239 reg = <0>;
5303 reg = <0 0x0ae90000 0 0x200>,
5304 <0 0x0ae90200 0 0x200>,
5305 <0 0x0ae90400 0 0x600>,
5306 <0 0x0ae91000 0 0x400>,
5307 <0 0x0ae91400 0 0x400>;
5334 #sound-dai-cells = <0>;
5340 #size-cells = <0>;
5342 port@0 {
5343 reg = <0>;
5386 reg = <0 0x0ae98000 0 0x200>,
5387 <0 0x0ae98200 0 0x200>,
5388 <0 0x0ae98400 0 0x600>,
5389 <0 0x0ae99000 0 0x400>,
5390 <0 0x0ae99400 0 0x400>;
5417 #sound-dai-cells = <0>;
5423 #size-cells = <0>;
5425 port@0 {
5426 reg = <0>;
5469 reg = <0 0x0ae9a000 0 0x200>,
5470 <0 0x0ae9a200 0 0x200>,
5471 <0 0x0ae9a400 0 0x600>,
5472 <0 0x0ae9b000 0 0x400>,
5473 <0 0x0ae9b400 0 0x400>;
5500 #sound-dai-cells = <0>;
5506 #size-cells = <0>;
5508 port@0 {
5509 reg = <0>;
5551 reg = <0 0x0aea0000 0 0x200>,
5552 <0 0x0aea0200 0 0x200>,
5553 <0 0x0aea0400 0 0x600>,
5554 <0 0x0aea1000 0 0x400>,
5555 <0 0x0aea1400 0 0x400>;
5572 assigned-clock-parents = <&mdss_dp3_phy 0>,
5582 #sound-dai-cells = <0>;
5588 #size-cells = <0>;
5590 port@0 {
5591 reg = <0>;
5632 reg = <0 0x0aec2a00 0 0x19c>,
5633 <0 0x0aec2200 0 0xec>,
5634 <0 0x0aec2600 0 0xec>,
5635 <0 0x0aec2000 0 0x1c8>;
5645 #phy-cells = <0>;
5652 reg = <0 0x0aec5a00 0 0x19c>,
5653 <0 0x0aec5200 0 0xec>,
5654 <0 0x0aec5600 0 0xec>,
5655 <0 0x0aec5000 0 0x1c8>;
5665 #phy-cells = <0>;
5672 reg = <0 0x0af00000 0 0x20000>;
5677 <0>, /* dsi0 */
5678 <0>,
5679 <0>, /* dsi1 */
5680 <0>,
5687 <&mdss_dp3_phy 0>, /* dp3 */
5698 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
5700 qcom,pdc-ranges = <0 480 42>, <42 251 5>,
5710 reg = <0 0x0c300000 0 0x400>;
5716 #clock-cells = <0>;
5721 reg = <0 0x0c3f0000 0 0x400>;
5726 reg = <0 0x0c400000 0 0x3000>,
5727 <0 0x0c500000 0 0x400000>,
5728 <0 0x0c440000 0 0x80000>;
5731 qcom,ee = <0>;
5732 qcom,channel = <0>;
5739 reg = <0 0x0c42d000 0 0x4000>,
5740 <0 0x0c4c0000 0 0x10000>;
5749 #size-cells = <0>;
5753 reg = <0 0x0c432000 0 0x4000>,
5754 <0 0x0c4d0000 0 0x10000>;
5763 #size-cells = <0>;
5769 reg = <0 0x0f100000 0 0xf00000>;
5779 gpio-ranges = <&tlmm 0 0 239>;
6451 reg = <0x0 0x10002000 0x0 0x1000>,
6452 <0x0 0x16280000 0x0 0x180000>;
6470 reg = <0x0 0x10003000 0x0 0x1000>;
6490 reg = <0x0 0x10004000 0x0 0x1000>;
6497 #size-cells = <0>;
6499 port@0 {
6500 reg = <0>;
6527 reg = <0x0 0x1000f000 0x0 0x1000>;
6546 reg = <0x0 0x10041000 0x0 0x1000>;
6553 #size-cells = <0>;
6583 reg = <0x0 0x10042000 0x0 0x1000>;
6590 #size-cells = <0>;
6628 reg = <0x0 0x10045000 0x0 0x1000>;
6635 #size-cells = <0>;
6637 port@0 {
6638 reg = <0>;
6665 reg = <0x0 0x10800000 0x0 0x1000>;
6684 reg = <0x0 0x1082c000 0x0 0x1000>;
6703 reg = <0x0 0x10841000 0x0 0x1000>;
6722 reg = <0x0 0x10844000 0x0 0x1000>;
6741 reg = <0x0 0x10846000 0x0 0x1000>;
6765 reg = <0x0 0x1098b000 0x0 0x1000>;
6773 reg = <0x0 0x109d0000 0x0 0x1000>;
6793 reg = <0x0 0x10ac0000 0x0 0x1000>;
6813 reg = <0x0 0x10ac1000 0x0 0x1000>;
6832 reg = <0x0 0x10ac4000 0x0 0x1000>;
6839 #size-cells = <0>;
6869 reg = <0x0 0x10ac5000 0x0 0x1000>;
6893 reg = <0x0 0x10b04000 0x0 0x1000>;
6900 #size-cells = <0>;
6938 reg = <0x0 0x10b05000 0x0 0x1000>;
6962 reg = <0x0 0x10b06000 0x0 0x1000>;
6986 reg = <0x0 0x10b08000 0x0 0x1000>;
6993 #size-cells = <0>;
6995 port@0 {
6996 reg = <0>;
7047 reg = <0x0 0x10b09000 0x0 0x1000>;
7066 reg = <0x0 0x10b0a000 0x0 0x1000>;
7085 reg = <0x0 0x10b0b000 0x0 0x1000>;
7104 reg = <0x0 0x10b0c000 0x0 0x1000>;
7123 reg = <0x0 0x10b0d000 0x0 0x1000>;
7142 reg = <0x0 0x10b20000 0x0 0x1000>;
7162 reg = <0x0 0x10b23000 0x0 0x1000>;
7187 reg = <0x0 0x10b24000 0x0 0x1000>;
7212 reg = <0x0 0x10c08000 0x0 0x1000>;
7231 reg = <0x0 0x10c0b000 0x0 0x1000>;
7238 #size-cells = <0>;
7260 reg = <0x0 0x10c28000 0x0 0x1000>;
7279 reg = <0x0 0x10c29000 0x0 0x1000>;
7298 reg = <0x0 0x10c2b000 0x0 0x1000>;
7305 #size-cells = <0>;
7367 reg = <0x0 0x10c2c000 0x0 0x1000>;
7374 #size-cells = <0>;
7376 port@0 {
7377 reg = <0>;
7412 reg = <0x0 0x10c38000 0x0 0x1000>;
7431 reg = <0x0 0x10c39000 0x0 0x1000>;
7450 reg = <0x0 0x10c3c000 0x0 0x1000>;
7457 #size-cells = <0>;
7503 reg = <0x0 0x10c3d000 0x0 0x1000>;
7527 reg = <0x0 0x10cc1000 0x0 0x1000>;
7549 reg = <0x0 0x10cc4000 0x0 0x1000>;
7556 #size-cells = <0>;
7578 reg = <0x0 0x10cc5000 0x0 0x1000>;
7602 reg = <0x0 0x10d04000 0x0 0x1000>;
7609 #size-cells = <0>;
7631 reg = <0x0 0x10d08000 0x0 0x1000>;
7650 reg = <0x0 0x10d09000 0x0 0x1000>;
7669 reg = <0x0 0x10d0a000 0x0 0x1000>;
7688 reg = <0x0 0x10d0b000 0x0 0x1000>;
7707 reg = <0x0 0x10d0c000 0x0 0x1000>;
7726 reg = <0x0 0x10d0d000 0x0 0x1000>;
7745 reg = <0x0 0x10d0e000 0x0 0x1000>;
7764 reg = <0x0 0x10d0f000 0x0 0x1000>;
7783 reg = <0x0 0x10d12000 0x0 0x1000>;
7790 #size-cells = <0>;
7792 port@0 {
7793 reg = <0>;
7868 reg = <0x0 0x10d13000 0x0 0x1000>;
7892 reg = <0 0x15000000 0 0x100000>;
8000 reg = <0 0x15400000 0 0x80000>;
8014 reg = <0 0x17000000 0 0x10000>, /* GICD */
8015 <0 0x17080000 0 0x300000>; /* GICR * 12 */
8023 redistributor-stride = <0x0 0x40000>;
8031 reg = <0 0x17040000 0 0x40000>;
8040 reg = <0 0x17430000 0 0x10000>, <0 0x18830000 0 0x10000>;
8047 reg = <0 0x17500000 0 0x10000>,
8048 <0 0x17510000 0 0x10000>,
8049 <0 0x17520000 0 0x10000>;
8050 reg-names = "drv-0", "drv-1", "drv-2";
8055 qcom,tcs-offset = <0xd00>;
8058 <WAKE_TCS 2>, <CONTROL_TCS 0>;
8151 reg = <0 0x17800000 0 0x1000>;
8155 ranges = <0 0 0 0 0x20000000>;
8158 reg = <0 0x17801000 0x1000>,
8159 <0 0x17802000 0x1000>;
8164 frame-number = <0>;
8168 reg = <0 0x17803000 0x1000>;
8178 reg = <0 0x17805000 0x1000>;
8188 reg = <0 0x17807000 0x1000>;
8198 reg = <0 0x17809000 0x1000>;
8208 reg = <0 0x1780b000 0x1000>;
8218 reg = <0 0x1780d000 0x1000>;
8230 reg = <0x0 0x18b4e000 0x0 0x400>;
8234 ranges = <0x0 0x0 0x18b4e000 0x400>;
8236 cpu_scp_lpri0: scp-sram-section@0 {
8238 reg = <0x0 0x200>;
8243 reg = <0x200 0x200>;
8249 reg = <0 0x1c840000 0 0x1000>,
8250 <0 0x1c850000 0 0x1000>;
8251 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
8256 reg = <0 0x24091000 0 0x1000>;
8268 opp-0 {
8313 reg = <0 0x240b3400 0 0x600>;
8326 reg = <0 0x240b5400 0 0x600>;
8338 opp-0 {
8367 reg = <0 0x240b6400 0 0x600>;
8379 reg = <0 0x25000000 0 0x200000>,
8380 <0 0x25200000 0 0x200000>,
8381 <0 0x25400000 0 0x200000>,
8382 <0 0x25600000 0 0x200000>,
8383 <0 0x25800000 0 0x200000>,
8384 <0 0x25a00000 0 0x200000>,
8385 <0 0x25c00000 0 0x200000>,
8386 <0 0x25e00000 0 0x200000>,
8387 <0 0x26000000 0 0x200000>,
8388 <0 0x26200000 0 0x200000>;
8404 reg = <0x0 0x32300000 0x0 0x10000>;
8407 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
8435 qcom,smem-states = <&smp2p_cdsp_out 0>;
8456 #size-cells = <0>;
8461 iommus = <&apps_smmu 0x0c01 0x20>;
8468 iommus = <&apps_smmu 0x0c02 0x20>;
8475 iommus = <&apps_smmu 0x0c03 0x20>;
8482 iommus = <&apps_smmu 0x0c04 0x20>;
8489 iommus = <&apps_smmu 0x0c05 0x20>;
8496 iommus = <&apps_smmu 0x0c06 0x20>;
8503 iommus = <&apps_smmu 0x0c07 0x20>;
8510 iommus = <&apps_smmu 0x0c08 0x20>;
8519 iommus = <&apps_smmu 0x0c0c 0x20>;
8526 iommus = <&apps_smmu 0x0c0d 0x20>;
8533 iommus = <&apps_smmu 0x0c0e 0x20>;
8540 iommus = <&apps_smmu 0x0c0f 0x20>;
8559 thermal-sensors = <&tsens0 0>;
8576 cpu0-0-top-thermal {
8588 cpu0-0-btm-thermal {
8708 hysteresis = <0>;
8733 thermal-sensors = <&tsens1 0>;
8750 cpu1-0-top-thermal {
8762 cpu1-0-btm-thermal {
8871 thermal-sensors = <&tsens2 0>;
8888 cpu2-0-top-thermal {
8900 cpu2-0-btm-thermal {
9009 thermal-sensors = <&tsens3 0>;
9098 gpuss-0-thermal {