Lines Matching +full:dload +full:- +full:mode
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
7 #include <dt-bindings/clock/qcom,qcs615-camcc.h>
8 #include <dt-bindings/clock/qcom,qcs615-dispcc.h>
9 #include <dt-bindings/clock/qcom,qcs615-gcc.h>
10 #include <dt-bindings/clock/qcom,qcs615-gpucc.h>
11 #include <dt-bindings/clock/qcom,qcs615-videocc.h>
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/interconnect/qcom,icc.h>
15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
16 #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/power/qcom-rpmpd.h>
19 #include <dt-bindings/power/qcom,rpmhpd.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
23 interrupt-parent = <&intc>;
24 #address-cells = <2>;
25 #size-cells = <2>;
28 #address-cells = <2>;
29 #size-cells = <0>;
33 compatible = "arm,cortex-a55";
35 enable-method = "psci";
36 power-domains = <&cpu_pd0>;
37 power-domain-names = "psci";
38 capacity-dmips-mhz = <1024>;
39 dynamic-power-coefficient = <100>;
40 next-level-cache = <&l2_0>;
42 qcom,freq-domain = <&cpufreq_hw 0>;
43 #cooling-cells = <2>;
44 operating-points-v2 = <&cpu0_opp_table>;
49 l2_0: l2-cache {
51 cache-level = <2>;
52 cache-unified;
53 next-level-cache = <&l3_0>;
59 compatible = "arm,cortex-a55";
61 enable-method = "psci";
62 power-domains = <&cpu_pd1>;
63 power-domain-names = "psci";
64 capacity-dmips-mhz = <1024>;
65 dynamic-power-coefficient = <100>;
66 next-level-cache = <&l2_100>;
68 qcom,freq-domain = <&cpufreq_hw 0>;
69 operating-points-v2 = <&cpu0_opp_table>;
74 l2_100: l2-cache {
76 cache-level = <2>;
77 cache-unified;
78 next-level-cache = <&l3_0>;
84 compatible = "arm,cortex-a55";
86 enable-method = "psci";
87 power-domains = <&cpu_pd2>;
88 power-domain-names = "psci";
89 capacity-dmips-mhz = <1024>;
90 dynamic-power-coefficient = <100>;
91 next-level-cache = <&l2_200>;
93 qcom,freq-domain = <&cpufreq_hw 0>;
94 operating-points-v2 = <&cpu0_opp_table>;
99 l2_200: l2-cache {
101 cache-level = <2>;
102 cache-unified;
103 next-level-cache = <&l3_0>;
109 compatible = "arm,cortex-a55";
111 enable-method = "psci";
112 power-domains = <&cpu_pd3>;
113 power-domain-names = "psci";
114 capacity-dmips-mhz = <1024>;
115 dynamic-power-coefficient = <100>;
116 next-level-cache = <&l2_300>;
118 qcom,freq-domain = <&cpufreq_hw 0>;
119 operating-points-v2 = <&cpu0_opp_table>;
124 l2_300: l2-cache {
126 cache-level = <2>;
127 cache-unified;
128 next-level-cache = <&l3_0>;
134 compatible = "arm,cortex-a55";
136 enable-method = "psci";
137 power-domains = <&cpu_pd4>;
138 power-domain-names = "psci";
139 capacity-dmips-mhz = <1024>;
140 dynamic-power-coefficient = <100>;
141 next-level-cache = <&l2_400>;
143 qcom,freq-domain = <&cpufreq_hw 0>;
144 operating-points-v2 = <&cpu0_opp_table>;
149 l2_400: l2-cache {
151 cache-level = <2>;
152 cache-unified;
153 next-level-cache = <&l3_0>;
159 compatible = "arm,cortex-a55";
161 enable-method = "psci";
162 power-domains = <&cpu_pd5>;
163 power-domain-names = "psci";
164 capacity-dmips-mhz = <1024>;
165 dynamic-power-coefficient = <100>;
166 next-level-cache = <&l2_500>;
168 qcom,freq-domain = <&cpufreq_hw 0>;
169 operating-points-v2 = <&cpu0_opp_table>;
174 l2_500: l2-cache {
176 cache-level = <2>;
177 cache-unified;
178 next-level-cache = <&l3_0>;
184 compatible = "arm,cortex-a76";
186 enable-method = "psci";
187 power-domains = <&cpu_pd6>;
188 power-domain-names = "psci";
189 capacity-dmips-mhz = <1740>;
190 dynamic-power-coefficient = <404>;
191 next-level-cache = <&l2_600>;
193 qcom,freq-domain = <&cpufreq_hw 1>;
194 #cooling-cells = <2>;
195 operating-points-v2 = <&cpu6_opp_table>;
200 l2_600: l2-cache {
202 cache-level = <2>;
203 cache-unified;
204 next-level-cache = <&l3_0>;
210 compatible = "arm,cortex-a76";
212 enable-method = "psci";
213 power-domains = <&cpu_pd7>;
214 power-domain-names = "psci";
215 capacity-dmips-mhz = <1740>;
216 dynamic-power-coefficient = <404>;
217 next-level-cache = <&l2_700>;
219 qcom,freq-domain = <&cpufreq_hw 1>;
220 operating-points-v2 = <&cpu6_opp_table>;
225 l2_700: l2-cache {
227 cache-level = <2>;
228 cache-unified;
229 next-level-cache = <&l3_0>;
233 cpu-map {
269 l3_0: l3-cache {
271 cache-level = <3>;
272 cache-unified;
276 cpu0_opp_table: opp-table-cpu0 {
277 compatible = "operating-points-v2";
278 opp-shared;
280 opp-300000000 {
281 opp-hz = /bits/ 64 <300000000>;
282 opp-peak-kBps = <(300000 * 4) (300000 * 16)>;
285 opp-576000000 {
286 opp-hz = /bits/ 64 <576000000>;
287 opp-peak-kBps = <(300000 * 4) (576000 * 16)>;
290 opp-748800000 {
291 opp-hz = /bits/ 64 <748800000>;
292 opp-peak-kBps = <(300000 * 4) (576000 * 16)>;
295 opp-998400000 {
296 opp-hz = /bits/ 64 <998400000>;
297 opp-peak-kBps = <(451000 * 4) (806400 * 16)>;
300 opp-1209600000 {
301 opp-hz = /bits/ 64 <1209600000>;
302 opp-peak-kBps = <(547000 * 4) (1017600 * 16)>;
305 opp-1363200000 {
306 opp-hz = /bits/ 64 <1363200000>;
307 opp-peak-kBps = <(768000 * 4) (1209600 * 16)>;
310 opp-1516800000 {
311 opp-hz = /bits/ 64 <1516800000>;
312 opp-peak-kBps = <(768000 * 4) (1209600 * 16)>;
315 opp-1593600000 {
316 opp-hz = /bits/ 64 <1593600000>;
317 opp-peak-kBps = <(1017000 * 4) (1363200 * 16)>;
321 cpu6_opp_table: opp-table-cpu6 {
322 compatible = "operating-points-v2";
323 opp-shared;
325 opp-300000000 {
326 opp-hz = /bits/ 64 <300000000>;
327 opp-peak-kBps = <(451000 * 4) (300000 * 16)>;
330 opp-652800000 {
331 opp-hz = /bits/ 64 <652800000>;
332 opp-peak-kBps = <(451000 * 4) (576000 * 16)>;
335 opp-768000000 {
336 opp-hz = /bits/ 64 <768000000>;
337 opp-peak-kBps = <(451000 * 4) (576000 * 16)>;
340 opp-979200000 {
341 opp-hz = /bits/ 64 <979200000>;
342 opp-peak-kBps = <(547000 * 4) (806400 * 16)>;
345 opp-1017600000 {
346 opp-hz = /bits/ 64 <1017600000>;
347 opp-peak-kBps = <(547000 * 4) (806400 * 16)>;
350 opp-1094400000 {
351 opp-hz = /bits/ 64 <109440000>;
352 opp-peak-kBps = <(1017600 * 4) (940800 * 16)>;
355 opp-1209600000 {
356 opp-hz = /bits/ 64 <1209600000>;
357 opp-peak-kBps = <(1017600 * 4) (1017600 * 16)>;
360 opp-1363200000 {
361 opp-hz = /bits/ 64 <1363200000>;
362 opp-peak-kBps = <(1555000 * 4) (1209600 * 16)>;
365 opp-1516800000 {
366 opp-hz = /bits/ 64 <1516800000>;
367 opp-peak-kBps = <(1555000 * 4) (1209600 * 16)>;
370 opp-1708800000 {
371 opp-hz = /bits/ 64 <1708800000>;
372 opp-peak-kBps = <(1555000 * 4) (1363200 * 16)>;
375 opp-1900800000 {
376 opp-hz = /bits/ 64 <1900800000>;
377 opp-peak-kBps = <(1555000 * 4) (1363200 * 16)>;
381 dummy_eud: dummy-sink {
382 compatible = "arm,coresight-dummy-sink";
384 in-ports {
387 remote-endpoint = <&replicator_swao_out1>;
393 idle-states {
394 entry-method = "psci";
396 little_cpu_sleep_0: cpu-sleep-0-0 {
397 compatible = "arm,idle-state";
398 idle-state-name = "silver-power-collapse";
399 arm,psci-suspend-param = <0x40000003>;
400 entry-latency-us = <549>;
401 exit-latency-us = <901>;
402 min-residency-us = <1774>;
403 local-timer-stop;
406 little_cpu_sleep_1: cpu-sleep-0-1 {
407 compatible = "arm,idle-state";
408 idle-state-name = "silver-rail-power-collapse";
409 arm,psci-suspend-param = <0x40000004>;
410 entry-latency-us = <702>;
411 exit-latency-us = <915>;
412 min-residency-us = <4001>;
413 local-timer-stop;
416 big_cpu_sleep_0: cpu-sleep-1-0 {
417 compatible = "arm,idle-state";
418 idle-state-name = "gold-power-collapse";
419 arm,psci-suspend-param = <0x40000003>;
420 entry-latency-us = <523>;
421 exit-latency-us = <1244>;
422 min-residency-us = <2207>;
423 local-timer-stop;
426 big_cpu_sleep_1: cpu-sleep-1-1 {
427 compatible = "arm,idle-state";
428 idle-state-name = "gold-rail-power-collapse";
429 arm,psci-suspend-param = <0x40000004>;
430 entry-latency-us = <526>;
431 exit-latency-us = <1854>;
432 min-residency-us = <5555>;
433 local-timer-stop;
437 domain-idle-states {
438 cluster_sleep_0: cluster-sleep-0 {
439 compatible = "domain-idle-state";
440 arm,psci-suspend-param = <0x41000044>;
441 entry-latency-us = <2752>;
442 exit-latency-us = <3048>;
443 min-residency-us = <6118>;
446 cluster_sleep_1: cluster-sleep-1 {
447 compatible = "domain-idle-state";
448 arm,psci-suspend-param = <0x41001344>;
449 entry-latency-us = <3263>;
450 exit-latency-us = <4562>;
451 min-residency-us = <8467>;
454 cluster_sleep_2: cluster-sleep-2 {
455 compatible = "domain-idle-state";
456 arm,psci-suspend-param = <0x4100b344>;
457 entry-latency-us = <3638>;
458 exit-latency-us = <6562>;
459 min-residency-us = <9826>;
471 compatible = "qcom,scm-qcs615", "qcom,scm";
472 qcom,dload-mode = <&tcsr 0x13000>;
476 camnoc_virt: interconnect-0 {
477 compatible = "qcom,qcs615-camnoc-virt";
478 #interconnect-cells = <2>;
479 qcom,bcm-voters = <&apps_bcm_voter>;
482 ipa_virt: interconnect-1 {
483 compatible = "qcom,qcs615-ipa-virt";
484 #interconnect-cells = <2>;
485 qcom,bcm-voters = <&apps_bcm_voter>;
488 mc_virt: interconnect-2 {
489 compatible = "qcom,qcs615-mc-virt";
490 #interconnect-cells = <2>;
491 qcom,bcm-voters = <&apps_bcm_voter>;
494 smp2p-adsp {
501 qcom,local-pid = <0>;
502 qcom,remote-pid = <2>;
504 adsp_smp2p_out: master-kernel {
505 qcom,entry-name = "master-kernel";
506 #qcom,smem-state-cells = <1>;
509 adsp_smp2p_in: slave-kernel {
510 qcom,entry-name = "slave-kernel";
511 interrupt-controller;
512 #interrupt-cells = <2>;
516 smp2p-cdsp {
522 qcom,local-pid = <0>;
523 qcom,remote-pid = <5>;
525 cdsp_smp2p_out: master-kernel {
526 qcom,entry-name = "master-kernel";
527 #qcom,smem-state-cells = <1>;
530 cdsp_smp2p_in: slave-kernel {
531 qcom,entry-name = "slave-kernel";
532 interrupt-controller;
533 #interrupt-cells = <2>;
538 qup_opp_table: opp-table-qup {
539 compatible = "operating-points-v2";
540 opp-shared;
542 opp-75000000 {
543 opp-hz = /bits/ 64 <75000000>;
544 required-opps = <&rpmhpd_opp_low_svs>;
547 opp-100000000 {
548 opp-hz = /bits/ 64 <100000000>;
549 required-opps = <&rpmhpd_opp_svs>;
552 opp-128000000 {
553 opp-hz = /bits/ 64 <128000000>;
554 required-opps = <&rpmhpd_opp_nom>;
559 compatible = "arm,psci-1.0";
562 cpu_pd0: power-domain-cpu0 {
563 #power-domain-cells = <0>;
564 power-domains = <&cluster_pd>;
565 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
568 cpu_pd1: power-domain-cpu1 {
569 #power-domain-cells = <0>;
570 power-domains = <&cluster_pd>;
571 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
574 cpu_pd2: power-domain-cpu2 {
575 #power-domain-cells = <0>;
576 power-domains = <&cluster_pd>;
577 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
580 cpu_pd3: power-domain-cpu3 {
581 #power-domain-cells = <0>;
582 power-domains = <&cluster_pd>;
583 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
586 cpu_pd4: power-domain-cpu4 {
587 #power-domain-cells = <0>;
588 power-domains = <&cluster_pd>;
589 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
592 cpu_pd5: power-domain-cpu5 {
593 #power-domain-cells = <0>;
594 power-domains = <&cluster_pd>;
595 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
598 cpu_pd6: power-domain-cpu6 {
599 #power-domain-cells = <0>;
600 power-domains = <&cluster_pd>;
601 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
604 cpu_pd7: power-domain-cpu7 {
605 #power-domain-cells = <0>;
606 power-domains = <&cluster_pd>;
607 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
610 cluster_pd: power-domain-cluster {
611 #power-domain-cells = <0>;
612 domain-idle-states = <&cluster_sleep_0
618 reserved-memory {
619 #address-cells = <2>;
620 #size-cells = <2>;
623 aop_cmd_db_mem: aop-cmd-db@85f20000 {
624 compatible = "qcom,cmd-db";
626 no-map;
632 no-map;
636 pil_video_mem: pil-video@93400000 {
638 no-map;
641 rproc_cdsp_mem: rproc-cdsp@93b00000 {
643 no-map;
646 rproc_adsp_mem: rproc-adsp@95900000 {
648 no-map;
653 compatible = "simple-bus";
655 dma-ranges = <0 0 0 0 0x10 0>;
656 #address-cells = <2>;
657 #size-cells = <2>;
659 gcc: clock-controller@100000 {
660 compatible = "qcom,qcs615-gcc";
666 #clock-cells = <1>;
667 #reset-cells = <1>;
668 #power-domain-cells = <1>;
672 compatible = "qcom,qcs615-qfprom", "qcom,qfprom";
674 #address-cells = <1>;
675 #size-cells = <1>;
677 qusb2_hstx_trim: hstx-trim@1f8 {
684 compatible = "qcom,qcs615-trng", "qcom,trng";
689 compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
693 reg-names = "hc",
699 interrupt-names = "hc_irq",
706 clock-names = "iface",
713 power-domains = <&rpmhpd RPMHPD_CX>;
714 operating-points-v2 = <&sdhc1_opp_table>;
720 interconnect-names = "sdhc-ddr",
721 "cpu-sdhc";
723 qcom,dll-config = <0x000f642c>;
724 qcom,ddr-config = <0x80040868>;
725 supports-cqe;
726 dma-coherent;
730 sdhc1_opp_table: opp-table {
731 compatible = "operating-points-v2";
733 opp-50000000 {
734 opp-hz = /bits/ 64 <50000000>;
735 required-opps = <&rpmhpd_opp_low_svs>;
738 opp-100000000 {
739 opp-hz = /bits/ 64 <100000000>;
740 required-opps = <&rpmhpd_opp_svs>;
743 opp-200000000 {
744 opp-hz = /bits/ 64 <200000000>;
745 required-opps = <&rpmhpd_opp_svs_l1>;
748 opp-384000000 {
749 opp-hz = /bits/ 64 <384000000>;
750 required-opps = <&rpmhpd_opp_nom>;
755 gpi_dma0: dma-controller@800000 {
756 compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma";
758 #dma-cells = <3>;
767 dma-channels = <8>;
768 dma-channel-mask = <0xf>;
774 compatible = "qcom,geni-se-qup";
779 clock-names = "m-ahb",
780 "s-ahb";
782 #address-cells = <2>;
783 #size-cells = <2>;
787 compatible = "qcom,geni-debug-uart";
790 clock-names = "se";
791 pinctrl-0 = <&qup_uart0_tx>, <&qup_uart0_rx>;
792 pinctrl-names = "default";
798 interconnect-names = "qup-core",
799 "qup-config";
800 power-domains = <&rpmhpd RPMHPD_CX>;
801 operating-points-v2 = <&qup_opp_table>;
806 compatible = "qcom,geni-i2c";
808 #address-cells = <1>;
809 #size-cells = <0>;
812 clock-names = "se";
813 pinctrl-0 = <&qup_i2c1_data_clk>;
814 pinctrl-names = "default";
821 interconnect-names = "qup-core",
822 "qup-config",
823 "qup-memory";
824 power-domains = <&rpmhpd RPMHPD_CX>;
825 required-opps = <&rpmhpd_opp_low_svs>;
828 dma-names = "tx",
834 compatible = "qcom,geni-i2c";
836 #address-cells = <1>;
837 #size-cells = <0>;
840 clock-names = "se";
841 pinctrl-0 = <&qup_i2c2_data_clk>;
842 pinctrl-names = "default";
849 interconnect-names = "qup-core",
850 "qup-config",
851 "qup-memory";
852 power-domains = <&rpmhpd RPMHPD_CX>;
853 required-opps = <&rpmhpd_opp_low_svs>;
856 dma-names = "tx",
862 compatible = "qcom,geni-spi";
866 clock-names = "se";
867 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
868 pinctrl-names = "default";
873 interconnect-names = "qup-core",
874 "qup-config";
875 power-domains = <&rpmhpd RPMHPD_CX>;
876 operating-points-v2 = <&qup_opp_table>;
879 dma-names = "tx",
881 #address-cells = <1>;
882 #size-cells = <0>;
887 compatible = "qcom,geni-uart";
891 clock-names = "se";
892 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>,
894 pinctrl-names = "default";
899 interconnect-names = "qup-core",
900 "qup-config";
901 power-domains = <&rpmhpd RPMHPD_CX>;
902 operating-points-v2 = <&qup_opp_table>;
907 compatible = "qcom,geni-i2c";
909 #address-cells = <1>;
910 #size-cells = <0>;
913 clock-names = "se";
914 pinctrl-0 = <&qup_i2c3_data_clk>;
915 pinctrl-names = "default";
922 interconnect-names = "qup-core",
923 "qup-config",
924 "qup-memory";
925 power-domains = <&rpmhpd RPMHPD_CX>;
926 required-opps = <&rpmhpd_opp_low_svs>;
929 dma-names = "tx",
935 gpi_dma1: dma-controller@a00000 {
936 compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma";
938 #dma-cells = <3>;
947 dma-channels = <8>;
948 dma-channel-mask = <0xf>;
954 compatible = "qcom,geni-se-qup";
959 clock-names = "m-ahb",
960 "s-ahb";
962 #address-cells = <2>;
963 #size-cells = <2>;
967 compatible = "qcom,geni-i2c";
970 clock-names = "se";
971 pinctrl-0 = <&qup_i2c4_data_clk>;
972 pinctrl-names = "default";
974 #address-cells = <1>;
975 #size-cells = <0>;
982 interconnect-names = "qup-core",
983 "qup-config",
984 "qup-memory";
985 power-domains = <&rpmhpd RPMHPD_CX>;
986 required-opps = <&rpmhpd_opp_low_svs>;
989 dma-names = "tx",
995 compatible = "qcom,geni-spi";
998 clock-names = "se";
999 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1000 pinctrl-names = "default";
1002 #address-cells = <1>;
1003 #size-cells = <0>;
1008 interconnect-names = "qup-core",
1009 "qup-config";
1010 power-domains = <&rpmhpd RPMHPD_CX>;
1011 operating-points-v2 = <&qup_opp_table>;
1014 dma-names = "tx",
1020 compatible = "qcom,geni-uart";
1023 clock-names = "se";
1024 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>,
1026 pinctrl-names = "default";
1032 interconnect-names = "qup-core",
1033 "qup-config";
1034 power-domains = <&rpmhpd RPMHPD_CX>;
1035 operating-points-v2 = <&qup_opp_table>;
1040 compatible = "qcom,geni-i2c";
1043 clock-names = "se";
1044 pinctrl-0 = <&qup_i2c5_data_clk>;
1045 pinctrl-names = "default";
1047 #address-cells = <1>;
1048 #size-cells = <0>;
1055 interconnect-names = "qup-core",
1056 "qup-config",
1057 "qup-memory";
1058 power-domains = <&rpmhpd RPMHPD_CX>;
1059 required-opps = <&rpmhpd_opp_low_svs>;
1062 dma-names = "tx",
1068 compatible = "qcom,geni-i2c";
1071 clock-names = "se";
1072 pinctrl-0 = <&qup_i2c6_data_clk>;
1073 pinctrl-names = "default";
1075 #address-cells = <1>;
1076 #size-cells = <0>;
1083 interconnect-names = "qup-core",
1084 "qup-config",
1085 "qup-memory";
1086 power-domains = <&rpmhpd RPMHPD_CX>;
1087 required-opps = <&rpmhpd_opp_low_svs>;
1090 dma-names = "tx",
1096 compatible = "qcom,geni-spi";
1099 clock-names = "se";
1100 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1101 pinctrl-names = "default";
1103 #address-cells = <1>;
1104 #size-cells = <0>;
1109 interconnect-names = "qup-core",
1110 "qup-config";
1111 power-domains = <&rpmhpd RPMHPD_CX>;
1112 operating-points-v2 = <&qup_opp_table>;
1115 dma-names = "tx",
1121 compatible = "qcom,geni-uart";
1124 clock-names = "se";
1125 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>,
1127 pinctrl-names = "default";
1133 interconnect-names = "qup-core",
1134 "qup-config";
1135 power-domains = <&rpmhpd RPMHPD_CX>;
1136 operating-points-v2 = <&qup_opp_table>;
1141 compatible = "qcom,geni-i2c";
1144 clock-names = "se";
1145 pinctrl-0 = <&qup_i2c7_data_clk>;
1146 pinctrl-names = "default";
1148 #address-cells = <1>;
1149 #size-cells = <0>;
1156 interconnect-names = "qup-core",
1157 "qup-config",
1158 "qup-memory";
1159 power-domains = <&rpmhpd RPMHPD_CX>;
1160 required-opps = <&rpmhpd_opp_low_svs>;
1163 dma-names = "tx",
1169 compatible = "qcom,geni-spi";
1172 clock-names = "se";
1173 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
1174 pinctrl-names = "default";
1176 #address-cells = <1>;
1177 #size-cells = <0>;
1182 interconnect-names = "qup-core",
1183 "qup-config";
1184 power-domains = <&rpmhpd RPMHPD_CX>;
1185 operating-points-v2 = <&qup_opp_table>;
1188 dma-names = "tx",
1194 compatible = "qcom,geni-uart";
1197 clock-names = "se";
1198 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>,
1200 pinctrl-names = "default";
1206 interconnect-names = "qup-core",
1207 "qup-config";
1208 power-domains = <&rpmhpd RPMHPD_CX>;
1209 operating-points-v2 = <&qup_opp_table>;
1216 compatible = "qcom,qcs615-config-noc";
1217 #interconnect-cells = <2>;
1218 qcom,bcm-voters = <&apps_bcm_voter>;
1223 compatible = "qcom,qcs615-system-noc";
1224 #interconnect-cells = <2>;
1225 qcom,bcm-voters = <&apps_bcm_voter>;
1230 compatible = "qcom,qcs615-aggre1-noc";
1231 #interconnect-cells = <2>;
1232 qcom,bcm-voters = <&apps_bcm_voter>;
1237 compatible = "qcom,qcs615-mmss-noc";
1238 #interconnect-cells = <2>;
1239 qcom,bcm-voters = <&apps_bcm_voter>;
1244 compatible = "qcom,pcie-qcs615", "qcom,pcie-sm8150";
1251 reg-names = "parf",
1257 #address-cells = <3>;
1258 #size-cells = <2>;
1261 bus-range = <0x00 0xff>;
1263 dma-coherent;
1265 linux,pci-domain = <0>;
1266 num-lanes = <1>;
1277 interrupt-names = "msi0",
1287 #interrupt-cells = <1>;
1288 interrupt-map-mask = <0 0 0 0x7>;
1289 interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1300 clock-names = "pipe",
1306 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
1307 assigned-clock-rates = <19200000>;
1313 interconnect-names = "pcie-mem", "cpu-pcie";
1315 iommu-map = <0x0 &apps_smmu 0x400 0x1>,
1319 reset-names = "pci";
1321 power-domains = <&gcc PCIE_0_GDSC>;
1324 phy-names = "pciephy";
1326 max-link-speed = <2>;
1328 operating-points-v2 = <&pcie_opp_table>;
1332 pcie_opp_table: opp-table {
1333 compatible = "operating-points-v2";
1336 opp-2500000 {
1337 opp-hz = /bits/ 64 <2500000>;
1338 required-opps = <&rpmhpd_opp_low_svs>;
1339 opp-peak-kBps = <250000 1>;
1343 opp-5000000 {
1344 opp-hz = /bits/ 64 <5000000>;
1345 required-opps = <&rpmhpd_opp_low_svs>;
1346 opp-peak-kBps = <500000 1>;
1353 #address-cells = <3>;
1354 #size-cells = <2>;
1356 bus-range = <0x01 0xff>;
1361 compatible = "qcom,qcs615-qmp-gen3x1-pcie-phy";
1369 clock-names = "aux",
1376 reset-names = "phy";
1378 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1379 assigned-clock-rates = <100000000>;
1381 #clock-cells = <0>;
1382 clock-output-names = "pcie_0_pipe_clk";
1384 #phy-cells = <0>;
1390 compatible = "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
1393 reg-names = "std",
1406 clock-names = "core_clk",
1416 reset-names = "rst";
1418 operating-points-v2 = <&ufs_opp_table>;
1423 interconnect-names = "ufs-ddr",
1424 "cpu-ufs";
1426 power-domains = <&gcc UFS_PHY_GDSC>;
1429 dma-coherent;
1431 lanes-per-direction = <1>;
1434 phy-names = "ufsphy";
1436 #reset-cells = <1>;
1440 ufs_opp_table: opp-table {
1441 compatible = "operating-points-v2";
1443 opp-50000000 {
1444 opp-hz = /bits/ 64 <50000000>,
1452 required-opps = <&rpmhpd_opp_low_svs>;
1455 opp-100000000 {
1456 opp-hz = /bits/ 64 <100000000>,
1464 required-opps = <&rpmhpd_opp_svs>;
1467 opp-200000000 {
1468 opp-hz = /bits/ 64 <200000000>,
1476 required-opps = <&rpmhpd_opp_nom>;
1482 compatible = "qcom,qcs615-qmp-ufs-phy", "qcom,sm6115-qmp-ufs-phy";
1487 clock-names = "ref",
1491 power-domains = <&gcc UFS_PHY_GDSC>;
1494 reset-names = "ufsphy";
1496 #clock-cells = <1>;
1497 #phy-cells = <0>;
1502 cryptobam: dma-controller@1dc4000 {
1503 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
1506 #dma-cells = <1>;
1508 qcom,controlled-remotely;
1509 num-channels = <16>;
1510 qcom,num-ees = <4>;
1515 compatible = "qcom,qcs615-qce", "qcom,sm8150-qce", "qcom,qce";
1518 dma-names = "rx", "tx";
1522 interconnect-names = "memory";
1526 compatible = "qcom,tcsr-mutex";
1528 #hwlock-cells = <1>;
1532 compatible = "qcom,qcs615-tcsr", "syscon";
1537 compatible = "qcom,qcs615-tlmm";
1541 reg-names = "east",
1545 gpio-ranges = <&tlmm 0 0 124>;
1546 gpio-controller;
1547 #gpio-cells = <2>;
1548 interrupt-controller;
1549 #interrupt-cells = <2>;
1550 wakeup-parent = <&pdc>;
1552 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
1558 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
1563 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
1568 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
1573 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
1578 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
1583 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
1588 qup_spi2_data_clk: qup-spi2-data-clk-state {
1593 qup_spi2_cs: qup-spi2-cs-state {
1598 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
1603 qup_spi4_data_clk: qup-spi4-data-clk-state {
1608 qup_spi4_cs: qup-spi4-cs-state {
1613 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
1618 qup_spi6_data_clk: qup-spi6-data-clk-state {
1623 qup_spi6_cs: qup-spi6-cs-state {
1628 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
1633 qup_spi7_data_clk: qup-spi7-data-clk-state {
1638 qup_spi7_cs: qup-spi7-cs-state {
1643 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
1648 qup_uart0_tx: qup-uart0-tx-state {
1653 qup_uart0_rx: qup-uart0-rx-state {
1658 qup_uart2_cts: qup-uart2-cts-state {
1663 qup_uart2_rts: qup-uart2-rts-state {
1668 qup_uart2_tx: qup-uart2-tx-state {
1673 qup_uart2_rx: qup-uart2-rx-state {
1678 qup_uart4_cts: qup-uart4-cts-state {
1683 qup_uart4_rts: qup-uart4-rts-state {
1688 qup_uart4_tx: qup-uart4-tx-state {
1693 qup_uart4_rx: qup-uart4-rx-state {
1698 qup_uart6_cts: qup-uart6-cts-state {
1703 qup_uart6_rts: qup-uart6-rts-state {
1708 qup_uart6_tx: qup-uart6-tx-state {
1713 qup_uart6_rx: qup-uart6-rx-state {
1718 qup_uart7_cts: qup-uart7-cts-state {
1723 qup_uart7_rts: qup-uart7-rts-state {
1728 qup_uart7_tx: qup-uart7-tx-state {
1733 qup_uart7_rx: qup-uart7-rx-state {
1738 sdc1_state_on: sdc1-on-state {
1739 clk-pins {
1741 bias-disable;
1742 drive-strength = <16>;
1745 cmd-pins {
1747 bias-pull-up;
1748 drive-strength = <10>;
1751 data-pins {
1753 bias-pull-up;
1754 drive-strength = <10>;
1757 rclk-pins {
1759 bias-pull-down;
1763 sdc1_state_off: sdc1-off-state {
1764 clk-pins {
1766 bias-disable;
1767 drive-strength = <2>;
1770 cmd-pins {
1772 bias-pull-up;
1773 drive-strength = <2>;
1776 data-pins {
1778 bias-pull-up;
1779 drive-strength = <2>;
1782 rclk-pins {
1784 bias-pull-down;
1788 sdc2_state_on: sdc2-on-state {
1789 clk-pins {
1791 bias-disable;
1792 drive-strength = <16>;
1795 cmd-pins {
1797 bias-pull-up;
1798 drive-strength = <10>;
1801 data-pins {
1803 bias-pull-up;
1804 drive-strength = <10>;
1808 sdc2_state_off: sdc2-off-state {
1809 clk-pins {
1811 bias-disable;
1812 drive-strength = <2>;
1815 cmd-pins {
1817 bias-pull-up;
1818 drive-strength = <2>;
1821 data-pins {
1823 bias-pull-up;
1824 drive-strength = <2>;
1829 gpucc: clock-controller@5090000 {
1830 compatible = "qcom,qcs615-gpucc";
1837 #clock-cells = <1>;
1838 #reset-cells = <1>;
1839 #power-domain-cells = <1>;
1843 compatible = "arm,coresight-stm", "arm,primecell";
1846 reg-names = "stm-base",
1847 "stm-stimulus-base";
1850 clock-names = "apb_pclk";
1852 out-ports {
1855 remote-endpoint = <&funnel_in0_in7>;
1862 compatible = "qcom,coresight-tpda", "arm,primecell";
1866 clock-names = "apb_pclk";
1868 in-ports {
1869 #address-cells = <1>;
1870 #size-cells = <0>;
1876 remote-endpoint = <&tpdm_center_out>;
1884 remote-endpoint = <&funnel_monaq_out>;
1892 remote-endpoint = <&funnel_ddr_0_out>;
1900 remote-endpoint = <&funnel_turing_out>;
1908 remote-endpoint = <&tpdm_vsense_out>;
1916 remote-endpoint = <&tpdm_dcc_out>;
1924 remote-endpoint = <&tpdm_prng_out>;
1932 remote-endpoint = <&tpdm_qm_out>;
1940 remote-endpoint = <&tpdm_west_out>;
1948 remote-endpoint = <&tpdm_pimem_out>;
1953 out-ports {
1956 remote-endpoint = <&funnel_qatb_in>;
1963 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1967 clock-names = "apb_pclk";
1969 in-ports {
1972 remote-endpoint = <&tpda_qdss_out>;
1977 out-ports {
1980 remote-endpoint = <&funnel_in0_in6>;
1987 compatible = "arm,coresight-cti", "arm,primecell";
1991 clock-names = "apb_pclk";
1995 compatible = "arm,coresight-cti", "arm,primecell";
1999 clock-names = "apb_pclk";
2003 compatible = "arm,coresight-cti", "arm,primecell";
2007 clock-names = "apb_pclk";
2011 compatible = "arm,coresight-cti", "arm,primecell";
2015 clock-names = "apb_pclk";
2019 compatible = "arm,coresight-cti", "arm,primecell";
2023 clock-names = "apb_pclk";
2027 compatible = "arm,coresight-cti", "arm,primecell";
2031 clock-names = "apb_pclk";
2035 compatible = "arm,coresight-cti", "arm,primecell";
2039 clock-names = "apb_pclk";
2043 compatible = "arm,coresight-cti", "arm,primecell";
2047 clock-names = "apb_pclk";
2051 compatible = "arm,coresight-cti", "arm,primecell";
2055 clock-names = "apb_pclk";
2059 compatible = "arm,coresight-cti", "arm,primecell";
2063 clock-names = "apb_pclk";
2067 compatible = "arm,coresight-cti", "arm,primecell";
2071 clock-names = "apb_pclk";
2075 compatible = "arm,coresight-cti", "arm,primecell";
2079 clock-names = "apb_pclk";
2083 compatible = "arm,coresight-cti", "arm,primecell";
2087 clock-names = "apb_pclk";
2091 compatible = "arm,coresight-cti", "arm,primecell";
2095 clock-names = "apb_pclk";
2099 compatible = "arm,coresight-cti", "arm,primecell";
2103 clock-names = "apb_pclk";
2107 compatible = "arm,coresight-cti", "arm,primecell";
2111 clock-names = "apb_pclk";
2115 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2119 clock-names = "apb_pclk";
2121 in-ports {
2122 #address-cells = <1>;
2123 #size-cells = <0>;
2129 remote-endpoint = <&funnel_qatb_out>;
2137 remote-endpoint = <&stm_out>;
2142 out-ports {
2145 remote-endpoint = <&funnel_merg_in0>;
2152 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2156 clock-names = "apb_pclk";
2158 in-ports {
2159 #address-cells = <1>;
2160 #size-cells = <0>;
2166 remote-endpoint = <&replicator_swao_out0>;
2174 remote-endpoint = <&tpdm_wcss_out>;
2182 remote-endpoint = <&funnel_apss_merg_out>;
2187 out-ports {
2190 remote-endpoint = <&funnel_merg_in1>;
2197 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2201 clock-names = "apb_pclk";
2203 in-ports {
2204 #address-cells = <1>;
2205 #size-cells = <0>;
2211 remote-endpoint = <&funnel_in0_out>;
2219 remote-endpoint = <&funnel_in1_out>;
2224 out-ports {
2227 remote-endpoint = <&tmc_etf_in>;
2234 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2238 clock-names = "apb_pclk";
2240 in-ports {
2243 remote-endpoint = <&tmc_etf_out>;
2248 out-ports {
2249 #address-cells = <1>;
2250 #size-cells = <0>;
2256 remote-endpoint = <&replicator1_in>;
2263 compatible = "arm,coresight-tmc", "arm,primecell";
2267 clock-names = "apb_pclk";
2269 in-ports {
2272 remote-endpoint = <&funnel_merg_out>;
2277 out-ports {
2280 remote-endpoint = <&replicator0_in>;
2287 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2291 clock-names = "apb_pclk";
2294 in-ports {
2297 remote-endpoint = <&replicator0_out1>;
2302 out-ports {
2305 remote-endpoint = <&funnel_swao_in6>;
2312 compatible = "arm,coresight-cti", "arm,primecell";
2316 clock-names = "apb_pclk";
2320 compatible = "qcom,coresight-tpdm", "arm,primecell";
2324 clock-names = "apb_pclk";
2326 qcom,cmb-element-bits = <64>;
2327 qcom,cmb-msrs-num = <32>;
2330 out-ports {
2333 remote-endpoint = <&tpda_qdss_in7>;
2340 compatible = "qcom,coresight-tpdm", "arm,primecell";
2344 clock-names = "apb_pclk";
2346 qcom,cmb-element-bits = <32>;
2347 qcom,cmb-msrs-num = <32>;
2349 out-ports {
2352 remote-endpoint = <&tpda_qdss_in9>;
2359 compatible = "qcom,coresight-tpdm", "arm,primecell";
2363 clock-names = "apb_pclk";
2365 qcom,cmb-element-bits = <64>;
2366 qcom,cmb-msrs-num = <32>;
2367 qcom,dsb-element-bits = <32>;
2368 qcom,dsb-msrs-num = <32>;
2370 out-ports {
2373 remote-endpoint = <&tpda_qdss_in13>;
2380 compatible = "qcom,coresight-tpdm", "arm,primecell";
2384 clock-names = "apb_pclk";
2386 qcom,dsb-element-bits = <32>;
2387 qcom,dsb-msrs-num = <32>;
2389 out-ports {
2392 remote-endpoint = <&funnel_turing_in>;
2399 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2403 clock-names = "apb_pclk";
2405 in-ports {
2408 remote-endpoint = <&tpdm_turing_out>;
2413 out-ports {
2416 remote-endpoint = <&tpda_qdss_in6>;
2423 compatible = "arm,coresight-cti", "arm,primecell";
2427 clock-names = "apb_pclk";
2431 compatible = "qcom,coresight-tpdm", "arm,primecell";
2435 clock-names = "apb_pclk";
2437 qcom,cmb-element-bits = <32>;
2438 qcom,cmb-msrs-num = <32>;
2441 out-ports {
2444 remote-endpoint = <&tpda_qdss_in8>;
2451 compatible = "qcom,coresight-tpdm", "arm,primecell";
2455 clock-names = "apb_pclk";
2457 qcom,cmb-element-bits = <32>;
2458 qcom,cmb-msrs-num = <32>;
2459 qcom,dsb-element-bits = <32>;
2460 qcom,dsb-msrs-num = <32>;
2463 out-ports {
2466 remote-endpoint = <&funnel_in1_in4>;
2473 compatible = "qcom,coresight-tpdm", "arm,primecell";
2477 clock-names = "apb_pclk";
2479 qcom,dsb-element-bits = <32>;
2480 qcom,dsb-msrs-num = <32>;
2482 out-ports {
2485 remote-endpoint = <&funnel_monaq_in>;
2492 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2496 clock-names = "apb_pclk";
2498 in-ports {
2501 remote-endpoint = <&tpdm_monaq_out>;
2506 out-ports {
2509 remote-endpoint = <&tpda_qdss_in4>;
2516 compatible = "qcom,coresight-tpdm", "arm,primecell";
2520 clock-names = "apb_pclk";
2522 qcom,dsb-element-bits = <32>;
2523 qcom,dsb-msrs-num = <32>;
2526 out-ports {
2529 remote-endpoint = <&tpda_qdss_in11>;
2536 compatible = "qcom,coresight-tpdm", "arm,primecell";
2540 clock-names = "apb_pclk";
2542 qcom,dsb-element-bits = <32>;
2543 qcom,dsb-msrs-num = <32>;
2546 out-ports {
2549 remote-endpoint = <&funnel_ddr_0_in>;
2556 compatible = "arm,coresight-cti", "arm,primecell";
2560 clock-names = "apb_pclk";
2564 compatible = "arm,coresight-cti", "arm,primecell";
2568 clock-names = "apb_pclk";
2572 compatible = "arm,coresight-cti", "arm,primecell";
2576 clock-names = "apb_pclk";
2580 compatible = "arm,coresight-cti", "arm,primecell";
2584 clock-names = "apb_pclk";
2588 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2592 clock-names = "apb_pclk";
2594 in-ports {
2597 remote-endpoint = <&tpdm_ddr_out>;
2602 out-ports {
2605 remote-endpoint = <&tpda_qdss_in5>;
2612 compatible = "qcom,coresight-tpda", "arm,primecell";
2616 clock-names = "apb_pclk";
2618 in-ports {
2619 #address-cells = <1>;
2620 #size-cells = <0>;
2626 remote-endpoint = <&tpdm_swao0_out>;
2634 remote-endpoint = <&tpdm_swao1_out>;
2640 out-ports {
2643 remote-endpoint = <&funnel_swao_in7>;
2650 compatible = "qcom,coresight-tpdm", "arm,primecell";
2654 clock-names = "apb_pclk";
2656 qcom,cmb-element-bits = <64>;
2657 qcom,cmb-msrs-num = <32>;
2660 out-ports {
2663 remote-endpoint = <&tpda_swao_in0>;
2670 compatible = "qcom,coresight-tpdm", "arm,primecell";
2674 clock-names = "apb_pclk";
2676 qcom,dsb-element-bits = <32>;
2677 qcom,dsb-msrs-num = <32>;
2680 out-ports {
2683 remote-endpoint = <&tpda_swao_in1>;
2690 compatible = "arm,coresight-cti", "arm,primecell";
2694 clock-names = "apb_pclk";
2698 compatible = "arm,coresight-cti", "arm,primecell";
2702 clock-names = "apb_pclk";
2706 compatible = "arm,coresight-cti", "arm,primecell";
2710 clock-names = "apb_pclk";
2714 compatible = "arm,coresight-cti", "arm,primecell";
2718 clock-names = "apb_pclk";
2722 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2726 clock-names = "apb_pclk";
2728 in-ports {
2729 #address-cells = <1>;
2730 #size-cells = <0>;
2736 remote-endpoint = <&replicator1_out>;
2744 remote-endpoint = <&tpda_swao_out>;
2749 out-ports {
2752 remote-endpoint = <&tmc_etf_swao_in>;
2759 compatible = "arm,coresight-tmc", "arm,primecell";
2763 clock-names = "apb_pclk";
2765 in-ports {
2768 remote-endpoint = <&funnel_swao_out>;
2773 out-ports {
2776 remote-endpoint = <&replicator_swao_in>;
2783 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2787 clock-names = "apb_pclk";
2789 in-ports {
2792 remote-endpoint = <&tmc_etf_swao_out>;
2797 out-ports {
2798 #address-cells = <1>;
2799 #size-cells = <0>;
2805 remote-endpoint = <&funnel_in1_in3>;
2813 remote-endpoint = <&eud_in>;
2820 compatible = "arm,coresight-cti", "arm,primecell";
2824 clock-names = "apb_pclk";
2828 compatible = "qcom,coresight-tpdm", "arm,primecell";
2832 clock-names = "apb_pclk";
2834 qcom,dsb-element-bits = <32>;
2835 qcom,dsb-msrs-num = <32>;
2837 out-ports {
2840 remote-endpoint = <&tpda_qdss_in12>;
2847 compatible = "arm,coresight-cti", "arm,primecell";
2851 clock-names = "apb_pclk";
2858 compatible = "arm,coresight-cti", "arm,primecell";
2862 clock-names = "apb_pclk";
2867 compatible = "qcom,coresight-tpdm", "arm,primecell";
2871 clock-names = "apb_pclk";
2873 qcom,dsb-element-bits = <32>;
2874 qcom,dsb-msrs-num = <32>;
2876 out-ports {
2879 remote-endpoint = <&tpda_qdss_in0>;
2886 compatible = "arm,coresight-cti", "arm,primecell";
2890 clock-names = "apb_pclk";
2894 compatible = "arm,coresight-cti", "arm,primecell";
2898 clock-names = "apb_pclk";
2902 compatible = "arm,coresight-cti", "arm,primecell";
2906 clock-names = "apb_pclk";
2915 clock-names = "apb_pclk";
2917 arm,coresight-loses-context-with-cpu;
2918 qcom,skip-power-up;
2920 out-ports {
2923 remote-endpoint = <&funnel_apss_in0>;
2930 compatible = "arm,coresight-cti", "arm,primecell";
2934 clock-names = "apb_pclk";
2943 clock-names = "apb_pclk";
2945 arm,coresight-loses-context-with-cpu;
2946 qcom,skip-power-up;
2948 out-ports {
2951 remote-endpoint = <&funnel_apss_in1>;
2958 compatible = "arm,coresight-cti", "arm,primecell";
2962 clock-names = "apb_pclk";
2971 clock-names = "apb_pclk";
2973 arm,coresight-loses-context-with-cpu;
2974 qcom,skip-power-up;
2976 out-ports {
2979 remote-endpoint = <&funnel_apss_in2>;
2986 compatible = "arm,coresight-cti", "arm,primecell";
2990 clock-names = "apb_pclk";
2999 clock-names = "apb_pclk";
3001 arm,coresight-loses-context-with-cpu;
3002 qcom,skip-power-up;
3004 out-ports {
3007 remote-endpoint = <&funnel_apss_in3>;
3014 compatible = "arm,coresight-cti", "arm,primecell";
3018 clock-names = "apb_pclk";
3027 clock-names = "apb_pclk";
3029 arm,coresight-loses-context-with-cpu;
3030 qcom,skip-power-up;
3032 out-ports {
3035 remote-endpoint = <&funnel_apss_in4>;
3042 compatible = "arm,coresight-cti", "arm,primecell";
3046 clock-names = "apb_pclk";
3055 clock-names = "apb_pclk";
3057 arm,coresight-loses-context-with-cpu;
3058 qcom,skip-power-up;
3060 out-ports {
3063 remote-endpoint = <&funnel_apss_in5>;
3070 compatible = "arm,coresight-cti", "arm,primecell";
3074 clock-names = "apb_pclk";
3083 clock-names = "apb_pclk";
3085 arm,coresight-loses-context-with-cpu;
3086 qcom,skip-power-up;
3088 out-ports {
3091 remote-endpoint = <&funnel_apss_in6>;
3098 compatible = "arm,coresight-cti", "arm,primecell";
3102 clock-names = "apb_pclk";
3111 clock-names = "apb_pclk";
3113 arm,coresight-loses-context-with-cpu;
3114 qcom,skip-power-up;
3116 out-ports {
3119 remote-endpoint = <&funnel_apss_in7>;
3126 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3130 clock-names = "apb_pclk";
3132 in-ports {
3133 #address-cells = <1>;
3134 #size-cells = <0>;
3140 remote-endpoint = <&etm0_out>;
3148 remote-endpoint = <&etm1_out>;
3156 remote-endpoint = <&etm2_out>;
3164 remote-endpoint = <&etm3_out>;
3172 remote-endpoint = <&etm4_out>;
3180 remote-endpoint = <&etm5_out>;
3188 remote-endpoint = <&etm6_out>;
3196 remote-endpoint = <&etm7_out>;
3201 out-ports {
3204 remote-endpoint = <&funnel_apss_merg_in0>;
3211 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3215 clock-names = "apb_pclk";
3217 in-ports {
3218 #address-cells = <1>;
3219 #size-cells = <0>;
3225 remote-endpoint = <&funnel_apss_out>;
3233 remote-endpoint = <&tpda_olc_out>;
3241 remote-endpoint = <&tpda_llm_silver_out>;
3249 remote-endpoint = <&tpda_llm_gold_out>;
3257 remote-endpoint = <&tpda_apss_out>;
3262 out-ports {
3265 remote-endpoint = <&funnel_in1_in7>;
3272 compatible = "qcom,coresight-tpdm", "arm,primecell";
3276 clock-names = "apb_pclk";
3278 qcom,cmb-element-bits = <64>;
3279 qcom,cmb-msrs-num = <32>;
3281 out-ports {
3284 remote-endpoint = <&tpda_olc_in>;
3291 compatible = "qcom,coresight-tpda", "arm,primecell";
3295 clock-names = "apb_pclk";
3297 in-ports {
3300 remote-endpoint = <&tpdm_olc_out>;
3305 out-ports {
3308 remote-endpoint = <&funnel_apss_merg_in2>;
3315 compatible = "qcom,coresight-tpdm", "arm,primecell";
3319 clock-names = "apb_pclk";
3321 qcom,dsb-element-bits = <32>;
3322 qcom,dsb-msrs-num = <32>;
3324 out-ports {
3327 remote-endpoint = <&tpda_apss_in>;
3334 compatible = "qcom,coresight-tpda", "arm,primecell";
3338 clock-names = "apb_pclk";
3340 in-ports {
3343 remote-endpoint = <&tpdm_apss_out>;
3348 out-ports {
3351 remote-endpoint = <&funnel_apss_merg_in5>;
3358 compatible = "qcom,coresight-tpdm", "arm,primecell";
3362 clock-names = "apb_pclk";
3364 qcom,cmb-element-bits = <32>;
3365 qcom,cmb-msrs-num = <32>;
3367 out-ports {
3370 remote-endpoint = <&tpda_llm_silver_in>;
3377 compatible = "qcom,coresight-tpdm", "arm,primecell";
3381 clock-names = "apb_pclk";
3383 qcom,cmb-element-bits = <32>;
3384 qcom,cmb-msrs-num = <32>;
3386 out-ports {
3389 remote-endpoint = <&tpda_llm_gold_in>;
3396 compatible = "qcom,coresight-tpda", "arm,primecell";
3400 clock-names = "apb_pclk";
3402 in-ports {
3405 remote-endpoint = <&tpdm_llm_silver_out>;
3410 out-ports {
3413 remote-endpoint = <&funnel_apss_merg_in3>;
3420 compatible = "qcom,coresight-tpda", "arm,primecell";
3424 clock-names = "apb_pclk";
3426 in-ports {
3429 remote-endpoint = <&tpdm_llm_gold_out>;
3434 out-ports {
3437 remote-endpoint = <&funnel_apss_merg_in4>;
3444 compatible = "arm,coresight-cti", "arm,primecell";
3448 clock-names = "apb_pclk";
3452 compatible = "arm,coresight-cti", "arm,primecell";
3456 clock-names = "apb_pclk";
3460 compatible = "arm,coresight-cti", "arm,primecell";
3464 clock-names = "apb_pclk";
3468 compatible = "qcom,qcs615-cdsp-pas", "qcom,sm8150-cdsp-pas";
3471 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3476 interrupt-names = "wdog",
3480 "stop-ack";
3483 clock-names = "xo";
3485 power-domains = <&rpmhpd RPMHPD_CX>;
3486 power-domain-names = "cx";
3488 memory-region = <&rproc_cdsp_mem>;
3492 qcom,smem-states = <&cdsp_smp2p_out 0>;
3493 qcom,smem-state-names = "stop";
3497 glink-edge {
3501 qcom,remote-pid = <5>;
3505 qcom,glink-channels = "fastrpcglink-apps-dsp";
3507 #address-cells = <1>;
3508 #size-cells = <0>;
3510 compute-cb@1 {
3511 compatible = "qcom,fastrpc-compute-cb";
3514 dma-coherent;
3517 compute-cb@2 {
3518 compatible = "qcom,fastrpc-compute-cb";
3521 dma-coherent;
3524 compute-cb@3 {
3525 compatible = "qcom,fastrpc-compute-cb";
3528 dma-coherent;
3531 compute-cb@4 {
3532 compatible = "qcom,fastrpc-compute-cb";
3535 dma-coherent;
3538 compute-cb@5 {
3539 compatible = "qcom,fastrpc-compute-cb";
3542 dma-coherent;
3545 compute-cb@6 {
3546 compatible = "qcom,fastrpc-compute-cb";
3549 dma-coherent;
3556 compatible = "qcom,qcs615-cpu-bwmon", "qcom,sdm845-bwmon";
3562 operating-points-v2 = <&cpu_bwmon_opp_table>;
3564 cpu_bwmon_opp_table: opp-table {
3565 compatible = "operating-points-v2";
3567 opp-0 {
3568 opp-peak-kBps = <12896000>;
3571 opp-1 {
3572 opp-peak-kBps = <14928000>;
3578 compatible = "qcom,qcs615-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3584 operating-points-v2 = <&llcc_bwmon_opp_table>;
3586 llcc_bwmon_opp_table: opp-table {
3587 compatible = "operating-points-v2";
3589 opp-0 {
3590 opp-peak-kBps = <800000>;
3593 opp-1 {
3594 opp-peak-kBps = <1200000>;
3597 opp-2 {
3598 opp-peak-kBps = <1804800>;
3601 opp-3 {
3602 opp-peak-kBps = <2188800>;
3605 opp-4 {
3606 opp-peak-kBps = <2726400>;
3609 opp-5 {
3610 opp-peak-kBps = <3072000>;
3613 opp-6 {
3614 opp-peak-kBps = <4070400>;
3617 opp-7 {
3618 opp-peak-kBps = <5414400>;
3621 opp-8 {
3622 opp-peak-kBps = <6220800>;
3628 compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
3630 reg-names = "hc";
3634 interrupt-names = "hc_irq",
3640 clock-names = "iface",
3644 power-domains = <&rpmhpd RPMHPD_CX>;
3645 operating-points-v2 = <&sdhc2_opp_table>;
3652 interconnect-names = "sdhc-ddr",
3653 "cpu-sdhc";
3655 qcom,dll-config = <0x0007642c>;
3656 qcom,ddr-config = <0x80040868>;
3657 dma-coherent;
3661 sdhc2_opp_table: opp-table {
3662 compatible = "operating-points-v2";
3664 opp-50000000 {
3665 opp-hz = /bits/ 64 <50000000>;
3666 required-opps = <&rpmhpd_opp_low_svs>;
3669 opp-100000000 {
3670 opp-hz = /bits/ 64 <100000000>;
3671 required-opps = <&rpmhpd_opp_svs>;
3674 opp-202000000 {
3675 opp-hz = /bits/ 64 <202000000>;
3676 required-opps = <&rpmhpd_opp_nom>;
3683 compatible = "qcom,qcs615-dc-noc";
3684 #interconnect-cells = <2>;
3685 qcom,bcm-voters = <&apps_bcm_voter>;
3688 llcc: system-cache-controller@9200000 {
3689 compatible = "qcom,qcs615-llcc";
3692 reg-names = "llcc0_base",
3698 compatible = "qcom,qcs615-gem-noc";
3699 #interconnect-cells = <2>;
3700 qcom,bcm-voters = <&apps_bcm_voter>;
3703 venus: video-codec@aa00000 {
3704 compatible = "qcom,qcs615-venus", "qcom,sc7180-venus";
3713 clock-names = "core",
3719 power-domains = <&videocc VENUS_GDSC>,
3722 power-domain-names = "venus",
3726 operating-points-v2 = <&venus_opp_table>;
3732 interconnect-names = "video-mem",
3733 "cpu-cfg";
3737 memory-region = <&pil_video_mem>;
3741 venus_opp_table: opp-table {
3742 compatible = "operating-points-v2";
3744 opp-133330000 {
3745 opp-hz = /bits/ 64 <133330000>;
3746 required-opps = <&rpmhpd_opp_low_svs>;
3749 opp-240000000 {
3750 opp-hz = /bits/ 64 <240000000>;
3751 required-opps = <&rpmhpd_opp_svs>;
3754 opp-300000000 {
3755 opp-hz = /bits/ 64 <300000000>;
3756 required-opps = <&rpmhpd_opp_svs_l1>;
3759 opp-380000000 {
3760 opp-hz = /bits/ 64 <380000000>;
3761 required-opps = <&rpmhpd_opp_nom>;
3764 opp-410000000 {
3765 opp-hz = /bits/ 64 <410000000>;
3766 required-opps = <&rpmhpd_opp_nom_l1>;
3769 opp-460000000 {
3770 opp-hz = /bits/ 64 <460000000>;
3771 required-opps = <&rpmhpd_opp_turbo>;
3776 videocc: clock-controller@ab00000 {
3777 compatible = "qcom,qcs615-videocc";
3783 #clock-cells = <1>;
3784 #reset-cells = <1>;
3785 #power-domain-cells = <1>;
3788 camcc: clock-controller@ad00000 {
3789 compatible = "qcom,qcs615-camcc";
3794 #clock-cells = <1>;
3795 #reset-cells = <1>;
3796 #power-domain-cells = <1>;
3799 mdss: display-subsystem@ae00000 {
3800 compatible = "qcom,sm6150-mdss";
3802 reg-names = "mdss";
3808 interconnect-names = "mdp0-mem",
3809 "cpu-cfg";
3811 power-domains = <&dispcc MDSS_CORE_GDSC>;
3818 interrupt-controller;
3819 #interrupt-cells = <1>;
3823 #address-cells = <2>;
3824 #size-cells = <2>;
3829 mdss_mdp: display-controller@ae01000 {
3830 compatible = "qcom,sm6150-dpu";
3833 reg-names = "mdp",
3840 clock-names = "iface",
3845 operating-points-v2 = <&mdp_opp_table>;
3846 power-domains = <&rpmhpd RPMHPD_CX>;
3848 interrupts-extended = <&mdss 0>;
3851 #address-cells = <1>;
3852 #size-cells = <0>;
3865 remote-endpoint = <&mdss_dsi0_in>;
3870 mdp_opp_table: opp-table {
3871 compatible = "operating-points-v2";
3873 opp-192000000 {
3874 opp-hz = /bits/ 64 <192000000>;
3875 required-opps = <&rpmhpd_opp_low_svs>;
3878 opp-256000000 {
3879 opp-hz = /bits/ 64 <256000000>;
3880 required-opps = <&rpmhpd_opp_svs>;
3883 opp-307200000 {
3884 opp-hz = /bits/ 64 <307200000>;
3885 required-opps = <&rpmhpd_opp_nom>;
3891 compatible = "qcom,sm6150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3893 reg-names = "dsi_ctrl";
3895 interrupts-extended = <&mdss 4>;
3903 clock-names = "byte",
3910 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
3912 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
3915 operating-points-v2 = <&dsi0_opp_table>;
3916 power-domains = <&rpmhpd RPMHPD_CX>;
3920 #address-cells = <1>;
3921 #size-cells = <0>;
3925 dsi0_opp_table: opp-table {
3926 compatible = "operating-points-v2";
3928 opp-164000000 {
3929 opp-hz = /bits/ 64 <164000000>;
3930 required-opps = <&rpmhpd_opp_low_svs>;
3935 #address-cells = <1>;
3936 #size-cells = <0>;
3942 remote-endpoint = <&dpu_intf1_out>;
3956 compatible = "qcom,sm6150-dsi-phy-14nm";
3960 reg-names = "dsi_phy",
3964 #clock-cells = <1>;
3965 #phy-cells = <0>;
3969 clock-names = "iface",
3976 dispcc: clock-controller@af00000 {
3977 compatible = "qcom,qcs615-dispcc";
3988 #clock-cells = <1>;
3989 #reset-cells = <1>;
3990 #power-domain-cells = <1>;
3993 pdc: interrupt-controller@b220000 {
3994 compatible = "qcom,qcs615-pdc", "qcom,pdc";
3997 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3998 interrupt-parent = <&intc>;
3999 #interrupt-cells = <2>;
4000 interrupt-controller;
4003 aoss_qmp: power-management@c300000 {
4004 compatible = "qcom,qcs615-aoss-qmp", "qcom,aoss-qmp";
4009 #clock-cells = <0>;
4013 compatible = "qcom,rpmh-stats";
4018 compatible = "qcom,qcs615-imem", "syscon", "simple-mfd";
4022 #address-cells = <1>;
4023 #size-cells = <1>;
4025 pil-reloc@2a94c {
4026 compatible = "qcom,pil-reloc-info";
4032 compatible = "qcom,qcs615-smmu-500", "qcom,smmu-500", "arm,mmu-500";
4034 #iommu-cells = <2>;
4035 #global-interrupts = <1>;
4036 dma-coherent;
4106 compatible = "qcom,spmi-pmic-arb";
4112 reg-names = "core",
4117 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4118 interrupt-names = "periph_irq";
4119 interrupt-controller;
4120 #interrupt-cells = <4>;
4121 #address-cells = <2>;
4122 #size-cells = <0>;
4127 intc: interrupt-controller@17a00000 {
4128 compatible = "arm,gic-v3";
4132 #address-cells = <0>;
4133 #interrupt-cells = <3>;
4134 interrupt-controller;
4135 #redistributor-regions = <1>;
4136 redistributor-stride = <0x0 0x20000>;
4140 compatible = "qcom,qcs615-apss-shared",
4141 "qcom,sdm845-apss-shared";
4143 #mbox-cells = <1>;
4147 compatible = "qcom,apss-wdt-qcs615", "qcom,kpss-wdt";
4154 compatible = "arm,armv7-timer-mem";
4157 #address-cells = <1>;
4158 #size-cells = <1>;
4163 frame-number = <0>;
4170 frame-number = <1>;
4177 frame-number = <2>;
4184 frame-number = <3>;
4191 frame-number = <4>;
4198 frame-number = <5>;
4205 frame-number = <6>;
4212 compatible = "qcom,rpmh-rsc";
4216 reg-names = "drv-0",
4217 "drv-1",
4218 "drv-2";
4224 qcom,drv-id = <2>;
4225 qcom,tcs-offset = <0xd00>;
4226 qcom,tcs-config = <ACTIVE_TCS 2>,
4232 power-domains = <&cluster_pd>;
4234 apps_bcm_voter: bcm-voter {
4235 compatible = "qcom,bcm-voter";
4238 rpmhcc: clock-controller {
4239 compatible = "qcom,qcs615-rpmh-clk";
4241 clock-names = "xo";
4243 #clock-cells = <1>;
4246 rpmhpd: power-controller {
4247 compatible = "qcom,qcs615-rpmhpd";
4248 #power-domain-cells = <1>;
4249 operating-points-v2 = <&rpmhpd_opp_table>;
4251 rpmhpd_opp_table: opp-table {
4252 compatible = "operating-points-v2";
4254 rpmhpd_opp_ret: opp-0 {
4255 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4258 rpmhpd_opp_min_svs: opp-1 {
4259 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4262 rpmhpd_opp_low_svs: opp-2 {
4263 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4266 rpmhpd_opp_svs: opp-3 {
4267 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4270 rpmhpd_opp_svs_l1: opp-4 {
4271 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4274 rpmhpd_opp_nom: opp-5 {
4275 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4278 rpmhpd_opp_nom_l1: opp-6 {
4279 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4282 rpmhpd_opp_nom_l2: opp-7 {
4283 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4286 rpmhpd_opp_turbo: opp-8 {
4287 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4290 rpmhpd_opp_turbo_l1: opp-9 {
4291 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4298 compatible = "qcom,qcs615-osm-l3", "qcom,sm8150-osm-l3", "qcom,osm-l3";
4302 clock-names = "xo", "alternate";
4304 #interconnect-cells = <1>;
4308 compatible = "qcom,qcs615-qusb2-phy";
4312 clock-names = "cfg_ahb", "ref";
4315 nvmem-cells = <&qusb2_hstx_trim>;
4317 #phy-cells = <0>;
4323 compatible = "qcom,qcs615-qusb2-phy";
4328 clock-names = "cfg_ahb",
4333 #phy-cells = <0>;
4339 compatible = "qcom,qcs615-qmp-usb3-phy";
4346 clock-names = "aux",
4353 reset-names = "phy", "phy_phy";
4355 qcom,tcsr-reg = <&tcsr 0xb244>;
4357 clock-output-names = "usb3_phy_pipe_clk_src";
4358 #clock-cells = <0>;
4360 #phy-cells = <0>;
4366 compatible = "qcom,qcs615-dwc3", "qcom,dwc3";
4375 clock-names = "cfg_noc",
4382 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4384 assigned-clock-rates = <19200000>, <200000000>;
4386 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4391 interrupt-names = "pwr_event",
4397 power-domains = <&gcc USB30_PRIM_GDSC>;
4398 required-opps = <&rpmhpd_opp_nom>;
4402 #address-cells = <2>;
4403 #size-cells = <2>;
4416 phy-names = "usb2-phy", "usb3-phy";
4418 snps,dis-u1-entry-quirk;
4419 snps,dis-u2-entry-quirk;
4423 snps,has-lpm-erratum;
4424 snps,hird-threshold = /bits/ 8 <0x10>;
4430 compatible = "qcom,qcs615-dwc3", "qcom,dwc3";
4439 clock-names = "cfg_noc",
4446 assigned-clocks = <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>,
4448 assigned-clock-rates = <19200000>, <200000000>;
4450 interrupts-extended = <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH>,
4454 interrupt-names = "pwr_event",
4459 power-domains = <&gcc USB20_SEC_GDSC>;
4460 required-opps = <&rpmhpd_opp_nom>;
4464 qcom,select-utmi-as-pipe-clk;
4466 #address-cells = <2>;
4467 #size-cells = <2>;
4480 phy-names = "usb2-phy";
4485 snps,has-lpm-erratum;
4486 snps,hird-threshold = /bits/ 8 <0x10>;
4488 maximum-speed = "high-speed";
4492 tsens0: thermal-sensor@c263000 {
4493 compatible = "qcom,qcs615-tsens", "qcom,tsens-v2";
4498 interrupt-names = "uplow", "critical";
4500 #thermal-sensor-cells = <1>;
4504 compatible = "qcom,qcs615-adsp-pas", "qcom,sm8150-adsp-pas";
4507 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
4512 interrupt-names = "wdog",
4516 "stop-ack";
4519 clock-names = "xo";
4521 power-domains = <&rpmhpd RPMHPD_CX>;
4522 power-domain-names = "cx";
4524 memory-region = <&rproc_adsp_mem>;
4528 qcom,smem-states = <&adsp_smp2p_out 0>;
4529 qcom,smem-state-names = "stop";
4533 glink_edge: glink-edge {
4537 qcom,remote-pid = <2>;
4541 qcom,glink-channels = "fastrpcglink-apps-dsp";
4543 #address-cells = <1>;
4544 #size-cells = <0>;
4546 compute-cb@3 {
4547 compatible = "qcom,fastrpc-compute-cb";
4550 dma-coherent;
4553 compute-cb@4 {
4554 compatible = "qcom,fastrpc-compute-cb";
4557 dma-coherent;
4560 compute-cb@5 {
4561 compatible = "qcom,fastrpc-compute-cb";
4564 dma-coherent;
4567 compute-cb@6 {
4568 compatible = "qcom,fastrpc-compute-cb";
4572 dma-coherent;
4579 compatible = "qcom,qcs615-cpufreq-hw", "qcom,cpufreq-hw";
4581 reg-names = "freq-domain0", "freq-domain1";
4584 clock-names = "xo", "alternate";
4586 #freq-domain-cells = <1>;
4587 #clock-cells = <1>;
4592 compatible = "arm,armv8-timer";
4599 thermal-zones {
4600 aoss-thermal {
4601 thermal-sensors = <&tsens0 0>;
4604 aoss-critical {
4612 cpuss-0-thermal {
4613 thermal-sensors = <&tsens0 1>;
4616 cpuss0-critical {
4624 cpuss-1-thermal {
4625 thermal-sensors = <&tsens0 2>;
4628 cpuss1-critical {
4636 cpuss-2-thermal {
4637 thermal-sensors = <&tsens0 3>;
4640 cpuss2-critical {
4648 cpuss-3-thermal {
4649 thermal-sensors = <&tsens0 4>;
4652 cpuss3-critical {
4660 cpu-1-0-thermal {
4661 thermal-sensors = <&tsens0 5>;
4664 cpu-critical {
4672 cpu-1-1-thermal {
4673 thermal-sensors = <&tsens0 6>;
4676 cpu-critical {
4684 cpu-1-2-thermal {
4685 thermal-sensors = <&tsens0 7>;
4688 cpu-critical {
4696 cpu-1-3-thermal {
4697 thermal-sensors = <&tsens0 8>;
4700 cpu-critical {
4708 gpu-thermal {
4709 thermal-sensors = <&tsens0 9>;
4712 gpu-critical {
4720 q6-hvx-thermal {
4721 thermal-sensors = <&tsens0 10>;
4724 q6-hvx-critical {
4732 mdm-core-thermal {
4733 thermal-sensors = <&tsens0 11>;
4736 mdm-core-critical {
4744 camera-thermal {
4745 thermal-sensors = <&tsens0 12>;
4748 camera-critical {
4756 wlan-thermal {
4757 thermal-sensors = <&tsens0 13>;
4760 wlan-critical {
4768 display-thermal {
4769 thermal-sensors = <&tsens0 14>;
4772 display-critical {
4780 video-thermal {
4781 thermal-sensors = <&tsens0 15>;
4784 video-critical {