Lines Matching +full:pdc +full:- +full:intc
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm8750-gcc.h>
8 #include <dt-bindings/clock/qcom,sm8750-tcsr.h>
9 #include <dt-bindings/dma/qcom-gpi.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interconnect/qcom,icc.h>
12 #include <dt-bindings/interconnect/qcom,sm8750-rpmh.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/mailbox/qcom-ipcc.h>
15 #include <dt-bindings/phy/phy-qcom-qmp.h>
16 #include <dt-bindings/power/qcom,rpmhpd.h>
17 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/soc/qcom,gpr.h>
19 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
20 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
23 interrupt-parent = <&intc>;
25 #address-cells = <2>;
26 #size-cells = <2>;
29 #address-cells = <2>;
30 #size-cells = <0>;
36 enable-method = "psci";
37 next-level-cache = <&l2_0>;
38 power-domains = <&cpu_pd0>;
39 power-domain-names = "psci";
41 l2_0: l2-cache {
43 cache-level = <2>;
44 cache-unified;
52 enable-method = "psci";
53 next-level-cache = <&l2_0>;
54 power-domains = <&cpu_pd1>;
55 power-domain-names = "psci";
62 enable-method = "psci";
63 next-level-cache = <&l2_0>;
64 power-domains = <&cpu_pd2>;
65 power-domain-names = "psci";
72 enable-method = "psci";
73 next-level-cache = <&l2_0>;
74 power-domains = <&cpu_pd3>;
75 power-domain-names = "psci";
82 enable-method = "psci";
83 next-level-cache = <&l2_0>;
84 power-domains = <&cpu_pd4>;
85 power-domain-names = "psci";
92 enable-method = "psci";
93 next-level-cache = <&l2_0>;
94 power-domains = <&cpu_pd5>;
95 power-domain-names = "psci";
102 enable-method = "psci";
103 next-level-cache = <&l2_1>;
104 power-domains = <&cpu_pd6>;
105 power-domain-names = "psci";
107 l2_1: l2-cache {
109 cache-level = <2>;
110 cache-unified;
118 enable-method = "psci";
119 next-level-cache = <&l2_1>;
120 power-domains = <&cpu_pd7>;
121 power-domain-names = "psci";
124 cpu-map {
162 idle-states {
163 entry-method = "psci";
165 cluster0_c4: cpu-sleep-0 {
166 compatible = "arm,idle-state";
167 idle-state-name = "ret";
168 arm,psci-suspend-param = <0x00000004>;
169 entry-latency-us = <93>;
170 exit-latency-us = <129>;
171 min-residency-us = <560>;
174 cluster1_c4: cpu-sleep-1 {
175 compatible = "arm,idle-state";
176 idle-state-name = "ret";
177 arm,psci-suspend-param = <0x00000004>;
178 entry-latency-us = <172>;
179 exit-latency-us = <130>;
180 min-residency-us = <686>;
184 domain-idle-states {
185 cluster_cl5: cluster-sleep-0 {
186 compatible = "domain-idle-state";
187 arm,psci-suspend-param = <0x01000054>;
188 entry-latency-us = <2150>;
189 exit-latency-us = <1983>;
190 min-residency-us = <9144>;
193 domain_ss3: domain-sleep-0 {
194 compatible = "domain-idle-state";
195 arm,psci-suspend-param = <0x0200c354>;
196 entry-latency-us = <2800>;
197 exit-latency-us = <4400>;
198 min-residency-us = <10150>;
205 compatible = "qcom,scm-sm8750", "qcom,scm";
211 clk_virt: interconnect-0 {
212 compatible = "qcom,sm8750-clk-virt";
213 #interconnect-cells = <2>;
214 qcom,bcm-voters = <&apps_bcm_voter>;
217 mc_virt: interconnect-1 {
218 compatible = "qcom,sm8750-mc-virt";
219 #interconnect-cells = <2>;
220 qcom,bcm-voters = <&apps_bcm_voter>;
230 compatible = "arm,armv8-pmuv3";
235 compatible = "arm,psci-1.0";
238 cpu_pd0: power-domain-cpu0 {
239 #power-domain-cells = <0>;
240 power-domains = <&cluster0_pd>;
241 domain-idle-states = <&cluster0_c4>;
244 cpu_pd1: power-domain-cpu1 {
245 #power-domain-cells = <0>;
246 power-domains = <&cluster0_pd>;
247 domain-idle-states = <&cluster0_c4>;
250 cpu_pd2: power-domain-cpu2 {
251 #power-domain-cells = <0>;
252 power-domains = <&cluster0_pd>;
253 domain-idle-states = <&cluster0_c4>;
256 cpu_pd3: power-domain-cpu3 {
257 #power-domain-cells = <0>;
258 power-domains = <&cluster0_pd>;
259 domain-idle-states = <&cluster0_c4>;
262 cpu_pd4: power-domain-cpu4 {
263 #power-domain-cells = <0>;
264 power-domains = <&cluster0_pd>;
265 domain-idle-states = <&cluster0_c4>;
268 cpu_pd5: power-domain-cpu5 {
269 #power-domain-cells = <0>;
270 power-domains = <&cluster0_pd>;
271 domain-idle-states = <&cluster0_c4>;
274 cpu_pd6: power-domain-cpu6 {
275 #power-domain-cells = <0>;
276 power-domains = <&cluster1_pd>;
277 domain-idle-states = <&cluster1_c4>;
280 cpu_pd7: power-domain-cpu7 {
281 #power-domain-cells = <0>;
282 power-domains = <&cluster1_pd>;
283 domain-idle-states = <&cluster1_c4>;
286 cluster0_pd: power-domain-cluster0 {
287 #power-domain-cells = <0>;
288 domain-idle-states = <&cluster_cl5>;
289 power-domains = <&system_pd>;
292 cluster1_pd: power-domain-cluster1 {
293 #power-domain-cells = <0>;
294 domain-idle-states = <&cluster_cl5>;
295 power-domains = <&system_pd>;
298 system_pd: power-domain-system {
299 #power-domain-cells = <0>;
300 domain-idle-states = <&domain_ss3>;
304 reserved-memory {
305 #address-cells = <2>;
306 #size-cells = <2>;
309 gunyah_hyp_mem: gunyah-hyp@80000000 {
311 no-map;
314 cpusys_vm_mem: cpusys-vm-mem@80e00000 {
316 no-map;
321 no-map;
324 xbl_dtlog_mem: xbl-dtlog@81a00000 {
326 no-map;
329 aop_image_mem: aop-image@81c00000 {
331 no-map;
334 aop_cmd_db_mem: aop-cmd-db@81c60000 {
335 compatible = "qcom,cmd-db";
337 no-map;
341 aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 {
343 no-map;
352 no-map;
355 pdp_ns_shared_mem: pdp-ns-shared@81f00000 {
357 no-map;
360 cpucp_scandump_mem: cpucp-scandump@82000000 {
362 no-map;
365 adsp_mhi_mem: adsp-mhi@82380000 {
367 no-map;
370 soccp_sdi_mem: soccp-sdi@823a0000 {
372 no-map;
375 pmic_minii_dump_mem: pmic-minii-dump@823e0000 {
377 no-map;
382 no-map;
385 global_sync_mem: global-sync@82600000 {
387 no-map;
390 tz_stat_mem: tz-stat@82700000 {
392 no-map;
397 no-map;
400 dsm_partition_1_mem: dsm-partition-1@84a00000 {
402 no-map;
405 dsm_partition_2_mem: dsm-partition-2@89300000 {
407 no-map;
412 no-map;
415 q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 {
417 no-map;
420 ipa_fw_mem: ipa-fw@9b080000 {
422 no-map;
425 ipa_gsi_mem: ipa-gsi@9b090000 {
427 no-map;
430 gpu_micro_code_mem: gpu-micro-code@9b09a000 {
432 no-map;
437 no-map;
441 spu_tz_shared_mem: spu-tz-shared@9b280000 {
443 no-map;
447 spu_modem_shared_mem: spu-modem-shared@9b2c0000 {
449 no-map;
454 no-map;
457 camera_2_mem: camera-2@9bb00000 {
459 no-map;
464 no-map;
469 no-map;
474 no-map;
477 q6_cdsp_dtb_mem: q6-cdsp-dtb@9eb00000 {
479 no-map;
484 no-map;
487 q6_adsp_dtb_mem: q6-adsp-dtb@9ed80000 {
489 no-map;
494 no-map;
497 xbl_ramdump_mem: xbl-ramdump@b8000000 {
499 no-map;
502 hwfence_shbuf: hwfence-shbuf@d4e23000 {
503 no-map;
508 tz_merged_mem: tz-merged@d8000000 {
510 no-map;
513 trust_ui_vm_mem: trust-ui-vm@f3800000 {
515 no-map;
518 oem_vm_mem: oem-vm@f7c00000 {
520 no-map;
523 llcc_lpi_mem: llcc-lpi@ff800000 {
525 no-map;
529 smp2p-adsp {
532 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
540 qcom,local-pid = <0>;
541 qcom,remote-pid = <2>;
543 smp2p_adsp_out: master-kernel {
544 qcom,entry-name = "master-kernel";
545 #qcom,smem-state-cells = <1>;
548 smp2p_adsp_in: slave-kernel {
549 qcom,entry-name = "slave-kernel";
550 interrupt-controller;
551 #interrupt-cells = <2>;
555 smp2p-cdsp {
558 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
566 qcom,local-pid = <0>;
567 qcom,remote-pid = <5>;
569 smp2p_cdsp_out: master-kernel {
570 qcom,entry-name = "master-kernel";
571 #qcom,smem-state-cells = <1>;
574 smp2p_cdsp_in: slave-kernel {
575 qcom,entry-name = "slave-kernel";
576 interrupt-controller;
577 #interrupt-cells = <2>;
581 smp2p-modem {
584 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
592 qcom,local-pid = <0>;
593 qcom,remote-pid = <1>;
595 smp2p_modem_out: master-kernel {
596 qcom,entry-name = "master-kernel";
597 #qcom,smem-state-cells = <1>;
600 smp2p_modem_in: slave-kernel {
601 qcom,entry-name = "slave-kernel";
602 interrupt-controller;
603 #interrupt-cells = <2>;
606 ipa_smp2p_out: ipa-ap-to-modem {
607 qcom,entry-name = "ipa";
608 #qcom,smem-state-cells = <1>;
611 ipa_smp2p_in: ipa-modem-to-ap {
612 qcom,entry-name = "ipa";
613 interrupt-controller;
614 #interrupt-cells = <2>;
621 compatible = "simple-bus";
623 #address-cells = <2>;
624 #size-cells = <2>;
625 dma-ranges = <0 0 0 0 0x10 0>;
628 gcc: clock-controller@100000 {
629 compatible = "qcom,sm8750-gcc";
641 #clock-cells = <1>;
642 #reset-cells = <1>;
643 #power-domain-cells = <1>;
647 compatible = "qcom,sm8750-ipcc", "qcom,ipcc";
651 interrupt-controller;
652 #interrupt-cells = <3>;
654 #mbox-cells = <2>;
657 gpi_dma2: dma-controller@800000 {
658 compatible = "qcom,sm8750-gpi-dma", "qcom,sm6350-gpi-dma";
674 dma-channels = <12>;
675 dma-channel-mask = <0x1e>;
676 #dma-cells = <3>;
684 compatible = "qcom,geni-se-qup";
689 clock-names = "m-ahb",
690 "s-ahb";
694 #address-cells = <2>;
695 #size-cells = <2>;
701 compatible = "qcom,geni-i2c";
707 clock-names = "se";
715 interconnect-names = "qup-core",
716 "qup-config",
717 "qup-memory";
721 dma-names = "tx",
724 pinctrl-0 = <&qup_i2c8_data_clk>;
725 pinctrl-names = "default";
727 #address-cells = <1>;
728 #size-cells = <0>;
734 compatible = "qcom,geni-spi";
740 clock-names = "se";
748 interconnect-names = "qup-core",
749 "qup-config",
750 "qup-memory";
754 dma-names = "tx",
757 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
758 pinctrl-names = "default";
760 #address-cells = <1>;
761 #size-cells = <0>;
767 compatible = "qcom,geni-i2c";
773 clock-names = "se";
781 interconnect-names = "qup-core",
782 "qup-config",
783 "qup-memory";
787 dma-names = "tx",
790 pinctrl-0 = <&qup_i2c9_data_clk>;
791 pinctrl-names = "default";
793 #address-cells = <1>;
794 #size-cells = <0>;
800 compatible = "qcom,geni-spi";
806 clock-names = "se";
814 interconnect-names = "qup-core",
815 "qup-config",
816 "qup-memory";
820 dma-names = "tx",
823 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
824 pinctrl-names = "default";
826 #address-cells = <1>;
827 #size-cells = <0>;
833 compatible = "qcom,geni-i2c";
839 clock-names = "se";
847 interconnect-names = "qup-core",
848 "qup-config",
849 "qup-memory";
853 dma-names = "tx",
856 pinctrl-0 = <&qup_i2c10_data_clk>;
857 pinctrl-names = "default";
859 #address-cells = <1>;
860 #size-cells = <0>;
866 compatible = "qcom,geni-spi";
872 clock-names = "se";
880 interconnect-names = "qup-core",
881 "qup-config",
882 "qup-memory";
886 dma-names = "tx",
889 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
890 pinctrl-names = "default";
892 #address-cells = <1>;
893 #size-cells = <0>;
899 compatible = "qcom,geni-i2c";
905 clock-names = "se";
913 interconnect-names = "qup-core",
914 "qup-config",
915 "qup-memory";
919 dma-names = "tx",
922 pinctrl-0 = <&qup_i2c11_data_clk>;
923 pinctrl-names = "default";
925 #address-cells = <1>;
926 #size-cells = <0>;
932 compatible = "qcom,geni-spi";
938 clock-names = "se";
946 interconnect-names = "qup-core",
947 "qup-config",
948 "qup-memory";
952 dma-names = "tx",
955 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
956 pinctrl-names = "default";
958 #address-cells = <1>;
959 #size-cells = <0>;
965 compatible = "qcom,geni-i2c";
971 clock-names = "se";
979 interconnect-names = "qup-core",
980 "qup-config",
981 "qup-memory";
985 dma-names = "tx",
988 pinctrl-0 = <&qup_i2c12_data_clk>;
989 pinctrl-names = "default";
991 #address-cells = <1>;
992 #size-cells = <0>;
998 compatible = "qcom,geni-spi";
1004 clock-names = "se";
1012 interconnect-names = "qup-core",
1013 "qup-config",
1014 "qup-memory";
1018 dma-names = "tx",
1021 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1022 pinctrl-names = "default";
1024 #address-cells = <1>;
1025 #size-cells = <0>;
1031 compatible = "qcom,geni-i2c";
1037 clock-names = "se";
1045 interconnect-names = "qup-core",
1046 "qup-config",
1047 "qup-memory";
1051 dma-names = "tx",
1054 pinctrl-0 = <&qup_i2c13_data_clk>;
1055 pinctrl-names = "default";
1057 #address-cells = <1>;
1058 #size-cells = <0>;
1064 compatible = "qcom,geni-spi";
1070 clock-names = "se";
1078 interconnect-names = "qup-core",
1079 "qup-config",
1080 "qup-memory";
1084 dma-names = "tx",
1087 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1088 pinctrl-names = "default";
1090 #address-cells = <1>;
1091 #size-cells = <0>;
1097 compatible = "qcom,geni-uart";
1103 clock-names = "se";
1109 interconnect-names = "qup-core",
1110 "qup-config";
1112 pinctrl-0 = <&qup_uart14_default>;
1113 pinctrl-names = "default";
1119 compatible = "qcom,geni-i2c";
1125 clock-names = "se";
1133 interconnect-names = "qup-core",
1134 "qup-config",
1135 "qup-memory";
1139 dma-names = "tx",
1142 pinctrl-0 = <&qup_i2c15_data_clk>;
1143 pinctrl-names = "default";
1145 #address-cells = <1>;
1146 #size-cells = <0>;
1152 compatible = "qcom,geni-spi";
1158 clock-names = "se";
1166 interconnect-names = "qup-core",
1167 "qup-config",
1168 "qup-memory";
1172 dma-names = "tx",
1175 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1176 pinctrl-names = "default";
1178 #address-cells = <1>;
1179 #size-cells = <0>;
1186 compatible = "qcom,geni-se-i2c-master-hub";
1190 clock-names = "s-ahb";
1192 #address-cells = <2>;
1193 #size-cells = <2>;
1199 compatible = "qcom,geni-i2c-master-hub";
1206 clock-names = "se",
1213 interconnect-names = "qup-core",
1214 "qup-config";
1216 pinctrl-0 = <&hub_i2c0_data_clk>;
1217 pinctrl-names = "default";
1219 #address-cells = <1>;
1220 #size-cells = <0>;
1226 compatible = "qcom,geni-i2c-master-hub";
1233 clock-names = "se",
1240 interconnect-names = "qup-core",
1241 "qup-config";
1243 pinctrl-0 = <&hub_i2c1_data_clk>;
1244 pinctrl-names = "default";
1246 #address-cells = <1>;
1247 #size-cells = <0>;
1253 compatible = "qcom,geni-i2c-master-hub";
1260 clock-names = "se",
1267 interconnect-names = "qup-core",
1268 "qup-config";
1270 pinctrl-0 = <&hub_i2c2_data_clk>;
1271 pinctrl-names = "default";
1273 #address-cells = <1>;
1274 #size-cells = <0>;
1280 compatible = "qcom,geni-i2c-master-hub";
1287 clock-names = "se",
1294 interconnect-names = "qup-core",
1295 "qup-config";
1297 pinctrl-0 = <&hub_i2c3_data_clk>;
1298 pinctrl-names = "default";
1300 #address-cells = <1>;
1301 #size-cells = <0>;
1307 compatible = "qcom,geni-i2c-master-hub";
1314 clock-names = "se",
1321 interconnect-names = "qup-core",
1322 "qup-config";
1324 pinctrl-0 = <&hub_i2c4_data_clk>;
1325 pinctrl-names = "default";
1327 #address-cells = <1>;
1328 #size-cells = <0>;
1334 compatible = "qcom,geni-i2c-master-hub";
1341 clock-names = "se",
1348 interconnect-names = "qup-core",
1349 "qup-config";
1351 pinctrl-0 = <&hub_i2c5_data_clk>;
1352 pinctrl-names = "default";
1354 #address-cells = <1>;
1355 #size-cells = <0>;
1361 compatible = "qcom,geni-i2c-master-hub";
1368 clock-names = "se",
1375 interconnect-names = "qup-core",
1376 "qup-config";
1378 pinctrl-0 = <&hub_i2c6_data_clk>;
1379 pinctrl-names = "default";
1381 #address-cells = <1>;
1382 #size-cells = <0>;
1388 compatible = "qcom,geni-i2c-master-hub";
1395 clock-names = "se",
1402 interconnect-names = "qup-core",
1403 "qup-config";
1405 pinctrl-0 = <&hub_i2c7_data_clk>;
1406 pinctrl-names = "default";
1408 #address-cells = <1>;
1409 #size-cells = <0>;
1415 compatible = "qcom,geni-i2c-master-hub";
1422 clock-names = "se",
1429 interconnect-names = "qup-core",
1430 "qup-config";
1432 pinctrl-0 = <&hub_i2c8_data_clk>;
1433 pinctrl-names = "default";
1435 #address-cells = <1>;
1436 #size-cells = <0>;
1442 compatible = "qcom,geni-i2c-master-hub";
1449 clock-names = "se",
1456 interconnect-names = "qup-core",
1457 "qup-config";
1459 pinctrl-0 = <&hub_i2c9_data_clk>;
1460 pinctrl-names = "default";
1462 #address-cells = <1>;
1463 #size-cells = <0>;
1469 gpi_dma1: dma-controller@a00000 {
1470 compatible = "qcom,sm8750-gpi-dma", "qcom,sm6350-gpi-dma";
1486 dma-channels = <12>;
1487 dma-channel-mask = <0x1e>;
1488 #dma-cells = <3>;
1496 compatible = "qcom,geni-se-qup";
1501 clock-names = "m-ahb",
1502 "s-ahb";
1506 #address-cells = <2>;
1507 #size-cells = <2>;
1513 compatible = "qcom,geni-i2c";
1519 clock-names = "se";
1527 interconnect-names = "qup-core",
1528 "qup-config",
1529 "qup-memory";
1533 dma-names = "tx",
1536 pinctrl-0 = <&qup_i2c0_data_clk>;
1537 pinctrl-names = "default";
1539 #address-cells = <1>;
1540 #size-cells = <0>;
1546 compatible = "qcom,geni-spi";
1552 clock-names = "se";
1560 interconnect-names = "qup-core",
1561 "qup-config",
1562 "qup-memory";
1566 dma-names = "tx",
1569 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1570 pinctrl-names = "default";
1572 #address-cells = <1>;
1573 #size-cells = <0>;
1579 compatible = "qcom,geni-i2c";
1585 clock-names = "se";
1593 interconnect-names = "qup-core",
1594 "qup-config",
1595 "qup-memory";
1599 dma-names = "tx",
1602 pinctrl-0 = <&qup_i2c1_data_clk>;
1603 pinctrl-names = "default";
1605 #address-cells = <1>;
1606 #size-cells = <0>;
1612 compatible = "qcom,geni-spi";
1618 clock-names = "se";
1626 interconnect-names = "qup-core",
1627 "qup-config",
1628 "qup-memory";
1632 dma-names = "tx",
1635 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1636 pinctrl-names = "default";
1638 #address-cells = <1>;
1639 #size-cells = <0>;
1645 compatible = "qcom,geni-i2c";
1651 clock-names = "se";
1659 interconnect-names = "qup-core",
1660 "qup-config",
1661 "qup-memory";
1665 dma-names = "tx",
1668 pinctrl-0 = <&qup_i2c2_data_clk>;
1669 pinctrl-names = "default";
1671 #address-cells = <1>;
1672 #size-cells = <0>;
1678 compatible = "qcom,geni-spi";
1684 clock-names = "se";
1692 interconnect-names = "qup-core",
1693 "qup-config",
1694 "qup-memory";
1698 dma-names = "tx",
1701 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1702 pinctrl-names = "default";
1704 #address-cells = <1>;
1705 #size-cells = <0>;
1711 compatible = "qcom,geni-i2c";
1717 clock-names = "se";
1725 interconnect-names = "qup-core",
1726 "qup-config",
1727 "qup-memory";
1731 dma-names = "tx",
1734 pinctrl-0 = <&qup_i2c3_data_clk>;
1735 pinctrl-names = "default";
1737 #address-cells = <1>;
1738 #size-cells = <0>;
1744 compatible = "qcom,geni-spi";
1750 clock-names = "se";
1758 interconnect-names = "qup-core",
1759 "qup-config",
1760 "qup-memory";
1764 dma-names = "tx",
1767 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1768 pinctrl-names = "default";
1770 #address-cells = <1>;
1771 #size-cells = <0>;
1777 compatible = "qcom,geni-i2c";
1783 clock-names = "se";
1791 interconnect-names = "qup-core",
1792 "qup-config",
1793 "qup-memory";
1797 dma-names = "tx",
1800 pinctrl-0 = <&qup_i2c4_data_clk>;
1801 pinctrl-names = "default";
1803 #address-cells = <1>;
1804 #size-cells = <0>;
1810 compatible = "qcom,geni-spi";
1816 clock-names = "se";
1824 interconnect-names = "qup-core",
1825 "qup-config",
1826 "qup-memory";
1830 dma-names = "tx",
1833 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1834 pinctrl-names = "default";
1836 #address-cells = <1>;
1837 #size-cells = <0>;
1843 compatible = "qcom,geni-i2c";
1849 clock-names = "se";
1857 interconnect-names = "qup-core",
1858 "qup-config",
1859 "qup-memory";
1863 dma-names = "tx",
1866 pinctrl-0 = <&qup_i2c5_data_clk>;
1867 pinctrl-names = "default";
1869 #address-cells = <1>;
1870 #size-cells = <0>;
1876 compatible = "qcom,geni-spi";
1882 clock-names = "se";
1890 interconnect-names = "qup-core",
1891 "qup-config",
1892 "qup-memory";
1896 dma-names = "tx",
1899 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1900 pinctrl-names = "default";
1902 #address-cells = <1>;
1903 #size-cells = <0>;
1909 compatible = "qcom,geni-i2c";
1915 clock-names = "se";
1923 interconnect-names = "qup-core",
1924 "qup-config",
1925 "qup-memory";
1929 dma-names = "tx",
1932 pinctrl-0 = <&qup_i2c6_data_clk>;
1933 pinctrl-names = "default";
1935 #address-cells = <1>;
1936 #size-cells = <0>;
1942 compatible = "qcom,geni-spi";
1948 clock-names = "se";
1956 interconnect-names = "qup-core",
1957 "qup-config",
1958 "qup-memory";
1962 dma-names = "tx",
1965 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1966 pinctrl-names = "default";
1968 #address-cells = <1>;
1969 #size-cells = <0>;
1975 compatible = "qcom,geni-debug-uart";
1981 clock-names = "se";
1987 interconnect-names = "qup-core",
1988 "qup-config";
1990 pinctrl-0 = <&qup_uart7_default>;
1991 pinctrl-names = "default";
1998 compatible = "qcom,sm8750-trng", "qcom,trng";
2003 compatible = "qcom,sm8750-cnoc-main";
2005 qcom,bcm-voters = <&apps_bcm_voter>;
2006 #interconnect-cells = <2>;
2010 compatible = "qcom,sm8750-config-noc";
2012 qcom,bcm-voters = <&apps_bcm_voter>;
2013 #interconnect-cells = <2>;
2017 compatible = "qcom,sm8750-system-noc";
2019 qcom,bcm-voters = <&apps_bcm_voter>;
2020 #interconnect-cells = <2>;
2024 compatible = "qcom,sm8750-pcie-anoc";
2026 qcom,bcm-voters = <&apps_bcm_voter>;
2027 #interconnect-cells = <2>;
2033 compatible = "qcom,sm8750-aggre1-noc";
2035 qcom,bcm-voters = <&apps_bcm_voter>;
2036 #interconnect-cells = <2>;
2042 compatible = "qcom,sm8750-aggre2-noc";
2044 qcom,bcm-voters = <&apps_bcm_voter>;
2045 #interconnect-cells = <2>;
2050 compatible = "qcom,sm8750-mmss-noc";
2052 qcom,bcm-voters = <&apps_bcm_voter>;
2053 #interconnect-cells = <2>;
2057 compatible = "qcom,sm8750-inline-crypto-engine",
2058 "qcom,inline-crypto-engine";
2064 cryptobam: dma-controller@1dc4000 {
2065 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2070 #dma-cells = <1>;
2076 qcom,controlled-remotely;
2080 compatible = "qcom,sm8750-qce", "qcom,sm8150-qce", "qcom,qce";
2085 interconnect-names = "memory";
2088 dma-names = "rx", "tx";
2095 compatible = "qcom,tcsr-mutex";
2097 #hwlock-cells = <1>;
2101 compatible = "qcom,sm8750-mpss-pas";
2104 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2110 interrupt-names = "wdog",
2114 "stop-ack",
2115 "shutdown-ack";
2118 clock-names = "xo";
2123 power-domains = <&rpmhpd RPMHPD_CX>,
2125 power-domain-names = "cx",
2128 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>,
2134 qcom,smem-states = <&smp2p_modem_out 0>;
2135 qcom,smem-state-names = "stop";
2139 glink-edge {
2140 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2147 qcom,remote-pid = <1>;
2154 compatible = "qcom,sm8750-adsp-pas", "qcom,sm8550-adsp-pas";
2157 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2163 interrupt-names = "wdog",
2167 "stop-ack",
2168 "shutdown-ack";
2171 clock-names = "xo";
2176 power-domains = <&rpmhpd RPMHPD_LCX>,
2178 power-domain-names = "lcx",
2181 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
2185 qcom,smem-states = <&smp2p_adsp_out 0>;
2186 qcom,smem-state-names = "stop";
2190 remoteproc_adsp_glink: glink-edge {
2191 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2196 qcom,remote-pid = <2>;
2201 qcom,glink-channels = "adsp_apps";
2204 #address-cells = <1>;
2205 #size-cells = <0>;
2210 #sound-dai-cells = <0>;
2211 qcom,protection-domain = "avs/audio",
2215 compatible = "qcom,q6apm-lpass-dais";
2216 #sound-dai-cells = <1>;
2220 compatible = "qcom,q6apm-dais";
2229 qcom,protection-domain = "avs/audio",
2232 q6prmcc: clock-controller {
2233 compatible = "qcom,q6prm-lpass-clocks";
2234 #clock-cells = <2>;
2242 compatible = "qcom,sm8750-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
2248 clock-names = "mclk",
2253 #clock-cells = <0>;
2254 clock-output-names = "wsa2-mclk";
2255 #sound-dai-cells = <1>;
2259 compatible = "qcom,soundwire-v2.1.0", "qcom,soundwire-v2.0.0";
2263 clock-names = "iface";
2266 pinctrl-0 = <&wsa2_swr_active>;
2267 pinctrl-names = "default";
2269 qcom,din-ports = <4>;
2270 qcom,dout-ports = <9>;
2272 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0x18f 0x18f 0x0f 0x0f 0xff …
2273 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0x00 0x00 0x06 0x0d 0xff 0x00>;
2274 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2275 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>;
2276 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>;
2277 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0f 0x0f 0x00 0xff 0xff 0x1…
2278 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x01 0x00…
2279 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0x…
2280 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0x…
2282 #address-cells = <2>;
2283 #size-cells = <0>;
2284 #sound-dai-cells = <1>;
2289 compatible = "qcom,sm8750-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro";
2295 clock-names = "mclk",
2300 #clock-cells = <0>;
2301 clock-output-names = "mclk";
2302 #sound-dai-cells = <1>;
2306 compatible = "qcom,soundwire-v2.1.0", "qcom,soundwire-v2.0.0";
2310 clock-names = "iface";
2313 pinctrl-0 = <&rx_swr_active>;
2314 pinctrl-names = "default";
2316 qcom,din-ports = <1>;
2317 qcom,dout-ports = <11>;
2319 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0x31 0xff 0xff 0xff>;
2320 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>;
2321 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>;
2322 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0x00 0xff 0xff 0xff>;
2323 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0x0f 0xff 0xff 0xff>;
2324 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0x18 0xff 0xff 0xff>;
2325 …qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0x01 0xff 0xff 0xff…
2326 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0x…
2327 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0xff 0xff 0xff>;
2329 #address-cells = <2>;
2330 #size-cells = <0>;
2331 #sound-dai-cells = <1>;
2336 compatible = "qcom,sm8750-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro";
2342 clock-names = "mclk",
2347 #clock-cells = <0>;
2348 clock-output-names = "mclk";
2349 #sound-dai-cells = <1>;
2353 compatible = "qcom,sm8750-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
2359 clock-names = "mclk",
2364 #clock-cells = <0>;
2365 clock-output-names = "mclk";
2366 #sound-dai-cells = <1>;
2370 compatible = "qcom,soundwire-v2.1.0", "qcom,soundwire-v2.0.0";
2374 clock-names = "iface";
2377 pinctrl-0 = <&wsa_swr_active>;
2378 pinctrl-names = "default";
2380 qcom,din-ports = <4>;
2381 qcom,dout-ports = <9>;
2383 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0x18f 0x18f 0x0f 0x0f 0xff …
2384 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0x00 0x00 0x06 0x0d 0xff 0x00>;
2385 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2386 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>;
2387 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>;
2388 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0f 0x0f 0x00 0xff 0xff 0x1…
2389 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x01 0x00…
2390 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0x…
2391 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0x…
2393 #address-cells = <2>;
2394 #size-cells = <0>;
2395 #sound-dai-cells = <1>;
2400 compatible = "qcom,sm8750-lpass-ag-noc";
2402 qcom,bcm-voters = <&apps_bcm_voter>;
2403 #interconnect-cells = <2>;
2407 compatible = "qcom,sm8750-lpass-lpiaon-noc";
2409 qcom,bcm-voters = <&apps_bcm_voter>;
2410 #interconnect-cells = <2>;
2414 compatible = "qcom,sm8750-lpass-lpicx-noc";
2416 qcom,bcm-voters = <&apps_bcm_voter>;
2417 #interconnect-cells = <2>;
2421 compatible = "qcom,soundwire-v2.1.0", "qcom,soundwire-v2.0.0";
2425 interrupt-names = "core", "wakeup";
2427 clock-names = "iface";
2430 pinctrl-0 = <&tx_swr_active>;
2431 pinctrl-names = "default";
2433 qcom,din-ports = <4>;
2434 qcom,dout-ports = <0>;
2436 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2437 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2438 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2439 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2440 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2441 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2442 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2443 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2444 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2446 #address-cells = <2>;
2447 #size-cells = <0>;
2448 #sound-dai-cells = <1>;
2453 compatible = "qcom,sm8750-lpass-va-macro", "qcom,sm8550-lpass-va-macro";
2458 clock-names = "mclk",
2462 #clock-cells = <0>;
2463 clock-output-names = "fsgen";
2464 #sound-dai-cells = <1>;
2468 compatible = "qcom,sm8750-lpass-lpi-pinctrl",
2469 "qcom,sm8650-lpass-lpi-pinctrl";
2474 clock-names = "core", "audio";
2476 gpio-controller;
2477 #gpio-cells = <2>;
2478 gpio-ranges = <&lpass_tlmm 0 0 23>;
2480 tx_swr_active: tx-swr-active-state {
2481 clk-pins {
2484 drive-strength = <2>;
2485 slew-rate = <1>;
2486 bias-disable;
2489 data-pins {
2492 drive-strength = <2>;
2493 slew-rate = <1>;
2494 bias-bus-hold;
2498 rx_swr_active: rx-swr-active-state {
2499 clk-pins {
2502 drive-strength = <2>;
2503 slew-rate = <1>;
2504 bias-disable;
2507 data-pins {
2510 drive-strength = <2>;
2511 slew-rate = <1>;
2512 bias-bus-hold;
2516 dmic01_default: dmic01-default-state {
2517 clk-pins {
2520 drive-strength = <8>;
2521 output-high;
2524 data-pins {
2527 drive-strength = <8>;
2528 input-enable;
2532 dmic23_default: dmic23-default-state {
2533 clk-pins {
2536 drive-strength = <8>;
2537 output-high;
2540 data-pins {
2543 drive-strength = <8>;
2544 input-enable;
2548 wsa_swr_active: wsa-swr-active-state {
2549 clk-pins {
2552 drive-strength = <2>;
2553 slew-rate = <1>;
2554 bias-disable;
2557 data-pins {
2560 drive-strength = <2>;
2561 slew-rate = <1>;
2562 bias-bus-hold;
2566 wsa2_swr_active: wsa2-swr-active-state {
2567 clk-pins {
2570 drive-strength = <2>;
2571 slew-rate = <1>;
2572 bias-disable;
2575 data-pins {
2578 drive-strength = <2>;
2579 slew-rate = <1>;
2580 bias-bus-hold;
2586 compatible = "qcom,sm8750-m31-eusb2-phy";
2590 clock-names = "ref";
2594 #phy-cells = <0>;
2600 compatible = "qcom,sm8750-qmp-usb3-dp-phy";
2607 clock-names = "aux",
2614 reset-names = "phy",
2617 power-domains = <&gcc GCC_USB3_PHY_GDSC>;
2619 #clock-cells = <1>;
2620 #phy-cells = <1>;
2622 orientation-switch;
2627 #address-cells = <1>;
2628 #size-cells = <0>;
2641 remote-endpoint = <&usb_dwc3_ss>;
2655 compatible = "qcom,sm8750-dwc3", "qcom,snps-dwc3";
2663 clock-names = "cfg_noc",
2669 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2671 assigned-clock-rates = <19200000>,
2674 interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
2675 <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
2676 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2677 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
2678 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
2679 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
2680 interrupt-names = "dwc_usb3",
2687 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
2688 required-opps = <&rpmhpd_opp_nom>;
2696 interconnect-names = "usb-ddr", "apps-usb";
2702 phy-names = "usb2-phy",
2703 "usb3-phy";
2705 snps,hird-threshold = /bits/ 8 <0x0>;
2706 snps,usb2-gadget-lpm-disable;
2709 snps,dis-u1-entry-quirk;
2710 snps,dis-u2-entry-quirk;
2711 snps,is-utmi-l1-suspend;
2713 snps,usb2-lpm-disable;
2714 snps,has-lpm-erratum;
2715 tx-fifo-resize;
2717 dma-coherent;
2718 usb-role-switch;
2723 #address-cells = <1>;
2724 #size-cells = <0>;
2737 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
2743 pdc: interrupt-controller@b220000 { label
2744 compatible = "qcom,sm8750-pdc", "qcom,pdc";
2747 qcom,pdc-ranges = <0 745 51>, <51 527 47>,
2750 #interrupt-cells = <2>;
2751 interrupt-parent = <&intc>;
2752 interrupt-controller;
2755 aoss_qmp: power-management@c300000 {
2756 compatible = "qcom,sm8750-aoss-qmp", "qcom,aoss-qmp";
2759 interrupt-parent = <&ipcc>;
2760 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
2765 #clock-cells = <0>;
2769 compatible = "qcom,rpmh-stats";
2775 compatible = "qcom,spmi-pmic-arb";
2781 reg-names = "core",
2787 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2788 interrupt-names = "periph_irq";
2792 qcom,bus-id = <0>;
2794 interrupt-controller;
2795 #interrupt-cells = <4>;
2797 #address-cells = <2>;
2798 #size-cells = <0>;
2802 compatible = "qcom,sm8750-tlmm";
2807 gpio-controller;
2808 #gpio-cells = <2>;
2810 interrupt-controller;
2811 #interrupt-cells = <2>;
2813 gpio-ranges = <&tlmm 0 0 216>;
2814 wakeup-parent = <&pdc>;
2816 hub_i2c0_data_clk: hub-i2c0-data-clk-state {
2820 drive-strength = <2>;
2821 bias-pull-up;
2824 hub_i2c1_data_clk: hub-i2c1-data-clk-state {
2828 drive-strength = <2>;
2829 bias-pull-up;
2832 hub_i2c2_data_clk: hub-i2c2-data-clk-state {
2836 drive-strength = <2>;
2837 bias-pull-up;
2840 hub_i2c3_data_clk: hub-i2c3-data-clk-state {
2844 drive-strength = <2>;
2845 bias-pull-up;
2848 hub_i2c4_data_clk: hub-i2c4-data-clk-state {
2852 drive-strength = <2>;
2853 bias-pull-up;
2856 hub_i2c5_data_clk: hub-i2c5-data-clk-state {
2860 drive-strength = <2>;
2861 bias-pull-up;
2864 hub_i2c6_data_clk: hub-i2c6-data-clk-state {
2868 drive-strength = <2>;
2869 bias-pull-up;
2872 hub_i2c7_data_clk: hub-i2c7-data-clk-state {
2876 drive-strength = <2>;
2877 bias-pull-up;
2880 hub_i2c8_data_clk: hub-i2c8-data-clk-state {
2884 drive-strength = <2>;
2885 bias-pull-up;
2888 hub_i2c9_data_clk: hub-i2c9-data-clk-state {
2892 drive-strength = <2>;
2893 bias-pull-up;
2896 pcie0_default_state: pcie0-default-state {
2897 perst-pins {
2900 drive-strength = <2>;
2901 bias-pull-down;
2904 clkreq-pins {
2907 drive-strength = <2>;
2908 bias-pull-up;
2911 wake-pins {
2914 drive-strength = <2>;
2915 bias-pull-up;
2919 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
2923 drive-strength = <2>;
2924 bias-pull-up;
2927 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
2931 drive-strength = <2>;
2932 bias-pull-up;
2935 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
2939 drive-strength = <2>;
2940 bias-pull-up;
2943 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
2947 drive-strength = <2>;
2948 bias-pull-up;
2951 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
2955 drive-strength = <2>;
2956 bias-pull-up;
2959 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
2963 drive-strength = <2>;
2964 bias-pull-up;
2967 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
2971 drive-strength = <2>;
2972 bias-pull-up;
2975 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
2979 drive-strength = <2>;
2980 bias-pull-up;
2983 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
2987 drive-strength = <2>;
2988 bias-pull-up;
2991 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
2995 drive-strength = <2>;
2996 bias-pull-up;
2999 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3003 drive-strength = <2>;
3004 bias-pull-up;
3007 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3011 drive-strength = <2>;
3012 bias-pull-up;
3015 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3019 drive-strength = <2>;
3020 bias-pull-up;
3023 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3027 drive-strength = <2>;
3028 bias-pull-up;
3031 qup_spi0_cs: qup-spi0-cs-state {
3034 drive-strength = <6>;
3035 bias-disable;
3038 qup_spi0_data_clk: qup-spi0-data-clk-state {
3042 drive-strength = <6>;
3043 bias-disable;
3046 qup_spi1_cs: qup-spi1-cs-state {
3049 drive-strength = <6>;
3050 bias-disable;
3053 qup_spi1_data_clk: qup-spi1-data-clk-state {
3057 drive-strength = <6>;
3058 bias-disable;
3061 qup_spi2_cs: qup-spi2-cs-state {
3064 drive-strength = <6>;
3065 bias-disable;
3068 qup_spi2_data_clk: qup-spi2-data-clk-state {
3072 drive-strength = <6>;
3073 bias-disable;
3076 qup_spi3_cs: qup-spi3-cs-state {
3079 drive-strength = <6>;
3080 bias-disable;
3083 qup_spi3_data_clk: qup-spi3-data-clk-state {
3087 drive-strength = <6>;
3088 bias-disable;
3091 qup_spi4_cs: qup-spi4-cs-state {
3094 drive-strength = <6>;
3095 bias-disable;
3098 qup_spi4_data_clk: qup-spi4-data-clk-state {
3102 drive-strength = <6>;
3103 bias-disable;
3106 qup_spi5_cs: qup-spi5-cs-state {
3109 drive-strength = <6>;
3110 bias-disable;
3113 qup_spi5_data_clk: qup-spi5-data-clk-state {
3117 drive-strength = <6>;
3118 bias-disable;
3121 qup_spi6_cs: qup-spi6-cs-state {
3124 drive-strength = <6>;
3125 bias-disable;
3128 qup_spi6_data_clk: qup-spi6-data-clk-state {
3132 drive-strength = <6>;
3133 bias-disable;
3136 qup_spi8_cs: qup-spi8-cs-state {
3139 drive-strength = <6>;
3140 bias-disable;
3143 qup_spi8_data_clk: qup-spi8-data-clk-state {
3147 drive-strength = <6>;
3148 bias-disable;
3151 qup_spi9_cs: qup-spi9-cs-state {
3154 drive-strength = <6>;
3155 bias-disable;
3158 qup_spi9_data_clk: qup-spi9-data-clk-state {
3162 drive-strength = <6>;
3163 bias-disable;
3166 qup_spi10_cs: qup-spi10-cs-state {
3169 drive-strength = <6>;
3170 bias-disable;
3173 qup_spi10_data_clk: qup-spi10-data-clk-state {
3177 drive-strength = <6>;
3178 bias-disable;
3181 qup_spi11_cs: qup-spi11-cs-state {
3184 drive-strength = <6>;
3185 bias-disable;
3188 qup_spi11_data_clk: qup-spi11-data-clk-state {
3192 drive-strength = <6>;
3193 bias-disable;
3196 qup_spi12_cs: qup-spi12-cs-state {
3199 drive-strength = <6>;
3200 bias-disable;
3203 qup_spi12_data_clk: qup-spi12-data-clk-state {
3207 drive-strength = <6>;
3208 bias-disable;
3211 qup_spi13_cs: qup-spi13-cs-state {
3214 drive-strength = <6>;
3215 bias-pull-up;
3218 qup_spi13_data_clk: qup-spi13-data-clk-state {
3222 drive-strength = <6>;
3223 bias-disable;
3226 qup_spi15_cs: qup-spi15-cs-state {
3229 drive-strength = <6>;
3230 bias-disable;
3233 qup_spi15_data_clk: qup-spi15-data-clk-state {
3237 drive-strength = <6>;
3238 bias-disable;
3241 qup_uart7_default: qup-uart7-default-state {
3245 drive-strength = <2>;
3246 bias-disable;
3249 qup_uart14_default: qup-uart14-default-state {
3253 drive-strength = <2>;
3254 bias-pull-up;
3257 qup_uart14_cts_rts: qup-uart14-cts-rts-state {
3261 drive-strength = <2>;
3262 bias-pull-down;
3265 sdc2_sleep: sdc2-sleep-state {
3266 clk-pins {
3268 drive-strength = <2>;
3269 bias-disable;
3272 cmd-pins {
3274 drive-strength = <2>;
3275 bias-pull-up;
3278 data-pins {
3280 drive-strength = <2>;
3281 bias-pull-up;
3285 sdc2_default: sdc2-default-state {
3286 clk-pins {
3288 drive-strength = <16>;
3289 bias-disable;
3292 cmd-pins {
3294 drive-strength = <10>;
3295 bias-pull-up;
3298 data-pins {
3300 drive-strength = <10>;
3301 bias-pull-up;
3306 tcsrcc: clock-controller@f204008 {
3307 compatible = "qcom,sm8750-tcsr", "syscon";
3312 #clock-cells = <1>;
3313 #reset-cells = <1>;
3317 compatible = "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500";
3434 #iommu-cells = <2>;
3435 #global-interrupts = <1>;
3437 dma-coherent;
3440 intc: interrupt-controller@16000000 { label
3441 compatible = "arm,gic-v3";
3447 #interrupt-cells = <3>;
3448 interrupt-controller;
3450 #redistributor-regions = <1>;
3451 redistributor-stride = <0x0 0x40000>;
3453 #address-cells = <2>;
3454 #size-cells = <2>;
3457 gic_its: msi-controller@16040000 {
3458 compatible = "arm,gic-v3-its";
3461 msi-controller;
3462 #msi-cells = <1>;
3468 compatible = "qcom,pcie-sm8750", "qcom,pcie-sm8550";
3475 reg-names = "parf",
3482 #address-cells = <3>;
3483 #size-cells = <2>;
3487 bus-range = <0x00 0xff>;
3489 dma-coherent;
3491 linux,pci-domain = <0>;
3493 msi-map = <0x0 &gic_its 0x1400 0x1>,
3495 msi-map-mask = <0xff00>;
3497 num-lanes = <2>;
3508 interrupt-names = "msi0",
3518 #interrupt-cells = <1>;
3519 interrupt-map-mask = <0 0 0 0x7>;
3520 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
3521 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
3522 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
3523 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
3533 clock-names = "aux",
3546 interconnect-names = "pcie-mem",
3547 "cpu-pcie";
3549 iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
3553 reset-names = "pci";
3555 power-domains = <&gcc GCC_PCIE_0_GDSC>;
3557 operating-points-v2 = <&pcie0_opp_table>;
3561 pcie0_opp_table: opp-table {
3562 compatible = "operating-points-v2";
3565 opp-2500000 {
3566 opp-hz = /bits/ 64 <2500000>;
3567 required-opps = <&rpmhpd_opp_low_svs>;
3568 opp-peak-kBps = <250000 1>;
3572 opp-5000000 {
3573 opp-hz = /bits/ 64 <5000000>;
3574 required-opps = <&rpmhpd_opp_low_svs>;
3575 opp-peak-kBps = <500000 1>;
3579 opp-10000000 {
3580 opp-hz = /bits/ 64 <10000000>;
3581 required-opps = <&rpmhpd_opp_low_svs>;
3582 opp-peak-kBps = <1000000 1>;
3586 opp-8000000 {
3587 opp-hz = /bits/ 64 <8000000>;
3588 required-opps = <&rpmhpd_opp_nom>;
3589 opp-peak-kBps = <984500 1>;
3593 opp-16000000 {
3594 opp-hz = /bits/ 64 <16000000>;
3595 required-opps = <&rpmhpd_opp_nom>;
3596 opp-peak-kBps = <1969000 1>;
3604 bus-range = <0x01 0xff>;
3606 #address-cells = <3>;
3607 #size-cells = <2>;
3614 compatible = "qcom,sm8750-qmp-gen3x2-pcie-phy";
3622 clock-names = "aux",
3628 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
3629 assigned-clock-rates = <100000000>;
3632 reset-names = "phy";
3634 power-domains = <&gcc GCC_PCIE_0_PHY_GDSC>;
3636 #clock-cells = <0>;
3637 clock-output-names = "pcie0_pipe_clk";
3639 #phy-cells = <0>;
3645 compatible = "qcom,sm8750-qmp-ufs-phy";
3652 clock-names = "ref",
3657 reset-names = "ufsphy";
3659 power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>;
3661 #clock-cells = <1>;
3662 #phy-cells = <0>;
3668 compatible = "qcom,sm8750-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
3681 clock-names = "core_clk",
3690 operating-points-v2 = <&ufs_opp_table>;
3693 reset-names = "rst";
3699 interconnect-names = "ufs-ddr",
3700 "cpu-ufs";
3702 power-domains = <&gcc GCC_UFS_PHY_GDSC>;
3703 required-opps = <&rpmhpd_opp_nom>;
3706 dma-coherent;
3708 lanes-per-direction = <2>;
3711 phy-names = "ufsphy";
3713 #reset-cells = <1>;
3717 ufs_opp_table: opp-table {
3718 compatible = "operating-points-v2";
3720 opp-100000000 {
3721 opp-hz = /bits/ 64 <100000000>,
3729 required-opps = <&rpmhpd_opp_low_svs>;
3732 opp-403000000 {
3733 opp-hz = /bits/ 64 <403000000>,
3741 required-opps = <&rpmhpd_opp_nom>;
3747 compatible = "qcom,rpmh-rsc";
3751 reg-names = "drv-0",
3752 "drv-1",
3753 "drv-2";
3758 qcom,tcs-offset = <0xd00>;
3759 qcom,drv-id = <2>;
3760 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
3765 power-domains = <&system_pd>;
3767 apps_bcm_voter: bcm-voter {
3768 compatible = "qcom,bcm-voter";
3771 rpmhcc: clock-controller {
3772 compatible = "qcom,sm8750-rpmh-clk";
3775 clock-names = "xo";
3777 #clock-cells = <1>;
3780 rpmhpd: power-controller {
3781 compatible = "qcom,sm8750-rpmhpd";
3783 operating-points-v2 = <&rpmhpd_opp_table>;
3785 #power-domain-cells = <1>;
3787 rpmhpd_opp_table: opp-table {
3788 compatible = "operating-points-v2";
3790 rpmhpd_opp_ret: opp-16 {
3791 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3794 rpmhpd_opp_min_svs: opp-48 {
3795 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3798 rpmhpd_opp_low_svs_d3: opp-50 {
3799 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>;
3802 rpmhpd_opp_low_svs_d2: opp-52 {
3803 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
3806 rpmhpd_opp_low_svs_d1: opp-56 {
3807 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
3810 rpmhpd_opp_low_svs_d0: opp-60 {
3811 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
3814 rpmhpd_opp_low_svs: opp-64 {
3815 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3818 rpmhpd_opp_low_svs_l1: opp-80 {
3819 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
3822 rpmhpd_opp_svs: opp-128 {
3823 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3826 rpmhpd_opp_svs_l0: opp-144 {
3827 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
3830 rpmhpd_opp_svs_l1: opp-192 {
3831 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3834 rpmhpd_opp_svs_l2: opp-224 {
3835 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
3838 rpmhpd_opp_nom: opp-256 {
3839 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3842 rpmhpd_opp_nom_l1: opp-320 {
3843 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3846 rpmhpd_opp_nom_l2: opp-336 {
3847 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3850 rpmhpd_opp_turbo: opp-384 {
3851 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3854 rpmhpd_opp_turbo_l1: opp-416 {
3855 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3858 rpmhpd_opp_turbo_l2: opp-432 {
3859 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
3862 rpmhpd_opp_turbo_l3: opp-448 {
3863 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
3866 rpmhpd_opp_turbo_l4: opp-452 {
3867 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
3870 rpmhpd_opp_super_turbo_no_cpr: opp-480 {
3871 opp-level =
3879 compatible = "arm,armv7-timer-mem";
3882 #address-cells = <2>;
3883 #size-cells = <1>;
3893 frame-number = <0>;
3901 frame-number = <1>;
3911 frame-number = <2>;
3921 frame-number = <3>;
3931 frame-number = <4>;
3941 frame-number = <5>;
3951 frame-number = <6>;
3959 compatible = "qcom,sm8750-cpu-bwmon", "qcom,sdm845-bwmon";
3967 operating-points-v2 = <&cpu_bwmon_opp_table>;
3969 nonposted-mmio;
3971 cpu_bwmon_opp_table: opp-table {
3972 compatible = "operating-points-v2";
3974 opp-0 {
3975 opp-peak-kBps = <800000>;
3978 opp-1 {
3979 opp-peak-kBps = <2188000>;
3982 opp-2 {
3983 opp-peak-kBps = <5414400>;
3986 opp-3 {
3987 opp-peak-kBps = <6220800>;
3990 opp-4 {
3991 opp-peak-kBps = <6835200>;
3994 opp-5 {
3995 opp-peak-kBps = <8371200>;
3998 opp-6 {
3999 opp-peak-kBps = <10944000>;
4002 opp-7 {
4003 opp-peak-kBps = <12748800>;
4006 opp-8 {
4007 opp-peak-kBps = <14745600>;
4010 opp-9 {
4011 opp-peak-kBps = <16896000>;
4014 opp-10 {
4015 opp-peak-kBps = <19046400>;
4022 compatible = "qcom,sm8750-cpu-bwmon", "qcom,sdm845-bwmon";
4030 operating-points-v2 = <&cpu_bwmon_opp_table>;
4034 compatible = "qcom,sm8750-gem-noc";
4036 qcom,bcm-voters = <&apps_bcm_voter>;
4037 #interconnect-cells = <2>;
4040 system-cache-controller@24800000 {
4041 compatible = "qcom,sm8750-llcc";
4048 reg-names = "llcc0_base",
4059 compatible = "qcom,sm8750-nsp-noc";
4061 qcom,bcm-voters = <&apps_bcm_voter>;
4062 #interconnect-cells = <2>;
4066 compatible = "qcom,sm8750-cdsp-pas", "qcom,sm8650-cdsp-pas";
4069 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
4075 interrupt-names = "wdog",
4079 "stop-ack",
4080 "shutdown-ack";
4083 clock-names = "xo";
4088 power-domains = <&rpmhpd RPMHPD_CX>,
4091 power-domain-names = "cx",
4095 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>, <&global_sync_mem>;
4097 qcom,smem-states = <&smp2p_cdsp_out 0>;
4098 qcom,smem-state-names = "stop";
4102 glink-edge {
4103 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
4108 qcom,remote-pid = <5>;
4113 qcom,glink-channels = "fastrpcglink-apps-dsp";
4115 qcom,non-secure-domain;
4116 #address-cells = <1>;
4117 #size-cells = <0>;
4119 compute-cb@1 {
4120 compatible = "qcom,fastrpc-compute-cb";
4125 dma-coherent;
4128 compute-cb@2 {
4129 compatible = "qcom,fastrpc-compute-cb";
4135 dma-coherent;
4138 compute-cb@3 {
4139 compatible = "qcom,fastrpc-compute-cb";
4145 dma-coherent;
4148 compute-cb@4 {
4149 compatible = "qcom,fastrpc-compute-cb";
4155 dma-coherent;
4158 compute-cb@5 {
4159 compatible = "qcom,fastrpc-compute-cb";
4165 dma-coherent;
4168 compute-cb@6 {
4169 compatible = "qcom,fastrpc-compute-cb";
4175 dma-coherent;
4178 compute-cb@7 {
4179 compatible = "qcom,fastrpc-compute-cb";
4185 dma-coherent;
4188 compute-cb@8 {
4189 compatible = "qcom,fastrpc-compute-cb";
4195 dma-coherent;
4200 compute-cb@12 {
4201 compatible = "qcom,fastrpc-compute-cb";
4207 dma-coherent;
4210 compute-cb@13 {
4211 compatible = "qcom,fastrpc-compute-cb";
4218 dma-coherent;
4221 compute-cb@14 {
4222 compatible = "qcom,fastrpc-compute-cb";
4227 dma-coherent;
4235 compatible = "arm,armv8-timer";