Lines Matching +full:ipa +full:- +full:shared
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm8750-gcc.h>
8 #include <dt-bindings/clock/qcom,sm8750-tcsr.h>
9 #include <dt-bindings/dma/qcom-gpi.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interconnect/qcom,icc.h>
12 #include <dt-bindings/interconnect/qcom,sm8750-rpmh.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/mailbox/qcom-ipcc.h>
15 #include <dt-bindings/power/qcom,rpmhpd.h>
16 #include <dt-bindings/power/qcom-rpmpd.h>
17 #include <dt-bindings/soc/qcom,gpr.h>
18 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
19 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
22 interrupt-parent = <&intc>;
24 #address-cells = <2>;
25 #size-cells = <2>;
28 #address-cells = <2>;
29 #size-cells = <0>;
35 enable-method = "psci";
36 next-level-cache = <&l2_0>;
37 power-domains = <&cpu_pd0>;
38 power-domain-names = "psci";
40 l2_0: l2-cache {
42 cache-level = <2>;
43 cache-unified;
51 enable-method = "psci";
52 next-level-cache = <&l2_0>;
53 power-domains = <&cpu_pd1>;
54 power-domain-names = "psci";
61 enable-method = "psci";
62 next-level-cache = <&l2_0>;
63 power-domains = <&cpu_pd2>;
64 power-domain-names = "psci";
71 enable-method = "psci";
72 next-level-cache = <&l2_0>;
73 power-domains = <&cpu_pd3>;
74 power-domain-names = "psci";
81 enable-method = "psci";
82 next-level-cache = <&l2_0>;
83 power-domains = <&cpu_pd4>;
84 power-domain-names = "psci";
91 enable-method = "psci";
92 next-level-cache = <&l2_0>;
93 power-domains = <&cpu_pd5>;
94 power-domain-names = "psci";
101 enable-method = "psci";
102 next-level-cache = <&l2_1>;
103 power-domains = <&cpu_pd6>;
104 power-domain-names = "psci";
106 l2_1: l2-cache {
108 cache-level = <2>;
109 cache-unified;
117 enable-method = "psci";
118 next-level-cache = <&l2_1>;
119 power-domains = <&cpu_pd7>;
120 power-domain-names = "psci";
123 cpu-map {
161 idle-states {
162 entry-method = "psci";
164 cluster0_c4: cpu-sleep-0 {
165 compatible = "arm,idle-state";
166 idle-state-name = "ret";
167 arm,psci-suspend-param = <0x00000004>;
168 entry-latency-us = <93>;
169 exit-latency-us = <129>;
170 min-residency-us = <560>;
173 cluster1_c4: cpu-sleep-1 {
174 compatible = "arm,idle-state";
175 idle-state-name = "ret";
176 arm,psci-suspend-param = <0x00000004>;
177 entry-latency-us = <172>;
178 exit-latency-us = <130>;
179 min-residency-us = <686>;
183 domain-idle-states {
184 cluster_cl5: cluster-sleep-0 {
185 compatible = "domain-idle-state";
186 arm,psci-suspend-param = <0x01000054>;
187 entry-latency-us = <2150>;
188 exit-latency-us = <1983>;
189 min-residency-us = <9144>;
192 domain_ss3: domain-sleep-0 {
193 compatible = "domain-idle-state";
194 arm,psci-suspend-param = <0x0200c354>;
195 entry-latency-us = <2800>;
196 exit-latency-us = <4400>;
197 min-residency-us = <10150>;
204 compatible = "qcom,scm-sm8750", "qcom,scm";
210 clk_virt: interconnect-0 {
211 compatible = "qcom,sm8750-clk-virt";
212 #interconnect-cells = <2>;
213 qcom,bcm-voters = <&apps_bcm_voter>;
216 mc_virt: interconnect-1 {
217 compatible = "qcom,sm8750-mc-virt";
218 #interconnect-cells = <2>;
219 qcom,bcm-voters = <&apps_bcm_voter>;
229 compatible = "arm,armv8-pmuv3";
234 compatible = "arm,psci-1.0";
237 cpu_pd0: power-domain-cpu0 {
238 #power-domain-cells = <0>;
239 power-domains = <&cluster0_pd>;
240 domain-idle-states = <&cluster0_c4>;
243 cpu_pd1: power-domain-cpu1 {
244 #power-domain-cells = <0>;
245 power-domains = <&cluster0_pd>;
246 domain-idle-states = <&cluster0_c4>;
249 cpu_pd2: power-domain-cpu2 {
250 #power-domain-cells = <0>;
251 power-domains = <&cluster0_pd>;
252 domain-idle-states = <&cluster0_c4>;
255 cpu_pd3: power-domain-cpu3 {
256 #power-domain-cells = <0>;
257 power-domains = <&cluster0_pd>;
258 domain-idle-states = <&cluster0_c4>;
261 cpu_pd4: power-domain-cpu4 {
262 #power-domain-cells = <0>;
263 power-domains = <&cluster0_pd>;
264 domain-idle-states = <&cluster0_c4>;
267 cpu_pd5: power-domain-cpu5 {
268 #power-domain-cells = <0>;
269 power-domains = <&cluster0_pd>;
270 domain-idle-states = <&cluster0_c4>;
273 cpu_pd6: power-domain-cpu6 {
274 #power-domain-cells = <0>;
275 power-domains = <&cluster1_pd>;
276 domain-idle-states = <&cluster1_c4>;
279 cpu_pd7: power-domain-cpu7 {
280 #power-domain-cells = <0>;
281 power-domains = <&cluster1_pd>;
282 domain-idle-states = <&cluster1_c4>;
285 cluster0_pd: power-domain-cluster0 {
286 #power-domain-cells = <0>;
287 domain-idle-states = <&cluster_cl5>;
288 power-domains = <&system_pd>;
291 cluster1_pd: power-domain-cluster1 {
292 #power-domain-cells = <0>;
293 domain-idle-states = <&cluster_cl5>;
294 power-domains = <&system_pd>;
297 system_pd: power-domain-system {
298 #power-domain-cells = <0>;
299 domain-idle-states = <&domain_ss3>;
303 reserved-memory {
304 #address-cells = <2>;
305 #size-cells = <2>;
308 gunyah_hyp_mem: gunyah-hyp@80000000 {
310 no-map;
313 cpusys_vm_mem: cpusys-vm-mem@80e00000 {
315 no-map;
320 no-map;
323 xbl_dtlog_mem: xbl-dtlog@81a00000 {
325 no-map;
328 aop_image_mem: aop-image@81c00000 {
330 no-map;
333 aop_cmd_db_mem: aop-cmd-db@81c60000 {
334 compatible = "qcom,cmd-db";
336 no-map;
340 aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 {
342 no-map;
351 no-map;
354 pdp_ns_shared_mem: pdp-ns-shared@81f00000 {
356 no-map;
359 cpucp_scandump_mem: cpucp-scandump@82000000 {
361 no-map;
364 adsp_mhi_mem: adsp-mhi@82380000 {
366 no-map;
369 soccp_sdi_mem: soccp-sdi@823a0000 {
371 no-map;
374 pmic_minii_dump_mem: pmic-minii-dump@823e0000 {
376 no-map;
381 no-map;
384 global_sync_mem: global-sync@82600000 {
386 no-map;
389 tz_stat_mem: tz-stat@82700000 {
391 no-map;
396 no-map;
399 dsm_partition_1_mem: dsm-partition-1@84a00000 {
401 no-map;
404 dsm_partition_2_mem: dsm-partition-2@89300000 {
406 no-map;
411 no-map;
414 q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 {
416 no-map;
419 ipa_fw_mem: ipa-fw@9b080000 {
421 no-map;
424 ipa_gsi_mem: ipa-gsi@9b090000 {
426 no-map;
429 gpu_micro_code_mem: gpu-micro-code@9b09a000 {
431 no-map;
436 no-map;
439 /* First part of the "SPU secure shared memory" region */
440 spu_tz_shared_mem: spu-tz-shared@9b280000 {
442 no-map;
445 /* Second part of the "SPU secure shared memory" region */
446 spu_modem_shared_mem: spu-modem-shared@9b2c0000 {
448 no-map;
453 no-map;
456 camera_2_mem: camera-2@9bb00000 {
458 no-map;
463 no-map;
468 no-map;
473 no-map;
476 q6_cdsp_dtb_mem: q6-cdsp-dtb@9eb00000 {
478 no-map;
483 no-map;
486 q6_adsp_dtb_mem: q6-adsp-dtb@9ed80000 {
488 no-map;
493 no-map;
496 xbl_ramdump_mem: xbl-ramdump@b8000000 {
498 no-map;
501 hwfence_shbuf: hwfence-shbuf@d4e23000 {
502 no-map;
507 tz_merged_mem: tz-merged@d8000000 {
509 no-map;
512 trust_ui_vm_mem: trust-ui-vm@f3800000 {
514 no-map;
517 oem_vm_mem: oem-vm@f7c00000 {
519 no-map;
522 llcc_lpi_mem: llcc-lpi@ff800000 {
524 no-map;
528 smp2p-adsp {
531 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
539 qcom,local-pid = <0>;
540 qcom,remote-pid = <2>;
542 smp2p_adsp_out: master-kernel {
543 qcom,entry-name = "master-kernel";
544 #qcom,smem-state-cells = <1>;
547 smp2p_adsp_in: slave-kernel {
548 qcom,entry-name = "slave-kernel";
549 interrupt-controller;
550 #interrupt-cells = <2>;
554 smp2p-cdsp {
557 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
565 qcom,local-pid = <0>;
566 qcom,remote-pid = <5>;
568 smp2p_cdsp_out: master-kernel {
569 qcom,entry-name = "master-kernel";
570 #qcom,smem-state-cells = <1>;
573 smp2p_cdsp_in: slave-kernel {
574 qcom,entry-name = "slave-kernel";
575 interrupt-controller;
576 #interrupt-cells = <2>;
580 smp2p-modem {
583 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
591 qcom,local-pid = <0>;
592 qcom,remote-pid = <1>;
594 smp2p_modem_out: master-kernel {
595 qcom,entry-name = "master-kernel";
596 #qcom,smem-state-cells = <1>;
599 smp2p_modem_in: slave-kernel {
600 qcom,entry-name = "slave-kernel";
601 interrupt-controller;
602 #interrupt-cells = <2>;
605 ipa_smp2p_out: ipa-ap-to-modem {
606 qcom,entry-name = "ipa";
607 #qcom,smem-state-cells = <1>;
610 ipa_smp2p_in: ipa-modem-to-ap {
611 qcom,entry-name = "ipa";
612 interrupt-controller;
613 #interrupt-cells = <2>;
620 compatible = "simple-bus";
622 #address-cells = <2>;
623 #size-cells = <2>;
624 dma-ranges = <0 0 0 0 0x10 0>;
627 gcc: clock-controller@100000 {
628 compatible = "qcom,sm8750-gcc";
640 #clock-cells = <1>;
641 #reset-cells = <1>;
642 #power-domain-cells = <1>;
646 compatible = "qcom,sm8750-ipcc", "qcom,ipcc";
650 interrupt-controller;
651 #interrupt-cells = <3>;
653 #mbox-cells = <2>;
656 gpi_dma2: dma-controller@800000 {
657 compatible = "qcom,sm8750-gpi-dma", "qcom,sm6350-gpi-dma";
673 dma-channels = <12>;
674 dma-channel-mask = <0x1e>;
675 #dma-cells = <3>;
683 compatible = "qcom,geni-se-qup";
688 clock-names = "m-ahb",
689 "s-ahb";
693 #address-cells = <2>;
694 #size-cells = <2>;
700 compatible = "qcom,geni-i2c";
706 clock-names = "se";
714 interconnect-names = "qup-core",
715 "qup-config",
716 "qup-memory";
720 dma-names = "tx",
723 pinctrl-0 = <&qup_i2c8_data_clk>;
724 pinctrl-names = "default";
726 #address-cells = <1>;
727 #size-cells = <0>;
733 compatible = "qcom,geni-spi";
739 clock-names = "se";
747 interconnect-names = "qup-core",
748 "qup-config",
749 "qup-memory";
753 dma-names = "tx",
756 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
757 pinctrl-names = "default";
759 #address-cells = <1>;
760 #size-cells = <0>;
766 compatible = "qcom,geni-i2c";
772 clock-names = "se";
780 interconnect-names = "qup-core",
781 "qup-config",
782 "qup-memory";
786 dma-names = "tx",
789 pinctrl-0 = <&qup_i2c9_data_clk>;
790 pinctrl-names = "default";
792 #address-cells = <1>;
793 #size-cells = <0>;
799 compatible = "qcom,geni-spi";
805 clock-names = "se";
813 interconnect-names = "qup-core",
814 "qup-config",
815 "qup-memory";
819 dma-names = "tx",
822 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
823 pinctrl-names = "default";
825 #address-cells = <1>;
826 #size-cells = <0>;
832 compatible = "qcom,geni-i2c";
838 clock-names = "se";
846 interconnect-names = "qup-core",
847 "qup-config",
848 "qup-memory";
852 dma-names = "tx",
855 pinctrl-0 = <&qup_i2c10_data_clk>;
856 pinctrl-names = "default";
858 #address-cells = <1>;
859 #size-cells = <0>;
865 compatible = "qcom,geni-spi";
871 clock-names = "se";
879 interconnect-names = "qup-core",
880 "qup-config",
881 "qup-memory";
885 dma-names = "tx",
888 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
889 pinctrl-names = "default";
891 #address-cells = <1>;
892 #size-cells = <0>;
898 compatible = "qcom,geni-i2c";
904 clock-names = "se";
912 interconnect-names = "qup-core",
913 "qup-config",
914 "qup-memory";
918 dma-names = "tx",
921 pinctrl-0 = <&qup_i2c11_data_clk>;
922 pinctrl-names = "default";
924 #address-cells = <1>;
925 #size-cells = <0>;
931 compatible = "qcom,geni-spi";
937 clock-names = "se";
945 interconnect-names = "qup-core",
946 "qup-config",
947 "qup-memory";
951 dma-names = "tx",
954 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
955 pinctrl-names = "default";
957 #address-cells = <1>;
958 #size-cells = <0>;
964 compatible = "qcom,geni-i2c";
970 clock-names = "se";
978 interconnect-names = "qup-core",
979 "qup-config",
980 "qup-memory";
984 dma-names = "tx",
987 pinctrl-0 = <&qup_i2c12_data_clk>;
988 pinctrl-names = "default";
990 #address-cells = <1>;
991 #size-cells = <0>;
997 compatible = "qcom,geni-spi";
1003 clock-names = "se";
1011 interconnect-names = "qup-core",
1012 "qup-config",
1013 "qup-memory";
1017 dma-names = "tx",
1020 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1021 pinctrl-names = "default";
1023 #address-cells = <1>;
1024 #size-cells = <0>;
1030 compatible = "qcom,geni-i2c";
1036 clock-names = "se";
1044 interconnect-names = "qup-core",
1045 "qup-config",
1046 "qup-memory";
1050 dma-names = "tx",
1053 pinctrl-0 = <&qup_i2c13_data_clk>;
1054 pinctrl-names = "default";
1056 #address-cells = <1>;
1057 #size-cells = <0>;
1063 compatible = "qcom,geni-spi";
1069 clock-names = "se";
1077 interconnect-names = "qup-core",
1078 "qup-config",
1079 "qup-memory";
1083 dma-names = "tx",
1086 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1087 pinctrl-names = "default";
1089 #address-cells = <1>;
1090 #size-cells = <0>;
1096 compatible = "qcom,geni-uart";
1102 clock-names = "se";
1108 interconnect-names = "qup-core",
1109 "qup-config";
1111 pinctrl-0 = <&qup_uart14_default>;
1112 pinctrl-names = "default";
1118 compatible = "qcom,geni-i2c";
1124 clock-names = "se";
1132 interconnect-names = "qup-core",
1133 "qup-config",
1134 "qup-memory";
1138 dma-names = "tx",
1141 pinctrl-0 = <&qup_i2c15_data_clk>;
1142 pinctrl-names = "default";
1144 #address-cells = <1>;
1145 #size-cells = <0>;
1151 compatible = "qcom,geni-spi";
1157 clock-names = "se";
1165 interconnect-names = "qup-core",
1166 "qup-config",
1167 "qup-memory";
1171 dma-names = "tx",
1174 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1175 pinctrl-names = "default";
1177 #address-cells = <1>;
1178 #size-cells = <0>;
1185 compatible = "qcom,geni-se-i2c-master-hub";
1189 clock-names = "s-ahb";
1191 #address-cells = <2>;
1192 #size-cells = <2>;
1198 compatible = "qcom,geni-i2c-master-hub";
1205 clock-names = "se",
1212 interconnect-names = "qup-core",
1213 "qup-config";
1215 pinctrl-0 = <&hub_i2c0_data_clk>;
1216 pinctrl-names = "default";
1218 #address-cells = <1>;
1219 #size-cells = <0>;
1225 compatible = "qcom,geni-i2c-master-hub";
1232 clock-names = "se",
1239 interconnect-names = "qup-core",
1240 "qup-config";
1242 pinctrl-0 = <&hub_i2c1_data_clk>;
1243 pinctrl-names = "default";
1245 #address-cells = <1>;
1246 #size-cells = <0>;
1252 compatible = "qcom,geni-i2c-master-hub";
1259 clock-names = "se",
1266 interconnect-names = "qup-core",
1267 "qup-config";
1269 pinctrl-0 = <&hub_i2c2_data_clk>;
1270 pinctrl-names = "default";
1272 #address-cells = <1>;
1273 #size-cells = <0>;
1279 compatible = "qcom,geni-i2c-master-hub";
1286 clock-names = "se",
1293 interconnect-names = "qup-core",
1294 "qup-config";
1296 pinctrl-0 = <&hub_i2c3_data_clk>;
1297 pinctrl-names = "default";
1299 #address-cells = <1>;
1300 #size-cells = <0>;
1306 compatible = "qcom,geni-i2c-master-hub";
1313 clock-names = "se",
1320 interconnect-names = "qup-core",
1321 "qup-config";
1323 pinctrl-0 = <&hub_i2c4_data_clk>;
1324 pinctrl-names = "default";
1326 #address-cells = <1>;
1327 #size-cells = <0>;
1333 compatible = "qcom,geni-i2c-master-hub";
1340 clock-names = "se",
1347 interconnect-names = "qup-core",
1348 "qup-config";
1350 pinctrl-0 = <&hub_i2c5_data_clk>;
1351 pinctrl-names = "default";
1353 #address-cells = <1>;
1354 #size-cells = <0>;
1360 compatible = "qcom,geni-i2c-master-hub";
1367 clock-names = "se",
1374 interconnect-names = "qup-core",
1375 "qup-config";
1377 pinctrl-0 = <&hub_i2c6_data_clk>;
1378 pinctrl-names = "default";
1380 #address-cells = <1>;
1381 #size-cells = <0>;
1387 compatible = "qcom,geni-i2c-master-hub";
1394 clock-names = "se",
1401 interconnect-names = "qup-core",
1402 "qup-config";
1404 pinctrl-0 = <&hub_i2c7_data_clk>;
1405 pinctrl-names = "default";
1407 #address-cells = <1>;
1408 #size-cells = <0>;
1414 compatible = "qcom,geni-i2c-master-hub";
1421 clock-names = "se",
1428 interconnect-names = "qup-core",
1429 "qup-config";
1431 pinctrl-0 = <&hub_i2c8_data_clk>;
1432 pinctrl-names = "default";
1434 #address-cells = <1>;
1435 #size-cells = <0>;
1441 compatible = "qcom,geni-i2c-master-hub";
1448 clock-names = "se",
1455 interconnect-names = "qup-core",
1456 "qup-config";
1458 pinctrl-0 = <&hub_i2c9_data_clk>;
1459 pinctrl-names = "default";
1461 #address-cells = <1>;
1462 #size-cells = <0>;
1468 gpi_dma1: dma-controller@a00000 {
1469 compatible = "qcom,sm8750-gpi-dma", "qcom,sm6350-gpi-dma";
1485 dma-channels = <12>;
1486 dma-channel-mask = <0x1e>;
1487 #dma-cells = <3>;
1495 compatible = "qcom,geni-se-qup";
1500 clock-names = "m-ahb",
1501 "s-ahb";
1505 #address-cells = <2>;
1506 #size-cells = <2>;
1512 compatible = "qcom,geni-i2c";
1518 clock-names = "se";
1526 interconnect-names = "qup-core",
1527 "qup-config",
1528 "qup-memory";
1532 dma-names = "tx",
1535 pinctrl-0 = <&qup_i2c0_data_clk>;
1536 pinctrl-names = "default";
1538 #address-cells = <1>;
1539 #size-cells = <0>;
1545 compatible = "qcom,geni-spi";
1551 clock-names = "se";
1559 interconnect-names = "qup-core",
1560 "qup-config",
1561 "qup-memory";
1565 dma-names = "tx",
1568 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1569 pinctrl-names = "default";
1571 #address-cells = <1>;
1572 #size-cells = <0>;
1578 compatible = "qcom,geni-i2c";
1584 clock-names = "se";
1592 interconnect-names = "qup-core",
1593 "qup-config",
1594 "qup-memory";
1598 dma-names = "tx",
1601 pinctrl-0 = <&qup_i2c1_data_clk>;
1602 pinctrl-names = "default";
1604 #address-cells = <1>;
1605 #size-cells = <0>;
1611 compatible = "qcom,geni-spi";
1617 clock-names = "se";
1625 interconnect-names = "qup-core",
1626 "qup-config",
1627 "qup-memory";
1631 dma-names = "tx",
1634 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1635 pinctrl-names = "default";
1637 #address-cells = <1>;
1638 #size-cells = <0>;
1644 compatible = "qcom,geni-i2c";
1650 clock-names = "se";
1658 interconnect-names = "qup-core",
1659 "qup-config",
1660 "qup-memory";
1664 dma-names = "tx",
1667 pinctrl-0 = <&qup_i2c2_data_clk>;
1668 pinctrl-names = "default";
1670 #address-cells = <1>;
1671 #size-cells = <0>;
1677 compatible = "qcom,geni-spi";
1683 clock-names = "se";
1691 interconnect-names = "qup-core",
1692 "qup-config",
1693 "qup-memory";
1697 dma-names = "tx",
1700 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1701 pinctrl-names = "default";
1703 #address-cells = <1>;
1704 #size-cells = <0>;
1710 compatible = "qcom,geni-i2c";
1716 clock-names = "se";
1724 interconnect-names = "qup-core",
1725 "qup-config",
1726 "qup-memory";
1730 dma-names = "tx",
1733 pinctrl-0 = <&qup_i2c3_data_clk>;
1734 pinctrl-names = "default";
1736 #address-cells = <1>;
1737 #size-cells = <0>;
1743 compatible = "qcom,geni-spi";
1749 clock-names = "se";
1757 interconnect-names = "qup-core",
1758 "qup-config",
1759 "qup-memory";
1763 dma-names = "tx",
1766 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1767 pinctrl-names = "default";
1769 #address-cells = <1>;
1770 #size-cells = <0>;
1776 compatible = "qcom,geni-i2c";
1782 clock-names = "se";
1790 interconnect-names = "qup-core",
1791 "qup-config",
1792 "qup-memory";
1796 dma-names = "tx",
1799 pinctrl-0 = <&qup_i2c4_data_clk>;
1800 pinctrl-names = "default";
1802 #address-cells = <1>;
1803 #size-cells = <0>;
1809 compatible = "qcom,geni-spi";
1815 clock-names = "se";
1823 interconnect-names = "qup-core",
1824 "qup-config",
1825 "qup-memory";
1829 dma-names = "tx",
1832 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1833 pinctrl-names = "default";
1835 #address-cells = <1>;
1836 #size-cells = <0>;
1842 compatible = "qcom,geni-i2c";
1848 clock-names = "se";
1856 interconnect-names = "qup-core",
1857 "qup-config",
1858 "qup-memory";
1862 dma-names = "tx",
1865 pinctrl-0 = <&qup_i2c5_data_clk>;
1866 pinctrl-names = "default";
1868 #address-cells = <1>;
1869 #size-cells = <0>;
1875 compatible = "qcom,geni-spi";
1881 clock-names = "se";
1889 interconnect-names = "qup-core",
1890 "qup-config",
1891 "qup-memory";
1895 dma-names = "tx",
1898 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1899 pinctrl-names = "default";
1901 #address-cells = <1>;
1902 #size-cells = <0>;
1908 compatible = "qcom,geni-i2c";
1914 clock-names = "se";
1922 interconnect-names = "qup-core",
1923 "qup-config",
1924 "qup-memory";
1928 dma-names = "tx",
1931 pinctrl-0 = <&qup_i2c6_data_clk>;
1932 pinctrl-names = "default";
1934 #address-cells = <1>;
1935 #size-cells = <0>;
1941 compatible = "qcom,geni-spi";
1947 clock-names = "se";
1955 interconnect-names = "qup-core",
1956 "qup-config",
1957 "qup-memory";
1961 dma-names = "tx",
1964 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1965 pinctrl-names = "default";
1967 #address-cells = <1>;
1968 #size-cells = <0>;
1974 compatible = "qcom,geni-debug-uart";
1980 clock-names = "se";
1986 interconnect-names = "qup-core",
1987 "qup-config";
1989 pinctrl-0 = <&qup_uart7_default>;
1990 pinctrl-names = "default";
1997 compatible = "qcom,sm8750-trng", "qcom,trng";
2002 compatible = "qcom,sm8750-cnoc-main";
2004 qcom,bcm-voters = <&apps_bcm_voter>;
2005 #interconnect-cells = <2>;
2009 compatible = "qcom,sm8750-config-noc";
2011 qcom,bcm-voters = <&apps_bcm_voter>;
2012 #interconnect-cells = <2>;
2016 compatible = "qcom,sm8750-system-noc";
2018 qcom,bcm-voters = <&apps_bcm_voter>;
2019 #interconnect-cells = <2>;
2023 compatible = "qcom,sm8750-pcie-anoc";
2025 qcom,bcm-voters = <&apps_bcm_voter>;
2026 #interconnect-cells = <2>;
2032 compatible = "qcom,sm8750-aggre1-noc";
2034 qcom,bcm-voters = <&apps_bcm_voter>;
2035 #interconnect-cells = <2>;
2041 compatible = "qcom,sm8750-aggre2-noc";
2043 qcom,bcm-voters = <&apps_bcm_voter>;
2044 #interconnect-cells = <2>;
2049 compatible = "qcom,sm8750-mmss-noc";
2051 qcom,bcm-voters = <&apps_bcm_voter>;
2052 #interconnect-cells = <2>;
2056 compatible = "qcom,sm8750-inline-crypto-engine",
2057 "qcom,inline-crypto-engine";
2063 cryptobam: dma-controller@1dc4000 {
2064 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2069 #dma-cells = <1>;
2075 qcom,controlled-remotely;
2079 compatible = "qcom,sm8750-qce", "qcom,sm8150-qce", "qcom,qce";
2084 interconnect-names = "memory";
2087 dma-names = "rx", "tx";
2094 compatible = "qcom,tcsr-mutex";
2096 #hwlock-cells = <1>;
2100 compatible = "qcom,sm8750-mpss-pas";
2103 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2109 interrupt-names = "wdog",
2113 "stop-ack",
2114 "shutdown-ack";
2117 clock-names = "xo";
2122 power-domains = <&rpmhpd RPMHPD_CX>,
2124 power-domain-names = "cx",
2127 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>,
2133 qcom,smem-states = <&smp2p_modem_out 0>;
2134 qcom,smem-state-names = "stop";
2138 glink-edge {
2139 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2146 qcom,remote-pid = <1>;
2153 compatible = "qcom,sm8750-adsp-pas", "qcom,sm8550-adsp-pas";
2156 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2162 interrupt-names = "wdog",
2166 "stop-ack",
2167 "shutdown-ack";
2170 clock-names = "xo";
2175 power-domains = <&rpmhpd RPMHPD_LCX>,
2177 power-domain-names = "lcx",
2180 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
2184 qcom,smem-states = <&smp2p_adsp_out 0>;
2185 qcom,smem-state-names = "stop";
2189 remoteproc_adsp_glink: glink-edge {
2190 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2195 qcom,remote-pid = <2>;
2200 qcom,glink-channels = "adsp_apps";
2203 #address-cells = <1>;
2204 #size-cells = <0>;
2209 #sound-dai-cells = <0>;
2210 qcom,protection-domain = "avs/audio",
2214 compatible = "qcom,q6apm-lpass-dais";
2215 #sound-dai-cells = <1>;
2219 compatible = "qcom,q6apm-dais";
2228 qcom,protection-domain = "avs/audio",
2231 q6prmcc: clock-controller {
2232 compatible = "qcom,q6prm-lpass-clocks";
2233 #clock-cells = <2>;
2241 compatible = "qcom,sm8750-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
2247 clock-names = "mclk",
2252 #clock-cells = <0>;
2253 clock-output-names = "wsa2-mclk";
2254 #sound-dai-cells = <1>;
2258 compatible = "qcom,soundwire-v2.1.0", "qcom,soundwire-v2.0.0";
2262 clock-names = "iface";
2265 pinctrl-0 = <&wsa2_swr_active>;
2266 pinctrl-names = "default";
2268 qcom,din-ports = <4>;
2269 qcom,dout-ports = <9>;
2271 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0x18f 0x18f 0x0f 0x0f 0xff …
2272 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0x00 0x00 0x06 0x0d 0xff 0x00>;
2273 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2274 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>;
2275 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>;
2276 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0f 0x0f 0x00 0xff 0xff 0x1…
2277 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x01 0x00…
2278 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0x…
2279 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0x…
2281 #address-cells = <2>;
2282 #size-cells = <0>;
2283 #sound-dai-cells = <1>;
2288 compatible = "qcom,sm8750-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro";
2294 clock-names = "mclk",
2299 #clock-cells = <0>;
2300 clock-output-names = "mclk";
2301 #sound-dai-cells = <1>;
2305 compatible = "qcom,soundwire-v2.1.0", "qcom,soundwire-v2.0.0";
2309 clock-names = "iface";
2312 pinctrl-0 = <&rx_swr_active>;
2313 pinctrl-names = "default";
2315 qcom,din-ports = <1>;
2316 qcom,dout-ports = <11>;
2318 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0x31 0xff 0xff 0xff>;
2319 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>;
2320 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>;
2321 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0x00 0xff 0xff 0xff>;
2322 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0x0f 0xff 0xff 0xff>;
2323 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0x18 0xff 0xff 0xff>;
2324 …qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0x01 0xff 0xff 0xff…
2325 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0x…
2326 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0xff 0xff 0xff>;
2328 #address-cells = <2>;
2329 #size-cells = <0>;
2330 #sound-dai-cells = <1>;
2335 compatible = "qcom,sm8750-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro";
2341 clock-names = "mclk",
2346 #clock-cells = <0>;
2347 clock-output-names = "mclk";
2348 #sound-dai-cells = <1>;
2352 compatible = "qcom,sm8750-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
2358 clock-names = "mclk",
2363 #clock-cells = <0>;
2364 clock-output-names = "mclk";
2365 #sound-dai-cells = <1>;
2369 compatible = "qcom,soundwire-v2.1.0", "qcom,soundwire-v2.0.0";
2373 clock-names = "iface";
2376 pinctrl-0 = <&wsa_swr_active>;
2377 pinctrl-names = "default";
2379 qcom,din-ports = <4>;
2380 qcom,dout-ports = <9>;
2382 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0x18f 0x18f 0x0f 0x0f 0xff …
2383 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0x00 0x00 0x06 0x0d 0xff 0x00>;
2384 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2385 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>;
2386 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>;
2387 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0f 0x0f 0x00 0xff 0xff 0x1…
2388 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x01 0x00…
2389 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0x…
2390 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0x…
2392 #address-cells = <2>;
2393 #size-cells = <0>;
2394 #sound-dai-cells = <1>;
2399 compatible = "qcom,sm8750-lpass-ag-noc";
2401 qcom,bcm-voters = <&apps_bcm_voter>;
2402 #interconnect-cells = <2>;
2406 compatible = "qcom,sm8750-lpass-lpiaon-noc";
2408 qcom,bcm-voters = <&apps_bcm_voter>;
2409 #interconnect-cells = <2>;
2413 compatible = "qcom,sm8750-lpass-lpicx-noc";
2415 qcom,bcm-voters = <&apps_bcm_voter>;
2416 #interconnect-cells = <2>;
2420 compatible = "qcom,soundwire-v2.1.0", "qcom,soundwire-v2.0.0";
2424 interrupt-names = "core", "wakeup";
2426 clock-names = "iface";
2429 pinctrl-0 = <&tx_swr_active>;
2430 pinctrl-names = "default";
2432 qcom,din-ports = <4>;
2433 qcom,dout-ports = <0>;
2435 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2436 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2437 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2438 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2439 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2440 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2441 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2442 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2443 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2445 #address-cells = <2>;
2446 #size-cells = <0>;
2447 #sound-dai-cells = <1>;
2452 compatible = "qcom,sm8750-lpass-va-macro", "qcom,sm8550-lpass-va-macro";
2457 clock-names = "mclk",
2461 #clock-cells = <0>;
2462 clock-output-names = "fsgen";
2463 #sound-dai-cells = <1>;
2467 compatible = "qcom,sm8750-lpass-lpi-pinctrl",
2468 "qcom,sm8650-lpass-lpi-pinctrl";
2473 clock-names = "core", "audio";
2475 gpio-controller;
2476 #gpio-cells = <2>;
2477 gpio-ranges = <&lpass_tlmm 0 0 23>;
2479 tx_swr_active: tx-swr-active-state {
2480 clk-pins {
2483 drive-strength = <2>;
2484 slew-rate = <1>;
2485 bias-disable;
2488 data-pins {
2491 drive-strength = <2>;
2492 slew-rate = <1>;
2493 bias-bus-hold;
2497 rx_swr_active: rx-swr-active-state {
2498 clk-pins {
2501 drive-strength = <2>;
2502 slew-rate = <1>;
2503 bias-disable;
2506 data-pins {
2509 drive-strength = <2>;
2510 slew-rate = <1>;
2511 bias-bus-hold;
2515 dmic01_default: dmic01-default-state {
2516 clk-pins {
2519 drive-strength = <8>;
2520 output-high;
2523 data-pins {
2526 drive-strength = <8>;
2527 input-enable;
2531 dmic23_default: dmic23-default-state {
2532 clk-pins {
2535 drive-strength = <8>;
2536 output-high;
2539 data-pins {
2542 drive-strength = <8>;
2543 input-enable;
2547 wsa_swr_active: wsa-swr-active-state {
2548 clk-pins {
2551 drive-strength = <2>;
2552 slew-rate = <1>;
2553 bias-disable;
2556 data-pins {
2559 drive-strength = <2>;
2560 slew-rate = <1>;
2561 bias-bus-hold;
2565 wsa2_swr_active: wsa2-swr-active-state {
2566 clk-pins {
2569 drive-strength = <2>;
2570 slew-rate = <1>;
2571 bias-disable;
2574 data-pins {
2577 drive-strength = <2>;
2578 slew-rate = <1>;
2579 bias-bus-hold;
2584 pdc: interrupt-controller@b220000 {
2585 compatible = "qcom,sm8750-pdc", "qcom,pdc";
2588 qcom,pdc-ranges = <0 745 51>, <51 527 47>,
2591 #interrupt-cells = <2>;
2592 interrupt-parent = <&intc>;
2593 interrupt-controller;
2596 aoss_qmp: power-management@c300000 {
2597 compatible = "qcom,sm8750-aoss-qmp", "qcom,aoss-qmp";
2600 interrupt-parent = <&ipcc>;
2601 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
2606 #clock-cells = <0>;
2610 compatible = "qcom,rpmh-stats";
2616 compatible = "qcom,spmi-pmic-arb";
2622 reg-names = "core",
2628 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2629 interrupt-names = "periph_irq";
2633 qcom,bus-id = <0>;
2635 interrupt-controller;
2636 #interrupt-cells = <4>;
2638 #address-cells = <2>;
2639 #size-cells = <0>;
2643 compatible = "qcom,sm8750-tlmm";
2648 gpio-controller;
2649 #gpio-cells = <2>;
2651 interrupt-controller;
2652 #interrupt-cells = <2>;
2654 gpio-ranges = <&tlmm 0 0 216>;
2655 wakeup-parent = <&pdc>;
2657 hub_i2c0_data_clk: hub-i2c0-data-clk-state {
2661 drive-strength = <2>;
2662 bias-pull-up;
2665 hub_i2c1_data_clk: hub-i2c1-data-clk-state {
2669 drive-strength = <2>;
2670 bias-pull-up;
2673 hub_i2c2_data_clk: hub-i2c2-data-clk-state {
2677 drive-strength = <2>;
2678 bias-pull-up;
2681 hub_i2c3_data_clk: hub-i2c3-data-clk-state {
2685 drive-strength = <2>;
2686 bias-pull-up;
2689 hub_i2c4_data_clk: hub-i2c4-data-clk-state {
2693 drive-strength = <2>;
2694 bias-pull-up;
2697 hub_i2c5_data_clk: hub-i2c5-data-clk-state {
2701 drive-strength = <2>;
2702 bias-pull-up;
2705 hub_i2c6_data_clk: hub-i2c6-data-clk-state {
2709 drive-strength = <2>;
2710 bias-pull-up;
2713 hub_i2c7_data_clk: hub-i2c7-data-clk-state {
2717 drive-strength = <2>;
2718 bias-pull-up;
2721 hub_i2c8_data_clk: hub-i2c8-data-clk-state {
2725 drive-strength = <2>;
2726 bias-pull-up;
2729 hub_i2c9_data_clk: hub-i2c9-data-clk-state {
2733 drive-strength = <2>;
2734 bias-pull-up;
2737 pcie0_default_state: pcie0-default-state {
2738 perst-pins {
2741 drive-strength = <2>;
2742 bias-pull-down;
2745 clkreq-pins {
2748 drive-strength = <2>;
2749 bias-pull-up;
2752 wake-pins {
2755 drive-strength = <2>;
2756 bias-pull-up;
2760 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
2764 drive-strength = <2>;
2765 bias-pull-up;
2768 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
2772 drive-strength = <2>;
2773 bias-pull-up;
2776 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
2780 drive-strength = <2>;
2781 bias-pull-up;
2784 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
2788 drive-strength = <2>;
2789 bias-pull-up;
2792 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
2796 drive-strength = <2>;
2797 bias-pull-up;
2800 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
2804 drive-strength = <2>;
2805 bias-pull-up;
2808 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
2812 drive-strength = <2>;
2813 bias-pull-up;
2816 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
2820 drive-strength = <2>;
2821 bias-pull-up;
2824 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
2828 drive-strength = <2>;
2829 bias-pull-up;
2832 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
2836 drive-strength = <2>;
2837 bias-pull-up;
2840 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
2844 drive-strength = <2>;
2845 bias-pull-up;
2848 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
2852 drive-strength = <2>;
2853 bias-pull-up;
2856 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
2860 drive-strength = <2>;
2861 bias-pull-up;
2864 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
2868 drive-strength = <2>;
2869 bias-pull-up;
2872 qup_spi0_cs: qup-spi0-cs-state {
2875 drive-strength = <6>;
2876 bias-disable;
2879 qup_spi0_data_clk: qup-spi0-data-clk-state {
2883 drive-strength = <6>;
2884 bias-disable;
2887 qup_spi1_cs: qup-spi1-cs-state {
2890 drive-strength = <6>;
2891 bias-disable;
2894 qup_spi1_data_clk: qup-spi1-data-clk-state {
2898 drive-strength = <6>;
2899 bias-disable;
2902 qup_spi2_cs: qup-spi2-cs-state {
2905 drive-strength = <6>;
2906 bias-disable;
2909 qup_spi2_data_clk: qup-spi2-data-clk-state {
2913 drive-strength = <6>;
2914 bias-disable;
2917 qup_spi3_cs: qup-spi3-cs-state {
2920 drive-strength = <6>;
2921 bias-disable;
2924 qup_spi3_data_clk: qup-spi3-data-clk-state {
2928 drive-strength = <6>;
2929 bias-disable;
2932 qup_spi4_cs: qup-spi4-cs-state {
2935 drive-strength = <6>;
2936 bias-disable;
2939 qup_spi4_data_clk: qup-spi4-data-clk-state {
2943 drive-strength = <6>;
2944 bias-disable;
2947 qup_spi5_cs: qup-spi5-cs-state {
2950 drive-strength = <6>;
2951 bias-disable;
2954 qup_spi5_data_clk: qup-spi5-data-clk-state {
2958 drive-strength = <6>;
2959 bias-disable;
2962 qup_spi6_cs: qup-spi6-cs-state {
2965 drive-strength = <6>;
2966 bias-disable;
2969 qup_spi6_data_clk: qup-spi6-data-clk-state {
2973 drive-strength = <6>;
2974 bias-disable;
2977 qup_spi8_cs: qup-spi8-cs-state {
2980 drive-strength = <6>;
2981 bias-disable;
2984 qup_spi8_data_clk: qup-spi8-data-clk-state {
2988 drive-strength = <6>;
2989 bias-disable;
2992 qup_spi9_cs: qup-spi9-cs-state {
2995 drive-strength = <6>;
2996 bias-disable;
2999 qup_spi9_data_clk: qup-spi9-data-clk-state {
3003 drive-strength = <6>;
3004 bias-disable;
3007 qup_spi10_cs: qup-spi10-cs-state {
3010 drive-strength = <6>;
3011 bias-disable;
3014 qup_spi10_data_clk: qup-spi10-data-clk-state {
3018 drive-strength = <6>;
3019 bias-disable;
3022 qup_spi11_cs: qup-spi11-cs-state {
3025 drive-strength = <6>;
3026 bias-disable;
3029 qup_spi11_data_clk: qup-spi11-data-clk-state {
3033 drive-strength = <6>;
3034 bias-disable;
3037 qup_spi12_cs: qup-spi12-cs-state {
3040 drive-strength = <6>;
3041 bias-disable;
3044 qup_spi12_data_clk: qup-spi12-data-clk-state {
3048 drive-strength = <6>;
3049 bias-disable;
3052 qup_spi13_cs: qup-spi13-cs-state {
3055 drive-strength = <6>;
3056 bias-pull-up;
3059 qup_spi13_data_clk: qup-spi13-data-clk-state {
3063 drive-strength = <6>;
3064 bias-disable;
3067 qup_spi15_cs: qup-spi15-cs-state {
3070 drive-strength = <6>;
3071 bias-disable;
3074 qup_spi15_data_clk: qup-spi15-data-clk-state {
3078 drive-strength = <6>;
3079 bias-disable;
3082 qup_uart7_default: qup-uart7-default-state {
3086 drive-strength = <2>;
3087 bias-disable;
3090 qup_uart14_default: qup-uart14-default-state {
3094 drive-strength = <2>;
3095 bias-pull-up;
3098 qup_uart14_cts_rts: qup-uart14-cts-rts-state {
3102 drive-strength = <2>;
3103 bias-pull-down;
3106 sdc2_sleep: sdc2-sleep-state {
3107 clk-pins {
3109 drive-strength = <2>;
3110 bias-disable;
3113 cmd-pins {
3115 drive-strength = <2>;
3116 bias-pull-up;
3119 data-pins {
3121 drive-strength = <2>;
3122 bias-pull-up;
3126 sdc2_default: sdc2-default-state {
3127 clk-pins {
3129 drive-strength = <16>;
3130 bias-disable;
3133 cmd-pins {
3135 drive-strength = <10>;
3136 bias-pull-up;
3139 data-pins {
3141 drive-strength = <10>;
3142 bias-pull-up;
3147 tcsrcc: clock-controller@f204008 {
3148 compatible = "qcom,sm8750-tcsr", "syscon";
3153 #clock-cells = <1>;
3154 #reset-cells = <1>;
3158 compatible = "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500";
3275 #iommu-cells = <2>;
3276 #global-interrupts = <1>;
3278 dma-coherent;
3281 intc: interrupt-controller@16000000 {
3282 compatible = "arm,gic-v3";
3288 #interrupt-cells = <3>;
3289 interrupt-controller;
3291 #redistributor-regions = <1>;
3292 redistributor-stride = <0x0 0x40000>;
3294 #address-cells = <2>;
3295 #size-cells = <2>;
3298 gic_its: msi-controller@16040000 {
3299 compatible = "arm,gic-v3-its";
3302 msi-controller;
3303 #msi-cells = <1>;
3308 compatible = "qcom,sm8750-qmp-ufs-phy";
3315 clock-names = "ref",
3320 reset-names = "ufsphy";
3322 power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>;
3324 #clock-cells = <1>;
3325 #phy-cells = <0>;
3331 compatible = "qcom,sm8750-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
3344 clock-names = "core_clk",
3353 operating-points-v2 = <&ufs_opp_table>;
3356 reset-names = "rst";
3362 interconnect-names = "ufs-ddr",
3363 "cpu-ufs";
3365 power-domains = <&gcc GCC_UFS_PHY_GDSC>;
3366 required-opps = <&rpmhpd_opp_nom>;
3369 dma-coherent;
3371 lanes-per-direction = <2>;
3374 phy-names = "ufsphy";
3376 #reset-cells = <1>;
3380 ufs_opp_table: opp-table {
3381 compatible = "operating-points-v2";
3383 opp-100000000 {
3384 opp-hz = /bits/ 64 <100000000>,
3392 required-opps = <&rpmhpd_opp_low_svs>;
3395 opp-403000000 {
3396 opp-hz = /bits/ 64 <403000000>,
3404 required-opps = <&rpmhpd_opp_nom>;
3410 compatible = "qcom,rpmh-rsc";
3414 reg-names = "drv-0",
3415 "drv-1",
3416 "drv-2";
3421 qcom,tcs-offset = <0xd00>;
3422 qcom,drv-id = <2>;
3423 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
3428 power-domains = <&system_pd>;
3430 apps_bcm_voter: bcm-voter {
3431 compatible = "qcom,bcm-voter";
3434 rpmhcc: clock-controller {
3435 compatible = "qcom,sm8750-rpmh-clk";
3438 clock-names = "xo";
3440 #clock-cells = <1>;
3443 rpmhpd: power-controller {
3444 compatible = "qcom,sm8750-rpmhpd";
3446 operating-points-v2 = <&rpmhpd_opp_table>;
3448 #power-domain-cells = <1>;
3450 rpmhpd_opp_table: opp-table {
3451 compatible = "operating-points-v2";
3453 rpmhpd_opp_ret: opp-16 {
3454 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3457 rpmhpd_opp_min_svs: opp-48 {
3458 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3461 rpmhpd_opp_low_svs_d3: opp-50 {
3462 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>;
3465 rpmhpd_opp_low_svs_d2: opp-52 {
3466 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
3469 rpmhpd_opp_low_svs_d1: opp-56 {
3470 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
3473 rpmhpd_opp_low_svs_d0: opp-60 {
3474 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
3477 rpmhpd_opp_low_svs: opp-64 {
3478 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3481 rpmhpd_opp_low_svs_l1: opp-80 {
3482 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
3485 rpmhpd_opp_svs: opp-128 {
3486 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3489 rpmhpd_opp_svs_l0: opp-144 {
3490 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
3493 rpmhpd_opp_svs_l1: opp-192 {
3494 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3497 rpmhpd_opp_svs_l2: opp-224 {
3498 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
3501 rpmhpd_opp_nom: opp-256 {
3502 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3505 rpmhpd_opp_nom_l1: opp-320 {
3506 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3509 rpmhpd_opp_nom_l2: opp-336 {
3510 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3513 rpmhpd_opp_turbo: opp-384 {
3514 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3517 rpmhpd_opp_turbo_l1: opp-416 {
3518 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3521 rpmhpd_opp_turbo_l2: opp-432 {
3522 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
3525 rpmhpd_opp_turbo_l3: opp-448 {
3526 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
3529 rpmhpd_opp_turbo_l4: opp-452 {
3530 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
3533 rpmhpd_opp_super_turbo_no_cpr: opp-480 {
3534 opp-level =
3542 compatible = "arm,armv7-timer-mem";
3545 #address-cells = <2>;
3546 #size-cells = <1>;
3556 frame-number = <0>;
3564 frame-number = <1>;
3574 frame-number = <2>;
3584 frame-number = <3>;
3594 frame-number = <4>;
3604 frame-number = <5>;
3614 frame-number = <6>;
3621 compatible = "qcom,sm8750-gem-noc";
3623 qcom,bcm-voters = <&apps_bcm_voter>;
3624 #interconnect-cells = <2>;
3627 system-cache-controller@24800000 {
3628 compatible = "qcom,sm8750-llcc";
3635 reg-names = "llcc0_base",
3646 compatible = "qcom,sm8750-nsp-noc";
3648 qcom,bcm-voters = <&apps_bcm_voter>;
3649 #interconnect-cells = <2>;
3653 compatible = "qcom,sm8750-cdsp-pas", "qcom,sm8650-cdsp-pas";
3656 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3662 interrupt-names = "wdog",
3666 "stop-ack",
3667 "shutdown-ack";
3670 clock-names = "xo";
3675 power-domains = <&rpmhpd RPMHPD_CX>,
3678 power-domain-names = "cx",
3682 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>, <&global_sync_mem>;
3684 qcom,smem-states = <&smp2p_cdsp_out 0>;
3685 qcom,smem-state-names = "stop";
3689 glink-edge {
3690 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3695 qcom,remote-pid = <5>;
3700 qcom,glink-channels = "fastrpcglink-apps-dsp";
3702 qcom,non-secure-domain;
3703 #address-cells = <1>;
3704 #size-cells = <0>;
3706 compute-cb@1 {
3707 compatible = "qcom,fastrpc-compute-cb";
3712 dma-coherent;
3715 compute-cb@2 {
3716 compatible = "qcom,fastrpc-compute-cb";
3722 dma-coherent;
3725 compute-cb@3 {
3726 compatible = "qcom,fastrpc-compute-cb";
3732 dma-coherent;
3735 compute-cb@4 {
3736 compatible = "qcom,fastrpc-compute-cb";
3742 dma-coherent;
3745 compute-cb@5 {
3746 compatible = "qcom,fastrpc-compute-cb";
3752 dma-coherent;
3755 compute-cb@6 {
3756 compatible = "qcom,fastrpc-compute-cb";
3762 dma-coherent;
3765 compute-cb@7 {
3766 compatible = "qcom,fastrpc-compute-cb";
3772 dma-coherent;
3775 compute-cb@8 {
3776 compatible = "qcom,fastrpc-compute-cb";
3782 dma-coherent;
3787 compute-cb@12 {
3788 compatible = "qcom,fastrpc-compute-cb";
3794 dma-coherent;
3797 compute-cb@13 {
3798 compatible = "qcom,fastrpc-compute-cb";
3805 dma-coherent;
3808 compute-cb@14 {
3809 compatible = "qcom,fastrpc-compute-cb";
3814 dma-coherent;
3822 compatible = "arm,armv8-timer";