Lines Matching +full:ufs +full:- +full:ddr
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
7 #include <dt-bindings/clock/qcom,rpmh.h>
8 #include <dt-bindings/clock/qcom,sm8650-camcc.h>
9 #include <dt-bindings/clock/qcom,sm8650-dispcc.h>
10 #include <dt-bindings/clock/qcom,sm8650-gcc.h>
11 #include <dt-bindings/clock/qcom,sm8650-gpucc.h>
12 #include <dt-bindings/clock/qcom,sm8650-tcsr.h>
13 #include <dt-bindings/clock/qcom,sm8650-videocc.h>
14 #include <dt-bindings/dma/qcom-gpi.h>
15 #include <dt-bindings/firmware/qcom,scm.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interconnect/qcom,icc.h>
18 #include <dt-bindings/interconnect/qcom,sm8650-rpmh.h>
19 #include <dt-bindings/interconnect/qcom,osm-l3.h>
20 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 #include <dt-bindings/mailbox/qcom-ipcc.h>
22 #include <dt-bindings/phy/phy-qcom-qmp.h>
23 #include <dt-bindings/power/qcom,rpmhpd.h>
24 #include <dt-bindings/power/qcom-rpmpd.h>
25 #include <dt-bindings/reset/qcom,sm8650-gpucc.h>
26 #include <dt-bindings/soc/qcom,gpr.h>
27 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
28 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
29 #include <dt-bindings/thermal/thermal.h>
32 interrupt-parent = <&intc>;
34 #address-cells = <2>;
35 #size-cells = <2>;
40 xo_board: xo-board {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
45 sleep_clk: sleep-clk {
46 compatible = "fixed-clock";
47 #clock-cells = <0>;
50 bi_tcxo_div2: bi-tcxo-div2-clk {
51 compatible = "fixed-factor-clock";
52 #clock-cells = <0>;
55 clock-mult = <1>;
56 clock-div = <2>;
59 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
60 compatible = "fixed-factor-clock";
61 #clock-cells = <0>;
64 clock-mult = <1>;
65 clock-div = <2>;
70 #address-cells = <2>;
71 #size-cells = <0>;
75 compatible = "arm,cortex-a520";
80 power-domains = <&cpu_pd0>;
81 power-domain-names = "psci";
83 enable-method = "psci";
84 next-level-cache = <&l2_0>;
85 capacity-dmips-mhz = <1024>;
86 dynamic-power-coefficient = <100>;
88 qcom,freq-domain = <&cpufreq_hw 0>;
90 operating-points-v2 = <&cpu0_opp_table>;
99 #cooling-cells = <2>;
101 l2_0: l2-cache {
103 cache-level = <2>;
104 cache-unified;
105 next-level-cache = <&l3_0>;
107 l3_0: l3-cache {
109 cache-level = <3>;
110 cache-unified;
117 compatible = "arm,cortex-a520";
122 power-domains = <&cpu_pd1>;
123 power-domain-names = "psci";
125 enable-method = "psci";
126 next-level-cache = <&l2_0>;
127 capacity-dmips-mhz = <1024>;
128 dynamic-power-coefficient = <100>;
130 qcom,freq-domain = <&cpufreq_hw 0>;
132 operating-points-v2 = <&cpu0_opp_table>;
141 #cooling-cells = <2>;
146 compatible = "arm,cortex-a720";
151 power-domains = <&cpu_pd2>;
152 power-domain-names = "psci";
154 enable-method = "psci";
155 next-level-cache = <&l2_200>;
156 capacity-dmips-mhz = <1792>;
157 dynamic-power-coefficient = <238>;
159 qcom,freq-domain = <&cpufreq_hw 3>;
161 operating-points-v2 = <&cpu2_opp_table>;
170 #cooling-cells = <2>;
172 l2_200: l2-cache {
174 cache-level = <2>;
175 cache-unified;
176 next-level-cache = <&l3_0>;
182 compatible = "arm,cortex-a720";
187 power-domains = <&cpu_pd3>;
188 power-domain-names = "psci";
190 enable-method = "psci";
191 next-level-cache = <&l2_300>;
192 capacity-dmips-mhz = <1792>;
193 dynamic-power-coefficient = <238>;
195 qcom,freq-domain = <&cpufreq_hw 3>;
197 operating-points-v2 = <&cpu2_opp_table>;
206 #cooling-cells = <2>;
208 l2_300: l2-cache {
210 cache-level = <2>;
211 cache-unified;
212 next-level-cache = <&l3_0>;
218 compatible = "arm,cortex-a720";
223 power-domains = <&cpu_pd4>;
224 power-domain-names = "psci";
226 enable-method = "psci";
227 next-level-cache = <&l2_400>;
228 capacity-dmips-mhz = <1792>;
229 dynamic-power-coefficient = <238>;
231 qcom,freq-domain = <&cpufreq_hw 3>;
233 operating-points-v2 = <&cpu2_opp_table>;
242 #cooling-cells = <2>;
244 l2_400: l2-cache {
246 cache-level = <2>;
247 cache-unified;
248 next-level-cache = <&l3_0>;
254 compatible = "arm,cortex-a720";
259 power-domains = <&cpu_pd5>;
260 power-domain-names = "psci";
262 enable-method = "psci";
263 next-level-cache = <&l2_500>;
264 capacity-dmips-mhz = <1792>;
265 dynamic-power-coefficient = <238>;
267 qcom,freq-domain = <&cpufreq_hw 1>;
269 operating-points-v2 = <&cpu5_opp_table>;
278 #cooling-cells = <2>;
280 l2_500: l2-cache {
282 cache-level = <2>;
283 cache-unified;
284 next-level-cache = <&l3_0>;
290 compatible = "arm,cortex-a720";
295 power-domains = <&cpu_pd6>;
296 power-domain-names = "psci";
298 enable-method = "psci";
299 next-level-cache = <&l2_600>;
300 capacity-dmips-mhz = <1792>;
301 dynamic-power-coefficient = <238>;
303 qcom,freq-domain = <&cpufreq_hw 1>;
305 operating-points-v2 = <&cpu5_opp_table>;
314 #cooling-cells = <2>;
316 l2_600: l2-cache {
318 cache-level = <2>;
319 cache-unified;
320 next-level-cache = <&l3_0>;
326 compatible = "arm,cortex-x4";
331 power-domains = <&cpu_pd7>;
332 power-domain-names = "psci";
334 enable-method = "psci";
335 next-level-cache = <&l2_700>;
336 capacity-dmips-mhz = <1894>;
337 dynamic-power-coefficient = <588>;
339 qcom,freq-domain = <&cpufreq_hw 2>;
341 operating-points-v2 = <&cpu7_opp_table>;
350 #cooling-cells = <2>;
352 l2_700: l2-cache {
354 cache-level = <2>;
355 cache-unified;
356 next-level-cache = <&l3_0>;
360 cpu-map {
396 idle-states {
397 entry-method = "psci";
399 silver_cpu_sleep_0: cpu-sleep-0-0 {
400 compatible = "arm,idle-state";
401 idle-state-name = "silver-rail-power-collapse";
402 arm,psci-suspend-param = <0x40000004>;
403 entry-latency-us = <550>;
404 exit-latency-us = <750>;
405 min-residency-us = <6700>;
406 local-timer-stop;
409 gold_cpu_sleep_0: cpu-sleep-1-0 {
410 compatible = "arm,idle-state";
411 idle-state-name = "gold-rail-power-collapse";
412 arm,psci-suspend-param = <0x40000004>;
413 entry-latency-us = <600>;
414 exit-latency-us = <1300>;
415 min-residency-us = <8136>;
416 local-timer-stop;
419 gold_plus_cpu_sleep_0: cpu-sleep-2-0 {
420 compatible = "arm,idle-state";
421 idle-state-name = "gold-plus-rail-power-collapse";
422 arm,psci-suspend-param = <0x40000004>;
423 entry-latency-us = <500>;
424 exit-latency-us = <1350>;
425 min-residency-us = <7480>;
426 local-timer-stop;
430 domain-idle-states {
431 cluster_sleep_0: cluster-sleep-0 {
432 compatible = "domain-idle-state";
433 arm,psci-suspend-param = <0x41000044>;
434 entry-latency-us = <750>;
435 exit-latency-us = <2350>;
436 min-residency-us = <9144>;
439 cluster_sleep_1: cluster-sleep-1 {
440 compatible = "domain-idle-state";
441 arm,psci-suspend-param = <0x4100c344>;
442 entry-latency-us = <2800>;
443 exit-latency-us = <4400>;
444 min-residency-us = <10150>;
449 ete-0 {
450 compatible = "arm,embedded-trace-extension";
454 out-ports {
457 remote-endpoint = <&funnel_ete_in_ete0>;
463 ete-1 {
464 compatible = "arm,embedded-trace-extension";
468 out-ports {
471 remote-endpoint = <&funnel_ete_in_ete1>;
477 ete-2 {
478 compatible = "arm,embedded-trace-extension";
482 out-ports {
485 remote-endpoint = <&funnel_ete_in_ete2>;
491 ete-3 {
492 compatible = "arm,embedded-trace-extension";
496 out-ports {
499 remote-endpoint = <&funnel_ete_in_ete3>;
505 ete-4 {
506 compatible = "arm,embedded-trace-extension";
510 out-ports {
513 remote-endpoint = <&funnel_ete_in_ete4>;
519 ete-5 {
520 compatible = "arm,embedded-trace-extension";
524 out-ports {
527 remote-endpoint = <&funnel_ete_in_ete5>;
533 ete-6 {
534 compatible = "arm,embedded-trace-extension";
538 out-ports {
541 remote-endpoint = <&funnel_ete_in_ete6>;
547 ete-7 {
548 compatible = "arm,embedded-trace-extension";
552 out-ports {
555 remote-endpoint = <&funnel_ete_in_ete7>;
561 funnel-ete {
562 compatible = "arm,coresight-static-funnel";
564 in-ports {
565 #address-cells = <1>;
566 #size-cells = <0>;
572 remote-endpoint = <&ete0_out_funnel_ete>;
580 remote-endpoint = <&ete1_out_funnel_ete>;
588 remote-endpoint = <&ete2_out_funnel_ete>;
596 remote-endpoint = <&ete3_out_funnel_ete>;
604 remote-endpoint = <&ete4_out_funnel_ete>;
612 remote-endpoint = <&ete5_out_funnel_ete>;
620 remote-endpoint = <&ete6_out_funnel_ete>;
628 remote-endpoint = <&ete7_out_funnel_ete>;
633 out-ports {
636 remote-endpoint = <&funnel_apss_in_funnel_ete>;
644 compatible = "qcom,scm-sm8650", "qcom,scm";
645 qcom,dload-mode = <&tcsr 0x19000>;
651 clk_virt: interconnect-0 {
652 compatible = "qcom,sm8650-clk-virt";
653 #interconnect-cells = <2>;
654 qcom,bcm-voters = <&apps_bcm_voter>;
657 mc_virt: interconnect-1 {
658 compatible = "qcom,sm8650-mc-virt";
659 #interconnect-cells = <2>;
660 qcom,bcm-voters = <&apps_bcm_voter>;
663 qup_opp_table_100mhz: opp-table-qup100mhz {
664 compatible = "operating-points-v2";
666 opp-75000000 {
667 opp-hz = /bits/ 64 <75000000>;
668 required-opps = <&rpmhpd_opp_low_svs>;
671 opp-100000000 {
672 opp-hz = /bits/ 64 <100000000>;
673 required-opps = <&rpmhpd_opp_svs>;
677 qup_opp_table_120mhz: opp-table-qup120mhz {
678 compatible = "operating-points-v2";
680 opp-75000000 {
681 opp-hz = /bits/ 64 <75000000>;
682 required-opps = <&rpmhpd_opp_low_svs>;
685 opp-120000000 {
686 opp-hz = /bits/ 64 <120000000>;
687 required-opps = <&rpmhpd_opp_svs>;
691 qup_opp_table_128mhz: opp-table-qup128mhz {
692 compatible = "operating-points-v2";
694 opp-75000000 {
695 opp-hz = /bits/ 64 <75000000>;
696 required-opps = <&rpmhpd_opp_low_svs>;
699 opp-128000000 {
700 opp-hz = /bits/ 64 <128000000>;
701 required-opps = <&rpmhpd_opp_svs>;
705 qup_opp_table_240mhz: opp-table-qup240mhz {
706 compatible = "operating-points-v2";
708 opp-150000000 {
709 opp-hz = /bits/ 64 <150000000>;
710 required-opps = <&rpmhpd_opp_low_svs>;
713 opp-240000000 {
714 opp-hz = /bits/ 64 <240000000>;
715 required-opps = <&rpmhpd_opp_svs>;
725 cpu0_opp_table: opp-table-cpu0 {
726 compatible = "operating-points-v2";
727 opp-shared;
729 opp-307200000 {
730 opp-hz = /bits/ 64 <307200000>;
731 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
734 opp-364800000 {
735 opp-hz = /bits/ 64 <364800000>;
736 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
739 opp-460800000 {
740 opp-hz = /bits/ 64 <460800000>;
741 opp-peak-kBps = <(300000 * 16) (547000 * 4) (384000 * 32)>;
744 opp-556800000 {
745 opp-hz = /bits/ 64 <556800000>;
746 opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
749 opp-672000000 {
750 opp-hz = /bits/ 64 <672000000>;
751 opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
754 opp-787200000 {
755 opp-hz = /bits/ 64 <787200000>;
756 opp-peak-kBps = <(300000 * 16) (547000 * 4) (729600 * 32)>;
759 opp-902400000 {
760 opp-hz = /bits/ 64 <902400000>;
761 opp-peak-kBps = <(300000 * 16) (547000 * 4) (844800 * 32)>;
764 opp-1017600000 {
765 opp-hz = /bits/ 64 <1017600000>;
766 opp-peak-kBps = <(466000 * 16) (547000 * 4) (940800 * 32)>;
769 opp-1132800000 {
770 opp-hz = /bits/ 64 <1132800000>;
771 opp-peak-kBps = <(466000 * 16) (547000 * 4) (1036800 * 32)>;
774 opp-1248000000 {
775 opp-hz = /bits/ 64 <1248000000>;
776 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1132800 * 32)>;
779 opp-1344000000 {
780 opp-hz = /bits/ 64 <1344000000>;
781 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1248000 * 32)>;
784 opp-1440000000 {
785 opp-hz = /bits/ 64 <1440000000>;
786 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1248000 * 32)>;
789 opp-1459200000 {
790 opp-hz = /bits/ 64 <1459200000>;
791 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1248000 * 32)>;
794 opp-1536000000 {
795 opp-hz = /bits/ 64 <1536000000>;
796 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1440000 * 32)>;
799 opp-1574400000 {
800 opp-hz = /bits/ 64 <1574400000>;
801 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1440000 * 32)>;
804 opp-1651200000 {
805 opp-hz = /bits/ 64 <1651200000>;
806 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1440000 * 32)>;
809 opp-1689600000 {
810 opp-hz = /bits/ 64 <1689600000>;
811 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1440000 * 32)>;
814 opp-1747200000 {
815 opp-hz = /bits/ 64 <1747200000>;
816 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1440000 * 32)>;
819 opp-1804800000 {
820 opp-hz = /bits/ 64 <1804800000>;
821 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1555200 * 32)>;
824 opp-1843200000 {
825 opp-hz = /bits/ 64 <1843200000>;
826 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1555200 * 32)>;
829 opp-1920000000 {
830 opp-hz = /bits/ 64 <1920000000>;
831 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1651200 * 32)>;
834 opp-1939200000 {
835 opp-hz = /bits/ 64 <1939200000>;
836 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1651200 * 32)>;
839 opp-2035200000 {
840 opp-hz = /bits/ 64 <2035200000>;
841 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1843200 * 32)>;
844 opp-2150400000 {
845 opp-hz = /bits/ 64 <2150400000>;
846 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1843200 * 32)>;
849 opp-2265600000 {
850 opp-hz = /bits/ 64 <2265600000>;
851 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (2035200 * 32)>;
855 cpu2_opp_table: opp-table-cpu2 {
856 compatible = "operating-points-v2";
857 opp-shared;
859 opp-460800000 {
860 opp-hz = /bits/ 64 <460800000>;
861 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
864 opp-499200000 {
865 opp-hz = /bits/ 64 <499200000>;
866 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
869 opp-576000000 {
870 opp-hz = /bits/ 64 <576000000>;
871 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
874 opp-614400000 {
875 opp-hz = /bits/ 64 <614400000>;
876 opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
879 opp-691200000 {
880 opp-hz = /bits/ 64 <691200000>;
881 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
884 opp-729600000 {
885 opp-hz = /bits/ 64 <729600000>;
886 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
889 opp-806400000 {
890 opp-hz = /bits/ 64 <806400000>;
891 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
894 opp-844800000 {
895 opp-hz = /bits/ 64 <844800000>;
896 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
899 opp-902400000 {
900 opp-hz = /bits/ 64 <902400000>;
901 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
904 opp-960000000 {
905 opp-hz = /bits/ 64 <960000000>;
906 opp-peak-kBps = <(466000 * 16) (768000 * 4) (844800 * 32)>;
909 opp-1036800000 {
910 opp-hz = /bits/ 64 <1036800000>;
911 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
914 opp-1075200000 {
915 opp-hz = /bits/ 64 <1075200000>;
916 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
919 opp-1152000000 {
920 opp-hz = /bits/ 64 <1152000000>;
921 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
924 opp-1190400000 {
925 opp-hz = /bits/ 64 <1190400000>;
926 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (1036800 * 32)>;
929 opp-1267200000 {
930 opp-hz = /bits/ 64 <1267200000>;
931 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
934 opp-1286400000 {
935 opp-hz = /bits/ 64 <1286400000>;
936 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
939 opp-1382400000 {
940 opp-hz = /bits/ 64 <1382400000>;
941 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
944 opp-1401600000 {
945 opp-hz = /bits/ 64 <1401600000>;
946 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1248000 * 32)>;
949 opp-1497600000 {
950 opp-hz = /bits/ 64 <1497600000>;
951 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
954 opp-1612800000 {
955 opp-hz = /bits/ 64 <1612800000>;
956 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
959 opp-1708800000 {
960 opp-hz = /bits/ 64 <1708800000>;
961 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
964 opp-1728000000 {
965 opp-hz = /bits/ 64 <1728000000>;
966 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
969 opp-1824000000 {
970 opp-hz = /bits/ 64 <1824000000>;
971 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
974 opp-1843200000 {
975 opp-hz = /bits/ 64 <1843200000>;
976 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
979 opp-1920000000 {
980 opp-hz = /bits/ 64 <1920000000>;
981 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1440000 * 32)>;
984 opp-1958400000 {
985 opp-hz = /bits/ 64 <1958400000>;
986 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
989 opp-2035200000 {
990 opp-hz = /bits/ 64 <2035200000>;
991 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
994 opp-2073600000 {
995 opp-hz = /bits/ 64 <2073600000>;
996 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
999 opp-2131200000 {
1000 opp-hz = /bits/ 64 <2131200000>;
1001 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1004 opp-2188800000 {
1005 opp-hz = /bits/ 64 <2188800000>;
1006 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1009 opp-2246400000 {
1010 opp-hz = /bits/ 64 <2246400000>;
1011 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1014 opp-2304000000 {
1015 opp-hz = /bits/ 64 <2304000000>;
1016 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1019 opp-2323200000 {
1020 opp-hz = /bits/ 64 <2323200000>;
1021 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1024 opp-2380800000 {
1025 opp-hz = /bits/ 64 <2380800000>;
1026 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1029 opp-2400000000 {
1030 opp-hz = /bits/ 64 <2400000000>;
1031 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1034 opp-2438400000 {
1035 opp-hz = /bits/ 64 <2438400000>;
1036 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1039 opp-2515200000 {
1040 opp-hz = /bits/ 64 <2515200000>;
1041 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1044 opp-2572800000 {
1045 opp-hz = /bits/ 64 <2572800000>;
1046 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>;
1049 opp-2630400000 {
1050 opp-hz = /bits/ 64 <2630400000>;
1051 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>;
1054 opp-2707200000 {
1055 opp-hz = /bits/ 64 <2707200000>;
1056 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>;
1059 opp-2764800000 {
1060 opp-hz = /bits/ 64 <2764800000>;
1061 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1843200 * 32)>;
1064 opp-2841600000 {
1065 opp-hz = /bits/ 64 <2841600000>;
1066 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
1069 opp-2899200000 {
1070 opp-hz = /bits/ 64 <2899200000>;
1071 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
1074 opp-2956800000 {
1075 opp-hz = /bits/ 64 <2956800000>;
1076 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
1079 opp-3014400000 {
1080 opp-hz = /bits/ 64 <3014400000>;
1081 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
1084 opp-3072000000 {
1085 opp-hz = /bits/ 64 <3072000000>;
1086 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
1089 opp-3148800000 {
1090 opp-hz = /bits/ 64 <3148800000>;
1091 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>;
1095 cpu5_opp_table: opp-table-cpu5 {
1096 compatible = "operating-points-v2";
1097 opp-shared;
1099 opp-460800000 {
1100 opp-hz = /bits/ 64 <460800000>;
1101 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
1104 opp-499200000 {
1105 opp-hz = /bits/ 64 <499200000>;
1106 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
1109 opp-576000000 {
1110 opp-hz = /bits/ 64 <576000000>;
1111 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
1114 opp-614400000 {
1115 opp-hz = /bits/ 64 <614400000>;
1116 opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
1119 opp-691200000 {
1120 opp-hz = /bits/ 64 <691200000>;
1121 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
1124 opp-729600000 {
1125 opp-hz = /bits/ 64 <729600000>;
1126 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
1129 opp-806400000 {
1130 opp-hz = /bits/ 64 <806400000>;
1131 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
1134 opp-844800000 {
1135 opp-hz = /bits/ 64 <844800000>;
1136 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
1139 opp-902400000 {
1140 opp-hz = /bits/ 64 <902400000>;
1141 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
1144 opp-960000000 {
1145 opp-hz = /bits/ 64 <960000000>;
1146 opp-peak-kBps = <(466000 * 16) (768000 * 4) (844800 * 32)>;
1149 opp-1036800000 {
1150 opp-hz = /bits/ 64 <1036800000>;
1151 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
1154 opp-1075200000 {
1155 opp-hz = /bits/ 64 <1075200000>;
1156 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
1159 opp-1152000000 {
1160 opp-hz = /bits/ 64 <1152000000>;
1161 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
1164 opp-1190400000 {
1165 opp-hz = /bits/ 64 <1190400000>;
1166 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (1036800 * 32)>;
1169 opp-1267200000 {
1170 opp-hz = /bits/ 64 <1267200000>;
1171 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
1174 opp-1286400000 {
1175 opp-hz = /bits/ 64 <1286400000>;
1176 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
1179 opp-1382400000 {
1180 opp-hz = /bits/ 64 <1382400000>;
1181 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
1184 opp-1401600000 {
1185 opp-hz = /bits/ 64 <1401600000>;
1186 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1248000 * 32)>;
1189 opp-1497600000 {
1190 opp-hz = /bits/ 64 <1497600000>;
1191 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
1194 opp-1612800000 {
1195 opp-hz = /bits/ 64 <1612800000>;
1196 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
1199 opp-1708800000 {
1200 opp-hz = /bits/ 64 <1708800000>;
1201 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
1204 opp-1728000000 {
1205 opp-hz = /bits/ 64 <1728000000>;
1206 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
1209 opp-1824000000 {
1210 opp-hz = /bits/ 64 <1824000000>;
1211 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
1214 opp-1843200000 {
1215 opp-hz = /bits/ 64 <1843200000>;
1216 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
1219 opp-1920000000 {
1220 opp-hz = /bits/ 64 <1920000000>;
1221 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1440000 * 32)>;
1224 opp-1958400000 {
1225 opp-hz = /bits/ 64 <1958400000>;
1226 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1229 opp-2035200000 {
1230 opp-hz = /bits/ 64 <2035200000>;
1231 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1234 opp-2073600000 {
1235 opp-hz = /bits/ 64 <2073600000>;
1236 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1239 opp-2131200000 {
1240 opp-hz = /bits/ 64 <2131200000>;
1241 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1244 opp-2188800000 {
1245 opp-hz = /bits/ 64 <2188800000>;
1246 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1249 opp-2246400000 {
1250 opp-hz = /bits/ 64 <2246400000>;
1251 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1254 opp-2304000000 {
1255 opp-hz = /bits/ 64 <2304000000>;
1256 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1259 opp-2323200000 {
1260 opp-hz = /bits/ 64 <2323200000>;
1261 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1264 opp-2380800000 {
1265 opp-hz = /bits/ 64 <2380800000>;
1266 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1269 opp-2400000000 {
1270 opp-hz = /bits/ 64 <2400000000>;
1271 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1274 opp-2438400000 {
1275 opp-hz = /bits/ 64 <2438400000>;
1276 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1279 opp-2515200000 {
1280 opp-hz = /bits/ 64 <2515200000>;
1281 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1284 opp-2572800000 {
1285 opp-hz = /bits/ 64 <2572800000>;
1286 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>;
1289 opp-2630400000 {
1290 opp-hz = /bits/ 64 <2630400000>;
1291 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>;
1294 opp-2707200000 {
1295 opp-hz = /bits/ 64 <2707200000>;
1296 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>;
1299 opp-2764800000 {
1300 opp-hz = /bits/ 64 <2764800000>;
1301 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1843200 * 32)>;
1304 opp-2841600000 {
1305 opp-hz = /bits/ 64 <2841600000>;
1306 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
1309 opp-2899200000 {
1310 opp-hz = /bits/ 64 <2899200000>;
1311 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
1314 opp-2956800000 {
1315 opp-hz = /bits/ 64 <2956800000>;
1316 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
1319 opp-3014400000 {
1320 opp-hz = /bits/ 64 <3014400000>;
1321 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
1324 opp-3072000000 {
1325 opp-hz = /bits/ 64 <3072000000>;
1326 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
1329 opp-3148800000 {
1330 opp-hz = /bits/ 64 <3148800000>;
1331 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>;
1335 cpu7_opp_table: opp-table-cpu7 {
1336 compatible = "operating-points-v2";
1337 opp-shared;
1339 opp-480000000 {
1340 opp-hz = /bits/ 64 <480000000>;
1341 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
1344 opp-499200000 {
1345 opp-hz = /bits/ 64 <499200000>;
1346 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
1349 opp-576000000 {
1350 opp-hz = /bits/ 64 <576000000>;
1351 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
1354 opp-614400000 {
1355 opp-hz = /bits/ 64 <614400000>;
1356 opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
1359 opp-672000000 {
1360 opp-hz = /bits/ 64 <672000000>;
1361 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
1364 opp-729600000 {
1365 opp-hz = /bits/ 64 <729600000>;
1366 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
1369 opp-787200000 {
1370 opp-hz = /bits/ 64 <787200000>;
1371 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
1374 opp-844800000 {
1375 opp-hz = /bits/ 64 <844800000>;
1376 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
1379 opp-902400000 {
1380 opp-hz = /bits/ 64 <902400000>;
1381 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
1384 opp-940800000 {
1385 opp-hz = /bits/ 64 <940800000>;
1386 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
1389 opp-1017600000 {
1390 opp-hz = /bits/ 64 <1017600000>;
1391 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
1394 opp-1075200000 {
1395 opp-hz = /bits/ 64 <1075200000>;
1396 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
1399 opp-1132800000 {
1400 opp-hz = /bits/ 64 <1132800000>;
1401 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
1404 opp-1190400000 {
1405 opp-hz = /bits/ 64 <1190400000>;
1406 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (1036800 * 32)>;
1409 opp-1248000000 {
1410 opp-hz = /bits/ 64 <1248000000>;
1411 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
1414 opp-1305600000 {
1415 opp-hz = /bits/ 64 <1305600000>;
1416 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
1419 opp-1363200000 {
1420 opp-hz = /bits/ 64 <1363200000>;
1421 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
1424 opp-1420800000 {
1425 opp-hz = /bits/ 64 <1420800000>;
1426 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1248000 * 32)>;
1429 opp-1478400000 {
1430 opp-hz = /bits/ 64 <1478400000>;
1431 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
1434 opp-1555200000 {
1435 opp-hz = /bits/ 64 <1555200000>;
1436 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
1439 opp-1593600000 {
1440 opp-hz = /bits/ 64 <1593600000>;
1441 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
1444 opp-1670400000 {
1445 opp-hz = /bits/ 64 <1670400000>;
1446 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
1449 opp-1708800000 {
1450 opp-hz = /bits/ 64 <1708800000>;
1451 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
1454 opp-1804800000 {
1455 opp-hz = /bits/ 64 <1804800000>;
1456 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
1459 opp-1824000000 {
1460 opp-hz = /bits/ 64 <1824000000>;
1461 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
1464 opp-1939200000 {
1465 opp-hz = /bits/ 64 <1939200000>;
1466 opp-peak-kBps = <(806000 * 16) (3686000 * 4) (1440000 * 32)>;
1469 opp-2035200000 {
1470 opp-hz = /bits/ 64 <2035200000>;
1471 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1474 opp-2073600000 {
1475 opp-hz = /bits/ 64 <2073600000>;
1476 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1479 opp-2112000000 {
1480 opp-hz = /bits/ 64 <2112000000>;
1481 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1484 opp-2169600000 {
1485 opp-hz = /bits/ 64 <2169600000>;
1486 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1489 opp-2208000000 {
1490 opp-hz = /bits/ 64 <2208000000>;
1491 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1494 opp-2246400000 {
1495 opp-hz = /bits/ 64 <2246400000>;
1496 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1499 opp-2304000000 {
1500 opp-hz = /bits/ 64 <2304000000>;
1501 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1504 opp-2342400000 {
1505 opp-hz = /bits/ 64 <2342400000>;
1506 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1509 opp-2380800000 {
1510 opp-hz = /bits/ 64 <2380800000>;
1511 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1514 opp-2438400000 {
1515 opp-hz = /bits/ 64 <2438400000>;
1516 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1519 opp-2457600000 {
1520 opp-hz = /bits/ 64 <2457600000>;
1521 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1524 opp-2496000000 {
1525 opp-hz = /bits/ 64 <2496000000>;
1526 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1529 opp-2553600000 {
1530 opp-hz = /bits/ 64 <2553600000>;
1531 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1534 opp-2630400000 {
1535 opp-hz = /bits/ 64 <2630400000>;
1536 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>;
1539 opp-2688000000 {
1540 opp-hz = /bits/ 64 <2688000000>;
1541 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>;
1544 opp-2745600000 {
1545 opp-hz = /bits/ 64 <2745600000>;
1546 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1843200 * 32)>;
1549 opp-2803200000 {
1550 opp-hz = /bits/ 64 <2803200000>;
1551 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
1554 opp-2880000000 {
1555 opp-hz = /bits/ 64 <2880000000>;
1556 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
1559 opp-2937600000 {
1560 opp-hz = /bits/ 64 <2937600000>;
1561 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
1564 opp-2995200000 {
1565 opp-hz = /bits/ 64 <2995200000>;
1566 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
1569 opp-3052800000 {
1570 opp-hz = /bits/ 64 <3052800000>;
1571 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
1574 opp-3187200000 {
1575 opp-hz = /bits/ 64 <3187200000>;
1576 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>;
1579 opp-3302400000 {
1580 opp-hz = /bits/ 64 <3302400000>;
1581 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>;
1585 pmu-a520 {
1586 compatible = "arm,cortex-a520-pmu";
1590 pmu-a720 {
1591 compatible = "arm,cortex-a720-pmu";
1595 pmu-x4 {
1596 compatible = "arm,cortex-x4-pmu";
1601 compatible = "arm,psci-1.0";
1604 cpu_pd0: power-domain-cpu0 {
1605 #power-domain-cells = <0>;
1606 power-domains = <&cluster_pd>;
1607 domain-idle-states = <&silver_cpu_sleep_0>;
1610 cpu_pd1: power-domain-cpu1 {
1611 #power-domain-cells = <0>;
1612 power-domains = <&cluster_pd>;
1613 domain-idle-states = <&silver_cpu_sleep_0>;
1616 cpu_pd2: power-domain-cpu2 {
1617 #power-domain-cells = <0>;
1618 power-domains = <&cluster_pd>;
1619 domain-idle-states = <&gold_cpu_sleep_0>;
1622 cpu_pd3: power-domain-cpu3 {
1623 #power-domain-cells = <0>;
1624 power-domains = <&cluster_pd>;
1625 domain-idle-states = <&gold_cpu_sleep_0>;
1628 cpu_pd4: power-domain-cpu4 {
1629 #power-domain-cells = <0>;
1630 power-domains = <&cluster_pd>;
1631 domain-idle-states = <&gold_cpu_sleep_0>;
1634 cpu_pd5: power-domain-cpu5 {
1635 #power-domain-cells = <0>;
1636 power-domains = <&cluster_pd>;
1637 domain-idle-states = <&gold_cpu_sleep_0>;
1640 cpu_pd6: power-domain-cpu6 {
1641 #power-domain-cells = <0>;
1642 power-domains = <&cluster_pd>;
1643 domain-idle-states = <&gold_cpu_sleep_0>;
1646 cpu_pd7: power-domain-cpu7 {
1647 #power-domain-cells = <0>;
1648 power-domains = <&cluster_pd>;
1649 domain-idle-states = <&gold_plus_cpu_sleep_0>;
1652 cluster_pd: power-domain-cluster {
1653 #power-domain-cells = <0>;
1654 domain-idle-states = <&cluster_sleep_0>,
1659 reserved_memory: reserved-memory {
1660 #address-cells = <2>;
1661 #size-cells = <2>;
1666 no-map;
1669 cpusys_vm_mem: cpusys-vm@80e00000 {
1671 no-map;
1675 xbl_dt_log_merged_mem: xbl-dt-log-merged@81a00000 {
1677 no-map;
1680 aop_cmd_db_mem: aop-cmd-db@81c60000 {
1681 compatible = "qcom,cmd-db";
1683 no-map;
1687 aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 {
1689 no-map;
1698 no-map;
1701 adsp_mhi_mem: adsp-mhi@81f00000 {
1703 no-map;
1708 no-map;
1711 global_sync_mem: global-sync@82600000 {
1713 no-map;
1716 tz_stat_mem: tz-stat@82700000 {
1718 no-map;
1723 no-map;
1726 qlink_logging_mem: qlink-logging@84800000 {
1728 no-map;
1731 mpss_dsm_mem: mpss-dsm@86b00000 {
1733 no-map;
1736 mpss_dsm_mem_2: mpss-dsm-2@8b400000 {
1738 no-map;
1743 no-map;
1746 q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 {
1748 no-map;
1751 ipa_fw_mem: ipa-fw@9b080000 {
1753 no-map;
1756 ipa_gsi_mem: ipa-gsi@9b090000 {
1758 no-map;
1761 gpu_micro_code_mem: gpu-micro-code@9b09a000 {
1763 no-map;
1768 no-map;
1772 spu_tz_shared_mem: spu-tz-shared@9b280000 {
1774 no-map;
1778 spu_modem_shared_mem: spu-modem-shared@9b2e0000 {
1780 no-map;
1785 no-map;
1790 no-map;
1795 no-map;
1800 no-map;
1803 q6_cdsp_dtb_mem: q6-cdsp-dtb@9de00000 {
1805 no-map;
1808 q6_adsp_dtb_mem: q6-adsp-dtb@9de80000 {
1810 no-map;
1815 no-map;
1819 compatible = "qcom,rmtfs-mem";
1821 no-map;
1823 qcom,client-id = <1>;
1828 tz_merged_mem: tz-merged@d8000000 {
1830 no-map;
1833 hwfence_shbuf: hwfence-shbuf@e6440000 {
1835 no-map;
1838 trust_ui_vm_mem: trust-ui-vm@f3800000 {
1840 no-map;
1843 oem_vm_mem: oem-vm@f7c00000 {
1845 no-map;
1848 llcc_lpi_mem: llcc-lpi@ff800000 {
1850 no-map;
1854 smp2p-adsp {
1857 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
1865 qcom,local-pid = <0>;
1866 qcom,remote-pid = <2>;
1868 smp2p_adsp_out: master-kernel {
1869 qcom,entry-name = "master-kernel";
1870 #qcom,smem-state-cells = <1>;
1873 smp2p_adsp_in: slave-kernel {
1874 qcom,entry-name = "slave-kernel";
1875 interrupt-controller;
1876 #interrupt-cells = <2>;
1880 smp2p-cdsp {
1883 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
1891 qcom,local-pid = <0>;
1892 qcom,remote-pid = <5>;
1894 smp2p_cdsp_out: master-kernel {
1895 qcom,entry-name = "master-kernel";
1896 #qcom,smem-state-cells = <1>;
1899 smp2p_cdsp_in: slave-kernel {
1900 qcom,entry-name = "slave-kernel";
1901 interrupt-controller;
1902 #interrupt-cells = <2>;
1906 smp2p-modem {
1909 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
1917 qcom,local-pid = <0>;
1918 qcom,remote-pid = <1>;
1920 smp2p_modem_out: master-kernel {
1921 qcom,entry-name = "master-kernel";
1922 #qcom,smem-state-cells = <1>;
1925 smp2p_modem_in: slave-kernel {
1926 qcom,entry-name = "slave-kernel";
1927 interrupt-controller;
1928 #interrupt-cells = <2>;
1931 ipa_smp2p_out: ipa-ap-to-modem {
1932 qcom,entry-name = "ipa";
1933 #qcom,smem-state-cells = <1>;
1936 ipa_smp2p_in: ipa-modem-to-ap {
1937 qcom,entry-name = "ipa";
1938 interrupt-controller;
1939 #interrupt-cells = <2>;
1944 compatible = "simple-bus";
1946 #address-cells = <2>;
1947 #size-cells = <2>;
1948 dma-ranges = <0 0 0 0 0x10 0>;
1951 gcc: clock-controller@100000 {
1952 compatible = "qcom,sm8650-gcc";
1966 #clock-cells = <1>;
1967 #reset-cells = <1>;
1968 #power-domain-cells = <1>;
1972 compatible = "qcom,sm8650-ipcc", "qcom,ipcc";
1976 interrupt-controller;
1977 #interrupt-cells = <3>;
1979 #mbox-cells = <2>;
1982 gpi_dma2: dma-controller@800000 {
1983 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma";
1999 dma-channels = <12>;
2000 dma-channel-mask = <0x3f>;
2001 #dma-cells = <3>;
2005 dma-coherent;
2011 compatible = "qcom,geni-se-qup";
2016 clock-names = "m-ahb",
2017 "s-ahb";
2021 dma-coherent;
2023 #address-cells = <2>;
2024 #size-cells = <2>;
2030 compatible = "qcom,geni-i2c";
2036 clock-names = "se";
2044 interconnect-names = "qup-core",
2045 "qup-config",
2046 "qup-memory";
2048 power-domains = <&rpmhpd RPMHPD_CX>;
2050 operating-points-v2 = <&qup_opp_table_120mhz>;
2054 dma-names = "tx",
2057 pinctrl-0 = <&qup_i2c8_data_clk>;
2058 pinctrl-names = "default";
2060 #address-cells = <1>;
2061 #size-cells = <0>;
2067 compatible = "qcom,geni-spi";
2073 clock-names = "se";
2081 interconnect-names = "qup-core",
2082 "qup-config",
2083 "qup-memory";
2085 power-domains = <&rpmhpd RPMHPD_CX>;
2087 operating-points-v2 = <&qup_opp_table_100mhz>;
2091 dma-names = "tx",
2094 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
2095 pinctrl-names = "default";
2097 #address-cells = <1>;
2098 #size-cells = <0>;
2104 compatible = "qcom,geni-i2c";
2110 clock-names = "se";
2118 interconnect-names = "qup-core",
2119 "qup-config",
2120 "qup-memory";
2122 power-domains = <&rpmhpd RPMHPD_CX>;
2124 operating-points-v2 = <&qup_opp_table_120mhz>;
2128 dma-names = "tx",
2131 pinctrl-0 = <&qup_i2c9_data_clk>;
2132 pinctrl-names = "default";
2134 #address-cells = <1>;
2135 #size-cells = <0>;
2141 compatible = "qcom,geni-spi";
2147 clock-names = "se";
2155 interconnect-names = "qup-core",
2156 "qup-config",
2157 "qup-memory";
2159 power-domains = <&rpmhpd RPMHPD_CX>;
2161 operating-points-v2 = <&qup_opp_table_120mhz>;
2165 dma-names = "tx",
2168 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
2169 pinctrl-names = "default";
2171 #address-cells = <1>;
2172 #size-cells = <0>;
2178 compatible = "qcom,geni-i2c";
2184 clock-names = "se";
2192 interconnect-names = "qup-core",
2193 "qup-config",
2194 "qup-memory";
2196 power-domains = <&rpmhpd RPMHPD_CX>;
2198 operating-points-v2 = <&qup_opp_table_120mhz>;
2202 dma-names = "tx",
2205 pinctrl-0 = <&qup_i2c10_data_clk>;
2206 pinctrl-names = "default";
2208 #address-cells = <1>;
2209 #size-cells = <0>;
2215 compatible = "qcom,geni-spi";
2221 clock-names = "se";
2229 interconnect-names = "qup-core",
2230 "qup-config",
2231 "qup-memory";
2233 power-domains = <&rpmhpd RPMHPD_CX>;
2235 operating-points-v2 = <&qup_opp_table_120mhz>;
2239 dma-names = "tx",
2242 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
2243 pinctrl-names = "default";
2245 #address-cells = <1>;
2246 #size-cells = <0>;
2252 compatible = "qcom,geni-i2c";
2258 clock-names = "se";
2266 interconnect-names = "qup-core",
2267 "qup-config",
2268 "qup-memory";
2270 power-domains = <&rpmhpd RPMHPD_CX>;
2272 operating-points-v2 = <&qup_opp_table_120mhz>;
2276 dma-names = "tx",
2279 pinctrl-0 = <&qup_i2c11_data_clk>;
2280 pinctrl-names = "default";
2282 #address-cells = <1>;
2283 #size-cells = <0>;
2289 compatible = "qcom,geni-spi";
2295 clock-names = "se";
2303 interconnect-names = "qup-core",
2304 "qup-config",
2305 "qup-memory";
2307 power-domains = <&rpmhpd RPMHPD_CX>;
2309 operating-points-v2 = <&qup_opp_table_120mhz>;
2313 dma-names = "tx",
2316 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
2317 pinctrl-names = "default";
2319 #address-cells = <1>;
2320 #size-cells = <0>;
2326 compatible = "qcom,geni-i2c";
2332 clock-names = "se";
2340 interconnect-names = "qup-core",
2341 "qup-config",
2342 "qup-memory";
2344 power-domains = <&rpmhpd RPMHPD_CX>;
2346 operating-points-v2 = <&qup_opp_table_100mhz>;
2350 dma-names = "tx",
2353 pinctrl-0 = <&qup_i2c12_data_clk>;
2354 pinctrl-names = "default";
2356 #address-cells = <1>;
2357 #size-cells = <0>;
2363 compatible = "qcom,geni-spi";
2369 clock-names = "se";
2377 interconnect-names = "qup-core",
2378 "qup-config",
2379 "qup-memory";
2381 power-domains = <&rpmhpd RPMHPD_CX>;
2383 operating-points-v2 = <&qup_opp_table_100mhz>;
2387 dma-names = "tx",
2390 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
2391 pinctrl-names = "default";
2393 #address-cells = <1>;
2394 #size-cells = <0>;
2400 compatible = "qcom,geni-i2c";
2406 clock-names = "se";
2414 interconnect-names = "qup-core",
2415 "qup-config",
2416 "qup-memory";
2418 power-domains = <&rpmhpd RPMHPD_CX>;
2420 operating-points-v2 = <&qup_opp_table_100mhz>;
2424 dma-names = "tx",
2427 pinctrl-0 = <&qup_i2c13_data_clk>;
2428 pinctrl-names = "default";
2430 #address-cells = <1>;
2431 #size-cells = <0>;
2437 compatible = "qcom,geni-spi";
2443 clock-names = "se";
2451 interconnect-names = "qup-core",
2452 "qup-config",
2453 "qup-memory";
2455 power-domains = <&rpmhpd RPMHPD_CX>;
2457 operating-points-v2 = <&qup_opp_table_100mhz>;
2461 dma-names = "tx",
2464 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
2465 pinctrl-names = "default";
2467 #address-cells = <1>;
2468 #size-cells = <0>;
2474 compatible = "qcom,geni-uart";
2480 clock-names = "se";
2486 interconnect-names = "qup-core",
2487 "qup-config";
2489 power-domains = <&rpmhpd RPMHPD_CX>;
2491 operating-points-v2 = <&qup_opp_table_128mhz>;
2493 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
2494 pinctrl-names = "default";
2500 compatible = "qcom,geni-debug-uart";
2506 clock-names = "se";
2512 interconnect-names = "qup-core",
2513 "qup-config";
2515 power-domains = <&rpmhpd RPMHPD_CX>;
2517 operating-points-v2 = <&qup_opp_table_100mhz>;
2519 pinctrl-0 = <&qup_uart15_default>;
2520 pinctrl-names = "default";
2527 compatible = "qcom,geni-se-i2c-master-hub";
2531 clock-names = "s-ahb";
2533 #address-cells = <2>;
2534 #size-cells = <2>;
2540 compatible = "qcom,geni-i2c-master-hub";
2547 clock-names = "se",
2554 interconnect-names = "qup-core",
2555 "qup-config";
2557 power-domains = <&rpmhpd RPMHPD_CX>;
2559 required-opps = <&rpmhpd_opp_low_svs>;
2561 pinctrl-0 = <&hub_i2c0_data_clk>;
2562 pinctrl-names = "default";
2564 #address-cells = <1>;
2565 #size-cells = <0>;
2571 compatible = "qcom,geni-i2c-master-hub";
2578 clock-names = "se",
2585 interconnect-names = "qup-core",
2586 "qup-config";
2588 power-domains = <&rpmhpd RPMHPD_CX>;
2590 required-opps = <&rpmhpd_opp_low_svs>;
2592 pinctrl-0 = <&hub_i2c1_data_clk>;
2593 pinctrl-names = "default";
2595 #address-cells = <1>;
2596 #size-cells = <0>;
2602 compatible = "qcom,geni-i2c-master-hub";
2609 clock-names = "se",
2616 interconnect-names = "qup-core",
2617 "qup-config";
2619 power-domains = <&rpmhpd RPMHPD_CX>;
2621 required-opps = <&rpmhpd_opp_low_svs>;
2623 pinctrl-0 = <&hub_i2c2_data_clk>;
2624 pinctrl-names = "default";
2626 #address-cells = <1>;
2627 #size-cells = <0>;
2633 compatible = "qcom,geni-i2c-master-hub";
2640 clock-names = "se",
2647 interconnect-names = "qup-core",
2648 "qup-config";
2650 power-domains = <&rpmhpd RPMHPD_CX>;
2652 required-opps = <&rpmhpd_opp_low_svs>;
2654 pinctrl-0 = <&hub_i2c3_data_clk>;
2655 pinctrl-names = "default";
2657 #address-cells = <1>;
2658 #size-cells = <0>;
2664 compatible = "qcom,geni-i2c-master-hub";
2671 clock-names = "se",
2678 interconnect-names = "qup-core",
2679 "qup-config";
2681 power-domains = <&rpmhpd RPMHPD_CX>;
2683 required-opps = <&rpmhpd_opp_low_svs>;
2685 pinctrl-0 = <&hub_i2c4_data_clk>;
2686 pinctrl-names = "default";
2688 #address-cells = <1>;
2689 #size-cells = <0>;
2695 compatible = "qcom,geni-i2c-master-hub";
2702 clock-names = "se",
2709 interconnect-names = "qup-core",
2710 "qup-config";
2712 power-domains = <&rpmhpd RPMHPD_CX>;
2714 required-opps = <&rpmhpd_opp_low_svs>;
2716 pinctrl-0 = <&hub_i2c5_data_clk>;
2717 pinctrl-names = "default";
2719 #address-cells = <1>;
2720 #size-cells = <0>;
2726 compatible = "qcom,geni-i2c-master-hub";
2733 clock-names = "se",
2740 interconnect-names = "qup-core",
2741 "qup-config";
2743 power-domains = <&rpmhpd RPMHPD_CX>;
2745 required-opps = <&rpmhpd_opp_low_svs>;
2747 pinctrl-0 = <&hub_i2c6_data_clk>;
2748 pinctrl-names = "default";
2750 #address-cells = <1>;
2751 #size-cells = <0>;
2757 compatible = "qcom,geni-i2c-master-hub";
2764 clock-names = "se",
2771 interconnect-names = "qup-core",
2772 "qup-config";
2774 power-domains = <&rpmhpd RPMHPD_CX>;
2776 required-opps = <&rpmhpd_opp_low_svs>;
2778 pinctrl-0 = <&hub_i2c7_data_clk>;
2779 pinctrl-names = "default";
2781 #address-cells = <1>;
2782 #size-cells = <0>;
2788 compatible = "qcom,geni-i2c-master-hub";
2795 clock-names = "se",
2802 interconnect-names = "qup-core",
2803 "qup-config";
2805 power-domains = <&rpmhpd RPMHPD_CX>;
2807 required-opps = <&rpmhpd_opp_low_svs>;
2809 pinctrl-0 = <&hub_i2c8_data_clk>;
2810 pinctrl-names = "default";
2812 #address-cells = <1>;
2813 #size-cells = <0>;
2819 compatible = "qcom,geni-i2c-master-hub";
2826 clock-names = "se",
2833 interconnect-names = "qup-core",
2834 "qup-config";
2836 power-domains = <&rpmhpd RPMHPD_CX>;
2838 required-opps = <&rpmhpd_opp_low_svs>;
2840 pinctrl-0 = <&hub_i2c9_data_clk>;
2841 pinctrl-names = "default";
2843 #address-cells = <1>;
2844 #size-cells = <0>;
2850 gpi_dma1: dma-controller@a00000 {
2851 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma";
2867 dma-channels = <12>;
2868 dma-channel-mask = <0xc>;
2869 #dma-cells = <3>;
2872 dma-coherent;
2878 compatible = "qcom,geni-se-qup";
2883 clock-names = "m-ahb",
2884 "s-ahb";
2888 interconnect-names = "qup-core";
2892 dma-coherent;
2894 #address-cells = <2>;
2895 #size-cells = <2>;
2901 compatible = "qcom,geni-i2c";
2907 clock-names = "se";
2915 interconnect-names = "qup-core",
2916 "qup-config",
2917 "qup-memory";
2919 power-domains = <&rpmhpd RPMHPD_CX>;
2921 operating-points-v2 = <&qup_opp_table_120mhz>;
2925 dma-names = "tx",
2928 pinctrl-0 = <&qup_i2c0_data_clk>;
2929 pinctrl-names = "default";
2931 #address-cells = <1>;
2932 #size-cells = <0>;
2938 compatible = "qcom,geni-spi";
2944 clock-names = "se";
2952 interconnect-names = "qup-core",
2953 "qup-config",
2954 "qup-memory";
2956 power-domains = <&rpmhpd RPMHPD_CX>;
2958 operating-points-v2 = <&qup_opp_table_120mhz>;
2962 dma-names = "tx",
2965 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
2966 pinctrl-names = "default";
2968 #address-cells = <1>;
2969 #size-cells = <0>;
2975 compatible = "qcom,geni-i2c";
2981 clock-names = "se";
2989 interconnect-names = "qup-core",
2990 "qup-config",
2991 "qup-memory";
2993 power-domains = <&rpmhpd RPMHPD_CX>;
2995 operating-points-v2 = <&qup_opp_table_120mhz>;
2999 dma-names = "tx",
3002 pinctrl-0 = <&qup_i2c1_data_clk>;
3003 pinctrl-names = "default";
3005 #address-cells = <1>;
3006 #size-cells = <0>;
3012 compatible = "qcom,geni-spi";
3018 clock-names = "se";
3026 interconnect-names = "qup-core",
3027 "qup-config",
3028 "qup-memory";
3030 power-domains = <&rpmhpd RPMHPD_CX>;
3032 operating-points-v2 = <&qup_opp_table_120mhz>;
3036 dma-names = "tx",
3039 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
3040 pinctrl-names = "default";
3042 #address-cells = <1>;
3043 #size-cells = <0>;
3049 compatible = "qcom,geni-i2c";
3055 clock-names = "se";
3063 interconnect-names = "qup-core",
3064 "qup-config",
3065 "qup-memory";
3067 power-domains = <&rpmhpd RPMHPD_CX>;
3069 operating-points-v2 = <&qup_opp_table_240mhz>;
3073 dma-names = "tx",
3076 pinctrl-0 = <&qup_i2c2_data_clk>;
3077 pinctrl-names = "default";
3079 #address-cells = <1>;
3080 #size-cells = <0>;
3086 compatible = "qcom,geni-spi";
3092 clock-names = "se";
3100 interconnect-names = "qup-core",
3101 "qup-config",
3102 "qup-memory";
3104 power-domains = <&rpmhpd RPMHPD_CX>;
3106 operating-points-v2 = <&qup_opp_table_240mhz>;
3110 dma-names = "tx",
3113 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
3114 pinctrl-names = "default";
3116 #address-cells = <1>;
3117 #size-cells = <0>;
3123 compatible = "qcom,geni-i2c";
3129 clock-names = "se";
3137 interconnect-names = "qup-core",
3138 "qup-config",
3139 "qup-memory";
3141 power-domains = <&rpmhpd RPMHPD_CX>;
3143 operating-points-v2 = <&qup_opp_table_100mhz>;
3147 dma-names = "tx",
3150 pinctrl-0 = <&qup_i2c3_data_clk>;
3151 pinctrl-names = "default";
3153 #address-cells = <1>;
3154 #size-cells = <0>;
3160 compatible = "qcom,geni-spi";
3166 clock-names = "se";
3174 interconnect-names = "qup-core",
3175 "qup-config",
3176 "qup-memory";
3178 power-domains = <&rpmhpd RPMHPD_CX>;
3180 operating-points-v2 = <&qup_opp_table_100mhz>;
3184 dma-names = "tx",
3187 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
3188 pinctrl-names = "default";
3190 #address-cells = <1>;
3191 #size-cells = <0>;
3197 compatible = "qcom,geni-i2c";
3203 clock-names = "se";
3211 interconnect-names = "qup-core",
3212 "qup-config",
3213 "qup-memory";
3215 power-domains = <&rpmhpd RPMHPD_CX>;
3217 operating-points-v2 = <&qup_opp_table_120mhz>;
3221 dma-names = "tx",
3224 pinctrl-0 = <&qup_i2c4_data_clk>;
3225 pinctrl-names = "default";
3227 #address-cells = <1>;
3228 #size-cells = <0>;
3234 compatible = "qcom,geni-spi";
3240 clock-names = "se";
3248 interconnect-names = "qup-core",
3249 "qup-config",
3250 "qup-memory";
3252 power-domains = <&rpmhpd RPMHPD_CX>;
3254 operating-points-v2 = <&qup_opp_table_120mhz>;
3258 dma-names = "tx",
3261 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
3262 pinctrl-names = "default";
3264 #address-cells = <1>;
3265 #size-cells = <0>;
3271 compatible = "qcom,geni-i2c";
3277 clock-names = "se";
3285 interconnect-names = "qup-core",
3286 "qup-config",
3287 "qup-memory";
3289 power-domains = <&rpmhpd RPMHPD_CX>;
3291 operating-points-v2 = <&qup_opp_table_100mhz>;
3295 dma-names = "tx",
3298 pinctrl-0 = <&qup_i2c5_data_clk>;
3299 pinctrl-names = "default";
3301 #address-cells = <1>;
3302 #size-cells = <0>;
3308 compatible = "qcom,geni-spi";
3314 clock-names = "se";
3322 interconnect-names = "qup-core",
3323 "qup-config",
3324 "qup-memory";
3326 power-domains = <&rpmhpd RPMHPD_CX>;
3328 operating-points-v2 = <&qup_opp_table_100mhz>;
3332 dma-names = "tx",
3335 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
3336 pinctrl-names = "default";
3338 #address-cells = <1>;
3339 #size-cells = <0>;
3345 compatible = "qcom,geni-i2c";
3351 clock-names = "se";
3359 interconnect-names = "qup-core",
3360 "qup-config",
3361 "qup-memory";
3363 power-domains = <&rpmhpd RPMHPD_CX>;
3365 operating-points-v2 = <&qup_opp_table_120mhz>;
3369 dma-names = "tx",
3372 pinctrl-0 = <&qup_i2c6_data_clk>;
3373 pinctrl-names = "default";
3375 #address-cells = <1>;
3376 #size-cells = <0>;
3382 compatible = "qcom,geni-spi";
3388 clock-names = "se";
3396 interconnect-names = "qup-core",
3397 "qup-config",
3398 "qup-memory";
3400 power-domains = <&rpmhpd RPMHPD_CX>;
3402 operating-points-v2 = <&qup_opp_table_120mhz>;
3406 dma-names = "tx",
3409 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
3410 pinctrl-names = "default";
3412 #address-cells = <1>;
3413 #size-cells = <0>;
3419 compatible = "qcom,geni-i2c";
3425 clock-names = "se";
3433 interconnect-names = "qup-core",
3434 "qup-config",
3435 "qup-memory";
3437 power-domains = <&rpmhpd RPMHPD_CX>;
3439 operating-points-v2 = <&qup_opp_table_100mhz>;
3443 dma-names = "tx",
3446 pinctrl-0 = <&qup_i2c7_data_clk>;
3447 pinctrl-names = "default";
3449 #address-cells = <1>;
3450 #size-cells = <0>;
3456 compatible = "qcom,geni-spi";
3462 clock-names = "se";
3470 interconnect-names = "qup-core",
3471 "qup-config",
3472 "qup-memory";
3474 power-domains = <&rpmhpd RPMHPD_CX>;
3476 operating-points-v2 = <&qup_opp_table_100mhz>;
3480 dma-names = "tx",
3483 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
3484 pinctrl-names = "default";
3486 #address-cells = <1>;
3487 #size-cells = <0>;
3494 compatible = "qcom,sm8650-cnoc-main";
3497 qcom,bcm-voters = <&apps_bcm_voter>;
3499 #interconnect-cells = <2>;
3503 compatible = "qcom,sm8650-config-noc";
3506 qcom,bcm-voters = <&apps_bcm_voter>;
3508 #interconnect-cells = <2>;
3512 compatible = "qcom,sm8650-system-noc";
3515 qcom,bcm-voters = <&apps_bcm_voter>;
3517 #interconnect-cells = <2>;
3521 compatible = "qcom,sm8650-pcie-anoc";
3527 qcom,bcm-voters = <&apps_bcm_voter>;
3529 #interconnect-cells = <2>;
3533 compatible = "qcom,sm8650-aggre1-noc";
3539 qcom,bcm-voters = <&apps_bcm_voter>;
3541 #interconnect-cells = <2>;
3545 compatible = "qcom,sm8650-aggre2-noc";
3550 qcom,bcm-voters = <&apps_bcm_voter>;
3552 #interconnect-cells = <2>;
3556 compatible = "qcom,sm8650-mmss-noc";
3559 qcom,bcm-voters = <&apps_bcm_voter>;
3561 #interconnect-cells = <2>;
3565 compatible = "qcom,sm8650-trng", "qcom,trng";
3571 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550";
3577 reg-names = "parf", "dbi", "elbi", "atu", "config";
3588 interrupt-names = "msi0",
3606 clock-names = "aux",
3616 reset-names = "pci";
3622 interconnect-names = "pcie-mem",
3623 "cpu-pcie";
3625 power-domains = <&gcc PCIE_0_GDSC>;
3627 operating-points-v2 = <&pcie0_opp_table>;
3629 iommu-map = <0 &apps_smmu 0x1400 0x1>,
3632 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH 0>,
3636 interrupt-map-mask = <0 0 0 0x7>;
3637 #interrupt-cells = <1>;
3639 msi-map = <0x0 &gic_its 0x1400 0x1>,
3641 msi-map-mask = <0xff00>;
3643 linux,pci-domain = <0>;
3644 num-lanes = <2>;
3645 bus-range = <0 0xff>;
3648 phy-names = "pciephy";
3650 #address-cells = <3>;
3651 #size-cells = <2>;
3655 dma-coherent;
3659 pcie0_opp_table: opp-table {
3660 compatible = "operating-points-v2";
3663 opp-2500000 {
3664 opp-hz = /bits/ 64 <2500000>;
3665 required-opps = <&rpmhpd_opp_low_svs>;
3666 opp-peak-kBps = <250000 1>;
3670 opp-5000000 {
3671 opp-hz = /bits/ 64 <5000000>;
3672 required-opps = <&rpmhpd_opp_low_svs>;
3673 opp-peak-kBps = <500000 1>;
3677 opp-10000000 {
3678 opp-hz = /bits/ 64 <10000000>;
3679 required-opps = <&rpmhpd_opp_low_svs>;
3680 opp-peak-kBps = <1000000 1>;
3684 opp-8000000 {
3685 opp-hz = /bits/ 64 <8000000>;
3686 required-opps = <&rpmhpd_opp_nom>;
3687 opp-peak-kBps = <984500 1>;
3691 opp-16000000 {
3692 opp-hz = /bits/ 64 <16000000>;
3693 required-opps = <&rpmhpd_opp_nom>;
3694 opp-peak-kBps = <1969000 1>;
3701 bus-range = <0x01 0xff>;
3703 #address-cells = <3>;
3704 #size-cells = <2>;
3710 compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy";
3718 clock-names = "aux",
3724 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
3725 assigned-clock-rates = <100000000>;
3728 reset-names = "phy";
3730 power-domains = <&gcc PCIE_0_PHY_GDSC>;
3732 #clock-cells = <0>;
3733 clock-output-names = "pcie0_pipe_clk";
3735 #phy-cells = <0>;
3742 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550";
3748 reg-names = "parf",
3763 interrupt-names = "msi0",
3781 clock-names = "aux",
3790 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
3791 assigned-clock-rates = <19200000>;
3795 reset-names = "pci",
3802 interconnect-names = "pcie-mem",
3803 "cpu-pcie";
3805 power-domains = <&gcc PCIE_1_GDSC>;
3807 operating-points-v2 = <&pcie1_opp_table>;
3809 iommu-map = <0 &apps_smmu 0x1480 0x1>,
3812 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH 0>,
3816 interrupt-map-mask = <0 0 0 0x7>;
3817 #interrupt-cells = <1>;
3819 msi-map = <0x0 &gic_its 0x1480 0x1>,
3821 msi-map-mask = <0xff00>;
3823 linux,pci-domain = <1>;
3824 num-lanes = <2>;
3825 bus-range = <0 0xff>;
3828 phy-names = "pciephy";
3830 dma-coherent;
3832 #address-cells = <3>;
3833 #size-cells = <2>;
3839 pcie1_opp_table: opp-table {
3840 compatible = "operating-points-v2";
3843 opp-2500000 {
3844 opp-hz = /bits/ 64 <2500000>;
3845 required-opps = <&rpmhpd_opp_low_svs>;
3846 opp-peak-kBps = <250000 1>;
3850 opp-5000000 {
3851 opp-hz = /bits/ 64 <5000000>;
3852 required-opps = <&rpmhpd_opp_low_svs>;
3853 opp-peak-kBps = <500000 1>;
3857 opp-10000000 {
3858 opp-hz = /bits/ 64 <10000000>;
3859 required-opps = <&rpmhpd_opp_low_svs>;
3860 opp-peak-kBps = <1000000 1>;
3864 opp-8000000 {
3865 opp-hz = /bits/ 64 <8000000>;
3866 required-opps = <&rpmhpd_opp_nom>;
3867 opp-peak-kBps = <984500 1>;
3871 opp-16000000 {
3872 opp-hz = /bits/ 64 <16000000>;
3873 required-opps = <&rpmhpd_opp_nom>;
3874 opp-peak-kBps = <1969000 1>;
3878 opp-32000000 {
3879 opp-hz = /bits/ 64 <32000000>;
3880 required-opps = <&rpmhpd_opp_nom>;
3881 opp-peak-kBps = <3938000 1>;
3888 bus-range = <0x01 0xff>;
3890 #address-cells = <3>;
3891 #size-cells = <2>;
3897 compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy";
3905 clock-names = "aux",
3911 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
3912 assigned-clock-rates = <100000000>;
3916 reset-names = "phy",
3919 power-domains = <&gcc PCIE_1_PHY_GDSC>;
3921 #clock-cells = <1>;
3922 clock-output-names = "pcie1_pipe_clk";
3924 #phy-cells = <0>;
3929 cryptobam: dma-controller@1dc4000 {
3930 compatible = "qcom,bam-v1.7.0";
3935 #dma-cells = <1>;
3941 qcom,num-ees = <4>;
3942 num-channels = <20>;
3943 qcom,controlled-remotely;
3947 compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce";
3952 interconnect-names = "memory";
3955 dma-names = "rx", "tx";
3962 compatible = "qcom,sm8650-qmp-ufs-phy";
3968 clock-names = "ref",
3973 reset-names = "ufsphy";
3975 power-domains = <&gcc UFS_MEM_PHY_GDSC>;
3977 #clock-cells = <1>;
3978 #phy-cells = <0>;
3984 compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
3997 clock-names = "core_clk",
4007 reset-names = "rst";
4013 interconnect-names = "ufs-ddr",
4014 "cpu-ufs";
4016 power-domains = <&gcc UFS_PHY_GDSC>;
4017 required-opps = <&rpmhpd_opp_nom>;
4019 operating-points-v2 = <&ufs_opp_table>;
4023 lanes-per-direction = <2>;
4027 phy-names = "ufsphy";
4029 #reset-cells = <1>;
4033 ufs_opp_table: opp-table {
4034 compatible = "operating-points-v2";
4036 opp-100000000 {
4037 opp-hz = /bits/ 64 <100000000>,
4045 required-opps = <&rpmhpd_opp_low_svs>;
4048 opp-201500000 {
4049 opp-hz = /bits/ 64 <201500000>,
4057 required-opps = <&rpmhpd_opp_svs>;
4060 opp-403000000 {
4061 opp-hz = /bits/ 64 <403000000>,
4069 required-opps = <&rpmhpd_opp_nom>;
4075 compatible = "qcom,sm8650-inline-crypto-engine",
4076 "qcom,inline-crypto-engine";
4083 compatible = "qcom,tcsr-mutex";
4086 #hwlock-cells = <1>;
4089 tcsr: clock-controller@1fc0000 {
4090 compatible = "qcom,sm8650-tcsr", "syscon";
4095 #clock-cells = <1>;
4096 #reset-cells = <1>;
4100 compatible = "qcom,adreno-43051401", "qcom,adreno";
4104 reg-names = "kgsl_3d0_reg_memory",
4113 operating-points-v2 = <&gpu_opp_table>;
4116 #cooling-cells = <2>;
4120 interconnect-names = "gfx-mem";
4124 zap-shader {
4125 memory-region = <&gpu_micro_code_mem>;
4129 gpu_opp_table: opp-table {
4130 compatible = "operating-points-v2";
4132 opp-231000000 {
4133 opp-hz = /bits/ 64 <231000000>;
4134 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
4135 opp-peak-kBps = <2136718>;
4138 opp-310000000 {
4139 opp-hz = /bits/ 64 <310000000>;
4140 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
4141 opp-peak-kBps = <2136718>;
4144 opp-366000000 {
4145 opp-hz = /bits/ 64 <366000000>;
4146 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
4147 opp-peak-kBps = <6074218>;
4150 opp-422000000 {
4151 opp-hz = /bits/ 64 <422000000>;
4152 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4153 opp-peak-kBps = <8171875>;
4156 opp-500000000 {
4157 opp-hz = /bits/ 64 <500000000>;
4158 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
4159 opp-peak-kBps = <8171875>;
4162 opp-578000000 {
4163 opp-hz = /bits/ 64 <578000000>;
4164 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4165 opp-peak-kBps = <8171875>;
4168 opp-629000000 {
4169 opp-hz = /bits/ 64 <629000000>;
4170 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
4171 opp-peak-kBps = <10687500>;
4174 opp-680000000 {
4175 opp-hz = /bits/ 64 <680000000>;
4176 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4177 opp-peak-kBps = <12449218>;
4180 opp-720000000 {
4181 opp-hz = /bits/ 64 <720000000>;
4182 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
4183 opp-peak-kBps = <12449218>;
4186 opp-770000000 {
4187 opp-hz = /bits/ 64 <770000000>;
4188 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4189 opp-peak-kBps = <12449218>;
4192 opp-834000000 {
4193 opp-hz = /bits/ 64 <834000000>;
4194 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4195 opp-peak-kBps = <14398437>;
4201 compatible = "qcom,adreno-gmu-750.1", "qcom,adreno-gmu";
4205 reg-names = "gmu", "rscc", "gmu_pdc";
4209 interrupt-names = "hfi", "gmu";
4218 clock-names = "ahb",
4226 power-domains = <&gpucc GPU_CX_GDSC>,
4228 power-domain-names = "cx",
4235 operating-points-v2 = <&gmu_opp_table>;
4237 gmu_opp_table: opp-table {
4238 compatible = "operating-points-v2";
4240 opp-260000000 {
4241 opp-hz = /bits/ 64 <260000000>;
4242 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4245 opp-625000000 {
4246 opp-hz = /bits/ 64 <625000000>;
4247 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4252 gpucc: clock-controller@3d90000 {
4253 compatible = "qcom,sm8650-gpucc";
4260 #clock-cells = <1>;
4261 #reset-cells = <1>;
4262 #power-domain-cells = <1>;
4266 compatible = "qcom,sm8650-smmu-500", "qcom,adreno-smmu",
4267 "qcom,smmu-500", "arm,mmu-500";
4269 #iommu-cells = <2>;
4270 #global-interrupts = <1>;
4301 clock-names = "hlos",
4305 power-domains = <&gpucc GPU_CX_GDSC>;
4306 dma-coherent;
4310 compatible = "qcom,sm8650-ipa", "qcom,sm8550-ipa";
4317 reg-names = "ipa-reg",
4318 "ipa-shared",
4321 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING 0>,
4325 interrupt-names = "ipa",
4327 "ipa-clock-query",
4328 "ipa-setup-ready";
4331 clock-names = "core";
4337 interconnect-names = "memory",
4342 qcom,smem-states = <&ipa_smp2p_out 0>,
4344 qcom,smem-state-names = "ipa-clock-enabled-valid",
4345 "ipa-clock-enabled";
4351 compatible = "qcom,sm8650-mpss-pas";
4354 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING 0>,
4360 interrupt-names = "wdog",
4364 "stop-ack",
4365 "shutdown-ack";
4368 clock-names = "xo";
4373 power-domains = <&rpmhpd RPMHPD_CX>,
4375 power-domain-names = "cx",
4378 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>,
4384 qcom,smem-states = <&smp2p_modem_out 0>;
4385 qcom,smem-state-names = "stop";
4389 glink-edge {
4390 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
4397 qcom,remote-pid = <1>;
4404 compatible = "qcom,sm8650-adsp-pas";
4407 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
4412 interrupt-names = "wdog",
4416 "stop-ack";
4419 clock-names = "xo";
4424 power-domains = <&rpmhpd RPMHPD_LCX>,
4426 power-domain-names = "lcx",
4429 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
4433 qcom,smem-states = <&smp2p_adsp_out 0>;
4434 qcom,smem-state-names = "stop";
4438 remoteproc_adsp_glink: glink-edge {
4439 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
4446 qcom,remote-pid = <2>;
4453 qcom,glink-channels = "fastrpcglink-apps-dsp";
4457 qcom,non-secure-domain;
4459 #address-cells = <1>;
4460 #size-cells = <0>;
4462 compute-cb@3 {
4463 compatible = "qcom,fastrpc-compute-cb";
4468 dma-coherent;
4471 compute-cb@4 {
4472 compatible = "qcom,fastrpc-compute-cb";
4477 dma-coherent;
4480 compute-cb@5 {
4481 compatible = "qcom,fastrpc-compute-cb";
4486 dma-coherent;
4489 compute-cb@6 {
4490 compatible = "qcom,fastrpc-compute-cb";
4495 dma-coherent;
4498 compute-cb@7 {
4499 compatible = "qcom,fastrpc-compute-cb";
4505 dma-coherent;
4511 qcom,glink-channels = "adsp_apps";
4514 #address-cells = <1>;
4515 #size-cells = <0>;
4520 #sound-dai-cells = <0>;
4521 qcom,protection-domain = "avs/audio",
4525 compatible = "qcom,q6apm-lpass-dais";
4526 #sound-dai-cells = <1>;
4530 compatible = "qcom,q6apm-dais";
4539 qcom,protection-domain = "avs/audio",
4542 q6prmcc: clock-controller {
4543 compatible = "qcom,q6prm-lpass-clocks";
4544 #clock-cells = <2>;
4552 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
4558 clock-names = "mclk",
4563 #clock-cells = <0>;
4564 clock-output-names = "wsa2-mclk";
4565 #sound-dai-cells = <1>;
4569 compatible = "qcom,soundwire-v2.0.0";
4573 clock-names = "iface";
4576 pinctrl-0 = <&wsa2_swr_active>;
4577 pinctrl-names = "default";
4579 qcom,din-ports = <4>;
4580 qcom,dout-ports = <9>;
4582 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
4583 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
4584 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4585 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4586 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4587 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
4588 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
4589 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4590 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4592 #address-cells = <2>;
4593 #size-cells = <0>;
4594 #sound-dai-cells = <1>;
4599 compatible = "qcom,sm8650-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro";
4605 clock-names = "mclk",
4610 #clock-cells = <0>;
4611 clock-output-names = "mclk";
4612 #sound-dai-cells = <1>;
4616 compatible = "qcom,soundwire-v2.0.0";
4620 clock-names = "iface";
4623 pinctrl-0 = <&rx_swr_active>;
4624 pinctrl-names = "default";
4626 qcom,din-ports = <0>;
4627 qcom,dout-ports = <11>;
4629 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x03 0xff 0xff 0x31 0xff 0xff 0xff>;
4630 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x09 0x01 0xff 0xff 0x00 0xff 0xff 0xff>;
4631 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>;
4632 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0xff 0xff 0x00 0xff 0xff 0xff>;
4633 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0xff 0xff 0x0f 0xff 0xff 0xff>;
4634 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0x18 0xff 0xff 0xff>;
4635 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff 0xff 0x01 0xff 0xff 0xff>;
4636 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0x01 0x03 0xff 0xff 0x00 0xff 0xff 0xff>;
4637 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0xff 0xff 0xff>;
4639 #address-cells = <2>;
4640 #size-cells = <0>;
4641 #sound-dai-cells = <1>;
4646 compatible = "qcom,sm8650-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro";
4652 clock-names = "mclk",
4657 #clock-cells = <0>;
4658 clock-output-names = "mclk";
4659 #sound-dai-cells = <1>;
4663 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
4669 clock-names = "mclk",
4674 #clock-cells = <0>;
4675 clock-output-names = "mclk";
4676 #sound-dai-cells = <1>;
4680 compatible = "qcom,soundwire-v2.0.0";
4684 clock-names = "iface";
4687 pinctrl-0 = <&wsa_swr_active>;
4688 pinctrl-names = "default";
4690 qcom,din-ports = <4>;
4691 qcom,dout-ports = <9>;
4693 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
4694 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
4695 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4696 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4697 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4698 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
4699 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
4700 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4701 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4703 #address-cells = <2>;
4704 #size-cells = <0>;
4705 #sound-dai-cells = <1>;
4710 compatible = "qcom,soundwire-v2.0.0";
4714 interrupt-names = "core", "wakeup";
4716 clock-names = "iface";
4719 pinctrl-0 = <&tx_swr_active>;
4720 pinctrl-names = "default";
4722 qcom,din-ports = <4>;
4723 qcom,dout-ports = <0>;
4725 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
4726 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
4727 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
4728 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
4729 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
4730 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
4731 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
4732 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
4733 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
4735 #address-cells = <2>;
4736 #size-cells = <0>;
4737 #sound-dai-cells = <1>;
4742 compatible = "qcom,sm8650-lpass-va-macro", "qcom,sm8550-lpass-va-macro";
4747 clock-names = "mclk",
4751 #clock-cells = <0>;
4752 clock-output-names = "fsgen";
4753 #sound-dai-cells = <1>;
4757 compatible = "qcom,sm8650-lpass-lpi-pinctrl";
4762 clock-names = "core", "audio";
4764 gpio-controller;
4765 #gpio-cells = <2>;
4766 gpio-ranges = <&lpass_tlmm 0 0 23>;
4768 tx_swr_active: tx-swr-active-state {
4769 clk-pins {
4772 drive-strength = <2>;
4773 slew-rate = <1>;
4774 bias-disable;
4777 data-pins {
4780 drive-strength = <2>;
4781 slew-rate = <1>;
4782 bias-bus-hold;
4786 rx_swr_active: rx-swr-active-state {
4787 clk-pins {
4790 drive-strength = <2>;
4791 slew-rate = <1>;
4792 bias-disable;
4795 data-pins {
4798 drive-strength = <2>;
4799 slew-rate = <1>;
4800 bias-bus-hold;
4804 dmic01_default: dmic01-default-state {
4805 clk-pins {
4808 drive-strength = <8>;
4809 output-high;
4812 data-pins {
4815 drive-strength = <8>;
4816 input-enable;
4820 dmic23_default: dmic23-default-state {
4821 clk-pins {
4824 drive-strength = <8>;
4825 output-high;
4828 data-pins {
4831 drive-strength = <8>;
4832 input-enable;
4836 wsa_swr_active: wsa-swr-active-state {
4837 clk-pins {
4840 drive-strength = <2>;
4841 slew-rate = <1>;
4842 bias-disable;
4845 data-pins {
4848 drive-strength = <2>;
4849 slew-rate = <1>;
4850 bias-bus-hold;
4854 wsa2_swr_active: wsa2-swr-active-state {
4855 clk-pins {
4858 drive-strength = <2>;
4859 slew-rate = <1>;
4860 bias-disable;
4863 data-pins {
4866 drive-strength = <2>;
4867 slew-rate = <1>;
4868 bias-bus-hold;
4874 compatible = "qcom,sm8650-lpass-lpiaon-noc";
4877 #interconnect-cells = <2>;
4879 qcom,bcm-voters = <&apps_bcm_voter>;
4883 compatible = "qcom,sm8650-lpass-lpicx-noc";
4886 #interconnect-cells = <2>;
4888 qcom,bcm-voters = <&apps_bcm_voter>;
4892 compatible = "qcom,sm8650-lpass-ag-noc";
4895 #interconnect-cells = <2>;
4897 qcom,bcm-voters = <&apps_bcm_voter>;
4901 compatible = "qcom,sm8650-sdhci", "qcom,sdhci-msm-v5";
4906 interrupt-names = "hc_irq",
4912 clock-names = "iface",
4920 interconnect-names = "sdhc-ddr",
4921 "cpu-sdhc";
4923 power-domains = <&rpmhpd RPMHPD_CX>;
4924 operating-points-v2 = <&sdhc2_opp_table>;
4928 bus-width = <4>;
4930 /* Forbid SDR104/SDR50 - broken hw! */
4931 sdhci-caps-mask = <0x3 0>;
4933 qcom,dll-config = <0x0007642c>;
4934 qcom,ddr-config = <0x80040868>;
4936 dma-coherent;
4940 sdhc2_opp_table: opp-table {
4941 compatible = "operating-points-v2";
4943 opp-19200000 {
4944 opp-hz = /bits/ 64 <19200000>;
4945 required-opps = <&rpmhpd_opp_min_svs>;
4948 opp-50000000 {
4949 opp-hz = /bits/ 64 <50000000>;
4950 required-opps = <&rpmhpd_opp_low_svs>;
4953 opp-100000000 {
4954 opp-hz = /bits/ 64 <100000000>;
4955 required-opps = <&rpmhpd_opp_svs>;
4958 opp-202000000 {
4959 opp-hz = /bits/ 64 <202000000>;
4960 required-opps = <&rpmhpd_opp_svs_l1>;
4965 videocc: clock-controller@aaf0000 {
4966 compatible = "qcom,sm8650-videocc";
4970 power-domains = <&rpmhpd RPMHPD_MMCX>;
4971 #clock-cells = <1>;
4972 #reset-cells = <1>;
4973 #power-domain-cells = <1>;
4977 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
4980 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
4984 clock-names = "camnoc_axi",
4987 pinctrl-0 = <&cci0_0_default &cci0_1_default>;
4988 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
4989 pinctrl-names = "default", "sleep";
4991 #address-cells = <1>;
4992 #size-cells = <0>;
4994 cci0_i2c0: i2c-bus@0 {
4996 clock-frequency = <1000000>;
4997 #address-cells = <1>;
4998 #size-cells = <0>;
5001 cci0_i2c1: i2c-bus@1 {
5003 clock-frequency = <1000000>;
5004 #address-cells = <1>;
5005 #size-cells = <0>;
5010 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
5013 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
5017 clock-names = "camnoc_axi",
5020 pinctrl-0 = <&cci1_0_default &cci1_1_default>;
5021 pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>;
5022 pinctrl-names = "default", "sleep";
5024 #address-cells = <1>;
5025 #size-cells = <0>;
5027 cci1_i2c0: i2c-bus@0 {
5029 clock-frequency = <1000000>;
5030 #address-cells = <1>;
5031 #size-cells = <0>;
5034 cci1_i2c1: i2c-bus@1 {
5036 clock-frequency = <1000000>;
5037 #address-cells = <1>;
5038 #size-cells = <0>;
5043 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
5046 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
5050 clock-names = "camnoc_axi",
5053 pinctrl-0 = <&cci2_0_default &cci2_1_default>;
5054 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>;
5055 pinctrl-names = "default", "sleep";
5057 #address-cells = <1>;
5058 #size-cells = <0>;
5060 cci2_i2c0: i2c-bus@0 {
5062 clock-frequency = <1000000>;
5063 #address-cells = <1>;
5064 #size-cells = <0>;
5067 cci2_i2c1: i2c-bus@1 {
5069 clock-frequency = <1000000>;
5070 #address-cells = <1>;
5071 #size-cells = <0>;
5075 camcc: clock-controller@ade0000 {
5076 compatible = "qcom,sm8650-camcc";
5082 power-domains = <&rpmhpd RPMHPD_MMCX>;
5083 #clock-cells = <1>;
5084 #reset-cells = <1>;
5085 #power-domain-cells = <1>;
5088 mdss: display-subsystem@ae00000 {
5089 compatible = "qcom,sm8650-mdss";
5091 reg-names = "mdss";
5105 interconnect-names = "mdp0-mem",
5106 "cpu-cfg";
5108 power-domains = <&dispcc MDSS_GDSC>;
5112 interrupt-controller;
5113 #interrupt-cells = <1>;
5115 #address-cells = <2>;
5116 #size-cells = <2>;
5121 mdss_mdp: display-controller@ae01000 {
5122 compatible = "qcom,sm8650-dpu";
5125 reg-names = "mdp",
5128 interrupts-extended = <&mdss 0>;
5135 clock-names = "nrt_bus",
5141 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
5142 assigned-clock-rates = <19200000>;
5144 operating-points-v2 = <&mdp_opp_table>;
5146 power-domains = <&rpmhpd RPMHPD_MMCX>;
5149 #address-cells = <1>;
5150 #size-cells = <0>;
5156 remote-endpoint = <&mdss_dsi0_in>;
5164 remote-endpoint = <&mdss_dsi1_in>;
5172 remote-endpoint = <&mdss_dp0_in>;
5177 mdp_opp_table: opp-table {
5178 compatible = "operating-points-v2";
5180 opp-200000000 {
5181 opp-hz = /bits/ 64 <200000000>;
5182 required-opps = <&rpmhpd_opp_low_svs>;
5185 opp-325000000 {
5186 opp-hz = /bits/ 64 <325000000>;
5187 required-opps = <&rpmhpd_opp_svs>;
5190 opp-375000000 {
5191 opp-hz = /bits/ 64 <375000000>;
5192 required-opps = <&rpmhpd_opp_svs_l1>;
5195 opp-514000000 {
5196 opp-hz = /bits/ 64 <514000000>;
5197 required-opps = <&rpmhpd_opp_nom>;
5203 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
5205 reg-names = "dsi_ctrl";
5207 interrupts-extended = <&mdss 4>;
5215 clock-names = "byte",
5222 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
5224 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
5227 operating-points-v2 = <&mdss_dsi_opp_table>;
5229 power-domains = <&rpmhpd RPMHPD_MMCX>;
5232 phy-names = "dsi";
5234 #address-cells = <1>;
5235 #size-cells = <0>;
5240 #address-cells = <1>;
5241 #size-cells = <0>;
5247 remote-endpoint = <&dpu_intf1_out>;
5259 mdss_dsi_opp_table: opp-table {
5260 compatible = "operating-points-v2";
5262 opp-187500000 {
5263 opp-hz = /bits/ 64 <187500000>;
5264 required-opps = <&rpmhpd_opp_low_svs>;
5267 opp-300000000 {
5268 opp-hz = /bits/ 64 <300000000>;
5269 required-opps = <&rpmhpd_opp_svs>;
5272 opp-358000000 {
5273 opp-hz = /bits/ 64 <358000000>;
5274 required-opps = <&rpmhpd_opp_svs_l1>;
5280 compatible = "qcom,sm8650-dsi-phy-4nm";
5284 reg-names = "dsi_phy",
5290 clock-names = "iface",
5293 #clock-cells = <1>;
5294 #phy-cells = <0>;
5300 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
5302 reg-names = "dsi_ctrl";
5304 interrupts-extended = <&mdss 5>;
5312 clock-names = "byte",
5319 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
5321 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
5324 operating-points-v2 = <&mdss_dsi_opp_table>;
5326 power-domains = <&rpmhpd RPMHPD_MMCX>;
5329 phy-names = "dsi";
5331 #address-cells = <1>;
5332 #size-cells = <0>;
5337 #address-cells = <1>;
5338 #size-cells = <0>;
5344 remote-endpoint = <&dpu_intf2_out>;
5358 compatible = "qcom,sm8650-dsi-phy-4nm";
5362 reg-names = "dsi_phy",
5368 clock-names = "iface",
5371 #clock-cells = <1>;
5372 #phy-cells = <0>;
5377 mdss_dp0: displayport-controller@af54000 {
5378 compatible = "qcom,sm8650-dp";
5385 interrupts-extended = <&mdss 12>;
5392 clock-names = "core_iface",
5398 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
5400 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
5403 operating-points-v2 = <&dp_opp_table>;
5405 power-domains = <&rpmhpd RPMHPD_MMCX>;
5408 phy-names = "dp";
5410 #sound-dai-cells = <0>;
5414 dp_opp_table: opp-table {
5415 compatible = "operating-points-v2";
5417 opp-162000000 {
5418 opp-hz = /bits/ 64 <162000000>;
5419 required-opps = <&rpmhpd_opp_low_svs_d1>;
5422 opp-270000000 {
5423 opp-hz = /bits/ 64 <270000000>;
5424 required-opps = <&rpmhpd_opp_low_svs>;
5427 opp-540000000 {
5428 opp-hz = /bits/ 64 <540000000>;
5429 required-opps = <&rpmhpd_opp_svs_l1>;
5432 opp-810000000 {
5433 opp-hz = /bits/ 64 <810000000>;
5434 required-opps = <&rpmhpd_opp_nom>;
5439 #address-cells = <1>;
5440 #size-cells = <0>;
5446 remote-endpoint = <&dpu_intf0_out>;
5454 remote-endpoint = <&usb_dp_qmpphy_dp_in>;
5461 dispcc: clock-controller@af00000 {
5462 compatible = "qcom,sm8650-dispcc";
5482 power-domains = <&rpmhpd RPMHPD_MMCX>;
5483 required-opps = <&rpmhpd_opp_low_svs>;
5485 #clock-cells = <1>;
5486 #reset-cells = <1>;
5487 #power-domain-cells = <1>;
5491 compatible = "qcom,sm8650-snps-eusb2-phy",
5492 "qcom,sm8550-snps-eusb2-phy";
5496 clock-names = "ref";
5500 #phy-cells = <0>;
5506 compatible = "qcom,sm8650-qmp-usb3-dp-phy";
5513 clock-names = "aux",
5520 reset-names = "phy",
5523 power-domains = <&gcc USB3_PHY_GDSC>;
5525 #clock-cells = <1>;
5526 #phy-cells = <1>;
5528 orientation-switch;
5533 #address-cells = <1>;
5534 #size-cells = <0>;
5547 remote-endpoint = <&usb_1_dwc3_ss>;
5555 remote-endpoint = <&mdss_dp0_out>;
5562 compatible = "qcom,sm8650-dwc3", "qcom,dwc3";
5565 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>,
5570 interrupt-names = "pwr_event",
5582 clock-names = "cfg_noc",
5589 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
5591 assigned-clock-rates = <19200000>, <200000000>;
5599 interconnect-names = "usb-ddr",
5600 "apps-usb";
5602 power-domains = <&gcc USB30_PRIM_GDSC>;
5603 required-opps = <&rpmhpd_opp_nom>;
5605 #address-cells = <2>;
5606 #size-cells = <2>;
5621 phy-names = "usb2-phy",
5622 "usb3-phy";
5624 snps,hird-threshold = /bits/ 8 <0x0>;
5625 snps,usb2-gadget-lpm-disable;
5628 snps,dis-u1-entry-quirk;
5629 snps,dis-u2-entry-quirk;
5630 snps,is-utmi-l1-suspend;
5632 snps,usb2-lpm-disable;
5633 snps,has-lpm-erratum;
5634 tx-fifo-resize;
5636 dma-coherent;
5639 #address-cells = <1>;
5640 #size-cells = <0>;
5653 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
5660 pdc: interrupt-controller@b220000 {
5661 compatible = "qcom,sm8650-pdc", "qcom,pdc";
5664 interrupt-parent = <&intc>;
5666 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
5670 #interrupt-cells = <2>;
5671 interrupt-controller;
5674 tsens0: thermal-sensor@c228000 {
5675 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2";
5681 interrupt-names = "uplow",
5686 #thermal-sensor-cells = <1>;
5689 tsens1: thermal-sensor@c229000 {
5690 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2";
5696 interrupt-names = "uplow",
5701 #thermal-sensor-cells = <1>;
5704 tsens2: thermal-sensor@c22a000 {
5705 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2";
5711 interrupt-names = "uplow",
5716 #thermal-sensor-cells = <1>;
5719 aoss_qmp: power-management@c300000 {
5720 compatible = "qcom,sm8650-aoss-qmp", "qcom,aoss-qmp";
5723 interrupt-parent = <&ipcc>;
5724 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
5729 #clock-cells = <0>;
5733 compatible = "qcom,rpmh-stats";
5738 compatible = "qcom,spmi-pmic-arb";
5744 reg-names = "core",
5750 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5751 interrupt-names = "periph_irq";
5755 qcom,bus-id = <0>;
5757 interrupt-controller;
5758 #interrupt-cells = <4>;
5760 #address-cells = <2>;
5761 #size-cells = <0>;
5765 compatible = "qcom,sm8650-tlmm";
5770 gpio-controller;
5771 #gpio-cells = <2>;
5773 interrupt-controller;
5774 #interrupt-cells = <2>;
5776 gpio-ranges = <&tlmm 0 0 211>;
5778 wakeup-parent = <&pdc>;
5780 cci0_0_default: cci0-0-default-state {
5781 sda-pins {
5784 drive-strength = <2>;
5785 bias-pull-up = <2200>;
5788 scl-pins {
5791 drive-strength = <2>;
5792 bias-pull-up = <2200>;
5796 cci0_0_sleep: cci0-0-sleep-state {
5797 sda-pins {
5800 drive-strength = <2>;
5801 bias-pull-down;
5804 scl-pins {
5807 drive-strength = <2>;
5808 bias-pull-down;
5812 cci0_1_default: cci0-1-default-state {
5813 sda-pins {
5816 drive-strength = <2>;
5817 bias-pull-up = <2200>;
5820 scl-pins {
5823 drive-strength = <2>;
5824 bias-pull-up = <2200>;
5828 cci0_1_sleep: cci0-1-sleep-state {
5829 sda-pins {
5832 drive-strength = <2>;
5833 bias-pull-down;
5836 scl-pins {
5839 drive-strength = <2>;
5840 bias-pull-down;
5844 cci1_0_default: cci1-0-default-state {
5845 sda-pins {
5848 drive-strength = <2>;
5849 bias-pull-up = <2200>;
5852 scl-pins {
5855 drive-strength = <2>;
5856 bias-pull-up = <2200>;
5860 cci1_0_sleep: cci1-0-sleep-state {
5861 sda-pins {
5864 drive-strength = <2>;
5865 bias-pull-down;
5868 scl-pins {
5871 drive-strength = <2>;
5872 bias-pull-down;
5876 cci1_1_default: cci1-1-default-state {
5877 sda-pins {
5880 drive-strength = <2>;
5881 bias-pull-up = <2200>;
5884 scl-pins {
5887 drive-strength = <2>;
5888 bias-pull-up = <2200>;
5892 cci1_1_sleep: cci1-1-sleep-state {
5893 sda-pins {
5896 drive-strength = <2>;
5897 bias-pull-down;
5900 scl-pins {
5903 drive-strength = <2>;
5904 bias-pull-down;
5908 cci2_0_default: cci2-0-default-state {
5909 sda-pins {
5912 drive-strength = <2>;
5913 bias-pull-up = <2200>;
5916 scl-pins {
5919 drive-strength = <2>;
5920 bias-pull-up = <2200>;
5924 cci2_0_sleep: cci2-0-sleep-state {
5925 sda-pins {
5928 drive-strength = <2>;
5929 bias-pull-down;
5932 scl-pins {
5935 drive-strength = <2>;
5936 bias-pull-down;
5940 cci2_1_default: cci2-1-default-state {
5941 sda-pins {
5944 drive-strength = <2>;
5945 bias-pull-up = <2200>;
5948 scl-pins {
5951 drive-strength = <2>;
5952 bias-pull-up = <2200>;
5956 cci2_1_sleep: cci2-1-sleep-state {
5957 sda-pins {
5960 drive-strength = <2>;
5961 bias-pull-down;
5964 scl-pins {
5967 drive-strength = <2>;
5968 bias-pull-down;
5972 hub_i2c0_data_clk: hub-i2c0-data-clk-state {
5976 drive-strength = <2>;
5977 bias-pull-up;
5980 hub_i2c1_data_clk: hub-i2c1-data-clk-state {
5984 drive-strength = <2>;
5985 bias-pull-up;
5988 hub_i2c2_data_clk: hub-i2c2-data-clk-state {
5992 drive-strength = <2>;
5993 bias-pull-up;
5996 hub_i2c3_data_clk: hub-i2c3-data-clk-state {
6000 drive-strength = <2>;
6001 bias-pull-up;
6004 hub_i2c4_data_clk: hub-i2c4-data-clk-state {
6008 drive-strength = <2>;
6009 bias-pull-up;
6012 hub_i2c5_data_clk: hub-i2c5-data-clk-state {
6016 drive-strength = <2>;
6017 bias-pull-up;
6020 hub_i2c6_data_clk: hub-i2c6-data-clk-state {
6024 drive-strength = <2>;
6025 bias-pull-up;
6028 hub_i2c7_data_clk: hub-i2c7-data-clk-state {
6032 drive-strength = <2>;
6033 bias-pull-up;
6036 hub_i2c8_data_clk: hub-i2c8-data-clk-state {
6040 drive-strength = <2>;
6041 bias-pull-up;
6044 hub_i2c9_data_clk: hub-i2c9-data-clk-state {
6048 drive-strength = <2>;
6049 bias-pull-up;
6052 pcie0_default_state: pcie0-default-state {
6053 perst-pins {
6056 drive-strength = <2>;
6057 bias-pull-down;
6060 clkreq-pins {
6063 drive-strength = <2>;
6064 bias-pull-up;
6067 wake-pins {
6070 drive-strength = <2>;
6071 bias-pull-up;
6075 pcie1_default_state: pcie1-default-state {
6076 perst-pins {
6079 drive-strength = <2>;
6080 bias-pull-down;
6083 clkreq-pins {
6086 drive-strength = <2>;
6087 bias-pull-up;
6090 wake-pins {
6093 drive-strength = <2>;
6094 bias-pull-up;
6098 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
6102 drive-strength = <2>;
6103 bias-pull-up;
6106 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
6110 drive-strength = <2>;
6111 bias-pull-up;
6114 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
6118 drive-strength = <2>;
6119 bias-pull-up;
6122 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
6126 drive-strength = <2>;
6127 bias-pull-up;
6130 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
6134 drive-strength = <2>;
6135 bias-pull-up;
6138 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
6142 drive-strength = <2>;
6143 bias-pull-up;
6146 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
6150 drive-strength = <2>;
6151 bias-pull-up;
6154 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
6158 drive-strength = <2>;
6159 bias-pull-up;
6162 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
6166 drive-strength = <2>;
6167 bias-pull-up;
6170 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
6174 drive-strength = <2>;
6175 bias-pull-up;
6178 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
6182 drive-strength = <2>;
6183 bias-pull-up;
6186 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
6190 drive-strength = <2>;
6191 bias-pull-up;
6194 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
6198 drive-strength = <2>;
6199 bias-pull-up;
6202 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
6206 drive-strength = <2>;
6207 bias-pull-up;
6210 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
6214 drive-strength = <2>;
6215 bias-pull-up;
6218 qup_spi0_cs: qup-spi0-cs-state {
6221 drive-strength = <6>;
6222 bias-disable;
6225 qup_spi0_data_clk: qup-spi0-data-clk-state {
6229 drive-strength = <6>;
6230 bias-disable;
6233 qup_spi1_cs: qup-spi1-cs-state {
6236 drive-strength = <6>;
6237 bias-disable;
6240 qup_spi1_data_clk: qup-spi1-data-clk-state {
6244 drive-strength = <6>;
6245 bias-disable;
6248 qup_spi2_cs: qup-spi2-cs-state {
6251 drive-strength = <6>;
6252 bias-disable;
6255 qup_spi2_data_clk: qup-spi2-data-clk-state {
6259 drive-strength = <6>;
6260 bias-disable;
6263 qup_spi3_cs: qup-spi3-cs-state {
6266 drive-strength = <6>;
6267 bias-disable;
6270 qup_spi3_data_clk: qup-spi3-data-clk-state {
6274 drive-strength = <6>;
6275 bias-disable;
6278 qup_spi4_cs: qup-spi4-cs-state {
6281 drive-strength = <6>;
6282 bias-disable;
6285 qup_spi4_data_clk: qup-spi4-data-clk-state {
6289 drive-strength = <6>;
6290 bias-disable;
6293 qup_spi5_cs: qup-spi5-cs-state {
6296 drive-strength = <6>;
6297 bias-disable;
6300 qup_spi5_data_clk: qup-spi5-data-clk-state {
6304 drive-strength = <6>;
6305 bias-disable;
6308 qup_spi6_cs: qup-spi6-cs-state {
6311 drive-strength = <6>;
6312 bias-disable;
6315 qup_spi6_data_clk: qup-spi6-data-clk-state {
6319 drive-strength = <6>;
6320 bias-disable;
6323 qup_spi7_cs: qup-spi7-cs-state {
6326 drive-strength = <6>;
6327 bias-disable;
6330 qup_spi7_data_clk: qup-spi7-data-clk-state {
6334 drive-strength = <6>;
6335 bias-disable;
6338 qup_spi8_cs: qup-spi8-cs-state {
6341 drive-strength = <6>;
6342 bias-disable;
6345 qup_spi8_data_clk: qup-spi8-data-clk-state {
6349 drive-strength = <6>;
6350 bias-disable;
6353 qup_spi9_cs: qup-spi9-cs-state {
6356 drive-strength = <6>;
6357 bias-disable;
6360 qup_spi9_data_clk: qup-spi9-data-clk-state {
6364 drive-strength = <6>;
6365 bias-disable;
6368 qup_spi10_cs: qup-spi10-cs-state {
6371 drive-strength = <6>;
6372 bias-disable;
6375 qup_spi10_data_clk: qup-spi10-data-clk-state {
6379 drive-strength = <6>;
6380 bias-disable;
6383 qup_spi11_cs: qup-spi11-cs-state {
6386 drive-strength = <6>;
6387 bias-disable;
6390 qup_spi11_data_clk: qup-spi11-data-clk-state {
6394 drive-strength = <6>;
6395 bias-disable;
6398 qup_spi12_cs: qup-spi12-cs-state {
6401 drive-strength = <6>;
6402 bias-disable;
6405 qup_spi12_data_clk: qup-spi12-data-clk-state {
6409 drive-strength = <6>;
6410 bias-disable;
6413 qup_spi13_cs: qup-spi13-cs-state {
6416 drive-strength = <6>;
6417 bias-disable;
6420 qup_spi13_data_clk: qup-spi13-data-clk-state {
6424 drive-strength = <6>;
6425 bias-disable;
6428 qup_spi14_cs: qup-spi14-cs-state {
6431 drive-strength = <6>;
6432 bias-disable;
6435 qup_spi14_data_clk: qup-spi14-data-clk-state {
6439 drive-strength = <6>;
6440 bias-disable;
6443 qup_uart14_default: qup-uart14-default-state {
6447 drive-strength = <2>;
6448 bias-pull-up;
6451 qup_uart14_cts_rts: qup-uart14-cts-rts-state {
6455 drive-strength = <2>;
6456 bias-pull-down;
6459 qup_uart15_default: qup-uart15-default-state {
6463 drive-strength = <2>;
6464 bias-disable;
6467 sdc2_sleep: sdc2-sleep-state {
6468 clk-pins {
6470 drive-strength = <2>;
6471 bias-disable;
6474 cmd-pins {
6476 drive-strength = <2>;
6477 bias-pull-up;
6480 data-pins {
6482 drive-strength = <2>;
6483 bias-pull-up;
6487 sdc2_default: sdc2-default-state {
6488 clk-pins {
6490 drive-strength = <16>;
6491 bias-disable;
6494 cmd-pins {
6496 drive-strength = <10>;
6497 bias-pull-up;
6500 data-pins {
6502 drive-strength = <10>;
6503 bias-pull-up;
6509 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
6514 clock-names = "apb_pclk";
6516 in-ports {
6517 #address-cells = <1>;
6518 #size-cells = <0>;
6524 remote-endpoint = <&funnel_apss_out_funnel_in1>;
6529 out-ports {
6532 remote-endpoint = <&funnel_qdss_in_funnel_in1>;
6539 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
6544 clock-names = "apb_pclk";
6546 in-ports {
6547 #address-cells = <1>;
6548 #size-cells = <0>;
6554 remote-endpoint = <&funnel_in1_out_funnel_qdss>;
6559 out-ports {
6562 remote-endpoint = <&funnel_aoss_in_funnel_qdss>;
6569 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
6574 clock-names = "apb_pclk";
6576 in-ports {
6577 #address-cells = <1>;
6578 #size-cells = <0>;
6584 remote-endpoint = <&funnel_qdss_out_funnel_aoss>;
6589 out-ports {
6592 remote-endpoint = <&tmc_etf_in_funnel_aoss>;
6599 compatible = "arm,coresight-tmc", "arm,primecell";
6604 clock-names = "apb_pclk";
6606 in-ports {
6609 remote-endpoint = <&funnel_aoss_out_tmc_etf>;
6616 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
6621 clock-names = "apb_pclk";
6623 in-ports {
6626 remote-endpoint = <&funnel_ete_out_funnel_apss>;
6631 out-ports {
6634 remote-endpoint = <&funnel_in1_in_funnel_apss>;
6641 compatible = "qcom,sm8650-smmu-500", "qcom,smmu-500", "arm,mmu-500";
6742 #iommu-cells = <2>;
6743 #global-interrupts = <1>;
6745 dma-coherent;
6748 intc: interrupt-controller@17100000 {
6749 compatible = "arm,gic-v3";
6755 #interrupt-cells = <4>;
6756 interrupt-controller;
6758 #redistributor-regions = <1>;
6759 redistributor-stride = <0 0x40000>;
6761 #address-cells = <2>;
6762 #size-cells = <2>;
6765 ppi-partitions {
6766 ppi_cluster0: interrupt-partition-0 {
6770 ppi_cluster1: interrupt-partition-1 {
6774 ppi_cluster2: interrupt-partition-2 {
6779 gic_its: msi-controller@17140000 {
6780 compatible = "arm,gic-v3-its";
6783 msi-controller;
6784 #msi-cells = <1>;
6789 compatible = "arm,armv7-timer-mem";
6793 #address-cells = <1>;
6794 #size-cells = <1>;
6803 frame-number = <0>;
6811 frame-number = <1>;
6821 frame-number = <2>;
6831 frame-number = <3>;
6841 frame-number = <4>;
6851 frame-number = <5>;
6861 frame-number = <6>;
6868 compatible = "qcom,rpmh-rsc";
6873 reg-names = "drv-0",
6874 "drv-1",
6875 "drv-2";
6881 power-domains = <&cluster_pd>;
6883 qcom,tcs-offset = <0xd00>;
6884 qcom,drv-id = <2>;
6885 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
6890 apps_bcm_voter: bcm-voter {
6891 compatible = "qcom,bcm-voter";
6894 rpmhcc: clock-controller {
6895 compatible = "qcom,sm8650-rpmh-clk";
6898 clock-names = "xo";
6900 #clock-cells = <1>;
6903 rpmhpd: power-controller {
6904 compatible = "qcom,sm8650-rpmhpd";
6906 operating-points-v2 = <&rpmhpd_opp_table>;
6908 #power-domain-cells = <1>;
6910 rpmhpd_opp_table: opp-table {
6911 compatible = "operating-points-v2";
6913 rpmhpd_opp_ret: opp-16 {
6914 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
6917 rpmhpd_opp_min_svs: opp-48 {
6918 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
6921 rpmhpd_opp_low_svs_d2: opp-52 {
6922 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
6925 rpmhpd_opp_low_svs_d1: opp-56 {
6926 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
6929 rpmhpd_opp_low_svs_d0: opp-60 {
6930 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
6933 rpmhpd_opp_low_svs: opp-64 {
6934 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
6937 rpmhpd_opp_low_svs_l1: opp-80 {
6938 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
6941 rpmhpd_opp_svs: opp-128 {
6942 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
6945 rpmhpd_opp_svs_l0: opp-144 {
6946 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
6949 rpmhpd_opp_svs_l1: opp-192 {
6950 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
6953 rpmhpd_opp_nom: opp-256 {
6954 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
6957 rpmhpd_opp_nom_l1: opp-320 {
6958 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
6961 rpmhpd_opp_nom_l2: opp-336 {
6962 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
6965 rpmhpd_opp_turbo: opp-384 {
6966 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
6969 rpmhpd_opp_turbo_l1: opp-416 {
6970 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
6977 compatible = "qcom,sm8650-epss-l3", "qcom,epss-l3";
6981 clock-names = "xo", "alternate";
6983 #interconnect-cells = <1>;
6987 compatible = "qcom,sm8650-cpufreq-epss", "qcom,cpufreq-epss";
6992 reg-names = "freq-domain0",
6993 "freq-domain1",
6994 "freq-domain2",
6995 "freq-domain3";
7001 interrupt-names = "dcvsh-irq-0",
7002 "dcvsh-irq-1",
7003 "dcvsh-irq-2",
7004 "dcvsh-irq-3";
7007 clock-names = "xo", "alternate";
7009 #freq-domain-cells = <1>;
7010 #clock-cells = <1>;
7014 compatible = "qcom,sm8650-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
7022 operating-points-v2 = <&llcc_bwmon_opp_table>;
7024 llcc_bwmon_opp_table: opp-table {
7025 compatible = "operating-points-v2";
7027 opp-0 {
7028 opp-peak-kBps = <2086000>;
7031 opp-1 {
7032 opp-peak-kBps = <2929000>;
7035 opp-2 {
7036 opp-peak-kBps = <5931000>;
7039 opp-3 {
7040 opp-peak-kBps = <6515000>;
7043 opp-4 {
7044 opp-peak-kBps = <7980000>;
7047 opp-5 {
7048 opp-peak-kBps = <10437000>;
7051 opp-6 {
7052 opp-peak-kBps = <12157000>;
7055 opp-7 {
7056 opp-peak-kBps = <14060000>;
7059 opp-8 {
7060 opp-peak-kBps = <16113000>;
7066 compatible = "qcom,sm8650-cpu-bwmon", "qcom,sdm845-bwmon";
7074 operating-points-v2 = <&cpu_bwmon_opp_table>;
7076 cpu_bwmon_opp_table: opp-table {
7077 compatible = "operating-points-v2";
7079 opp-0 {
7080 opp-peak-kBps = <4577000>;
7083 opp-1 {
7084 opp-peak-kBps = <7110000>;
7087 opp-2 {
7088 opp-peak-kBps = <9155000>;
7091 opp-3 {
7092 opp-peak-kBps = <12298000>;
7095 opp-4 {
7096 opp-peak-kBps = <14236000>;
7099 opp-5 {
7100 opp-peak-kBps = <16265000>;
7106 compatible = "qcom,sm8650-gem-noc";
7109 qcom,bcm-voters = <&apps_bcm_voter>;
7111 #interconnect-cells = <2>;
7114 system-cache-controller@25000000 {
7115 compatible = "qcom,sm8650-llcc";
7122 reg-names = "llcc0_base",
7133 compatible = "qcom,sm8650-nsp-noc";
7136 qcom,bcm-voters = <&apps_bcm_voter>;
7138 #interconnect-cells = <2>;
7142 compatible = "qcom,sm8650-cdsp-pas";
7145 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>,
7150 interrupt-names = "wdog",
7154 "stop-ack";
7157 clock-names = "xo";
7162 power-domains = <&rpmhpd RPMHPD_CX>,
7165 power-domain-names = "cx",
7169 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>, <&global_sync_mem>;
7173 qcom,smem-states = <&smp2p_cdsp_out 0>;
7174 qcom,smem-state-names = "stop";
7178 glink-edge {
7179 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
7186 qcom,remote-pid = <5>;
7193 qcom,glink-channels = "fastrpcglink-apps-dsp";
7197 qcom,non-secure-domain;
7199 #address-cells = <1>;
7200 #size-cells = <0>;
7202 compute-cb@1 {
7203 compatible = "qcom,fastrpc-compute-cb";
7209 dma-coherent;
7212 compute-cb@2 {
7213 compatible = "qcom,fastrpc-compute-cb";
7219 dma-coherent;
7222 compute-cb@3 {
7223 compatible = "qcom,fastrpc-compute-cb";
7229 dma-coherent;
7232 compute-cb@4 {
7233 compatible = "qcom,fastrpc-compute-cb";
7239 dma-coherent;
7242 compute-cb@5 {
7243 compatible = "qcom,fastrpc-compute-cb";
7249 dma-coherent;
7252 compute-cb@6 {
7253 compatible = "qcom,fastrpc-compute-cb";
7259 dma-coherent;
7262 compute-cb@7 {
7263 compatible = "qcom,fastrpc-compute-cb";
7269 dma-coherent;
7272 compute-cb@8 {
7273 compatible = "qcom,fastrpc-compute-cb";
7279 dma-coherent;
7284 compute-cb@12 {
7285 compatible = "qcom,fastrpc-compute-cb";
7291 dma-coherent;
7294 compute-cb@13 {
7295 compatible = "qcom,fastrpc-compute-cb";
7301 dma-coherent;
7304 compute-cb@14 {
7305 compatible = "qcom,fastrpc-compute-cb";
7311 dma-coherent;
7318 thermal-zones {
7319 aoss0-thermal {
7320 thermal-sensors = <&tsens0 0>;
7323 aoss0-hot {
7329 aoss0-critical {
7337 cpuss0-thermal {
7338 thermal-sensors = <&tsens0 1>;
7341 cpuss0-hot {
7347 cpuss0-critical {
7355 cpuss1-thermal {
7356 thermal-sensors = <&tsens0 2>;
7359 cpuss1-hot {
7365 cpuss1-critical {
7373 cpuss2-thermal {
7374 thermal-sensors = <&tsens0 3>;
7377 cpuss2-hot {
7383 cpuss2-critical {
7391 cpuss3-thermal {
7392 thermal-sensors = <&tsens0 4>;
7395 cpuss3-hot {
7401 cpuss3-critical {
7409 cpu2-top-thermal {
7410 thermal-sensors = <&tsens0 5>;
7413 cpu2-critical {
7421 cpu2-bottom-thermal {
7422 thermal-sensors = <&tsens0 6>;
7425 cpu2-critical {
7433 cpu3-top-thermal {
7434 thermal-sensors = <&tsens0 7>;
7437 cpu3-critical {
7445 cpu3-bottom-thermal {
7446 thermal-sensors = <&tsens0 8>;
7449 cpu3-critical {
7457 cpu4-top-thermal {
7458 thermal-sensors = <&tsens0 9>;
7461 cpu4-critical {
7469 cpu4-bottom-thermal {
7470 thermal-sensors = <&tsens0 10>;
7473 cpu4-critical {
7481 cpu5-top-thermal {
7482 thermal-sensors = <&tsens0 11>;
7485 cpu5-critical {
7493 cpu5-bottom-thermal {
7494 thermal-sensors = <&tsens0 12>;
7497 cpu5-critical {
7505 cpu6-top-thermal {
7506 thermal-sensors = <&tsens0 13>;
7509 cpu6-critical {
7517 cpu6-bottom-thermal {
7518 thermal-sensors = <&tsens0 14>;
7521 cpu6-critical {
7529 aoss1-thermal {
7530 thermal-sensors = <&tsens1 0>;
7533 aoss1-hot {
7539 aoss1-critical {
7547 cpu7-top-thermal {
7548 thermal-sensors = <&tsens1 1>;
7551 cpu7-critical {
7559 cpu7-middle-thermal {
7560 thermal-sensors = <&tsens1 2>;
7563 cpu7-critical {
7571 cpu7-bottom-thermal {
7572 thermal-sensors = <&tsens1 3>;
7575 cpu7-critical {
7583 cpu0-thermal {
7584 thermal-sensors = <&tsens1 4>;
7587 cpu0-critical {
7595 cpu1-thermal {
7596 thermal-sensors = <&tsens1 5>;
7599 cpu1-critical {
7607 nsphvx0-thermal {
7608 thermal-sensors = <&tsens2 6>;
7611 nsphvx0-hot {
7617 nsphvx0-critical {
7625 nsphvx1-thermal {
7626 thermal-sensors = <&tsens2 7>;
7629 nsphvx1-hot {
7635 nsphvx1-critical {
7643 nsphmx0-thermal {
7644 thermal-sensors = <&tsens2 8>;
7647 nsphmx0-hot {
7653 nsphmx0-critical {
7661 nsphmx1-thermal {
7662 thermal-sensors = <&tsens2 9>;
7665 nsphmx1-hot {
7671 nsphmx1-critical {
7679 nsphmx2-thermal {
7680 thermal-sensors = <&tsens2 10>;
7683 nsphmx2-hot {
7689 nsphmx2-critical {
7697 nsphmx3-thermal {
7698 thermal-sensors = <&tsens2 11>;
7701 nsphmx3-hot {
7707 nsphmx3-critical {
7715 video-thermal {
7716 thermal-sensors = <&tsens1 12>;
7719 video-hot {
7725 video-critical {
7733 ddr-thermal {
7734 thermal-sensors = <&tsens1 13>;
7737 ddr-hot {
7743 ddr-critical {
7751 camera0-thermal {
7752 thermal-sensors = <&tsens1 14>;
7755 camera0-hot {
7761 camera0-critical {
7769 camera1-thermal {
7770 thermal-sensors = <&tsens1 15>;
7773 camera1-hot {
7779 camera1-critical {
7787 aoss2-thermal {
7788 thermal-sensors = <&tsens2 0>;
7791 aoss2-hot {
7797 aoss2-critical {
7805 gpuss0-thermal {
7806 polling-delay-passive = <10>;
7808 thermal-sensors = <&tsens2 1>;
7810 cooling-maps {
7813 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
7818 gpu0_alert0: trip-point0 {
7824 trip-point1 {
7830 trip-point2 {
7838 gpuss1-thermal {
7839 polling-delay-passive = <10>;
7841 thermal-sensors = <&tsens2 2>;
7843 cooling-maps {
7846 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
7851 gpu1_alert0: trip-point0 {
7857 trip-point1 {
7863 trip-point2 {
7871 gpuss2-thermal {
7872 polling-delay-passive = <10>;
7874 thermal-sensors = <&tsens2 3>;
7876 cooling-maps {
7879 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
7884 gpu2_alert0: trip-point0 {
7890 trip-point1 {
7896 trip-point2 {
7904 gpuss3-thermal {
7905 polling-delay-passive = <10>;
7907 thermal-sensors = <&tsens2 4>;
7909 cooling-maps {
7912 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
7917 gpu3_alert0: trip-point0 {
7923 trip-point1 {
7929 trip-point2 {
7937 gpuss4-thermal {
7938 polling-delay-passive = <10>;
7940 thermal-sensors = <&tsens2 5>;
7942 cooling-maps {
7945 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
7950 gpu4_alert0: trip-point0 {
7956 trip-point1 {
7962 trip-point2 {
7970 gpuss5-thermal {
7971 polling-delay-passive = <10>;
7973 thermal-sensors = <&tsens2 6>;
7975 cooling-maps {
7978 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
7983 gpu5_alert0: trip-point0 {
7989 trip-point1 {
7995 trip-point2 {
8003 gpuss6-thermal {
8004 polling-delay-passive = <10>;
8006 thermal-sensors = <&tsens2 7>;
8008 cooling-maps {
8011 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
8016 gpu6_alert0: trip-point0 {
8022 trip-point1 {
8028 trip-point2 {
8036 gpuss7-thermal {
8037 polling-delay-passive = <10>;
8039 thermal-sensors = <&tsens2 8>;
8041 cooling-maps {
8044 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
8049 gpu7_alert0: trip-point0 {
8055 trip-point1 {
8061 trip-point2 {
8069 modem0-thermal {
8070 thermal-sensors = <&tsens2 9>;
8073 modem0-hot {
8079 modem0-critical {
8087 modem1-thermal {
8088 thermal-sensors = <&tsens2 10>;
8091 modem1-hot {
8097 modem1-critical {
8105 modem2-thermal {
8106 thermal-sensors = <&tsens2 11>;
8109 modem2-hot {
8115 modem2-critical {
8123 modem3-thermal {
8124 thermal-sensors = <&tsens2 12>;
8127 modem3-hot {
8133 modem3-critical {
8143 compatible = "arm,armv8-timer";