Lines Matching +full:sdm845 +full:- +full:cpu +full:- +full:bwmon
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm8650-camcc.h>
8 #include <dt-bindings/clock/qcom,sm8650-dispcc.h>
9 #include <dt-bindings/clock/qcom,sm8650-gcc.h>
10 #include <dt-bindings/clock/qcom,sm8650-gpucc.h>
11 #include <dt-bindings/clock/qcom,sm8650-tcsr.h>
12 #include <dt-bindings/clock/qcom,sm8650-videocc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/interconnect/qcom,icc.h>
17 #include <dt-bindings/interconnect/qcom,sm8650-rpmh.h>
18 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/mailbox/qcom-ipcc.h>
20 #include <dt-bindings/phy/phy-qcom-qmp.h>
21 #include <dt-bindings/power/qcom,rpmhpd.h>
22 #include <dt-bindings/power/qcom-rpmpd.h>
23 #include <dt-bindings/reset/qcom,sm8650-gpucc.h>
24 #include <dt-bindings/soc/qcom,gpr.h>
25 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
26 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
27 #include <dt-bindings/thermal/thermal.h>
30 interrupt-parent = <&intc>;
32 #address-cells = <2>;
33 #size-cells = <2>;
38 xo_board: xo-board {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
43 sleep_clk: sleep-clk {
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
48 bi_tcxo_div2: bi-tcxo-div2-clk {
49 compatible = "fixed-factor-clock";
50 #clock-cells = <0>;
53 clock-mult = <1>;
54 clock-div = <2>;
57 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
58 compatible = "fixed-factor-clock";
59 #clock-cells = <0>;
62 clock-mult = <1>;
63 clock-div = <2>;
68 #address-cells = <2>;
69 #size-cells = <0>;
71 CPU0: cpu@0 {
72 device_type = "cpu";
73 compatible = "arm,cortex-a520";
78 power-domains = <&CPU_PD0>;
79 power-domain-names = "psci";
81 enable-method = "psci";
82 next-level-cache = <&L2_0>;
83 capacity-dmips-mhz = <1024>;
84 dynamic-power-coefficient = <100>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
88 #cooling-cells = <2>;
90 L2_0: l2-cache {
92 cache-level = <2>;
93 cache-unified;
94 next-level-cache = <&L3_0>;
96 L3_0: l3-cache {
98 cache-level = <3>;
99 cache-unified;
104 CPU1: cpu@100 {
105 device_type = "cpu";
106 compatible = "arm,cortex-a520";
111 power-domains = <&CPU_PD1>;
112 power-domain-names = "psci";
114 enable-method = "psci";
115 next-level-cache = <&L2_0>;
116 capacity-dmips-mhz = <1024>;
117 dynamic-power-coefficient = <100>;
119 qcom,freq-domain = <&cpufreq_hw 0>;
121 #cooling-cells = <2>;
124 CPU2: cpu@200 {
125 device_type = "cpu";
126 compatible = "arm,cortex-a720";
131 power-domains = <&CPU_PD2>;
132 power-domain-names = "psci";
134 enable-method = "psci";
135 next-level-cache = <&L2_200>;
136 capacity-dmips-mhz = <1792>;
137 dynamic-power-coefficient = <238>;
139 qcom,freq-domain = <&cpufreq_hw 3>;
141 #cooling-cells = <2>;
143 L2_200: l2-cache {
145 cache-level = <2>;
146 cache-unified;
147 next-level-cache = <&L3_0>;
151 CPU3: cpu@300 {
152 device_type = "cpu";
153 compatible = "arm,cortex-a720";
158 power-domains = <&CPU_PD3>;
159 power-domain-names = "psci";
161 enable-method = "psci";
162 next-level-cache = <&L2_200>;
163 capacity-dmips-mhz = <1792>;
164 dynamic-power-coefficient = <238>;
166 qcom,freq-domain = <&cpufreq_hw 3>;
168 #cooling-cells = <2>;
171 CPU4: cpu@400 {
172 device_type = "cpu";
173 compatible = "arm,cortex-a720";
178 power-domains = <&CPU_PD4>;
179 power-domain-names = "psci";
181 enable-method = "psci";
182 next-level-cache = <&L2_400>;
183 capacity-dmips-mhz = <1792>;
184 dynamic-power-coefficient = <238>;
186 qcom,freq-domain = <&cpufreq_hw 3>;
188 #cooling-cells = <2>;
190 L2_400: l2-cache {
192 cache-level = <2>;
193 cache-unified;
194 next-level-cache = <&L3_0>;
198 CPU5: cpu@500 {
199 device_type = "cpu";
200 compatible = "arm,cortex-a720";
205 power-domains = <&CPU_PD5>;
206 power-domain-names = "psci";
208 enable-method = "psci";
209 next-level-cache = <&L2_500>;
210 capacity-dmips-mhz = <1792>;
211 dynamic-power-coefficient = <238>;
213 qcom,freq-domain = <&cpufreq_hw 1>;
215 #cooling-cells = <2>;
217 L2_500: l2-cache {
219 cache-level = <2>;
220 cache-unified;
221 next-level-cache = <&L3_0>;
225 CPU6: cpu@600 {
226 device_type = "cpu";
227 compatible = "arm,cortex-a720";
232 power-domains = <&CPU_PD6>;
233 power-domain-names = "psci";
235 enable-method = "psci";
236 next-level-cache = <&L2_600>;
237 capacity-dmips-mhz = <1792>;
238 dynamic-power-coefficient = <238>;
240 qcom,freq-domain = <&cpufreq_hw 1>;
242 #cooling-cells = <2>;
244 L2_600: l2-cache {
246 cache-level = <2>;
247 cache-unified;
248 next-level-cache = <&L3_0>;
252 CPU7: cpu@700 {
253 device_type = "cpu";
254 compatible = "arm,cortex-x4";
259 power-domains = <&CPU_PD7>;
260 power-domain-names = "psci";
262 enable-method = "psci";
263 next-level-cache = <&L2_700>;
264 capacity-dmips-mhz = <1894>;
265 dynamic-power-coefficient = <588>;
267 qcom,freq-domain = <&cpufreq_hw 2>;
269 #cooling-cells = <2>;
271 L2_700: l2-cache {
273 cache-level = <2>;
274 cache-unified;
275 next-level-cache = <&L3_0>;
279 cpu-map {
282 cpu = <&CPU0>;
286 cpu = <&CPU1>;
290 cpu = <&CPU2>;
294 cpu = <&CPU3>;
298 cpu = <&CPU4>;
302 cpu = <&CPU5>;
306 cpu = <&CPU6>;
310 cpu = <&CPU7>;
315 idle-states {
316 entry-method = "psci";
318 SILVER_CPU_SLEEP_0: cpu-sleep-0-0 {
319 compatible = "arm,idle-state";
320 idle-state-name = "silver-rail-power-collapse";
321 arm,psci-suspend-param = <0x40000004>;
322 entry-latency-us = <550>;
323 exit-latency-us = <750>;
324 min-residency-us = <6700>;
325 local-timer-stop;
328 GOLD_CPU_SLEEP_0: cpu-sleep-1-0 {
329 compatible = "arm,idle-state";
330 idle-state-name = "gold-rail-power-collapse";
331 arm,psci-suspend-param = <0x40000004>;
332 entry-latency-us = <600>;
333 exit-latency-us = <1300>;
334 min-residency-us = <8136>;
335 local-timer-stop;
338 GOLD_PLUS_CPU_SLEEP_0: cpu-sleep-2-0 {
339 compatible = "arm,idle-state";
340 idle-state-name = "gold-plus-rail-power-collapse";
341 arm,psci-suspend-param = <0x40000004>;
342 entry-latency-us = <500>;
343 exit-latency-us = <1350>;
344 min-residency-us = <7480>;
345 local-timer-stop;
349 domain-idle-states {
350 CLUSTER_SLEEP_0: cluster-sleep-0 {
351 compatible = "domain-idle-state";
352 arm,psci-suspend-param = <0x41000044>;
353 entry-latency-us = <750>;
354 exit-latency-us = <2350>;
355 min-residency-us = <9144>;
358 CLUSTER_SLEEP_1: cluster-sleep-1 {
359 compatible = "domain-idle-state";
360 arm,psci-suspend-param = <0x4100c344>;
361 entry-latency-us = <2800>;
362 exit-latency-us = <4400>;
363 min-residency-us = <10150>;
370 compatible = "qcom,scm-sm8650", "qcom,scm";
371 qcom,dload-mode = <&tcsr 0x19000>;
377 clk_virt: interconnect-0 {
378 compatible = "qcom,sm8650-clk-virt";
379 #interconnect-cells = <2>;
380 qcom,bcm-voters = <&apps_bcm_voter>;
383 mc_virt: interconnect-1 {
384 compatible = "qcom,sm8650-mc-virt";
385 #interconnect-cells = <2>;
386 qcom,bcm-voters = <&apps_bcm_voter>;
395 pmu-a520 {
396 compatible = "arm,cortex-a520-pmu";
400 pmu-a720 {
401 compatible = "arm,cortex-a720-pmu";
405 pmu-x4 {
406 compatible = "arm,cortex-x4-pmu";
411 compatible = "arm,psci-1.0";
414 CPU_PD0: power-domain-cpu0 {
415 #power-domain-cells = <0>;
416 power-domains = <&CLUSTER_PD>;
417 domain-idle-states = <&SILVER_CPU_SLEEP_0>;
420 CPU_PD1: power-domain-cpu1 {
421 #power-domain-cells = <0>;
422 power-domains = <&CLUSTER_PD>;
423 domain-idle-states = <&SILVER_CPU_SLEEP_0>;
426 CPU_PD2: power-domain-cpu2 {
427 #power-domain-cells = <0>;
428 power-domains = <&CLUSTER_PD>;
429 domain-idle-states = <&SILVER_CPU_SLEEP_0>;
432 CPU_PD3: power-domain-cpu3 {
433 #power-domain-cells = <0>;
434 power-domains = <&CLUSTER_PD>;
435 domain-idle-states = <&GOLD_CPU_SLEEP_0>;
438 CPU_PD4: power-domain-cpu4 {
439 #power-domain-cells = <0>;
440 power-domains = <&CLUSTER_PD>;
441 domain-idle-states = <&GOLD_CPU_SLEEP_0>;
444 CPU_PD5: power-domain-cpu5 {
445 #power-domain-cells = <0>;
446 power-domains = <&CLUSTER_PD>;
447 domain-idle-states = <&GOLD_CPU_SLEEP_0>;
450 CPU_PD6: power-domain-cpu6 {
451 #power-domain-cells = <0>;
452 power-domains = <&CLUSTER_PD>;
453 domain-idle-states = <&GOLD_CPU_SLEEP_0>;
456 CPU_PD7: power-domain-cpu7 {
457 #power-domain-cells = <0>;
458 power-domains = <&CLUSTER_PD>;
459 domain-idle-states = <&GOLD_PLUS_CPU_SLEEP_0>;
462 CLUSTER_PD: power-domain-cluster {
463 #power-domain-cells = <0>;
464 domain-idle-states = <&CLUSTER_SLEEP_0>,
469 reserved_memory: reserved-memory {
470 #address-cells = <2>;
471 #size-cells = <2>;
476 no-map;
479 cpusys_vm_mem: cpusys-vm@80e00000 {
481 no-map;
485 xbl_dt_log_merged_mem: xbl-dt-log-merged@81a00000 {
487 no-map;
490 aop_cmd_db_mem: aop-cmd-db@81c60000 {
491 compatible = "qcom,cmd-db";
493 no-map;
497 aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 {
499 no-map;
508 no-map;
511 adsp_mhi_mem: adsp-mhi@81f00000 {
513 no-map;
518 no-map;
521 global_sync_mem: global-sync@82600000 {
523 no-map;
526 tz_stat_mem: tz-stat@82700000 {
528 no-map;
533 no-map;
536 qlink_logging_mem: qlink-logging@84800000 {
538 no-map;
541 mpss_dsm_mem: mpss-dsm@86b00000 {
543 no-map;
546 mpss_dsm_mem_2: mpss-dsm-2@8b400000 {
548 no-map;
553 no-map;
556 q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 {
558 no-map;
561 ipa_fw_mem: ipa-fw@9b080000 {
563 no-map;
566 ipa_gsi_mem: ipa-gsi@9b090000 {
568 no-map;
571 gpu_micro_code_mem: gpu-micro-code@9b09a000 {
573 no-map;
578 no-map;
582 spu_tz_shared_mem: spu-tz-shared@9b280000 {
584 no-map;
588 spu_modem_shared_mem: spu-modem-shared@9b2e0000 {
590 no-map;
595 no-map;
600 no-map;
605 no-map;
610 no-map;
613 q6_cdsp_dtb_mem: q6-cdsp-dtb@9de00000 {
615 no-map;
618 q6_adsp_dtb_mem: q6-adsp-dtb@9de80000 {
620 no-map;
625 no-map;
629 compatible = "qcom,rmtfs-mem";
631 no-map;
633 qcom,client-id = <1>;
638 tz_merged_mem: tz-merged@d8000000 {
640 no-map;
643 hwfence_shbuf: hwfence-shbuf@e6440000 {
645 no-map;
648 trust_ui_vm_mem: trust-ui-vm@f3800000 {
650 no-map;
653 oem_vm_mem: oem-vm@f7c00000 {
655 no-map;
658 llcc_lpi_mem: llcc-lpi@ff800000 {
660 no-map;
664 smp2p-adsp {
667 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
675 qcom,local-pid = <0>;
676 qcom,remote-pid = <2>;
678 smp2p_adsp_out: master-kernel {
679 qcom,entry-name = "master-kernel";
680 #qcom,smem-state-cells = <1>;
683 smp2p_adsp_in: slave-kernel {
684 qcom,entry-name = "slave-kernel";
685 interrupt-controller;
686 #interrupt-cells = <2>;
690 smp2p-cdsp {
693 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
701 qcom,local-pid = <0>;
702 qcom,remote-pid = <5>;
704 smp2p_cdsp_out: master-kernel {
705 qcom,entry-name = "master-kernel";
706 #qcom,smem-state-cells = <1>;
709 smp2p_cdsp_in: slave-kernel {
710 qcom,entry-name = "slave-kernel";
711 interrupt-controller;
712 #interrupt-cells = <2>;
716 smp2p-modem {
719 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
727 qcom,local-pid = <0>;
728 qcom,remote-pid = <1>;
730 smp2p_modem_out: master-kernel {
731 qcom,entry-name = "master-kernel";
732 #qcom,smem-state-cells = <1>;
735 smp2p_modem_in: slave-kernel {
736 qcom,entry-name = "slave-kernel";
737 interrupt-controller;
738 #interrupt-cells = <2>;
741 ipa_smp2p_out: ipa-ap-to-modem {
742 qcom,entry-name = "ipa";
743 #qcom,smem-state-cells = <1>;
746 ipa_smp2p_in: ipa-modem-to-ap {
747 qcom,entry-name = "ipa";
748 interrupt-controller;
749 #interrupt-cells = <2>;
754 compatible = "simple-bus";
756 #address-cells = <2>;
757 #size-cells = <2>;
758 dma-ranges = <0 0 0 0 0x10 0>;
761 gcc: clock-controller@100000 {
762 compatible = "qcom,sm8650-gcc";
776 #clock-cells = <1>;
777 #reset-cells = <1>;
778 #power-domain-cells = <1>;
782 compatible = "qcom,sm8650-ipcc", "qcom,ipcc";
786 interrupt-controller;
787 #interrupt-cells = <3>;
789 #mbox-cells = <2>;
792 gpi_dma2: dma-controller@800000 {
793 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma";
809 dma-channels = <12>;
810 dma-channel-mask = <0x3f>;
811 #dma-cells = <3>;
815 dma-coherent;
821 compatible = "qcom,geni-se-qup";
826 clock-names = "m-ahb",
827 "s-ahb";
831 dma-coherent;
833 #address-cells = <2>;
834 #size-cells = <2>;
840 compatible = "qcom,geni-i2c";
846 clock-names = "se";
854 interconnect-names = "qup-core",
855 "qup-config",
856 "qup-memory";
860 dma-names = "tx",
863 pinctrl-0 = <&qup_i2c8_data_clk>;
864 pinctrl-names = "default";
866 #address-cells = <1>;
867 #size-cells = <0>;
873 compatible = "qcom,geni-spi";
879 clock-names = "se";
887 interconnect-names = "qup-core",
888 "qup-config",
889 "qup-memory";
893 dma-names = "tx",
896 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
897 pinctrl-names = "default";
899 #address-cells = <1>;
900 #size-cells = <0>;
906 compatible = "qcom,geni-i2c";
912 clock-names = "se";
920 interconnect-names = "qup-core",
921 "qup-config",
922 "qup-memory";
926 dma-names = "tx",
929 pinctrl-0 = <&qup_i2c9_data_clk>;
930 pinctrl-names = "default";
932 #address-cells = <1>;
933 #size-cells = <0>;
939 compatible = "qcom,geni-spi";
945 clock-names = "se";
953 interconnect-names = "qup-core",
954 "qup-config",
955 "qup-memory";
959 dma-names = "tx",
962 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
963 pinctrl-names = "default";
965 #address-cells = <1>;
966 #size-cells = <0>;
972 compatible = "qcom,geni-i2c";
978 clock-names = "se";
986 interconnect-names = "qup-core",
987 "qup-config",
988 "qup-memory";
992 dma-names = "tx",
995 pinctrl-0 = <&qup_i2c10_data_clk>;
996 pinctrl-names = "default";
998 #address-cells = <1>;
999 #size-cells = <0>;
1005 compatible = "qcom,geni-spi";
1011 clock-names = "se";
1019 interconnect-names = "qup-core",
1020 "qup-config",
1021 "qup-memory";
1025 dma-names = "tx",
1028 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1029 pinctrl-names = "default";
1031 #address-cells = <1>;
1032 #size-cells = <0>;
1038 compatible = "qcom,geni-i2c";
1044 clock-names = "se";
1052 interconnect-names = "qup-core",
1053 "qup-config",
1054 "qup-memory";
1058 dma-names = "tx",
1061 pinctrl-0 = <&qup_i2c11_data_clk>;
1062 pinctrl-names = "default";
1064 #address-cells = <1>;
1065 #size-cells = <0>;
1071 compatible = "qcom,geni-spi";
1077 clock-names = "se";
1085 interconnect-names = "qup-core",
1086 "qup-config",
1087 "qup-memory";
1091 dma-names = "tx",
1094 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1095 pinctrl-names = "default";
1097 #address-cells = <1>;
1098 #size-cells = <0>;
1104 compatible = "qcom,geni-i2c";
1110 clock-names = "se";
1118 interconnect-names = "qup-core",
1119 "qup-config",
1120 "qup-memory";
1124 dma-names = "tx",
1127 pinctrl-0 = <&qup_i2c12_data_clk>;
1128 pinctrl-names = "default";
1130 #address-cells = <1>;
1131 #size-cells = <0>;
1137 compatible = "qcom,geni-spi";
1143 clock-names = "se";
1151 interconnect-names = "qup-core",
1152 "qup-config",
1153 "qup-memory";
1157 dma-names = "tx",
1160 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1161 pinctrl-names = "default";
1163 #address-cells = <1>;
1164 #size-cells = <0>;
1170 compatible = "qcom,geni-i2c";
1176 clock-names = "se";
1184 interconnect-names = "qup-core",
1185 "qup-config",
1186 "qup-memory";
1190 dma-names = "tx",
1193 pinctrl-0 = <&qup_i2c13_data_clk>;
1194 pinctrl-names = "default";
1196 #address-cells = <1>;
1197 #size-cells = <0>;
1203 compatible = "qcom,geni-spi";
1209 clock-names = "se";
1217 interconnect-names = "qup-core",
1218 "qup-config",
1219 "qup-memory";
1223 dma-names = "tx",
1226 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1227 pinctrl-names = "default";
1229 #address-cells = <1>;
1230 #size-cells = <0>;
1236 compatible = "qcom,geni-uart";
1242 clock-names = "se";
1248 interconnect-names = "qup-core",
1249 "qup-config";
1251 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
1252 pinctrl-names = "default";
1258 compatible = "qcom,geni-debug-uart";
1264 clock-names = "se";
1270 interconnect-names = "qup-core",
1271 "qup-config";
1273 pinctrl-0 = <&qup_uart15_default>;
1274 pinctrl-names = "default";
1281 compatible = "qcom,geni-se-i2c-master-hub";
1285 clock-names = "s-ahb";
1287 #address-cells = <2>;
1288 #size-cells = <2>;
1294 compatible = "qcom,geni-i2c-master-hub";
1301 clock-names = "se",
1308 interconnect-names = "qup-core",
1309 "qup-config";
1311 pinctrl-0 = <&hub_i2c0_data_clk>;
1312 pinctrl-names = "default";
1314 #address-cells = <1>;
1315 #size-cells = <0>;
1321 compatible = "qcom,geni-i2c-master-hub";
1328 clock-names = "se",
1335 interconnect-names = "qup-core",
1336 "qup-config";
1338 pinctrl-0 = <&hub_i2c1_data_clk>;
1339 pinctrl-names = "default";
1341 #address-cells = <1>;
1342 #size-cells = <0>;
1348 compatible = "qcom,geni-i2c-master-hub";
1355 clock-names = "se",
1362 interconnect-names = "qup-core",
1363 "qup-config";
1365 pinctrl-0 = <&hub_i2c2_data_clk>;
1366 pinctrl-names = "default";
1368 #address-cells = <1>;
1369 #size-cells = <0>;
1375 compatible = "qcom,geni-i2c-master-hub";
1382 clock-names = "se",
1389 interconnect-names = "qup-core",
1390 "qup-config";
1392 pinctrl-0 = <&hub_i2c3_data_clk>;
1393 pinctrl-names = "default";
1395 #address-cells = <1>;
1396 #size-cells = <0>;
1402 compatible = "qcom,geni-i2c-master-hub";
1409 clock-names = "se",
1416 interconnect-names = "qup-core",
1417 "qup-config";
1419 pinctrl-0 = <&hub_i2c4_data_clk>;
1420 pinctrl-names = "default";
1422 #address-cells = <1>;
1423 #size-cells = <0>;
1429 compatible = "qcom,geni-i2c-master-hub";
1436 clock-names = "se",
1443 interconnect-names = "qup-core",
1444 "qup-config";
1446 pinctrl-0 = <&hub_i2c5_data_clk>;
1447 pinctrl-names = "default";
1449 #address-cells = <1>;
1450 #size-cells = <0>;
1456 compatible = "qcom,geni-i2c-master-hub";
1463 clock-names = "se",
1470 interconnect-names = "qup-core",
1471 "qup-config";
1473 pinctrl-0 = <&hub_i2c6_data_clk>;
1474 pinctrl-names = "default";
1476 #address-cells = <1>;
1477 #size-cells = <0>;
1483 compatible = "qcom,geni-i2c-master-hub";
1490 clock-names = "se",
1497 interconnect-names = "qup-core",
1498 "qup-config";
1500 pinctrl-0 = <&hub_i2c7_data_clk>;
1501 pinctrl-names = "default";
1503 #address-cells = <1>;
1504 #size-cells = <0>;
1510 compatible = "qcom,geni-i2c-master-hub";
1517 clock-names = "se",
1524 interconnect-names = "qup-core",
1525 "qup-config";
1527 pinctrl-0 = <&hub_i2c8_data_clk>;
1528 pinctrl-names = "default";
1530 #address-cells = <1>;
1531 #size-cells = <0>;
1537 compatible = "qcom,geni-i2c-master-hub";
1544 clock-names = "se",
1551 interconnect-names = "qup-core",
1552 "qup-config";
1554 pinctrl-0 = <&hub_i2c9_data_clk>;
1555 pinctrl-names = "default";
1557 #address-cells = <1>;
1558 #size-cells = <0>;
1564 gpi_dma1: dma-controller@a00000 {
1565 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma";
1581 dma-channels = <12>;
1582 dma-channel-mask = <0xc>;
1583 #dma-cells = <3>;
1586 dma-coherent;
1592 compatible = "qcom,geni-se-qup";
1597 clock-names = "m-ahb",
1598 "s-ahb";
1602 interconnect-names = "qup-core";
1606 dma-coherent;
1608 #address-cells = <2>;
1609 #size-cells = <2>;
1615 compatible = "qcom,geni-i2c";
1621 clock-names = "se";
1629 interconnect-names = "qup-core",
1630 "qup-config",
1631 "qup-memory";
1635 dma-names = "tx",
1638 pinctrl-0 = <&qup_i2c0_data_clk>;
1639 pinctrl-names = "default";
1641 #address-cells = <1>;
1642 #size-cells = <0>;
1648 compatible = "qcom,geni-spi";
1654 clock-names = "se";
1662 interconnect-names = "qup-core",
1663 "qup-config",
1664 "qup-memory";
1668 dma-names = "tx",
1671 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1672 pinctrl-names = "default";
1674 #address-cells = <1>;
1675 #size-cells = <0>;
1681 compatible = "qcom,geni-i2c";
1687 clock-names = "se";
1695 interconnect-names = "qup-core",
1696 "qup-config",
1697 "qup-memory";
1701 dma-names = "tx",
1704 pinctrl-0 = <&qup_i2c1_data_clk>;
1705 pinctrl-names = "default";
1707 #address-cells = <1>;
1708 #size-cells = <0>;
1714 compatible = "qcom,geni-spi";
1720 clock-names = "se";
1728 interconnect-names = "qup-core",
1729 "qup-config",
1730 "qup-memory";
1734 dma-names = "tx",
1737 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1738 pinctrl-names = "default";
1740 #address-cells = <1>;
1741 #size-cells = <0>;
1747 compatible = "qcom,geni-i2c";
1753 clock-names = "se";
1761 interconnect-names = "qup-core",
1762 "qup-config",
1763 "qup-memory";
1767 dma-names = "tx",
1770 pinctrl-0 = <&qup_i2c2_data_clk>;
1771 pinctrl-names = "default";
1773 #address-cells = <1>;
1774 #size-cells = <0>;
1780 compatible = "qcom,geni-spi";
1786 clock-names = "se";
1794 interconnect-names = "qup-core",
1795 "qup-config",
1796 "qup-memory";
1800 dma-names = "tx",
1803 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1804 pinctrl-names = "default";
1806 #address-cells = <1>;
1807 #size-cells = <0>;
1813 compatible = "qcom,geni-i2c";
1819 clock-names = "se";
1827 interconnect-names = "qup-core",
1828 "qup-config",
1829 "qup-memory";
1833 dma-names = "tx",
1836 pinctrl-0 = <&qup_i2c3_data_clk>;
1837 pinctrl-names = "default";
1839 #address-cells = <1>;
1840 #size-cells = <0>;
1846 compatible = "qcom,geni-spi";
1852 clock-names = "se";
1860 interconnect-names = "qup-core",
1861 "qup-config",
1862 "qup-memory";
1866 dma-names = "tx",
1869 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1870 pinctrl-names = "default";
1872 #address-cells = <1>;
1873 #size-cells = <0>;
1879 compatible = "qcom,geni-i2c";
1885 clock-names = "se";
1893 interconnect-names = "qup-core",
1894 "qup-config",
1895 "qup-memory";
1899 dma-names = "tx",
1902 pinctrl-0 = <&qup_i2c4_data_clk>;
1903 pinctrl-names = "default";
1905 #address-cells = <1>;
1906 #size-cells = <0>;
1912 compatible = "qcom,geni-spi";
1918 clock-names = "se";
1926 interconnect-names = "qup-core",
1927 "qup-config",
1928 "qup-memory";
1932 dma-names = "tx",
1935 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1936 pinctrl-names = "default";
1938 #address-cells = <1>;
1939 #size-cells = <0>;
1945 compatible = "qcom,geni-i2c";
1951 clock-names = "se";
1959 interconnect-names = "qup-core",
1960 "qup-config",
1961 "qup-memory";
1965 dma-names = "tx",
1968 pinctrl-0 = <&qup_i2c5_data_clk>;
1969 pinctrl-names = "default";
1971 #address-cells = <1>;
1972 #size-cells = <0>;
1978 compatible = "qcom,geni-spi";
1984 clock-names = "se";
1992 interconnect-names = "qup-core",
1993 "qup-config",
1994 "qup-memory";
1998 dma-names = "tx",
2001 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
2002 pinctrl-names = "default";
2004 #address-cells = <1>;
2005 #size-cells = <0>;
2011 compatible = "qcom,geni-i2c";
2017 clock-names = "se";
2025 interconnect-names = "qup-core",
2026 "qup-config",
2027 "qup-memory";
2031 dma-names = "tx",
2034 pinctrl-0 = <&qup_i2c6_data_clk>;
2035 pinctrl-names = "default";
2037 #address-cells = <1>;
2038 #size-cells = <0>;
2044 compatible = "qcom,geni-spi";
2050 clock-names = "se";
2058 interconnect-names = "qup-core",
2059 "qup-config",
2060 "qup-memory";
2064 dma-names = "tx",
2067 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
2068 pinctrl-names = "default";
2070 #address-cells = <1>;
2071 #size-cells = <0>;
2077 compatible = "qcom,geni-i2c";
2083 clock-names = "se";
2091 interconnect-names = "qup-core",
2092 "qup-config",
2093 "qup-memory";
2097 dma-names = "tx",
2100 pinctrl-0 = <&qup_i2c7_data_clk>;
2101 pinctrl-names = "default";
2103 #address-cells = <1>;
2104 #size-cells = <0>;
2110 compatible = "qcom,geni-spi";
2116 clock-names = "se";
2124 interconnect-names = "qup-core",
2125 "qup-config",
2126 "qup-memory";
2130 dma-names = "tx",
2133 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
2134 pinctrl-names = "default";
2136 #address-cells = <1>;
2137 #size-cells = <0>;
2144 compatible = "qcom,sm8650-cnoc-main";
2147 qcom,bcm-voters = <&apps_bcm_voter>;
2149 #interconnect-cells = <2>;
2153 compatible = "qcom,sm8650-config-noc";
2156 qcom,bcm-voters = <&apps_bcm_voter>;
2158 #interconnect-cells = <2>;
2162 compatible = "qcom,sm8650-system-noc";
2165 qcom,bcm-voters = <&apps_bcm_voter>;
2167 #interconnect-cells = <2>;
2171 compatible = "qcom,sm8650-pcie-anoc";
2177 qcom,bcm-voters = <&apps_bcm_voter>;
2179 #interconnect-cells = <2>;
2183 compatible = "qcom,sm8650-aggre1-noc";
2189 qcom,bcm-voters = <&apps_bcm_voter>;
2191 #interconnect-cells = <2>;
2195 compatible = "qcom,sm8650-aggre2-noc";
2200 qcom,bcm-voters = <&apps_bcm_voter>;
2202 #interconnect-cells = <2>;
2206 compatible = "qcom,sm8650-mmss-noc";
2209 qcom,bcm-voters = <&apps_bcm_voter>;
2211 #interconnect-cells = <2>;
2215 compatible = "qcom,sm8650-trng", "qcom,trng";
2221 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550";
2227 reg-names = "parf", "dbi", "elbi", "atu", "config";
2237 interrupt-names = "msi0",
2254 clock-names = "aux",
2264 reset-names = "pci";
2270 interconnect-names = "pcie-mem",
2271 "cpu-pcie";
2273 power-domains = <&gcc PCIE_0_GDSC>;
2275 iommu-map = <0 &apps_smmu 0x1400 0x1>,
2278 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
2282 interrupt-map-mask = <0 0 0 0x7>;
2283 #interrupt-cells = <1>;
2285 msi-map = <0x0 &gic_its 0x1400 0x1>,
2287 msi-map-mask = <0xff00>;
2289 linux,pci-domain = <0>;
2290 num-lanes = <2>;
2291 bus-range = <0 0xff>;
2294 phy-names = "pciephy";
2296 #address-cells = <3>;
2297 #size-cells = <2>;
2301 dma-coherent;
2308 bus-range = <0x01 0xff>;
2310 #address-cells = <3>;
2311 #size-cells = <2>;
2317 compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy";
2325 clock-names = "aux",
2331 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
2332 assigned-clock-rates = <100000000>;
2335 reset-names = "phy";
2337 power-domains = <&gcc PCIE_0_PHY_GDSC>;
2339 #clock-cells = <0>;
2340 clock-output-names = "pcie0_pipe_clk";
2342 #phy-cells = <0>;
2349 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550";
2355 reg-names = "parf",
2369 interrupt-names = "msi0",
2386 clock-names = "aux",
2395 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2396 assigned-clock-rates = <19200000>;
2400 reset-names = "pci",
2407 interconnect-names = "pcie-mem",
2408 "cpu-pcie";
2410 power-domains = <&gcc PCIE_1_GDSC>;
2412 iommu-map = <0 &apps_smmu 0x1480 0x1>,
2415 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2419 interrupt-map-mask = <0 0 0 0x7>;
2420 #interrupt-cells = <1>;
2422 msi-map = <0x0 &gic_its 0x1480 0x1>,
2424 msi-map-mask = <0xff00>;
2426 linux,pci-domain = <1>;
2427 num-lanes = <2>;
2428 bus-range = <0 0xff>;
2431 phy-names = "pciephy";
2433 dma-coherent;
2435 #address-cells = <3>;
2436 #size-cells = <2>;
2445 bus-range = <0x01 0xff>;
2447 #address-cells = <3>;
2448 #size-cells = <2>;
2454 compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy";
2462 clock-names = "aux",
2468 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2469 assigned-clock-rates = <100000000>;
2473 reset-names = "phy",
2476 power-domains = <&gcc PCIE_1_PHY_GDSC>;
2478 #clock-cells = <1>;
2479 clock-output-names = "pcie1_pipe_clk";
2481 #phy-cells = <0>;
2486 cryptobam: dma-controller@1dc4000 {
2487 compatible = "qcom,bam-v1.7.0";
2492 #dma-cells = <1>;
2498 qcom,controlled-remotely;
2502 compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce";
2507 interconnect-names = "memory";
2510 dma-names = "rx", "tx";
2517 compatible = "qcom,sm8650-qmp-ufs-phy";
2523 clock-names = "ref",
2528 reset-names = "ufsphy";
2530 power-domains = <&gcc UFS_MEM_PHY_GDSC>;
2532 #clock-cells = <1>;
2533 #phy-cells = <0>;
2539 compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
2552 clock-names = "core_clk",
2560 freq-table-hz = <100000000 403000000>,
2570 reset-names = "rst";
2576 interconnect-names = "ufs-ddr",
2577 "cpu-ufs";
2579 power-domains = <&gcc UFS_PHY_GDSC>;
2580 required-opps = <&rpmhpd_opp_nom>;
2584 lanes-per-direction = <2>;
2588 phy-names = "ufsphy";
2590 #reset-cells = <1>;
2596 compatible = "qcom,sm8650-inline-crypto-engine",
2597 "qcom,inline-crypto-engine";
2604 compatible = "qcom,tcsr-mutex";
2607 #hwlock-cells = <1>;
2610 tcsr: clock-controller@1fc0000 {
2611 compatible = "qcom,sm8650-tcsr", "syscon";
2616 #clock-cells = <1>;
2617 #reset-cells = <1>;
2621 compatible = "qcom,adreno-43051401", "qcom,adreno";
2625 reg-names = "kgsl_3d0_reg_memory",
2634 operating-points-v2 = <&gpu_opp_table>;
2637 #cooling-cells = <2>;
2641 zap-shader {
2642 memory-region = <&gpu_micro_code_mem>;
2646 gpu_opp_table: opp-table {
2647 compatible = "operating-points-v2";
2649 opp-231000000 {
2650 opp-hz = /bits/ 64 <231000000>;
2651 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
2654 opp-310000000 {
2655 opp-hz = /bits/ 64 <310000000>;
2656 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2659 opp-366000000 {
2660 opp-hz = /bits/ 64 <366000000>;
2661 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
2664 opp-422000000 {
2665 opp-hz = /bits/ 64 <422000000>;
2666 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2669 opp-500000000 {
2670 opp-hz = /bits/ 64 <500000000>;
2671 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
2674 opp-578000000 {
2675 opp-hz = /bits/ 64 <578000000>;
2676 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2679 opp-629000000 {
2680 opp-hz = /bits/ 64 <629000000>;
2681 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2684 opp-680000000 {
2685 opp-hz = /bits/ 64 <680000000>;
2686 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2689 opp-720000000 {
2690 opp-hz = /bits/ 64 <720000000>;
2691 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2694 opp-770000000 {
2695 opp-hz = /bits/ 64 <770000000>;
2696 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2699 opp-834000000 {
2700 opp-hz = /bits/ 64 <834000000>;
2701 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2707 compatible = "qcom,adreno-gmu-750.1", "qcom,adreno-gmu";
2711 reg-names = "gmu", "rscc", "gmu_pdc";
2715 interrupt-names = "hfi", "gmu";
2724 clock-names = "ahb",
2732 power-domains = <&gpucc GPU_CX_GDSC>,
2734 power-domain-names = "cx",
2741 operating-points-v2 = <&gmu_opp_table>;
2743 gmu_opp_table: opp-table {
2744 compatible = "operating-points-v2";
2746 opp-260000000 {
2747 opp-hz = /bits/ 64 <260000000>;
2748 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2751 opp-625000000 {
2752 opp-hz = /bits/ 64 <625000000>;
2753 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2758 gpucc: clock-controller@3d90000 {
2759 compatible = "qcom,sm8650-gpucc";
2766 #clock-cells = <1>;
2767 #reset-cells = <1>;
2768 #power-domain-cells = <1>;
2772 compatible = "qcom,sm8650-smmu-500", "qcom,adreno-smmu",
2773 "qcom,smmu-500", "arm,mmu-500";
2775 #iommu-cells = <2>;
2776 #global-interrupts = <1>;
2807 clock-names = "hlos",
2811 power-domains = <&gpucc GPU_CX_GDSC>;
2812 dma-coherent;
2816 compatible = "qcom,sm8650-ipa", "qcom,sm8550-ipa";
2823 reg-names = "ipa-reg",
2824 "ipa-shared",
2827 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
2831 interrupt-names = "ipa",
2833 "ipa-clock-query",
2834 "ipa-setup-ready";
2837 clock-names = "core";
2841 interconnect-names = "memory",
2846 qcom,smem-states = <&ipa_smp2p_out 0>,
2848 qcom,smem-state-names = "ipa-clock-enabled-valid",
2849 "ipa-clock-enabled";
2855 compatible = "qcom,sm8650-mpss-pas";
2858 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2864 interrupt-names = "wdog",
2868 "stop-ack",
2869 "shutdown-ack";
2872 clock-names = "xo";
2877 power-domains = <&rpmhpd RPMHPD_CX>,
2879 power-domain-names = "cx",
2882 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>,
2888 qcom,smem-states = <&smp2p_modem_out 0>;
2889 qcom,smem-state-names = "stop";
2893 glink-edge {
2894 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2901 qcom,remote-pid = <1>;
2908 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
2914 clock-names = "mclk",
2919 #clock-cells = <0>;
2920 clock-output-names = "wsa2-mclk";
2921 #sound-dai-cells = <1>;
2925 compatible = "qcom,soundwire-v2.0.0";
2929 clock-names = "iface";
2932 pinctrl-0 = <&wsa2_swr_active>;
2933 pinctrl-names = "default";
2935 qcom,din-ports = <4>;
2936 qcom,dout-ports = <9>;
2938 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
2939 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2940 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2941 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2942 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2943 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
2944 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
2945 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2946 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2948 #address-cells = <2>;
2949 #size-cells = <0>;
2950 #sound-dai-cells = <1>;
2955 compatible = "qcom,sm8650-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro";
2961 clock-names = "mclk",
2966 #clock-cells = <0>;
2967 clock-output-names = "mclk";
2968 #sound-dai-cells = <1>;
2972 compatible = "qcom,soundwire-v2.0.0";
2976 clock-names = "iface";
2979 pinctrl-0 = <&rx_swr_active>;
2980 pinctrl-names = "default";
2982 qcom,din-ports = <0>;
2983 qcom,dout-ports = <11>;
2985 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x03 0xff 0xff 0x31 0xff 0xff 0xff>;
2986 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x09 0x01 0xff 0xff 0x00 0xff 0xff 0xff>;
2987 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>;
2988 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0xff 0xff 0x00 0xff 0xff 0xff>;
2989 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0xff 0xff 0x0f 0xff 0xff 0xff>;
2990 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0x18 0xff 0xff 0xff>;
2991 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff 0xff 0x01 0xff 0xff 0xff>;
2992 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0x01 0x03 0xff 0xff 0x00 0xff 0xff 0xff>;
2993 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0xff 0xff 0xff>;
2995 #address-cells = <2>;
2996 #size-cells = <0>;
2997 #sound-dai-cells = <1>;
3002 compatible = "qcom,sm8650-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro";
3008 clock-names = "mclk",
3013 #clock-cells = <0>;
3014 clock-output-names = "mclk";
3015 #sound-dai-cells = <1>;
3019 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
3025 clock-names = "mclk",
3030 #clock-cells = <0>;
3031 clock-output-names = "mclk";
3032 #sound-dai-cells = <1>;
3036 compatible = "qcom,soundwire-v2.0.0";
3040 clock-names = "iface";
3043 pinctrl-0 = <&wsa_swr_active>;
3044 pinctrl-names = "default";
3046 qcom,din-ports = <4>;
3047 qcom,dout-ports = <9>;
3049 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
3050 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
3051 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3052 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3053 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3054 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
3055 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
3056 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
3057 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
3059 #address-cells = <2>;
3060 #size-cells = <0>;
3061 #sound-dai-cells = <1>;
3066 compatible = "qcom,soundwire-v2.0.0";
3070 interrupt-names = "core", "wakeup";
3072 clock-names = "iface";
3075 pinctrl-0 = <&tx_swr_active>;
3076 pinctrl-names = "default";
3078 qcom,din-ports = <4>;
3079 qcom,dout-ports = <0>;
3081 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
3082 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
3083 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
3084 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
3085 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
3086 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
3087 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
3088 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
3089 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
3091 #address-cells = <2>;
3092 #size-cells = <0>;
3093 #sound-dai-cells = <1>;
3098 compatible = "qcom,sm8650-lpass-va-macro", "qcom,sm8550-lpass-va-macro";
3103 clock-names = "mclk",
3107 #clock-cells = <0>;
3108 clock-output-names = "fsgen";
3109 #sound-dai-cells = <1>;
3113 compatible = "qcom,sm8650-lpass-lpi-pinctrl";
3118 clock-names = "core", "audio";
3120 gpio-controller;
3121 #gpio-cells = <2>;
3122 gpio-ranges = <&lpass_tlmm 0 0 23>;
3124 tx_swr_active: tx-swr-active-state {
3125 clk-pins {
3128 drive-strength = <2>;
3129 slew-rate = <1>;
3130 bias-disable;
3133 data-pins {
3136 drive-strength = <2>;
3137 slew-rate = <1>;
3138 bias-bus-hold;
3142 rx_swr_active: rx-swr-active-state {
3143 clk-pins {
3146 drive-strength = <2>;
3147 slew-rate = <1>;
3148 bias-disable;
3151 data-pins {
3154 drive-strength = <2>;
3155 slew-rate = <1>;
3156 bias-bus-hold;
3160 dmic01_default: dmic01-default-state {
3161 clk-pins {
3164 drive-strength = <8>;
3165 output-high;
3168 data-pins {
3171 drive-strength = <8>;
3172 input-enable;
3176 dmic23_default: dmic23-default-state {
3177 clk-pins {
3180 drive-strength = <8>;
3181 output-high;
3184 data-pins {
3187 drive-strength = <8>;
3188 input-enable;
3192 wsa_swr_active: wsa-swr-active-state {
3193 clk-pins {
3196 drive-strength = <2>;
3197 slew-rate = <1>;
3198 bias-disable;
3201 data-pins {
3204 drive-strength = <2>;
3205 slew-rate = <1>;
3206 bias-bus-hold;
3210 wsa2_swr_active: wsa2-swr-active-state {
3211 clk-pins {
3214 drive-strength = <2>;
3215 slew-rate = <1>;
3216 bias-disable;
3219 data-pins {
3222 drive-strength = <2>;
3223 slew-rate = <1>;
3224 bias-bus-hold;
3230 compatible = "qcom,sm8650-lpass-lpiaon-noc";
3233 #interconnect-cells = <2>;
3235 qcom,bcm-voters = <&apps_bcm_voter>;
3239 compatible = "qcom,sm8650-lpass-lpicx-noc";
3242 #interconnect-cells = <2>;
3244 qcom,bcm-voters = <&apps_bcm_voter>;
3248 compatible = "qcom,sm8650-lpass-ag-noc";
3251 #interconnect-cells = <2>;
3253 qcom,bcm-voters = <&apps_bcm_voter>;
3257 compatible = "qcom,sm8650-sdhci", "qcom,sdhci-msm-v5";
3262 interrupt-names = "hc_irq",
3268 clock-names = "iface",
3276 interconnect-names = "sdhc-ddr",
3277 "cpu-sdhc";
3279 power-domains = <&rpmhpd RPMHPD_CX>;
3280 operating-points-v2 = <&sdhc2_opp_table>;
3284 bus-width = <4>;
3286 /* Forbid SDR104/SDR50 - broken hw! */
3287 sdhci-caps-mask = <0x3 0>;
3289 qcom,dll-config = <0x0007642c>;
3290 qcom,ddr-config = <0x80040868>;
3292 dma-coherent;
3296 sdhc2_opp_table: opp-table {
3297 compatible = "operating-points-v2";
3299 opp-19200000 {
3300 opp-hz = /bits/ 64 <19200000>;
3301 required-opps = <&rpmhpd_opp_min_svs>;
3304 opp-50000000 {
3305 opp-hz = /bits/ 64 <50000000>;
3306 required-opps = <&rpmhpd_opp_low_svs>;
3309 opp-100000000 {
3310 opp-hz = /bits/ 64 <100000000>;
3311 required-opps = <&rpmhpd_opp_svs>;
3314 opp-202000000 {
3315 opp-hz = /bits/ 64 <202000000>;
3316 required-opps = <&rpmhpd_opp_svs_l1>;
3321 videocc: clock-controller@aaf0000 {
3322 compatible = "qcom,sm8650-videocc";
3326 power-domains = <&rpmhpd RPMHPD_MMCX>;
3327 #clock-cells = <1>;
3328 #reset-cells = <1>;
3329 #power-domain-cells = <1>;
3333 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
3336 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
3340 clock-names = "camnoc_axi",
3343 pinctrl-0 = <&cci0_0_default &cci0_1_default>;
3344 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
3345 pinctrl-names = "default", "sleep";
3347 #address-cells = <1>;
3348 #size-cells = <0>;
3350 cci0_i2c0: i2c-bus@0 {
3352 clock-frequency = <1000000>;
3353 #address-cells = <1>;
3354 #size-cells = <0>;
3357 cci0_i2c1: i2c-bus@1 {
3359 clock-frequency = <1000000>;
3360 #address-cells = <1>;
3361 #size-cells = <0>;
3366 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
3369 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
3373 clock-names = "camnoc_axi",
3376 pinctrl-0 = <&cci1_0_default &cci1_1_default>;
3377 pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>;
3378 pinctrl-names = "default", "sleep";
3380 #address-cells = <1>;
3381 #size-cells = <0>;
3383 cci1_i2c0: i2c-bus@0 {
3385 clock-frequency = <1000000>;
3386 #address-cells = <1>;
3387 #size-cells = <0>;
3390 cci1_i2c1: i2c-bus@1 {
3392 clock-frequency = <1000000>;
3393 #address-cells = <1>;
3394 #size-cells = <0>;
3399 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
3402 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
3406 clock-names = "camnoc_axi",
3409 pinctrl-0 = <&cci2_0_default &cci2_1_default>;
3410 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>;
3411 pinctrl-names = "default", "sleep";
3413 #address-cells = <1>;
3414 #size-cells = <0>;
3416 cci2_i2c0: i2c-bus@0 {
3418 clock-frequency = <1000000>;
3419 #address-cells = <1>;
3420 #size-cells = <0>;
3423 cci2_i2c1: i2c-bus@1 {
3425 clock-frequency = <1000000>;
3426 #address-cells = <1>;
3427 #size-cells = <0>;
3431 camcc: clock-controller@ade0000 {
3432 compatible = "qcom,sm8650-camcc";
3438 power-domains = <&rpmhpd RPMHPD_MMCX>;
3439 #clock-cells = <1>;
3440 #reset-cells = <1>;
3441 #power-domain-cells = <1>;
3444 mdss: display-subsystem@ae00000 {
3445 compatible = "qcom,sm8650-mdss";
3447 reg-names = "mdss";
3461 interconnect-names = "mdp0-mem",
3462 "mdp1-mem";
3464 power-domains = <&dispcc MDSS_GDSC>;
3468 interrupt-controller;
3469 #interrupt-cells = <1>;
3471 #address-cells = <2>;
3472 #size-cells = <2>;
3477 mdss_mdp: display-controller@ae01000 {
3478 compatible = "qcom,sm8650-dpu";
3481 reg-names = "mdp",
3484 interrupts-extended = <&mdss 0>;
3491 clock-names = "nrt_bus",
3497 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3498 assigned-clock-rates = <19200000>;
3500 operating-points-v2 = <&mdp_opp_table>;
3502 power-domains = <&rpmhpd RPMHPD_MMCX>;
3505 #address-cells = <1>;
3506 #size-cells = <0>;
3512 remote-endpoint = <&mdss_dsi0_in>;
3520 remote-endpoint = <&mdss_dsi1_in>;
3528 remote-endpoint = <&mdss_dp0_in>;
3533 mdp_opp_table: opp-table {
3534 compatible = "operating-points-v2";
3536 opp-200000000 {
3537 opp-hz = /bits/ 64 <200000000>;
3538 required-opps = <&rpmhpd_opp_low_svs>;
3541 opp-325000000 {
3542 opp-hz = /bits/ 64 <325000000>;
3543 required-opps = <&rpmhpd_opp_svs>;
3546 opp-375000000 {
3547 opp-hz = /bits/ 64 <375000000>;
3548 required-opps = <&rpmhpd_opp_svs_l1>;
3551 opp-514000000 {
3552 opp-hz = /bits/ 64 <514000000>;
3553 required-opps = <&rpmhpd_opp_nom>;
3559 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3561 reg-names = "dsi_ctrl";
3563 interrupts-extended = <&mdss 4>;
3571 clock-names = "byte",
3578 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
3580 assigned-clock-parents = <&mdss_dsi0_phy 0>,
3583 operating-points-v2 = <&mdss_dsi_opp_table>;
3585 power-domains = <&rpmhpd RPMHPD_MMCX>;
3588 phy-names = "dsi";
3590 #address-cells = <1>;
3591 #size-cells = <0>;
3596 #address-cells = <1>;
3597 #size-cells = <0>;
3603 remote-endpoint = <&dpu_intf1_out>;
3615 mdss_dsi_opp_table: opp-table {
3616 compatible = "operating-points-v2";
3618 opp-187500000 {
3619 opp-hz = /bits/ 64 <187500000>;
3620 required-opps = <&rpmhpd_opp_low_svs>;
3623 opp-300000000 {
3624 opp-hz = /bits/ 64 <300000000>;
3625 required-opps = <&rpmhpd_opp_svs>;
3628 opp-358000000 {
3629 opp-hz = /bits/ 64 <358000000>;
3630 required-opps = <&rpmhpd_opp_svs_l1>;
3636 compatible = "qcom,sm8650-dsi-phy-4nm";
3640 reg-names = "dsi_phy",
3646 clock-names = "iface",
3649 #clock-cells = <1>;
3650 #phy-cells = <0>;
3656 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3658 reg-names = "dsi_ctrl";
3660 interrupts-extended = <&mdss 5>;
3668 clock-names = "byte",
3675 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
3677 assigned-clock-parents = <&mdss_dsi1_phy 0>,
3680 operating-points-v2 = <&mdss_dsi_opp_table>;
3682 power-domains = <&rpmhpd RPMHPD_MMCX>;
3685 phy-names = "dsi";
3687 #address-cells = <1>;
3688 #size-cells = <0>;
3693 #address-cells = <1>;
3694 #size-cells = <0>;
3700 remote-endpoint = <&dpu_intf2_out>;
3714 compatible = "qcom,sm8650-dsi-phy-4nm";
3718 reg-names = "dsi_phy",
3724 clock-names = "iface",
3727 #clock-cells = <1>;
3728 #phy-cells = <0>;
3733 mdss_dp0: displayport-controller@af54000 {
3734 compatible = "qcom,sm8650-dp";
3741 interrupts-extended = <&mdss 12>;
3748 clock-names = "core_iface",
3754 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
3756 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3759 operating-points-v2 = <&dp_opp_table>;
3761 power-domains = <&rpmhpd RPMHPD_MMCX>;
3764 phy-names = "dp";
3766 #sound-dai-cells = <0>;
3770 dp_opp_table: opp-table {
3771 compatible = "operating-points-v2";
3773 opp-162000000 {
3774 opp-hz = /bits/ 64 <162000000>;
3775 required-opps = <&rpmhpd_opp_low_svs_d1>;
3778 opp-270000000 {
3779 opp-hz = /bits/ 64 <270000000>;
3780 required-opps = <&rpmhpd_opp_low_svs>;
3783 opp-540000000 {
3784 opp-hz = /bits/ 64 <540000000>;
3785 required-opps = <&rpmhpd_opp_svs_l1>;
3788 opp-810000000 {
3789 opp-hz = /bits/ 64 <810000000>;
3790 required-opps = <&rpmhpd_opp_nom>;
3795 #address-cells = <1>;
3796 #size-cells = <0>;
3802 remote-endpoint = <&dpu_intf0_out>;
3810 remote-endpoint = <&usb_dp_qmpphy_dp_in>;
3817 dispcc: clock-controller@af00000 {
3818 compatible = "qcom,sm8650-dispcc";
3838 power-domains = <&rpmhpd RPMHPD_MMCX>;
3839 required-opps = <&rpmhpd_opp_low_svs>;
3841 #clock-cells = <1>;
3842 #reset-cells = <1>;
3843 #power-domain-cells = <1>;
3849 compatible = "qcom,sm8650-snps-eusb2-phy",
3850 "qcom,sm8550-snps-eusb2-phy";
3854 clock-names = "ref";
3858 #phy-cells = <0>;
3864 compatible = "qcom,sm8650-qmp-usb3-dp-phy";
3871 clock-names = "aux",
3878 reset-names = "phy",
3881 power-domains = <&gcc USB3_PHY_GDSC>;
3883 #clock-cells = <1>;
3884 #phy-cells = <1>;
3886 orientation-switch;
3891 #address-cells = <1>;
3892 #size-cells = <0>;
3905 remote-endpoint = <&usb_1_dwc3_ss>;
3913 remote-endpoint = <&mdss_dp0_out>;
3920 compatible = "qcom,sm8650-dwc3", "qcom,dwc3";
3923 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3928 interrupt-names = "pwr_event",
3940 clock-names = "cfg_noc",
3947 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3949 assigned-clock-rates = <19200000>, <200000000>;
3953 power-domains = <&gcc USB30_PRIM_GDSC>;
3954 required-opps = <&rpmhpd_opp_nom>;
3956 #address-cells = <2>;
3957 #size-cells = <2>;
3972 phy-names = "usb2-phy",
3973 "usb3-phy";
3975 snps,hird-threshold = /bits/ 8 <0x0>;
3976 snps,usb2-gadget-lpm-disable;
3979 snps,dis-u1-entry-quirk;
3980 snps,dis-u2-entry-quirk;
3981 snps,is-utmi-l1-suspend;
3983 snps,usb2-lpm-disable;
3984 snps,has-lpm-erratum;
3985 tx-fifo-resize;
3987 dma-coherent;
3990 #address-cells = <1>;
3991 #size-cells = <0>;
4004 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
4011 pdc: interrupt-controller@b220000 {
4012 compatible = "qcom,sm8650-pdc", "qcom,pdc";
4015 interrupt-parent = <&intc>;
4017 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
4021 #interrupt-cells = <2>;
4022 interrupt-controller;
4025 tsens0: thermal-sensor@c228000 {
4026 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2";
4032 interrupt-names = "uplow",
4037 #thermal-sensor-cells = <1>;
4040 tsens1: thermal-sensor@c229000 {
4041 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2";
4047 interrupt-names = "uplow",
4052 #thermal-sensor-cells = <1>;
4055 tsens2: thermal-sensor@c22a000 {
4056 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2";
4062 interrupt-names = "uplow",
4067 #thermal-sensor-cells = <1>;
4070 aoss_qmp: power-management@c300000 {
4071 compatible = "qcom,sm8650-aoss-qmp", "qcom,aoss-qmp";
4074 interrupt-parent = <&ipcc>;
4075 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
4080 #clock-cells = <0>;
4084 compatible = "qcom,rpmh-stats";
4089 compatible = "qcom,spmi-pmic-arb";
4095 reg-names = "core",
4101 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4102 interrupt-names = "periph_irq";
4106 qcom,bus-id = <0>;
4108 interrupt-controller;
4109 #interrupt-cells = <4>;
4111 #address-cells = <2>;
4112 #size-cells = <0>;
4116 compatible = "qcom,sm8650-tlmm";
4121 gpio-controller;
4122 #gpio-cells = <2>;
4124 interrupt-controller;
4125 #interrupt-cells = <2>;
4127 gpio-ranges = <&tlmm 0 0 211>;
4129 wakeup-parent = <&pdc>;
4131 cci0_0_default: cci0-0-default-state {
4132 sda-pins {
4135 drive-strength = <2>;
4136 bias-pull-up = <2200>;
4139 scl-pins {
4142 drive-strength = <2>;
4143 bias-pull-up = <2200>;
4147 cci0_0_sleep: cci0-0-sleep-state {
4148 sda-pins {
4151 drive-strength = <2>;
4152 bias-pull-down;
4155 scl-pins {
4158 drive-strength = <2>;
4159 bias-pull-down;
4163 cci0_1_default: cci0-1-default-state {
4164 sda-pins {
4167 drive-strength = <2>;
4168 bias-pull-up = <2200>;
4171 scl-pins {
4174 drive-strength = <2>;
4175 bias-pull-up = <2200>;
4179 cci0_1_sleep: cci0-1-sleep-state {
4180 sda-pins {
4183 drive-strength = <2>;
4184 bias-pull-down;
4187 scl-pins {
4190 drive-strength = <2>;
4191 bias-pull-down;
4195 cci1_0_default: cci1-0-default-state {
4196 sda-pins {
4199 drive-strength = <2>;
4200 bias-pull-up = <2200>;
4203 scl-pins {
4206 drive-strength = <2>;
4207 bias-pull-up = <2200>;
4211 cci1_0_sleep: cci1-0-sleep-state {
4212 sda-pins {
4215 drive-strength = <2>;
4216 bias-pull-down;
4219 scl-pins {
4222 drive-strength = <2>;
4223 bias-pull-down;
4227 cci1_1_default: cci1-1-default-state {
4228 sda-pins {
4231 drive-strength = <2>;
4232 bias-pull-up = <2200>;
4235 scl-pins {
4238 drive-strength = <2>;
4239 bias-pull-up = <2200>;
4243 cci1_1_sleep: cci1-1-sleep-state {
4244 sda-pins {
4247 drive-strength = <2>;
4248 bias-pull-down;
4251 scl-pins {
4254 drive-strength = <2>;
4255 bias-pull-down;
4259 cci2_0_default: cci2-0-default-state {
4260 sda-pins {
4263 drive-strength = <2>;
4264 bias-pull-up = <2200>;
4267 scl-pins {
4270 drive-strength = <2>;
4271 bias-pull-up = <2200>;
4275 cci2_0_sleep: cci2-0-sleep-state {
4276 sda-pins {
4279 drive-strength = <2>;
4280 bias-pull-down;
4283 scl-pins {
4286 drive-strength = <2>;
4287 bias-pull-down;
4291 cci2_1_default: cci2-1-default-state {
4292 sda-pins {
4295 drive-strength = <2>;
4296 bias-pull-up = <2200>;
4299 scl-pins {
4302 drive-strength = <2>;
4303 bias-pull-up = <2200>;
4307 cci2_1_sleep: cci2-1-sleep-state {
4308 sda-pins {
4311 drive-strength = <2>;
4312 bias-pull-down;
4315 scl-pins {
4318 drive-strength = <2>;
4319 bias-pull-down;
4323 hub_i2c0_data_clk: hub-i2c0-data-clk-state {
4327 drive-strength = <2>;
4328 bias-pull-up;
4331 hub_i2c1_data_clk: hub-i2c1-data-clk-state {
4335 drive-strength = <2>;
4336 bias-pull-up;
4339 hub_i2c2_data_clk: hub-i2c2-data-clk-state {
4343 drive-strength = <2>;
4344 bias-pull-up;
4347 hub_i2c3_data_clk: hub-i2c3-data-clk-state {
4351 drive-strength = <2>;
4352 bias-pull-up;
4355 hub_i2c4_data_clk: hub-i2c4-data-clk-state {
4359 drive-strength = <2>;
4360 bias-pull-up;
4363 hub_i2c5_data_clk: hub-i2c5-data-clk-state {
4367 drive-strength = <2>;
4368 bias-pull-up;
4371 hub_i2c6_data_clk: hub-i2c6-data-clk-state {
4375 drive-strength = <2>;
4376 bias-pull-up;
4379 hub_i2c7_data_clk: hub-i2c7-data-clk-state {
4383 drive-strength = <2>;
4384 bias-pull-up;
4387 hub_i2c8_data_clk: hub-i2c8-data-clk-state {
4391 drive-strength = <2>;
4392 bias-pull-up;
4395 hub_i2c9_data_clk: hub-i2c9-data-clk-state {
4399 drive-strength = <2>;
4400 bias-pull-up;
4403 pcie0_default_state: pcie0-default-state {
4404 perst-pins {
4407 drive-strength = <2>;
4408 bias-pull-down;
4411 clkreq-pins {
4414 drive-strength = <2>;
4415 bias-pull-up;
4418 wake-pins {
4421 drive-strength = <2>;
4422 bias-pull-up;
4426 pcie1_default_state: pcie1-default-state {
4427 perst-pins {
4430 drive-strength = <2>;
4431 bias-pull-down;
4434 clkreq-pins {
4437 drive-strength = <2>;
4438 bias-pull-up;
4441 wake-pins {
4444 drive-strength = <2>;
4445 bias-pull-up;
4449 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
4453 drive-strength = <2>;
4454 bias-pull-up;
4457 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
4461 drive-strength = <2>;
4462 bias-pull-up;
4465 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
4469 drive-strength = <2>;
4470 bias-pull-up;
4473 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
4477 drive-strength = <2>;
4478 bias-pull-up;
4481 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
4485 drive-strength = <2>;
4486 bias-pull-up;
4489 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
4493 drive-strength = <2>;
4494 bias-pull-up;
4497 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
4501 drive-strength = <2>;
4502 bias-pull-up;
4505 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
4509 drive-strength = <2>;
4510 bias-pull-up;
4513 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
4517 drive-strength = <2>;
4518 bias-pull-up;
4521 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
4525 drive-strength = <2>;
4526 bias-pull-up;
4529 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
4533 drive-strength = <2>;
4534 bias-pull-up;
4537 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
4541 drive-strength = <2>;
4542 bias-pull-up;
4545 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
4549 drive-strength = <2>;
4550 bias-pull-up;
4553 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
4557 drive-strength = <2>;
4558 bias-pull-up;
4561 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
4565 drive-strength = <2>;
4566 bias-pull-up;
4569 qup_spi0_cs: qup-spi0-cs-state {
4572 drive-strength = <6>;
4573 bias-disable;
4576 qup_spi0_data_clk: qup-spi0-data-clk-state {
4580 drive-strength = <6>;
4581 bias-disable;
4584 qup_spi1_cs: qup-spi1-cs-state {
4587 drive-strength = <6>;
4588 bias-disable;
4591 qup_spi1_data_clk: qup-spi1-data-clk-state {
4595 drive-strength = <6>;
4596 bias-disable;
4599 qup_spi2_cs: qup-spi2-cs-state {
4602 drive-strength = <6>;
4603 bias-disable;
4606 qup_spi2_data_clk: qup-spi2-data-clk-state {
4610 drive-strength = <6>;
4611 bias-disable;
4614 qup_spi3_cs: qup-spi3-cs-state {
4617 drive-strength = <6>;
4618 bias-disable;
4621 qup_spi3_data_clk: qup-spi3-data-clk-state {
4625 drive-strength = <6>;
4626 bias-disable;
4629 qup_spi4_cs: qup-spi4-cs-state {
4632 drive-strength = <6>;
4633 bias-disable;
4636 qup_spi4_data_clk: qup-spi4-data-clk-state {
4640 drive-strength = <6>;
4641 bias-disable;
4644 qup_spi5_cs: qup-spi5-cs-state {
4647 drive-strength = <6>;
4648 bias-disable;
4651 qup_spi5_data_clk: qup-spi5-data-clk-state {
4655 drive-strength = <6>;
4656 bias-disable;
4659 qup_spi6_cs: qup-spi6-cs-state {
4662 drive-strength = <6>;
4663 bias-disable;
4666 qup_spi6_data_clk: qup-spi6-data-clk-state {
4670 drive-strength = <6>;
4671 bias-disable;
4674 qup_spi7_cs: qup-spi7-cs-state {
4677 drive-strength = <6>;
4678 bias-disable;
4681 qup_spi7_data_clk: qup-spi7-data-clk-state {
4685 drive-strength = <6>;
4686 bias-disable;
4689 qup_spi8_cs: qup-spi8-cs-state {
4692 drive-strength = <6>;
4693 bias-disable;
4696 qup_spi8_data_clk: qup-spi8-data-clk-state {
4700 drive-strength = <6>;
4701 bias-disable;
4704 qup_spi9_cs: qup-spi9-cs-state {
4707 drive-strength = <6>;
4708 bias-disable;
4711 qup_spi9_data_clk: qup-spi9-data-clk-state {
4715 drive-strength = <6>;
4716 bias-disable;
4719 qup_spi10_cs: qup-spi10-cs-state {
4722 drive-strength = <6>;
4723 bias-disable;
4726 qup_spi10_data_clk: qup-spi10-data-clk-state {
4730 drive-strength = <6>;
4731 bias-disable;
4734 qup_spi11_cs: qup-spi11-cs-state {
4737 drive-strength = <6>;
4738 bias-disable;
4741 qup_spi11_data_clk: qup-spi11-data-clk-state {
4745 drive-strength = <6>;
4746 bias-disable;
4749 qup_spi12_cs: qup-spi12-cs-state {
4752 drive-strength = <6>;
4753 bias-disable;
4756 qup_spi12_data_clk: qup-spi12-data-clk-state {
4760 drive-strength = <6>;
4761 bias-disable;
4764 qup_spi13_cs: qup-spi13-cs-state {
4767 drive-strength = <6>;
4768 bias-disable;
4771 qup_spi13_data_clk: qup-spi13-data-clk-state {
4775 drive-strength = <6>;
4776 bias-disable;
4779 qup_spi14_cs: qup-spi14-cs-state {
4782 drive-strength = <6>;
4783 bias-disable;
4786 qup_spi14_data_clk: qup-spi14-data-clk-state {
4790 drive-strength = <6>;
4791 bias-disable;
4794 qup_uart14_default: qup-uart14-default-state {
4798 drive-strength = <2>;
4799 bias-pull-up;
4802 qup_uart14_cts_rts: qup-uart14-cts-rts-state {
4806 drive-strength = <2>;
4807 bias-pull-down;
4810 qup_uart15_default: qup-uart15-default-state {
4814 drive-strength = <2>;
4815 bias-disable;
4818 sdc2_sleep: sdc2-sleep-state {
4819 clk-pins {
4821 drive-strength = <2>;
4822 bias-disable;
4825 cmd-pins {
4827 drive-strength = <2>;
4828 bias-pull-up;
4831 data-pins {
4833 drive-strength = <2>;
4834 bias-pull-up;
4838 sdc2_default: sdc2-default-state {
4839 clk-pins {
4841 drive-strength = <16>;
4842 bias-disable;
4845 cmd-pins {
4847 drive-strength = <10>;
4848 bias-pull-up;
4851 data-pins {
4853 drive-strength = <10>;
4854 bias-pull-up;
4860 compatible = "qcom,sm8650-smmu-500", "qcom,smmu-500", "arm,mmu-500";
4961 #iommu-cells = <2>;
4962 #global-interrupts = <1>;
4964 dma-coherent;
4967 intc: interrupt-controller@17100000 {
4968 compatible = "arm,gic-v3";
4974 #interrupt-cells = <3>;
4975 interrupt-controller;
4977 #redistributor-regions = <1>;
4978 redistributor-stride = <0 0x40000>;
4980 #address-cells = <2>;
4981 #size-cells = <2>;
4984 gic_its: msi-controller@17140000 {
4985 compatible = "arm,gic-v3-its";
4988 msi-controller;
4989 #msi-cells = <1>;
4994 compatible = "arm,armv7-timer-mem";
4998 #address-cells = <1>;
4999 #size-cells = <1>;
5008 frame-number = <0>;
5016 frame-number = <1>;
5026 frame-number = <2>;
5036 frame-number = <3>;
5046 frame-number = <4>;
5056 frame-number = <5>;
5066 frame-number = <6>;
5073 compatible = "qcom,rpmh-rsc";
5078 reg-names = "drv-0",
5079 "drv-1",
5080 "drv-2";
5086 power-domains = <&CLUSTER_PD>;
5088 qcom,tcs-offset = <0xd00>;
5089 qcom,drv-id = <2>;
5090 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
5095 apps_bcm_voter: bcm-voter {
5096 compatible = "qcom,bcm-voter";
5099 rpmhcc: clock-controller {
5100 compatible = "qcom,sm8650-rpmh-clk";
5103 clock-names = "xo";
5105 #clock-cells = <1>;
5108 rpmhpd: power-controller {
5109 compatible = "qcom,sm8650-rpmhpd";
5111 operating-points-v2 = <&rpmhpd_opp_table>;
5113 #power-domain-cells = <1>;
5115 rpmhpd_opp_table: opp-table {
5116 compatible = "operating-points-v2";
5118 rpmhpd_opp_ret: opp-16 {
5119 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5122 rpmhpd_opp_min_svs: opp-48 {
5123 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5126 rpmhpd_opp_low_svs_d2: opp-52 {
5127 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
5130 rpmhpd_opp_low_svs_d1: opp-56 {
5131 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
5134 rpmhpd_opp_low_svs_d0: opp-60 {
5135 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
5138 rpmhpd_opp_low_svs: opp-64 {
5139 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5142 rpmhpd_opp_low_svs_l1: opp-80 {
5143 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
5146 rpmhpd_opp_svs: opp-128 {
5147 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5150 rpmhpd_opp_svs_l0: opp-144 {
5151 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
5154 rpmhpd_opp_svs_l1: opp-192 {
5155 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5158 rpmhpd_opp_nom: opp-256 {
5159 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5162 rpmhpd_opp_nom_l1: opp-320 {
5163 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5166 rpmhpd_opp_nom_l2: opp-336 {
5167 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5170 rpmhpd_opp_turbo: opp-384 {
5171 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5174 rpmhpd_opp_turbo_l1: opp-416 {
5175 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5182 compatible = "qcom,sm8650-cpufreq-epss", "qcom,cpufreq-epss";
5187 reg-names = "freq-domain0",
5188 "freq-domain1",
5189 "freq-domain2",
5190 "freq-domain3";
5196 interrupt-names = "dcvsh-irq-0",
5197 "dcvsh-irq-1",
5198 "dcvsh-irq-2",
5199 "dcvsh-irq-3";
5202 clock-names = "xo", "alternate";
5204 #freq-domain-cells = <1>;
5205 #clock-cells = <1>;
5209 compatible = "qcom,sm8650-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
5217 operating-points-v2 = <&llcc_bwmon_opp_table>;
5219 llcc_bwmon_opp_table: opp-table {
5220 compatible = "operating-points-v2";
5222 opp-0 {
5223 opp-peak-kBps = <2086000>;
5226 opp-1 {
5227 opp-peak-kBps = <2929000>;
5230 opp-2 {
5231 opp-peak-kBps = <5931000>;
5234 opp-3 {
5235 opp-peak-kBps = <6515000>;
5238 opp-4 {
5239 opp-peak-kBps = <7980000>;
5242 opp-5 {
5243 opp-peak-kBps = <10437000>;
5246 opp-6 {
5247 opp-peak-kBps = <12157000>;
5250 opp-7 {
5251 opp-peak-kBps = <14060000>;
5254 opp-8 {
5255 opp-peak-kBps = <16113000>;
5261 compatible = "qcom,sm8650-cpu-bwmon", "qcom,sdm845-bwmon";
5269 operating-points-v2 = <&cpu_bwmon_opp_table>;
5271 cpu_bwmon_opp_table: opp-table {
5272 compatible = "operating-points-v2";
5274 opp-0 {
5275 opp-peak-kBps = <4577000>;
5278 opp-1 {
5279 opp-peak-kBps = <7110000>;
5282 opp-2 {
5283 opp-peak-kBps = <9155000>;
5286 opp-3 {
5287 opp-peak-kBps = <12298000>;
5290 opp-4 {
5291 opp-peak-kBps = <14236000>;
5294 opp-5 {
5295 opp-peak-kBps = <16265000>;
5301 compatible = "qcom,sm8650-gem-noc";
5304 qcom,bcm-voters = <&apps_bcm_voter>;
5306 #interconnect-cells = <2>;
5309 system-cache-controller@25000000 {
5310 compatible = "qcom,sm8650-llcc";
5317 reg-names = "llcc0_base",
5328 compatible = "qcom,sm8650-adsp-pas";
5331 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
5336 interrupt-names = "wdog",
5340 "stop-ack";
5343 clock-names = "xo";
5348 power-domains = <&rpmhpd RPMHPD_LCX>,
5350 power-domain-names = "lcx",
5353 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
5357 qcom,smem-states = <&smp2p_adsp_out 0>;
5358 qcom,smem-state-names = "stop";
5362 remoteproc_adsp_glink: glink-edge {
5363 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
5370 qcom,remote-pid = <2>;
5377 qcom,glink-channels = "fastrpcglink-apps-dsp";
5381 qcom,non-secure-domain;
5383 #address-cells = <1>;
5384 #size-cells = <0>;
5386 compute-cb@3 {
5387 compatible = "qcom,fastrpc-compute-cb";
5392 dma-coherent;
5395 compute-cb@4 {
5396 compatible = "qcom,fastrpc-compute-cb";
5401 dma-coherent;
5404 compute-cb@5 {
5405 compatible = "qcom,fastrpc-compute-cb";
5410 dma-coherent;
5413 compute-cb@6 {
5414 compatible = "qcom,fastrpc-compute-cb";
5419 dma-coherent;
5422 compute-cb@7 {
5423 compatible = "qcom,fastrpc-compute-cb";
5429 dma-coherent;
5435 qcom,glink-channels = "adsp_apps";
5438 #address-cells = <1>;
5439 #size-cells = <0>;
5444 #sound-dai-cells = <0>;
5445 qcom,protection-domain = "avs/audio",
5449 compatible = "qcom,q6apm-lpass-dais";
5450 #sound-dai-cells = <1>;
5454 compatible = "qcom,q6apm-dais";
5463 qcom,protection-domain = "avs/audio",
5466 q6prmcc: clock-controller {
5467 compatible = "qcom,q6prm-lpass-clocks";
5468 #clock-cells = <2>;
5476 compatible = "qcom,sm8650-nsp-noc";
5479 qcom,bcm-voters = <&apps_bcm_voter>;
5481 #interconnect-cells = <2>;
5485 compatible = "qcom,sm8650-cdsp-pas";
5488 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
5493 interrupt-names = "wdog",
5497 "stop-ack";
5500 clock-names = "xo";
5505 power-domains = <&rpmhpd RPMHPD_CX>,
5508 power-domain-names = "cx",
5512 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>, <&global_sync_mem>;
5516 qcom,smem-states = <&smp2p_cdsp_out 0>;
5517 qcom,smem-state-names = "stop";
5521 glink-edge {
5522 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
5529 qcom,remote-pid = <5>;
5536 qcom,glink-channels = "fastrpcglink-apps-dsp";
5540 qcom,non-secure-domain;
5542 #address-cells = <1>;
5543 #size-cells = <0>;
5545 compute-cb@1 {
5546 compatible = "qcom,fastrpc-compute-cb";
5552 dma-coherent;
5555 compute-cb@2 {
5556 compatible = "qcom,fastrpc-compute-cb";
5562 dma-coherent;
5565 compute-cb@3 {
5566 compatible = "qcom,fastrpc-compute-cb";
5572 dma-coherent;
5575 compute-cb@4 {
5576 compatible = "qcom,fastrpc-compute-cb";
5582 dma-coherent;
5585 compute-cb@5 {
5586 compatible = "qcom,fastrpc-compute-cb";
5592 dma-coherent;
5595 compute-cb@6 {
5596 compatible = "qcom,fastrpc-compute-cb";
5602 dma-coherent;
5605 compute-cb@7 {
5606 compatible = "qcom,fastrpc-compute-cb";
5612 dma-coherent;
5615 compute-cb@8 {
5616 compatible = "qcom,fastrpc-compute-cb";
5622 dma-coherent;
5627 compute-cb@10 {
5628 compatible = "qcom,fastrpc-compute-cb";
5634 dma-coherent;
5637 compute-cb@11 {
5638 compatible = "qcom,fastrpc-compute-cb";
5644 dma-coherent;
5647 compute-cb@12 {
5648 compatible = "qcom,fastrpc-compute-cb";
5654 dma-coherent;
5661 thermal-zones {
5662 aoss0-thermal {
5663 thermal-sensors = <&tsens0 0>;
5666 trip-point0 {
5672 aoss0-critical {
5680 cpuss0-thermal {
5681 thermal-sensors = <&tsens0 1>;
5684 trip-point0 {
5690 cpuss0-critical {
5698 cpuss1-thermal {
5699 thermal-sensors = <&tsens0 2>;
5702 trip-point0 {
5708 cpuss1-critical {
5716 cpuss2-thermal {
5717 thermal-sensors = <&tsens0 3>;
5720 trip-point0 {
5726 cpuss2-critical {
5734 cpuss3-thermal {
5735 thermal-sensors = <&tsens0 4>;
5738 trip-point0 {
5744 cpuss3-critical {
5752 cpu2-top-thermal {
5753 thermal-sensors = <&tsens0 5>;
5756 trip-point0 {
5762 trip-point1 {
5768 cpu2-critical {
5776 cpu2-bottom-thermal {
5777 thermal-sensors = <&tsens0 6>;
5780 trip-point0 {
5786 trip-point1 {
5792 cpu2-critical {
5800 cpu3-top-thermal {
5801 thermal-sensors = <&tsens0 7>;
5804 trip-point0 {
5810 trip-point1 {
5816 cpu3-critical {
5824 cpu3-bottom-thermal {
5825 thermal-sensors = <&tsens0 8>;
5828 trip-point0 {
5834 trip-point1 {
5840 cpu3-critical {
5848 cpu4-top-thermal {
5849 thermal-sensors = <&tsens0 9>;
5852 trip-point0 {
5858 trip-point1 {
5864 cpu4-critical {
5872 cpu4-bottom-thermal {
5873 thermal-sensors = <&tsens0 10>;
5876 trip-point0 {
5882 trip-point1 {
5888 cpu4-critical {
5896 cpu5-top-thermal {
5897 thermal-sensors = <&tsens0 11>;
5900 trip-point0 {
5906 trip-point1 {
5912 cpu5-critical {
5920 cpu5-bottom-thermal {
5921 thermal-sensors = <&tsens0 12>;
5924 trip-point0 {
5930 trip-point1 {
5936 cpu5-critical {
5944 cpu6-top-thermal {
5945 thermal-sensors = <&tsens0 13>;
5948 trip-point0 {
5954 trip-point1 {
5960 cpu6-critical {
5968 cpu6-bottom-thermal {
5969 thermal-sensors = <&tsens0 14>;
5972 trip-point0 {
5978 trip-point1 {
5984 cpu6-critical {
5992 aoss1-thermal {
5993 thermal-sensors = <&tsens1 0>;
5996 trip-point0 {
6002 aoss1-critical {
6010 cpu7-top-thermal {
6011 thermal-sensors = <&tsens1 1>;
6014 trip-point0 {
6020 trip-point1 {
6026 cpu7-critical {
6034 cpu7-middle-thermal {
6035 thermal-sensors = <&tsens1 2>;
6038 trip-point0 {
6044 trip-point1 {
6050 cpu7-critical {
6058 cpu7-bottom-thermal {
6059 thermal-sensors = <&tsens1 3>;
6062 trip-point0 {
6068 trip-point1 {
6074 cpu7-critical {
6082 cpu0-thermal {
6083 thermal-sensors = <&tsens1 4>;
6086 trip-point0 {
6092 trip-point1 {
6098 cpu0-critical {
6106 cpu1-thermal {
6107 thermal-sensors = <&tsens1 5>;
6110 trip-point0 {
6116 trip-point1 {
6122 cpu1-critical {
6130 nsphvx0-thermal {
6131 polling-delay-passive = <10>;
6133 thermal-sensors = <&tsens2 6>;
6136 trip-point0 {
6142 nsphvx1-critical {
6150 nsphvx1-thermal {
6151 polling-delay-passive = <10>;
6153 thermal-sensors = <&tsens2 7>;
6156 trip-point0 {
6162 nsphvx1-critical {
6170 nsphmx0-thermal {
6171 polling-delay-passive = <10>;
6173 thermal-sensors = <&tsens2 8>;
6176 trip-point0 {
6182 nsphmx0-critical {
6190 nsphmx1-thermal {
6191 polling-delay-passive = <10>;
6193 thermal-sensors = <&tsens2 9>;
6196 trip-point0 {
6202 nsphmx1-critical {
6210 nsphmx2-thermal {
6211 polling-delay-passive = <10>;
6213 thermal-sensors = <&tsens2 10>;
6216 trip-point0 {
6222 nsphmx2-critical {
6230 nsphmx3-thermal {
6231 polling-delay-passive = <10>;
6233 thermal-sensors = <&tsens2 11>;
6236 trip-point0 {
6242 nsphmx3-critical {
6250 video-thermal {
6251 polling-delay-passive = <10>;
6253 thermal-sensors = <&tsens1 12>;
6256 trip-point0 {
6262 video-critical {
6270 ddr-thermal {
6271 polling-delay-passive = <10>;
6273 thermal-sensors = <&tsens1 13>;
6276 trip-point0 {
6282 ddr-critical {
6290 camera0-thermal {
6291 thermal-sensors = <&tsens1 14>;
6294 trip-point0 {
6300 camera0-critical {
6308 camera1-thermal {
6309 thermal-sensors = <&tsens1 15>;
6312 trip-point0 {
6318 camera1-critical {
6326 aoss2-thermal {
6327 thermal-sensors = <&tsens2 0>;
6330 trip-point0 {
6336 aoss2-critical {
6344 gpuss0-thermal {
6345 polling-delay-passive = <10>;
6347 thermal-sensors = <&tsens2 1>;
6349 cooling-maps {
6352 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6357 gpu0_alert0: trip-point0 {
6363 trip-point1 {
6369 trip-point2 {
6377 gpuss1-thermal {
6378 polling-delay-passive = <10>;
6380 thermal-sensors = <&tsens2 2>;
6382 cooling-maps {
6385 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6390 gpu1_alert0: trip-point0 {
6396 trip-point1 {
6402 trip-point2 {
6410 gpuss2-thermal {
6411 polling-delay-passive = <10>;
6413 thermal-sensors = <&tsens2 3>;
6415 cooling-maps {
6418 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6423 gpu2_alert0: trip-point0 {
6429 trip-point1 {
6435 trip-point2 {
6443 gpuss3-thermal {
6444 polling-delay-passive = <10>;
6446 thermal-sensors = <&tsens2 4>;
6448 cooling-maps {
6451 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6456 gpu3_alert0: trip-point0 {
6462 trip-point1 {
6468 trip-point2 {
6476 gpuss4-thermal {
6477 polling-delay-passive = <10>;
6479 thermal-sensors = <&tsens2 5>;
6481 cooling-maps {
6484 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6489 gpu4_alert0: trip-point0 {
6495 trip-point1 {
6501 trip-point2 {
6509 gpuss5-thermal {
6510 polling-delay-passive = <10>;
6512 thermal-sensors = <&tsens2 6>;
6514 cooling-maps {
6517 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6522 gpu5_alert0: trip-point0 {
6528 trip-point1 {
6534 trip-point2 {
6542 gpuss6-thermal {
6543 polling-delay-passive = <10>;
6545 thermal-sensors = <&tsens2 7>;
6547 cooling-maps {
6550 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6555 gpu6_alert0: trip-point0 {
6561 trip-point1 {
6567 trip-point2 {
6575 gpuss7-thermal {
6576 polling-delay-passive = <10>;
6578 thermal-sensors = <&tsens2 8>;
6580 cooling-maps {
6583 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6588 gpu7_alert0: trip-point0 {
6594 trip-point1 {
6600 trip-point2 {
6608 modem0-thermal {
6609 thermal-sensors = <&tsens2 9>;
6612 trip-point0 {
6618 modem0-critical {
6626 modem1-thermal {
6627 thermal-sensors = <&tsens2 10>;
6630 trip-point0 {
6636 modem1-critical {
6644 modem2-thermal {
6645 thermal-sensors = <&tsens2 11>;
6648 trip-point0 {
6654 modem2-critical {
6662 modem3-thermal {
6663 thermal-sensors = <&tsens2 12>;
6666 trip-point0 {
6672 modem3-critical {
6682 compatible = "arm,armv8-timer";