Lines Matching +full:sda +full:- +full:pins
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm8650-camcc.h>
8 #include <dt-bindings/clock/qcom,sm8650-dispcc.h>
9 #include <dt-bindings/clock/qcom,sm8650-gcc.h>
10 #include <dt-bindings/clock/qcom,sm8650-gpucc.h>
11 #include <dt-bindings/clock/qcom,sm8650-tcsr.h>
12 #include <dt-bindings/clock/qcom,sm8650-videocc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/interconnect/qcom,icc.h>
17 #include <dt-bindings/interconnect/qcom,sm8650-rpmh.h>
18 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/mailbox/qcom-ipcc.h>
20 #include <dt-bindings/phy/phy-qcom-qmp.h>
21 #include <dt-bindings/power/qcom,rpmhpd.h>
22 #include <dt-bindings/power/qcom-rpmpd.h>
23 #include <dt-bindings/reset/qcom,sm8650-gpucc.h>
24 #include <dt-bindings/soc/qcom,gpr.h>
25 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
26 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
27 #include <dt-bindings/thermal/thermal.h>
30 interrupt-parent = <&intc>;
32 #address-cells = <2>;
33 #size-cells = <2>;
38 xo_board: xo-board {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
43 sleep_clk: sleep-clk {
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
48 bi_tcxo_div2: bi-tcxo-div2-clk {
49 compatible = "fixed-factor-clock";
50 #clock-cells = <0>;
53 clock-mult = <1>;
54 clock-div = <2>;
57 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
58 compatible = "fixed-factor-clock";
59 #clock-cells = <0>;
62 clock-mult = <1>;
63 clock-div = <2>;
68 #address-cells = <2>;
69 #size-cells = <0>;
73 compatible = "arm,cortex-a520";
78 power-domains = <&cpu_pd0>;
79 power-domain-names = "psci";
81 enable-method = "psci";
82 next-level-cache = <&l2_0>;
83 capacity-dmips-mhz = <1024>;
84 dynamic-power-coefficient = <100>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
88 #cooling-cells = <2>;
90 l2_0: l2-cache {
92 cache-level = <2>;
93 cache-unified;
94 next-level-cache = <&l3_0>;
96 l3_0: l3-cache {
98 cache-level = <3>;
99 cache-unified;
106 compatible = "arm,cortex-a520";
111 power-domains = <&cpu_pd1>;
112 power-domain-names = "psci";
114 enable-method = "psci";
115 next-level-cache = <&l2_0>;
116 capacity-dmips-mhz = <1024>;
117 dynamic-power-coefficient = <100>;
119 qcom,freq-domain = <&cpufreq_hw 0>;
121 #cooling-cells = <2>;
126 compatible = "arm,cortex-a720";
131 power-domains = <&cpu_pd2>;
132 power-domain-names = "psci";
134 enable-method = "psci";
135 next-level-cache = <&l2_200>;
136 capacity-dmips-mhz = <1792>;
137 dynamic-power-coefficient = <238>;
139 qcom,freq-domain = <&cpufreq_hw 3>;
141 #cooling-cells = <2>;
143 l2_200: l2-cache {
145 cache-level = <2>;
146 cache-unified;
147 next-level-cache = <&l3_0>;
153 compatible = "arm,cortex-a720";
158 power-domains = <&cpu_pd3>;
159 power-domain-names = "psci";
161 enable-method = "psci";
162 next-level-cache = <&l2_200>;
163 capacity-dmips-mhz = <1792>;
164 dynamic-power-coefficient = <238>;
166 qcom,freq-domain = <&cpufreq_hw 3>;
168 #cooling-cells = <2>;
173 compatible = "arm,cortex-a720";
178 power-domains = <&cpu_pd4>;
179 power-domain-names = "psci";
181 enable-method = "psci";
182 next-level-cache = <&l2_400>;
183 capacity-dmips-mhz = <1792>;
184 dynamic-power-coefficient = <238>;
186 qcom,freq-domain = <&cpufreq_hw 3>;
188 #cooling-cells = <2>;
190 l2_400: l2-cache {
192 cache-level = <2>;
193 cache-unified;
194 next-level-cache = <&l3_0>;
200 compatible = "arm,cortex-a720";
205 power-domains = <&cpu_pd5>;
206 power-domain-names = "psci";
208 enable-method = "psci";
209 next-level-cache = <&l2_500>;
210 capacity-dmips-mhz = <1792>;
211 dynamic-power-coefficient = <238>;
213 qcom,freq-domain = <&cpufreq_hw 1>;
215 #cooling-cells = <2>;
217 l2_500: l2-cache {
219 cache-level = <2>;
220 cache-unified;
221 next-level-cache = <&l3_0>;
227 compatible = "arm,cortex-a720";
232 power-domains = <&cpu_pd6>;
233 power-domain-names = "psci";
235 enable-method = "psci";
236 next-level-cache = <&l2_600>;
237 capacity-dmips-mhz = <1792>;
238 dynamic-power-coefficient = <238>;
240 qcom,freq-domain = <&cpufreq_hw 1>;
242 #cooling-cells = <2>;
244 l2_600: l2-cache {
246 cache-level = <2>;
247 cache-unified;
248 next-level-cache = <&l3_0>;
254 compatible = "arm,cortex-x4";
259 power-domains = <&cpu_pd7>;
260 power-domain-names = "psci";
262 enable-method = "psci";
263 next-level-cache = <&l2_700>;
264 capacity-dmips-mhz = <1894>;
265 dynamic-power-coefficient = <588>;
267 qcom,freq-domain = <&cpufreq_hw 2>;
269 #cooling-cells = <2>;
271 l2_700: l2-cache {
273 cache-level = <2>;
274 cache-unified;
275 next-level-cache = <&l3_0>;
279 cpu-map {
315 idle-states {
316 entry-method = "psci";
318 silver_cpu_sleep_0: cpu-sleep-0-0 {
319 compatible = "arm,idle-state";
320 idle-state-name = "silver-rail-power-collapse";
321 arm,psci-suspend-param = <0x40000004>;
322 entry-latency-us = <550>;
323 exit-latency-us = <750>;
324 min-residency-us = <6700>;
325 local-timer-stop;
328 gold_cpu_sleep_0: cpu-sleep-1-0 {
329 compatible = "arm,idle-state";
330 idle-state-name = "gold-rail-power-collapse";
331 arm,psci-suspend-param = <0x40000004>;
332 entry-latency-us = <600>;
333 exit-latency-us = <1300>;
334 min-residency-us = <8136>;
335 local-timer-stop;
338 gold_plus_cpu_sleep_0: cpu-sleep-2-0 {
339 compatible = "arm,idle-state";
340 idle-state-name = "gold-plus-rail-power-collapse";
341 arm,psci-suspend-param = <0x40000004>;
342 entry-latency-us = <500>;
343 exit-latency-us = <1350>;
344 min-residency-us = <7480>;
345 local-timer-stop;
349 domain-idle-states {
350 cluster_sleep_0: cluster-sleep-0 {
351 compatible = "domain-idle-state";
352 arm,psci-suspend-param = <0x41000044>;
353 entry-latency-us = <750>;
354 exit-latency-us = <2350>;
355 min-residency-us = <9144>;
358 cluster_sleep_1: cluster-sleep-1 {
359 compatible = "domain-idle-state";
360 arm,psci-suspend-param = <0x4100c344>;
361 entry-latency-us = <2800>;
362 exit-latency-us = <4400>;
363 min-residency-us = <10150>;
370 compatible = "qcom,scm-sm8650", "qcom,scm";
371 qcom,dload-mode = <&tcsr 0x19000>;
377 clk_virt: interconnect-0 {
378 compatible = "qcom,sm8650-clk-virt";
379 #interconnect-cells = <2>;
380 qcom,bcm-voters = <&apps_bcm_voter>;
383 mc_virt: interconnect-1 {
384 compatible = "qcom,sm8650-mc-virt";
385 #interconnect-cells = <2>;
386 qcom,bcm-voters = <&apps_bcm_voter>;
395 pmu-a520 {
396 compatible = "arm,cortex-a520-pmu";
400 pmu-a720 {
401 compatible = "arm,cortex-a720-pmu";
405 pmu-x4 {
406 compatible = "arm,cortex-x4-pmu";
411 compatible = "arm,psci-1.0";
414 cpu_pd0: power-domain-cpu0 {
415 #power-domain-cells = <0>;
416 power-domains = <&cluster_pd>;
417 domain-idle-states = <&silver_cpu_sleep_0>;
420 cpu_pd1: power-domain-cpu1 {
421 #power-domain-cells = <0>;
422 power-domains = <&cluster_pd>;
423 domain-idle-states = <&silver_cpu_sleep_0>;
426 cpu_pd2: power-domain-cpu2 {
427 #power-domain-cells = <0>;
428 power-domains = <&cluster_pd>;
429 domain-idle-states = <&silver_cpu_sleep_0>;
432 cpu_pd3: power-domain-cpu3 {
433 #power-domain-cells = <0>;
434 power-domains = <&cluster_pd>;
435 domain-idle-states = <&gold_cpu_sleep_0>;
438 cpu_pd4: power-domain-cpu4 {
439 #power-domain-cells = <0>;
440 power-domains = <&cluster_pd>;
441 domain-idle-states = <&gold_cpu_sleep_0>;
444 cpu_pd5: power-domain-cpu5 {
445 #power-domain-cells = <0>;
446 power-domains = <&cluster_pd>;
447 domain-idle-states = <&gold_cpu_sleep_0>;
450 cpu_pd6: power-domain-cpu6 {
451 #power-domain-cells = <0>;
452 power-domains = <&cluster_pd>;
453 domain-idle-states = <&gold_cpu_sleep_0>;
456 cpu_pd7: power-domain-cpu7 {
457 #power-domain-cells = <0>;
458 power-domains = <&cluster_pd>;
459 domain-idle-states = <&gold_plus_cpu_sleep_0>;
462 cluster_pd: power-domain-cluster {
463 #power-domain-cells = <0>;
464 domain-idle-states = <&cluster_sleep_0>,
469 reserved_memory: reserved-memory {
470 #address-cells = <2>;
471 #size-cells = <2>;
476 no-map;
479 cpusys_vm_mem: cpusys-vm@80e00000 {
481 no-map;
485 xbl_dt_log_merged_mem: xbl-dt-log-merged@81a00000 {
487 no-map;
490 aop_cmd_db_mem: aop-cmd-db@81c60000 {
491 compatible = "qcom,cmd-db";
493 no-map;
497 aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 {
499 no-map;
508 no-map;
511 adsp_mhi_mem: adsp-mhi@81f00000 {
513 no-map;
518 no-map;
521 global_sync_mem: global-sync@82600000 {
523 no-map;
526 tz_stat_mem: tz-stat@82700000 {
528 no-map;
533 no-map;
536 qlink_logging_mem: qlink-logging@84800000 {
538 no-map;
541 mpss_dsm_mem: mpss-dsm@86b00000 {
543 no-map;
546 mpss_dsm_mem_2: mpss-dsm-2@8b400000 {
548 no-map;
553 no-map;
556 q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 {
558 no-map;
561 ipa_fw_mem: ipa-fw@9b080000 {
563 no-map;
566 ipa_gsi_mem: ipa-gsi@9b090000 {
568 no-map;
571 gpu_micro_code_mem: gpu-micro-code@9b09a000 {
573 no-map;
578 no-map;
582 spu_tz_shared_mem: spu-tz-shared@9b280000 {
584 no-map;
588 spu_modem_shared_mem: spu-modem-shared@9b2e0000 {
590 no-map;
595 no-map;
600 no-map;
605 no-map;
610 no-map;
613 q6_cdsp_dtb_mem: q6-cdsp-dtb@9de00000 {
615 no-map;
618 q6_adsp_dtb_mem: q6-adsp-dtb@9de80000 {
620 no-map;
625 no-map;
629 compatible = "qcom,rmtfs-mem";
631 no-map;
633 qcom,client-id = <1>;
638 tz_merged_mem: tz-merged@d8000000 {
640 no-map;
643 hwfence_shbuf: hwfence-shbuf@e6440000 {
645 no-map;
648 trust_ui_vm_mem: trust-ui-vm@f3800000 {
650 no-map;
653 oem_vm_mem: oem-vm@f7c00000 {
655 no-map;
658 llcc_lpi_mem: llcc-lpi@ff800000 {
660 no-map;
664 smp2p-adsp {
667 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
675 qcom,local-pid = <0>;
676 qcom,remote-pid = <2>;
678 smp2p_adsp_out: master-kernel {
679 qcom,entry-name = "master-kernel";
680 #qcom,smem-state-cells = <1>;
683 smp2p_adsp_in: slave-kernel {
684 qcom,entry-name = "slave-kernel";
685 interrupt-controller;
686 #interrupt-cells = <2>;
690 smp2p-cdsp {
693 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
701 qcom,local-pid = <0>;
702 qcom,remote-pid = <5>;
704 smp2p_cdsp_out: master-kernel {
705 qcom,entry-name = "master-kernel";
706 #qcom,smem-state-cells = <1>;
709 smp2p_cdsp_in: slave-kernel {
710 qcom,entry-name = "slave-kernel";
711 interrupt-controller;
712 #interrupt-cells = <2>;
716 smp2p-modem {
719 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
727 qcom,local-pid = <0>;
728 qcom,remote-pid = <1>;
730 smp2p_modem_out: master-kernel {
731 qcom,entry-name = "master-kernel";
732 #qcom,smem-state-cells = <1>;
735 smp2p_modem_in: slave-kernel {
736 qcom,entry-name = "slave-kernel";
737 interrupt-controller;
738 #interrupt-cells = <2>;
741 ipa_smp2p_out: ipa-ap-to-modem {
742 qcom,entry-name = "ipa";
743 #qcom,smem-state-cells = <1>;
746 ipa_smp2p_in: ipa-modem-to-ap {
747 qcom,entry-name = "ipa";
748 interrupt-controller;
749 #interrupt-cells = <2>;
754 compatible = "simple-bus";
756 #address-cells = <2>;
757 #size-cells = <2>;
758 dma-ranges = <0 0 0 0 0x10 0>;
761 gcc: clock-controller@100000 {
762 compatible = "qcom,sm8650-gcc";
776 #clock-cells = <1>;
777 #reset-cells = <1>;
778 #power-domain-cells = <1>;
782 compatible = "qcom,sm8650-ipcc", "qcom,ipcc";
786 interrupt-controller;
787 #interrupt-cells = <3>;
789 #mbox-cells = <2>;
792 gpi_dma2: dma-controller@800000 {
793 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma";
809 dma-channels = <12>;
810 dma-channel-mask = <0x3f>;
811 #dma-cells = <3>;
815 dma-coherent;
821 compatible = "qcom,geni-se-qup";
826 clock-names = "m-ahb",
827 "s-ahb";
831 dma-coherent;
833 #address-cells = <2>;
834 #size-cells = <2>;
840 compatible = "qcom,geni-i2c";
846 clock-names = "se";
854 interconnect-names = "qup-core",
855 "qup-config",
856 "qup-memory";
860 dma-names = "tx",
863 pinctrl-0 = <&qup_i2c8_data_clk>;
864 pinctrl-names = "default";
866 #address-cells = <1>;
867 #size-cells = <0>;
873 compatible = "qcom,geni-spi";
879 clock-names = "se";
887 interconnect-names = "qup-core",
888 "qup-config",
889 "qup-memory";
893 dma-names = "tx",
896 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
897 pinctrl-names = "default";
899 #address-cells = <1>;
900 #size-cells = <0>;
906 compatible = "qcom,geni-i2c";
912 clock-names = "se";
920 interconnect-names = "qup-core",
921 "qup-config",
922 "qup-memory";
926 dma-names = "tx",
929 pinctrl-0 = <&qup_i2c9_data_clk>;
930 pinctrl-names = "default";
932 #address-cells = <1>;
933 #size-cells = <0>;
939 compatible = "qcom,geni-spi";
945 clock-names = "se";
953 interconnect-names = "qup-core",
954 "qup-config",
955 "qup-memory";
959 dma-names = "tx",
962 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
963 pinctrl-names = "default";
965 #address-cells = <1>;
966 #size-cells = <0>;
972 compatible = "qcom,geni-i2c";
978 clock-names = "se";
986 interconnect-names = "qup-core",
987 "qup-config",
988 "qup-memory";
992 dma-names = "tx",
995 pinctrl-0 = <&qup_i2c10_data_clk>;
996 pinctrl-names = "default";
998 #address-cells = <1>;
999 #size-cells = <0>;
1005 compatible = "qcom,geni-spi";
1011 clock-names = "se";
1019 interconnect-names = "qup-core",
1020 "qup-config",
1021 "qup-memory";
1025 dma-names = "tx",
1028 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1029 pinctrl-names = "default";
1031 #address-cells = <1>;
1032 #size-cells = <0>;
1038 compatible = "qcom,geni-i2c";
1044 clock-names = "se";
1052 interconnect-names = "qup-core",
1053 "qup-config",
1054 "qup-memory";
1058 dma-names = "tx",
1061 pinctrl-0 = <&qup_i2c11_data_clk>;
1062 pinctrl-names = "default";
1064 #address-cells = <1>;
1065 #size-cells = <0>;
1071 compatible = "qcom,geni-spi";
1077 clock-names = "se";
1085 interconnect-names = "qup-core",
1086 "qup-config",
1087 "qup-memory";
1091 dma-names = "tx",
1094 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1095 pinctrl-names = "default";
1097 #address-cells = <1>;
1098 #size-cells = <0>;
1104 compatible = "qcom,geni-i2c";
1110 clock-names = "se";
1118 interconnect-names = "qup-core",
1119 "qup-config",
1120 "qup-memory";
1124 dma-names = "tx",
1127 pinctrl-0 = <&qup_i2c12_data_clk>;
1128 pinctrl-names = "default";
1130 #address-cells = <1>;
1131 #size-cells = <0>;
1137 compatible = "qcom,geni-spi";
1143 clock-names = "se";
1151 interconnect-names = "qup-core",
1152 "qup-config",
1153 "qup-memory";
1157 dma-names = "tx",
1160 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1161 pinctrl-names = "default";
1163 #address-cells = <1>;
1164 #size-cells = <0>;
1170 compatible = "qcom,geni-i2c";
1176 clock-names = "se";
1184 interconnect-names = "qup-core",
1185 "qup-config",
1186 "qup-memory";
1190 dma-names = "tx",
1193 pinctrl-0 = <&qup_i2c13_data_clk>;
1194 pinctrl-names = "default";
1196 #address-cells = <1>;
1197 #size-cells = <0>;
1203 compatible = "qcom,geni-spi";
1209 clock-names = "se";
1217 interconnect-names = "qup-core",
1218 "qup-config",
1219 "qup-memory";
1223 dma-names = "tx",
1226 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1227 pinctrl-names = "default";
1229 #address-cells = <1>;
1230 #size-cells = <0>;
1236 compatible = "qcom,geni-uart";
1242 clock-names = "se";
1248 interconnect-names = "qup-core",
1249 "qup-config";
1251 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
1252 pinctrl-names = "default";
1258 compatible = "qcom,geni-debug-uart";
1264 clock-names = "se";
1270 interconnect-names = "qup-core",
1271 "qup-config";
1273 pinctrl-0 = <&qup_uart15_default>;
1274 pinctrl-names = "default";
1281 compatible = "qcom,geni-se-i2c-master-hub";
1285 clock-names = "s-ahb";
1287 #address-cells = <2>;
1288 #size-cells = <2>;
1294 compatible = "qcom,geni-i2c-master-hub";
1301 clock-names = "se",
1308 interconnect-names = "qup-core",
1309 "qup-config";
1311 pinctrl-0 = <&hub_i2c0_data_clk>;
1312 pinctrl-names = "default";
1314 #address-cells = <1>;
1315 #size-cells = <0>;
1321 compatible = "qcom,geni-i2c-master-hub";
1328 clock-names = "se",
1335 interconnect-names = "qup-core",
1336 "qup-config";
1338 pinctrl-0 = <&hub_i2c1_data_clk>;
1339 pinctrl-names = "default";
1341 #address-cells = <1>;
1342 #size-cells = <0>;
1348 compatible = "qcom,geni-i2c-master-hub";
1355 clock-names = "se",
1362 interconnect-names = "qup-core",
1363 "qup-config";
1365 pinctrl-0 = <&hub_i2c2_data_clk>;
1366 pinctrl-names = "default";
1368 #address-cells = <1>;
1369 #size-cells = <0>;
1375 compatible = "qcom,geni-i2c-master-hub";
1382 clock-names = "se",
1389 interconnect-names = "qup-core",
1390 "qup-config";
1392 pinctrl-0 = <&hub_i2c3_data_clk>;
1393 pinctrl-names = "default";
1395 #address-cells = <1>;
1396 #size-cells = <0>;
1402 compatible = "qcom,geni-i2c-master-hub";
1409 clock-names = "se",
1416 interconnect-names = "qup-core",
1417 "qup-config";
1419 pinctrl-0 = <&hub_i2c4_data_clk>;
1420 pinctrl-names = "default";
1422 #address-cells = <1>;
1423 #size-cells = <0>;
1429 compatible = "qcom,geni-i2c-master-hub";
1436 clock-names = "se",
1443 interconnect-names = "qup-core",
1444 "qup-config";
1446 pinctrl-0 = <&hub_i2c5_data_clk>;
1447 pinctrl-names = "default";
1449 #address-cells = <1>;
1450 #size-cells = <0>;
1456 compatible = "qcom,geni-i2c-master-hub";
1463 clock-names = "se",
1470 interconnect-names = "qup-core",
1471 "qup-config";
1473 pinctrl-0 = <&hub_i2c6_data_clk>;
1474 pinctrl-names = "default";
1476 #address-cells = <1>;
1477 #size-cells = <0>;
1483 compatible = "qcom,geni-i2c-master-hub";
1490 clock-names = "se",
1497 interconnect-names = "qup-core",
1498 "qup-config";
1500 pinctrl-0 = <&hub_i2c7_data_clk>;
1501 pinctrl-names = "default";
1503 #address-cells = <1>;
1504 #size-cells = <0>;
1510 compatible = "qcom,geni-i2c-master-hub";
1517 clock-names = "se",
1524 interconnect-names = "qup-core",
1525 "qup-config";
1527 pinctrl-0 = <&hub_i2c8_data_clk>;
1528 pinctrl-names = "default";
1530 #address-cells = <1>;
1531 #size-cells = <0>;
1537 compatible = "qcom,geni-i2c-master-hub";
1544 clock-names = "se",
1551 interconnect-names = "qup-core",
1552 "qup-config";
1554 pinctrl-0 = <&hub_i2c9_data_clk>;
1555 pinctrl-names = "default";
1557 #address-cells = <1>;
1558 #size-cells = <0>;
1564 gpi_dma1: dma-controller@a00000 {
1565 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma";
1581 dma-channels = <12>;
1582 dma-channel-mask = <0xc>;
1583 #dma-cells = <3>;
1586 dma-coherent;
1592 compatible = "qcom,geni-se-qup";
1597 clock-names = "m-ahb",
1598 "s-ahb";
1602 interconnect-names = "qup-core";
1606 dma-coherent;
1608 #address-cells = <2>;
1609 #size-cells = <2>;
1615 compatible = "qcom,geni-i2c";
1621 clock-names = "se";
1629 interconnect-names = "qup-core",
1630 "qup-config",
1631 "qup-memory";
1635 dma-names = "tx",
1638 pinctrl-0 = <&qup_i2c0_data_clk>;
1639 pinctrl-names = "default";
1641 #address-cells = <1>;
1642 #size-cells = <0>;
1648 compatible = "qcom,geni-spi";
1654 clock-names = "se";
1662 interconnect-names = "qup-core",
1663 "qup-config",
1664 "qup-memory";
1668 dma-names = "tx",
1671 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1672 pinctrl-names = "default";
1674 #address-cells = <1>;
1675 #size-cells = <0>;
1681 compatible = "qcom,geni-i2c";
1687 clock-names = "se";
1695 interconnect-names = "qup-core",
1696 "qup-config",
1697 "qup-memory";
1701 dma-names = "tx",
1704 pinctrl-0 = <&qup_i2c1_data_clk>;
1705 pinctrl-names = "default";
1707 #address-cells = <1>;
1708 #size-cells = <0>;
1714 compatible = "qcom,geni-spi";
1720 clock-names = "se";
1728 interconnect-names = "qup-core",
1729 "qup-config",
1730 "qup-memory";
1734 dma-names = "tx",
1737 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1738 pinctrl-names = "default";
1740 #address-cells = <1>;
1741 #size-cells = <0>;
1747 compatible = "qcom,geni-i2c";
1753 clock-names = "se";
1761 interconnect-names = "qup-core",
1762 "qup-config",
1763 "qup-memory";
1767 dma-names = "tx",
1770 pinctrl-0 = <&qup_i2c2_data_clk>;
1771 pinctrl-names = "default";
1773 #address-cells = <1>;
1774 #size-cells = <0>;
1780 compatible = "qcom,geni-spi";
1786 clock-names = "se";
1794 interconnect-names = "qup-core",
1795 "qup-config",
1796 "qup-memory";
1800 dma-names = "tx",
1803 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1804 pinctrl-names = "default";
1806 #address-cells = <1>;
1807 #size-cells = <0>;
1813 compatible = "qcom,geni-i2c";
1819 clock-names = "se";
1827 interconnect-names = "qup-core",
1828 "qup-config",
1829 "qup-memory";
1833 dma-names = "tx",
1836 pinctrl-0 = <&qup_i2c3_data_clk>;
1837 pinctrl-names = "default";
1839 #address-cells = <1>;
1840 #size-cells = <0>;
1846 compatible = "qcom,geni-spi";
1852 clock-names = "se";
1860 interconnect-names = "qup-core",
1861 "qup-config",
1862 "qup-memory";
1866 dma-names = "tx",
1869 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1870 pinctrl-names = "default";
1872 #address-cells = <1>;
1873 #size-cells = <0>;
1879 compatible = "qcom,geni-i2c";
1885 clock-names = "se";
1893 interconnect-names = "qup-core",
1894 "qup-config",
1895 "qup-memory";
1899 dma-names = "tx",
1902 pinctrl-0 = <&qup_i2c4_data_clk>;
1903 pinctrl-names = "default";
1905 #address-cells = <1>;
1906 #size-cells = <0>;
1912 compatible = "qcom,geni-spi";
1918 clock-names = "se";
1926 interconnect-names = "qup-core",
1927 "qup-config",
1928 "qup-memory";
1932 dma-names = "tx",
1935 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1936 pinctrl-names = "default";
1938 #address-cells = <1>;
1939 #size-cells = <0>;
1945 compatible = "qcom,geni-i2c";
1951 clock-names = "se";
1959 interconnect-names = "qup-core",
1960 "qup-config",
1961 "qup-memory";
1965 dma-names = "tx",
1968 pinctrl-0 = <&qup_i2c5_data_clk>;
1969 pinctrl-names = "default";
1971 #address-cells = <1>;
1972 #size-cells = <0>;
1978 compatible = "qcom,geni-spi";
1984 clock-names = "se";
1992 interconnect-names = "qup-core",
1993 "qup-config",
1994 "qup-memory";
1998 dma-names = "tx",
2001 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
2002 pinctrl-names = "default";
2004 #address-cells = <1>;
2005 #size-cells = <0>;
2011 compatible = "qcom,geni-i2c";
2017 clock-names = "se";
2025 interconnect-names = "qup-core",
2026 "qup-config",
2027 "qup-memory";
2031 dma-names = "tx",
2034 pinctrl-0 = <&qup_i2c6_data_clk>;
2035 pinctrl-names = "default";
2037 #address-cells = <1>;
2038 #size-cells = <0>;
2044 compatible = "qcom,geni-spi";
2050 clock-names = "se";
2058 interconnect-names = "qup-core",
2059 "qup-config",
2060 "qup-memory";
2064 dma-names = "tx",
2067 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
2068 pinctrl-names = "default";
2070 #address-cells = <1>;
2071 #size-cells = <0>;
2077 compatible = "qcom,geni-i2c";
2083 clock-names = "se";
2091 interconnect-names = "qup-core",
2092 "qup-config",
2093 "qup-memory";
2097 dma-names = "tx",
2100 pinctrl-0 = <&qup_i2c7_data_clk>;
2101 pinctrl-names = "default";
2103 #address-cells = <1>;
2104 #size-cells = <0>;
2110 compatible = "qcom,geni-spi";
2116 clock-names = "se";
2124 interconnect-names = "qup-core",
2125 "qup-config",
2126 "qup-memory";
2130 dma-names = "tx",
2133 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
2134 pinctrl-names = "default";
2136 #address-cells = <1>;
2137 #size-cells = <0>;
2144 compatible = "qcom,sm8650-cnoc-main";
2147 qcom,bcm-voters = <&apps_bcm_voter>;
2149 #interconnect-cells = <2>;
2153 compatible = "qcom,sm8650-config-noc";
2156 qcom,bcm-voters = <&apps_bcm_voter>;
2158 #interconnect-cells = <2>;
2162 compatible = "qcom,sm8650-system-noc";
2165 qcom,bcm-voters = <&apps_bcm_voter>;
2167 #interconnect-cells = <2>;
2171 compatible = "qcom,sm8650-pcie-anoc";
2177 qcom,bcm-voters = <&apps_bcm_voter>;
2179 #interconnect-cells = <2>;
2183 compatible = "qcom,sm8650-aggre1-noc";
2189 qcom,bcm-voters = <&apps_bcm_voter>;
2191 #interconnect-cells = <2>;
2195 compatible = "qcom,sm8650-aggre2-noc";
2200 qcom,bcm-voters = <&apps_bcm_voter>;
2202 #interconnect-cells = <2>;
2206 compatible = "qcom,sm8650-mmss-noc";
2209 qcom,bcm-voters = <&apps_bcm_voter>;
2211 #interconnect-cells = <2>;
2215 compatible = "qcom,sm8650-trng", "qcom,trng";
2221 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550";
2227 reg-names = "parf", "dbi", "elbi", "atu", "config";
2237 interrupt-names = "msi0",
2254 clock-names = "aux",
2264 reset-names = "pci";
2270 interconnect-names = "pcie-mem",
2271 "cpu-pcie";
2273 power-domains = <&gcc PCIE_0_GDSC>;
2275 iommu-map = <0 &apps_smmu 0x1400 0x1>,
2278 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
2282 interrupt-map-mask = <0 0 0 0x7>;
2283 #interrupt-cells = <1>;
2285 msi-map = <0x0 &gic_its 0x1400 0x1>,
2287 msi-map-mask = <0xff00>;
2289 linux,pci-domain = <0>;
2290 num-lanes = <2>;
2291 bus-range = <0 0xff>;
2294 phy-names = "pciephy";
2296 #address-cells = <3>;
2297 #size-cells = <2>;
2301 dma-coherent;
2308 bus-range = <0x01 0xff>;
2310 #address-cells = <3>;
2311 #size-cells = <2>;
2317 compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy";
2325 clock-names = "aux",
2331 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
2332 assigned-clock-rates = <100000000>;
2335 reset-names = "phy";
2337 power-domains = <&gcc PCIE_0_PHY_GDSC>;
2339 #clock-cells = <0>;
2340 clock-output-names = "pcie0_pipe_clk";
2342 #phy-cells = <0>;
2349 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550";
2355 reg-names = "parf",
2369 interrupt-names = "msi0",
2386 clock-names = "aux",
2395 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2396 assigned-clock-rates = <19200000>;
2400 reset-names = "pci",
2407 interconnect-names = "pcie-mem",
2408 "cpu-pcie";
2410 power-domains = <&gcc PCIE_1_GDSC>;
2412 iommu-map = <0 &apps_smmu 0x1480 0x1>,
2415 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2419 interrupt-map-mask = <0 0 0 0x7>;
2420 #interrupt-cells = <1>;
2422 msi-map = <0x0 &gic_its 0x1480 0x1>,
2424 msi-map-mask = <0xff00>;
2426 linux,pci-domain = <1>;
2427 num-lanes = <2>;
2428 bus-range = <0 0xff>;
2431 phy-names = "pciephy";
2433 dma-coherent;
2435 #address-cells = <3>;
2436 #size-cells = <2>;
2445 bus-range = <0x01 0xff>;
2447 #address-cells = <3>;
2448 #size-cells = <2>;
2454 compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy";
2462 clock-names = "aux",
2468 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2469 assigned-clock-rates = <100000000>;
2473 reset-names = "phy",
2476 power-domains = <&gcc PCIE_1_PHY_GDSC>;
2478 #clock-cells = <1>;
2479 clock-output-names = "pcie1_pipe_clk";
2481 #phy-cells = <0>;
2486 cryptobam: dma-controller@1dc4000 {
2487 compatible = "qcom,bam-v1.7.0";
2492 #dma-cells = <1>;
2498 qcom,controlled-remotely;
2502 compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce";
2507 interconnect-names = "memory";
2510 dma-names = "rx", "tx";
2517 compatible = "qcom,sm8650-qmp-ufs-phy";
2523 clock-names = "ref",
2528 reset-names = "ufsphy";
2530 power-domains = <&gcc UFS_MEM_PHY_GDSC>;
2532 #clock-cells = <1>;
2533 #phy-cells = <0>;
2539 compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
2552 clock-names = "core_clk",
2560 freq-table-hz = <100000000 403000000>,
2570 reset-names = "rst";
2576 interconnect-names = "ufs-ddr",
2577 "cpu-ufs";
2579 power-domains = <&gcc UFS_PHY_GDSC>;
2580 required-opps = <&rpmhpd_opp_nom>;
2584 lanes-per-direction = <2>;
2588 phy-names = "ufsphy";
2590 #reset-cells = <1>;
2596 compatible = "qcom,sm8650-inline-crypto-engine",
2597 "qcom,inline-crypto-engine";
2604 compatible = "qcom,tcsr-mutex";
2607 #hwlock-cells = <1>;
2610 tcsr: clock-controller@1fc0000 {
2611 compatible = "qcom,sm8650-tcsr", "syscon";
2616 #clock-cells = <1>;
2617 #reset-cells = <1>;
2621 compatible = "qcom,adreno-43051401", "qcom,adreno";
2625 reg-names = "kgsl_3d0_reg_memory",
2634 operating-points-v2 = <&gpu_opp_table>;
2637 #cooling-cells = <2>;
2641 zap-shader {
2642 memory-region = <&gpu_micro_code_mem>;
2646 gpu_opp_table: opp-table {
2647 compatible = "operating-points-v2";
2649 opp-231000000 {
2650 opp-hz = /bits/ 64 <231000000>;
2651 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
2654 opp-310000000 {
2655 opp-hz = /bits/ 64 <310000000>;
2656 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2659 opp-366000000 {
2660 opp-hz = /bits/ 64 <366000000>;
2661 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
2664 opp-422000000 {
2665 opp-hz = /bits/ 64 <422000000>;
2666 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2669 opp-500000000 {
2670 opp-hz = /bits/ 64 <500000000>;
2671 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
2674 opp-578000000 {
2675 opp-hz = /bits/ 64 <578000000>;
2676 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2679 opp-629000000 {
2680 opp-hz = /bits/ 64 <629000000>;
2681 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2684 opp-680000000 {
2685 opp-hz = /bits/ 64 <680000000>;
2686 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2689 opp-720000000 {
2690 opp-hz = /bits/ 64 <720000000>;
2691 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2694 opp-770000000 {
2695 opp-hz = /bits/ 64 <770000000>;
2696 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2699 opp-834000000 {
2700 opp-hz = /bits/ 64 <834000000>;
2701 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2707 compatible = "qcom,adreno-gmu-750.1", "qcom,adreno-gmu";
2711 reg-names = "gmu", "rscc", "gmu_pdc";
2715 interrupt-names = "hfi", "gmu";
2724 clock-names = "ahb",
2732 power-domains = <&gpucc GPU_CX_GDSC>,
2734 power-domain-names = "cx",
2741 operating-points-v2 = <&gmu_opp_table>;
2743 gmu_opp_table: opp-table {
2744 compatible = "operating-points-v2";
2746 opp-260000000 {
2747 opp-hz = /bits/ 64 <260000000>;
2748 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2751 opp-625000000 {
2752 opp-hz = /bits/ 64 <625000000>;
2753 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2758 gpucc: clock-controller@3d90000 {
2759 compatible = "qcom,sm8650-gpucc";
2766 #clock-cells = <1>;
2767 #reset-cells = <1>;
2768 #power-domain-cells = <1>;
2772 compatible = "qcom,sm8650-smmu-500", "qcom,adreno-smmu",
2773 "qcom,smmu-500", "arm,mmu-500";
2775 #iommu-cells = <2>;
2776 #global-interrupts = <1>;
2807 clock-names = "hlos",
2811 power-domains = <&gpucc GPU_CX_GDSC>;
2812 dma-coherent;
2816 compatible = "qcom,sm8650-ipa", "qcom,sm8550-ipa";
2823 reg-names = "ipa-reg",
2824 "ipa-shared",
2827 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
2831 interrupt-names = "ipa",
2833 "ipa-clock-query",
2834 "ipa-setup-ready";
2837 clock-names = "core";
2841 interconnect-names = "memory",
2846 qcom,smem-states = <&ipa_smp2p_out 0>,
2848 qcom,smem-state-names = "ipa-clock-enabled-valid",
2849 "ipa-clock-enabled";
2855 compatible = "qcom,sm8650-mpss-pas";
2858 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2864 interrupt-names = "wdog",
2868 "stop-ack",
2869 "shutdown-ack";
2872 clock-names = "xo";
2877 power-domains = <&rpmhpd RPMHPD_CX>,
2879 power-domain-names = "cx",
2882 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>,
2888 qcom,smem-states = <&smp2p_modem_out 0>;
2889 qcom,smem-state-names = "stop";
2893 glink-edge {
2894 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2901 qcom,remote-pid = <1>;
2908 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
2914 clock-names = "mclk",
2919 #clock-cells = <0>;
2920 clock-output-names = "wsa2-mclk";
2921 #sound-dai-cells = <1>;
2925 compatible = "qcom,soundwire-v2.0.0";
2929 clock-names = "iface";
2932 pinctrl-0 = <&wsa2_swr_active>;
2933 pinctrl-names = "default";
2935 qcom,din-ports = <4>;
2936 qcom,dout-ports = <9>;
2938 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
2939 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2940 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2941 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2942 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2943 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
2944 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
2945 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2946 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2948 #address-cells = <2>;
2949 #size-cells = <0>;
2950 #sound-dai-cells = <1>;
2955 compatible = "qcom,sm8650-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro";
2961 clock-names = "mclk",
2966 #clock-cells = <0>;
2967 clock-output-names = "mclk";
2968 #sound-dai-cells = <1>;
2972 compatible = "qcom,soundwire-v2.0.0";
2976 clock-names = "iface";
2979 pinctrl-0 = <&rx_swr_active>;
2980 pinctrl-names = "default";
2982 qcom,din-ports = <0>;
2983 qcom,dout-ports = <11>;
2985 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x03 0xff 0xff 0x31 0xff 0xff 0xff>;
2986 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x09 0x01 0xff 0xff 0x00 0xff 0xff 0xff>;
2987 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>;
2988 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0xff 0xff 0x00 0xff 0xff 0xff>;
2989 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0xff 0xff 0x0f 0xff 0xff 0xff>;
2990 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0x18 0xff 0xff 0xff>;
2991 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff 0xff 0x01 0xff 0xff 0xff>;
2992 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0x01 0x03 0xff 0xff 0x00 0xff 0xff 0xff>;
2993 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0xff 0xff 0xff>;
2995 #address-cells = <2>;
2996 #size-cells = <0>;
2997 #sound-dai-cells = <1>;
3002 compatible = "qcom,sm8650-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro";
3008 clock-names = "mclk",
3013 #clock-cells = <0>;
3014 clock-output-names = "mclk";
3015 #sound-dai-cells = <1>;
3019 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
3025 clock-names = "mclk",
3030 #clock-cells = <0>;
3031 clock-output-names = "mclk";
3032 #sound-dai-cells = <1>;
3036 compatible = "qcom,soundwire-v2.0.0";
3040 clock-names = "iface";
3043 pinctrl-0 = <&wsa_swr_active>;
3044 pinctrl-names = "default";
3046 qcom,din-ports = <4>;
3047 qcom,dout-ports = <9>;
3049 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
3050 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
3051 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3052 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3053 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3054 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
3055 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
3056 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
3057 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
3059 #address-cells = <2>;
3060 #size-cells = <0>;
3061 #sound-dai-cells = <1>;
3066 compatible = "qcom,soundwire-v2.0.0";
3070 interrupt-names = "core", "wakeup";
3072 clock-names = "iface";
3075 pinctrl-0 = <&tx_swr_active>;
3076 pinctrl-names = "default";
3078 qcom,din-ports = <4>;
3079 qcom,dout-ports = <0>;
3081 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
3082 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
3083 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
3084 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
3085 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
3086 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
3087 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
3088 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
3089 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
3091 #address-cells = <2>;
3092 #size-cells = <0>;
3093 #sound-dai-cells = <1>;
3098 compatible = "qcom,sm8650-lpass-va-macro", "qcom,sm8550-lpass-va-macro";
3103 clock-names = "mclk",
3107 #clock-cells = <0>;
3108 clock-output-names = "fsgen";
3109 #sound-dai-cells = <1>;
3113 compatible = "qcom,sm8650-lpass-lpi-pinctrl";
3118 clock-names = "core", "audio";
3120 gpio-controller;
3121 #gpio-cells = <2>;
3122 gpio-ranges = <&lpass_tlmm 0 0 23>;
3124 tx_swr_active: tx-swr-active-state {
3125 clk-pins {
3126 pins = "gpio0";
3128 drive-strength = <2>;
3129 slew-rate = <1>;
3130 bias-disable;
3133 data-pins {
3134 pins = "gpio1", "gpio2", "gpio14";
3136 drive-strength = <2>;
3137 slew-rate = <1>;
3138 bias-bus-hold;
3142 rx_swr_active: rx-swr-active-state {
3143 clk-pins {
3144 pins = "gpio3";
3146 drive-strength = <2>;
3147 slew-rate = <1>;
3148 bias-disable;
3151 data-pins {
3152 pins = "gpio4", "gpio5";
3154 drive-strength = <2>;
3155 slew-rate = <1>;
3156 bias-bus-hold;
3160 dmic01_default: dmic01-default-state {
3161 clk-pins {
3162 pins = "gpio6";
3164 drive-strength = <8>;
3165 output-high;
3168 data-pins {
3169 pins = "gpio7";
3171 drive-strength = <8>;
3172 input-enable;
3176 dmic23_default: dmic23-default-state {
3177 clk-pins {
3178 pins = "gpio8";
3180 drive-strength = <8>;
3181 output-high;
3184 data-pins {
3185 pins = "gpio9";
3187 drive-strength = <8>;
3188 input-enable;
3192 wsa_swr_active: wsa-swr-active-state {
3193 clk-pins {
3194 pins = "gpio10";
3196 drive-strength = <2>;
3197 slew-rate = <1>;
3198 bias-disable;
3201 data-pins {
3202 pins = "gpio11";
3204 drive-strength = <2>;
3205 slew-rate = <1>;
3206 bias-bus-hold;
3210 wsa2_swr_active: wsa2-swr-active-state {
3211 clk-pins {
3212 pins = "gpio15";
3214 drive-strength = <2>;
3215 slew-rate = <1>;
3216 bias-disable;
3219 data-pins {
3220 pins = "gpio16";
3222 drive-strength = <2>;
3223 slew-rate = <1>;
3224 bias-bus-hold;
3230 compatible = "qcom,sm8650-lpass-lpiaon-noc";
3233 #interconnect-cells = <2>;
3235 qcom,bcm-voters = <&apps_bcm_voter>;
3239 compatible = "qcom,sm8650-lpass-lpicx-noc";
3242 #interconnect-cells = <2>;
3244 qcom,bcm-voters = <&apps_bcm_voter>;
3248 compatible = "qcom,sm8650-lpass-ag-noc";
3251 #interconnect-cells = <2>;
3253 qcom,bcm-voters = <&apps_bcm_voter>;
3257 compatible = "qcom,sm8650-sdhci", "qcom,sdhci-msm-v5";
3262 interrupt-names = "hc_irq",
3268 clock-names = "iface",
3276 interconnect-names = "sdhc-ddr",
3277 "cpu-sdhc";
3279 power-domains = <&rpmhpd RPMHPD_CX>;
3280 operating-points-v2 = <&sdhc2_opp_table>;
3284 bus-width = <4>;
3286 /* Forbid SDR104/SDR50 - broken hw! */
3287 sdhci-caps-mask = <0x3 0>;
3289 qcom,dll-config = <0x0007642c>;
3290 qcom,ddr-config = <0x80040868>;
3292 dma-coherent;
3296 sdhc2_opp_table: opp-table {
3297 compatible = "operating-points-v2";
3299 opp-19200000 {
3300 opp-hz = /bits/ 64 <19200000>;
3301 required-opps = <&rpmhpd_opp_min_svs>;
3304 opp-50000000 {
3305 opp-hz = /bits/ 64 <50000000>;
3306 required-opps = <&rpmhpd_opp_low_svs>;
3309 opp-100000000 {
3310 opp-hz = /bits/ 64 <100000000>;
3311 required-opps = <&rpmhpd_opp_svs>;
3314 opp-202000000 {
3315 opp-hz = /bits/ 64 <202000000>;
3316 required-opps = <&rpmhpd_opp_svs_l1>;
3321 videocc: clock-controller@aaf0000 {
3322 compatible = "qcom,sm8650-videocc";
3326 power-domains = <&rpmhpd RPMHPD_MMCX>;
3327 #clock-cells = <1>;
3328 #reset-cells = <1>;
3329 #power-domain-cells = <1>;
3333 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
3336 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
3340 clock-names = "camnoc_axi",
3343 pinctrl-0 = <&cci0_0_default &cci0_1_default>;
3344 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
3345 pinctrl-names = "default", "sleep";
3347 #address-cells = <1>;
3348 #size-cells = <0>;
3350 cci0_i2c0: i2c-bus@0 {
3352 clock-frequency = <1000000>;
3353 #address-cells = <1>;
3354 #size-cells = <0>;
3357 cci0_i2c1: i2c-bus@1 {
3359 clock-frequency = <1000000>;
3360 #address-cells = <1>;
3361 #size-cells = <0>;
3366 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
3369 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
3373 clock-names = "camnoc_axi",
3376 pinctrl-0 = <&cci1_0_default &cci1_1_default>;
3377 pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>;
3378 pinctrl-names = "default", "sleep";
3380 #address-cells = <1>;
3381 #size-cells = <0>;
3383 cci1_i2c0: i2c-bus@0 {
3385 clock-frequency = <1000000>;
3386 #address-cells = <1>;
3387 #size-cells = <0>;
3390 cci1_i2c1: i2c-bus@1 {
3392 clock-frequency = <1000000>;
3393 #address-cells = <1>;
3394 #size-cells = <0>;
3399 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
3402 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
3406 clock-names = "camnoc_axi",
3409 pinctrl-0 = <&cci2_0_default &cci2_1_default>;
3410 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>;
3411 pinctrl-names = "default", "sleep";
3413 #address-cells = <1>;
3414 #size-cells = <0>;
3416 cci2_i2c0: i2c-bus@0 {
3418 clock-frequency = <1000000>;
3419 #address-cells = <1>;
3420 #size-cells = <0>;
3423 cci2_i2c1: i2c-bus@1 {
3425 clock-frequency = <1000000>;
3426 #address-cells = <1>;
3427 #size-cells = <0>;
3431 camcc: clock-controller@ade0000 {
3432 compatible = "qcom,sm8650-camcc";
3438 power-domains = <&rpmhpd RPMHPD_MMCX>;
3439 #clock-cells = <1>;
3440 #reset-cells = <1>;
3441 #power-domain-cells = <1>;
3444 mdss: display-subsystem@ae00000 {
3445 compatible = "qcom,sm8650-mdss";
3447 reg-names = "mdss";
3461 interconnect-names = "mdp0-mem",
3462 "mdp1-mem";
3464 power-domains = <&dispcc MDSS_GDSC>;
3468 interrupt-controller;
3469 #interrupt-cells = <1>;
3471 #address-cells = <2>;
3472 #size-cells = <2>;
3477 mdss_mdp: display-controller@ae01000 {
3478 compatible = "qcom,sm8650-dpu";
3481 reg-names = "mdp",
3484 interrupts-extended = <&mdss 0>;
3491 clock-names = "nrt_bus",
3497 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3498 assigned-clock-rates = <19200000>;
3500 operating-points-v2 = <&mdp_opp_table>;
3502 power-domains = <&rpmhpd RPMHPD_MMCX>;
3505 #address-cells = <1>;
3506 #size-cells = <0>;
3512 remote-endpoint = <&mdss_dsi0_in>;
3520 remote-endpoint = <&mdss_dsi1_in>;
3528 remote-endpoint = <&mdss_dp0_in>;
3533 mdp_opp_table: opp-table {
3534 compatible = "operating-points-v2";
3536 opp-200000000 {
3537 opp-hz = /bits/ 64 <200000000>;
3538 required-opps = <&rpmhpd_opp_low_svs>;
3541 opp-325000000 {
3542 opp-hz = /bits/ 64 <325000000>;
3543 required-opps = <&rpmhpd_opp_svs>;
3546 opp-375000000 {
3547 opp-hz = /bits/ 64 <375000000>;
3548 required-opps = <&rpmhpd_opp_svs_l1>;
3551 opp-514000000 {
3552 opp-hz = /bits/ 64 <514000000>;
3553 required-opps = <&rpmhpd_opp_nom>;
3559 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3561 reg-names = "dsi_ctrl";
3563 interrupts-extended = <&mdss 4>;
3571 clock-names = "byte",
3578 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
3580 assigned-clock-parents = <&mdss_dsi0_phy 0>,
3583 operating-points-v2 = <&mdss_dsi_opp_table>;
3585 power-domains = <&rpmhpd RPMHPD_MMCX>;
3588 phy-names = "dsi";
3590 #address-cells = <1>;
3591 #size-cells = <0>;
3596 #address-cells = <1>;
3597 #size-cells = <0>;
3603 remote-endpoint = <&dpu_intf1_out>;
3615 mdss_dsi_opp_table: opp-table {
3616 compatible = "operating-points-v2";
3618 opp-187500000 {
3619 opp-hz = /bits/ 64 <187500000>;
3620 required-opps = <&rpmhpd_opp_low_svs>;
3623 opp-300000000 {
3624 opp-hz = /bits/ 64 <300000000>;
3625 required-opps = <&rpmhpd_opp_svs>;
3628 opp-358000000 {
3629 opp-hz = /bits/ 64 <358000000>;
3630 required-opps = <&rpmhpd_opp_svs_l1>;
3636 compatible = "qcom,sm8650-dsi-phy-4nm";
3640 reg-names = "dsi_phy",
3646 clock-names = "iface",
3649 #clock-cells = <1>;
3650 #phy-cells = <0>;
3656 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3658 reg-names = "dsi_ctrl";
3660 interrupts-extended = <&mdss 5>;
3668 clock-names = "byte",
3675 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
3677 assigned-clock-parents = <&mdss_dsi1_phy 0>,
3680 operating-points-v2 = <&mdss_dsi_opp_table>;
3682 power-domains = <&rpmhpd RPMHPD_MMCX>;
3685 phy-names = "dsi";
3687 #address-cells = <1>;
3688 #size-cells = <0>;
3693 #address-cells = <1>;
3694 #size-cells = <0>;
3700 remote-endpoint = <&dpu_intf2_out>;
3714 compatible = "qcom,sm8650-dsi-phy-4nm";
3718 reg-names = "dsi_phy",
3724 clock-names = "iface",
3727 #clock-cells = <1>;
3728 #phy-cells = <0>;
3733 mdss_dp0: displayport-controller@af54000 {
3734 compatible = "qcom,sm8650-dp";
3741 interrupts-extended = <&mdss 12>;
3748 clock-names = "core_iface",
3754 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
3756 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3759 operating-points-v2 = <&dp_opp_table>;
3761 power-domains = <&rpmhpd RPMHPD_MMCX>;
3764 phy-names = "dp";
3766 #sound-dai-cells = <0>;
3770 dp_opp_table: opp-table {
3771 compatible = "operating-points-v2";
3773 opp-162000000 {
3774 opp-hz = /bits/ 64 <162000000>;
3775 required-opps = <&rpmhpd_opp_low_svs_d1>;
3778 opp-270000000 {
3779 opp-hz = /bits/ 64 <270000000>;
3780 required-opps = <&rpmhpd_opp_low_svs>;
3783 opp-540000000 {
3784 opp-hz = /bits/ 64 <540000000>;
3785 required-opps = <&rpmhpd_opp_svs_l1>;
3788 opp-810000000 {
3789 opp-hz = /bits/ 64 <810000000>;
3790 required-opps = <&rpmhpd_opp_nom>;
3795 #address-cells = <1>;
3796 #size-cells = <0>;
3802 remote-endpoint = <&dpu_intf0_out>;
3810 remote-endpoint = <&usb_dp_qmpphy_dp_in>;
3817 dispcc: clock-controller@af00000 {
3818 compatible = "qcom,sm8650-dispcc";
3838 power-domains = <&rpmhpd RPMHPD_MMCX>;
3839 required-opps = <&rpmhpd_opp_low_svs>;
3841 #clock-cells = <1>;
3842 #reset-cells = <1>;
3843 #power-domain-cells = <1>;
3847 compatible = "qcom,sm8650-snps-eusb2-phy",
3848 "qcom,sm8550-snps-eusb2-phy";
3852 clock-names = "ref";
3856 #phy-cells = <0>;
3862 compatible = "qcom,sm8650-qmp-usb3-dp-phy";
3869 clock-names = "aux",
3876 reset-names = "phy",
3879 power-domains = <&gcc USB3_PHY_GDSC>;
3881 #clock-cells = <1>;
3882 #phy-cells = <1>;
3884 orientation-switch;
3889 #address-cells = <1>;
3890 #size-cells = <0>;
3903 remote-endpoint = <&usb_1_dwc3_ss>;
3911 remote-endpoint = <&mdss_dp0_out>;
3918 compatible = "qcom,sm8650-dwc3", "qcom,dwc3";
3921 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3926 interrupt-names = "pwr_event",
3938 clock-names = "cfg_noc",
3945 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3947 assigned-clock-rates = <19200000>, <200000000>;
3951 power-domains = <&gcc USB30_PRIM_GDSC>;
3952 required-opps = <&rpmhpd_opp_nom>;
3954 #address-cells = <2>;
3955 #size-cells = <2>;
3970 phy-names = "usb2-phy",
3971 "usb3-phy";
3973 snps,hird-threshold = /bits/ 8 <0x0>;
3974 snps,usb2-gadget-lpm-disable;
3977 snps,dis-u1-entry-quirk;
3978 snps,dis-u2-entry-quirk;
3979 snps,is-utmi-l1-suspend;
3981 snps,usb2-lpm-disable;
3982 snps,has-lpm-erratum;
3983 tx-fifo-resize;
3985 dma-coherent;
3988 #address-cells = <1>;
3989 #size-cells = <0>;
4002 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
4009 pdc: interrupt-controller@b220000 {
4010 compatible = "qcom,sm8650-pdc", "qcom,pdc";
4013 interrupt-parent = <&intc>;
4015 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
4019 #interrupt-cells = <2>;
4020 interrupt-controller;
4023 tsens0: thermal-sensor@c228000 {
4024 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2";
4030 interrupt-names = "uplow",
4035 #thermal-sensor-cells = <1>;
4038 tsens1: thermal-sensor@c229000 {
4039 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2";
4045 interrupt-names = "uplow",
4050 #thermal-sensor-cells = <1>;
4053 tsens2: thermal-sensor@c22a000 {
4054 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2";
4060 interrupt-names = "uplow",
4065 #thermal-sensor-cells = <1>;
4068 aoss_qmp: power-management@c300000 {
4069 compatible = "qcom,sm8650-aoss-qmp", "qcom,aoss-qmp";
4072 interrupt-parent = <&ipcc>;
4073 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
4078 #clock-cells = <0>;
4082 compatible = "qcom,rpmh-stats";
4087 compatible = "qcom,spmi-pmic-arb";
4093 reg-names = "core",
4099 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4100 interrupt-names = "periph_irq";
4104 qcom,bus-id = <0>;
4106 interrupt-controller;
4107 #interrupt-cells = <4>;
4109 #address-cells = <2>;
4110 #size-cells = <0>;
4114 compatible = "qcom,sm8650-tlmm";
4119 gpio-controller;
4120 #gpio-cells = <2>;
4122 interrupt-controller;
4123 #interrupt-cells = <2>;
4125 gpio-ranges = <&tlmm 0 0 211>;
4127 wakeup-parent = <&pdc>;
4129 cci0_0_default: cci0-0-default-state {
4130 sda-pins {
4131 pins = "gpio113";
4133 drive-strength = <2>;
4134 bias-pull-up = <2200>;
4137 scl-pins {
4138 pins = "gpio114";
4140 drive-strength = <2>;
4141 bias-pull-up = <2200>;
4145 cci0_0_sleep: cci0-0-sleep-state {
4146 sda-pins {
4147 pins = "gpio113";
4149 drive-strength = <2>;
4150 bias-pull-down;
4153 scl-pins {
4154 pins = "gpio114";
4156 drive-strength = <2>;
4157 bias-pull-down;
4161 cci0_1_default: cci0-1-default-state {
4162 sda-pins {
4163 pins = "gpio115";
4165 drive-strength = <2>;
4166 bias-pull-up = <2200>;
4169 scl-pins {
4170 pins = "gpio116";
4172 drive-strength = <2>;
4173 bias-pull-up = <2200>;
4177 cci0_1_sleep: cci0-1-sleep-state {
4178 sda-pins {
4179 pins = "gpio115";
4181 drive-strength = <2>;
4182 bias-pull-down;
4185 scl-pins {
4186 pins = "gpio116";
4188 drive-strength = <2>;
4189 bias-pull-down;
4193 cci1_0_default: cci1-0-default-state {
4194 sda-pins {
4195 pins = "gpio117";
4197 drive-strength = <2>;
4198 bias-pull-up = <2200>;
4201 scl-pins {
4202 pins = "gpio118";
4204 drive-strength = <2>;
4205 bias-pull-up = <2200>;
4209 cci1_0_sleep: cci1-0-sleep-state {
4210 sda-pins {
4211 pins = "gpio117";
4213 drive-strength = <2>;
4214 bias-pull-down;
4217 scl-pins {
4218 pins = "gpio118";
4220 drive-strength = <2>;
4221 bias-pull-down;
4225 cci1_1_default: cci1-1-default-state {
4226 sda-pins {
4227 pins = "gpio12";
4229 drive-strength = <2>;
4230 bias-pull-up = <2200>;
4233 scl-pins {
4234 pins = "gpio13";
4236 drive-strength = <2>;
4237 bias-pull-up = <2200>;
4241 cci1_1_sleep: cci1-1-sleep-state {
4242 sda-pins {
4243 pins = "gpio12";
4245 drive-strength = <2>;
4246 bias-pull-down;
4249 scl-pins {
4250 pins = "gpio13";
4252 drive-strength = <2>;
4253 bias-pull-down;
4257 cci2_0_default: cci2-0-default-state {
4258 sda-pins {
4259 pins = "gpio112";
4261 drive-strength = <2>;
4262 bias-pull-up = <2200>;
4265 scl-pins {
4266 pins = "gpio153";
4268 drive-strength = <2>;
4269 bias-pull-up = <2200>;
4273 cci2_0_sleep: cci2-0-sleep-state {
4274 sda-pins {
4275 pins = "gpio112";
4277 drive-strength = <2>;
4278 bias-pull-down;
4281 scl-pins {
4282 pins = "gpio153";
4284 drive-strength = <2>;
4285 bias-pull-down;
4289 cci2_1_default: cci2-1-default-state {
4290 sda-pins {
4291 pins = "gpio119";
4293 drive-strength = <2>;
4294 bias-pull-up = <2200>;
4297 scl-pins {
4298 pins = "gpio120";
4300 drive-strength = <2>;
4301 bias-pull-up = <2200>;
4305 cci2_1_sleep: cci2-1-sleep-state {
4306 sda-pins {
4307 pins = "gpio119";
4309 drive-strength = <2>;
4310 bias-pull-down;
4313 scl-pins {
4314 pins = "gpio120";
4316 drive-strength = <2>;
4317 bias-pull-down;
4321 hub_i2c0_data_clk: hub-i2c0-data-clk-state {
4322 /* SDA, SCL */
4323 pins = "gpio64", "gpio65";
4325 drive-strength = <2>;
4326 bias-pull-up;
4329 hub_i2c1_data_clk: hub-i2c1-data-clk-state {
4330 /* SDA, SCL */
4331 pins = "gpio66", "gpio67";
4333 drive-strength = <2>;
4334 bias-pull-up;
4337 hub_i2c2_data_clk: hub-i2c2-data-clk-state {
4338 /* SDA, SCL */
4339 pins = "gpio68", "gpio69";
4341 drive-strength = <2>;
4342 bias-pull-up;
4345 hub_i2c3_data_clk: hub-i2c3-data-clk-state {
4346 /* SDA, SCL */
4347 pins = "gpio70", "gpio71";
4349 drive-strength = <2>;
4350 bias-pull-up;
4353 hub_i2c4_data_clk: hub-i2c4-data-clk-state {
4354 /* SDA, SCL */
4355 pins = "gpio72", "gpio73";
4357 drive-strength = <2>;
4358 bias-pull-up;
4361 hub_i2c5_data_clk: hub-i2c5-data-clk-state {
4362 /* SDA, SCL */
4363 pins = "gpio74", "gpio75";
4365 drive-strength = <2>;
4366 bias-pull-up;
4369 hub_i2c6_data_clk: hub-i2c6-data-clk-state {
4370 /* SDA, SCL */
4371 pins = "gpio76", "gpio77";
4373 drive-strength = <2>;
4374 bias-pull-up;
4377 hub_i2c7_data_clk: hub-i2c7-data-clk-state {
4378 /* SDA, SCL */
4379 pins = "gpio78", "gpio79";
4381 drive-strength = <2>;
4382 bias-pull-up;
4385 hub_i2c8_data_clk: hub-i2c8-data-clk-state {
4386 /* SDA, SCL */
4387 pins = "gpio206", "gpio207";
4389 drive-strength = <2>;
4390 bias-pull-up;
4393 hub_i2c9_data_clk: hub-i2c9-data-clk-state {
4394 /* SDA, SCL */
4395 pins = "gpio80", "gpio81";
4397 drive-strength = <2>;
4398 bias-pull-up;
4401 pcie0_default_state: pcie0-default-state {
4402 perst-pins {
4403 pins = "gpio94";
4405 drive-strength = <2>;
4406 bias-pull-down;
4409 clkreq-pins {
4410 pins = "gpio95";
4412 drive-strength = <2>;
4413 bias-pull-up;
4416 wake-pins {
4417 pins = "gpio96";
4419 drive-strength = <2>;
4420 bias-pull-up;
4424 pcie1_default_state: pcie1-default-state {
4425 perst-pins {
4426 pins = "gpio97";
4428 drive-strength = <2>;
4429 bias-pull-down;
4432 clkreq-pins {
4433 pins = "gpio98";
4435 drive-strength = <2>;
4436 bias-pull-up;
4439 wake-pins {
4440 pins = "gpio99";
4442 drive-strength = <2>;
4443 bias-pull-up;
4447 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
4448 /* SDA, SCL */
4449 pins = "gpio32", "gpio33";
4451 drive-strength = <2>;
4452 bias-pull-up;
4455 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
4456 /* SDA, SCL */
4457 pins = "gpio36", "gpio37";
4459 drive-strength = <2>;
4460 bias-pull-up;
4463 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
4464 /* SDA, SCL */
4465 pins = "gpio40", "gpio41";
4467 drive-strength = <2>;
4468 bias-pull-up;
4471 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
4472 /* SDA, SCL */
4473 pins = "gpio44", "gpio45";
4475 drive-strength = <2>;
4476 bias-pull-up;
4479 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
4480 /* SDA, SCL */
4481 pins = "gpio48", "gpio49";
4483 drive-strength = <2>;
4484 bias-pull-up;
4487 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
4488 /* SDA, SCL */
4489 pins = "gpio52", "gpio53";
4491 drive-strength = <2>;
4492 bias-pull-up;
4495 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
4496 /* SDA, SCL */
4497 pins = "gpio56", "gpio57";
4499 drive-strength = <2>;
4500 bias-pull-up;
4503 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
4504 /* SDA, SCL */
4505 pins = "gpio60", "gpio61";
4507 drive-strength = <2>;
4508 bias-pull-up;
4511 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
4512 /* SDA, SCL */
4513 pins = "gpio0", "gpio1";
4515 drive-strength = <2>;
4516 bias-pull-up;
4519 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
4520 /* SDA, SCL */
4521 pins = "gpio4", "gpio5";
4523 drive-strength = <2>;
4524 bias-pull-up;
4527 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
4528 /* SDA, SCL */
4529 pins = "gpio8", "gpio9";
4531 drive-strength = <2>;
4532 bias-pull-up;
4535 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
4536 /* SDA, SCL */
4537 pins = "gpio12", "gpio13";
4539 drive-strength = <2>;
4540 bias-pull-up;
4543 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
4544 /* SDA, SCL */
4545 pins = "gpio16", "gpio17";
4547 drive-strength = <2>;
4548 bias-pull-up;
4551 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
4552 /* SDA, SCL */
4553 pins = "gpio20", "gpio21";
4555 drive-strength = <2>;
4556 bias-pull-up;
4559 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
4560 /* SDA, SCL */
4561 pins = "gpio24", "gpio25";
4563 drive-strength = <2>;
4564 bias-pull-up;
4567 qup_spi0_cs: qup-spi0-cs-state {
4568 pins = "gpio35";
4570 drive-strength = <6>;
4571 bias-disable;
4574 qup_spi0_data_clk: qup-spi0-data-clk-state {
4576 pins = "gpio32", "gpio33", "gpio34";
4578 drive-strength = <6>;
4579 bias-disable;
4582 qup_spi1_cs: qup-spi1-cs-state {
4583 pins = "gpio39";
4585 drive-strength = <6>;
4586 bias-disable;
4589 qup_spi1_data_clk: qup-spi1-data-clk-state {
4591 pins = "gpio36", "gpio37", "gpio38";
4593 drive-strength = <6>;
4594 bias-disable;
4597 qup_spi2_cs: qup-spi2-cs-state {
4598 pins = "gpio43";
4600 drive-strength = <6>;
4601 bias-disable;
4604 qup_spi2_data_clk: qup-spi2-data-clk-state {
4606 pins = "gpio40", "gpio41", "gpio42";
4608 drive-strength = <6>;
4609 bias-disable;
4612 qup_spi3_cs: qup-spi3-cs-state {
4613 pins = "gpio47";
4615 drive-strength = <6>;
4616 bias-disable;
4619 qup_spi3_data_clk: qup-spi3-data-clk-state {
4621 pins = "gpio44", "gpio45", "gpio46";
4623 drive-strength = <6>;
4624 bias-disable;
4627 qup_spi4_cs: qup-spi4-cs-state {
4628 pins = "gpio51";
4630 drive-strength = <6>;
4631 bias-disable;
4634 qup_spi4_data_clk: qup-spi4-data-clk-state {
4636 pins = "gpio48", "gpio49", "gpio50";
4638 drive-strength = <6>;
4639 bias-disable;
4642 qup_spi5_cs: qup-spi5-cs-state {
4643 pins = "gpio55";
4645 drive-strength = <6>;
4646 bias-disable;
4649 qup_spi5_data_clk: qup-spi5-data-clk-state {
4651 pins = "gpio52", "gpio53", "gpio54";
4653 drive-strength = <6>;
4654 bias-disable;
4657 qup_spi6_cs: qup-spi6-cs-state {
4658 pins = "gpio59";
4660 drive-strength = <6>;
4661 bias-disable;
4664 qup_spi6_data_clk: qup-spi6-data-clk-state {
4666 pins = "gpio56", "gpio57", "gpio58";
4668 drive-strength = <6>;
4669 bias-disable;
4672 qup_spi7_cs: qup-spi7-cs-state {
4673 pins = "gpio63";
4675 drive-strength = <6>;
4676 bias-disable;
4679 qup_spi7_data_clk: qup-spi7-data-clk-state {
4681 pins = "gpio60", "gpio61", "gpio62";
4683 drive-strength = <6>;
4684 bias-disable;
4687 qup_spi8_cs: qup-spi8-cs-state {
4688 pins = "gpio3";
4690 drive-strength = <6>;
4691 bias-disable;
4694 qup_spi8_data_clk: qup-spi8-data-clk-state {
4696 pins = "gpio0", "gpio1", "gpio2";
4698 drive-strength = <6>;
4699 bias-disable;
4702 qup_spi9_cs: qup-spi9-cs-state {
4703 pins = "gpio7";
4705 drive-strength = <6>;
4706 bias-disable;
4709 qup_spi9_data_clk: qup-spi9-data-clk-state {
4711 pins = "gpio4", "gpio5", "gpio6";
4713 drive-strength = <6>;
4714 bias-disable;
4717 qup_spi10_cs: qup-spi10-cs-state {
4718 pins = "gpio11";
4720 drive-strength = <6>;
4721 bias-disable;
4724 qup_spi10_data_clk: qup-spi10-data-clk-state {
4726 pins = "gpio8", "gpio9", "gpio10";
4728 drive-strength = <6>;
4729 bias-disable;
4732 qup_spi11_cs: qup-spi11-cs-state {
4733 pins = "gpio15";
4735 drive-strength = <6>;
4736 bias-disable;
4739 qup_spi11_data_clk: qup-spi11-data-clk-state {
4741 pins = "gpio12", "gpio13", "gpio14";
4743 drive-strength = <6>;
4744 bias-disable;
4747 qup_spi12_cs: qup-spi12-cs-state {
4748 pins = "gpio19";
4750 drive-strength = <6>;
4751 bias-disable;
4754 qup_spi12_data_clk: qup-spi12-data-clk-state {
4756 pins = "gpio16", "gpio17", "gpio18";
4758 drive-strength = <6>;
4759 bias-disable;
4762 qup_spi13_cs: qup-spi13-cs-state {
4763 pins = "gpio23";
4765 drive-strength = <6>;
4766 bias-disable;
4769 qup_spi13_data_clk: qup-spi13-data-clk-state {
4771 pins = "gpio20", "gpio21", "gpio22";
4773 drive-strength = <6>;
4774 bias-disable;
4777 qup_spi14_cs: qup-spi14-cs-state {
4778 pins = "gpio27";
4780 drive-strength = <6>;
4781 bias-disable;
4784 qup_spi14_data_clk: qup-spi14-data-clk-state {
4786 pins = "gpio24", "gpio25", "gpio26";
4788 drive-strength = <6>;
4789 bias-disable;
4792 qup_uart14_default: qup-uart14-default-state {
4794 pins = "gpio26", "gpio27";
4796 drive-strength = <2>;
4797 bias-pull-up;
4800 qup_uart14_cts_rts: qup-uart14-cts-rts-state {
4802 pins = "gpio24", "gpio25";
4804 drive-strength = <2>;
4805 bias-pull-down;
4808 qup_uart15_default: qup-uart15-default-state {
4810 pins = "gpio30", "gpio31";
4812 drive-strength = <2>;
4813 bias-disable;
4816 sdc2_sleep: sdc2-sleep-state {
4817 clk-pins {
4818 pins = "sdc2_clk";
4819 drive-strength = <2>;
4820 bias-disable;
4823 cmd-pins {
4824 pins = "sdc2_cmd";
4825 drive-strength = <2>;
4826 bias-pull-up;
4829 data-pins {
4830 pins = "sdc2_data";
4831 drive-strength = <2>;
4832 bias-pull-up;
4836 sdc2_default: sdc2-default-state {
4837 clk-pins {
4838 pins = "sdc2_clk";
4839 drive-strength = <16>;
4840 bias-disable;
4843 cmd-pins {
4844 pins = "sdc2_cmd";
4845 drive-strength = <10>;
4846 bias-pull-up;
4849 data-pins {
4850 pins = "sdc2_data";
4851 drive-strength = <10>;
4852 bias-pull-up;
4858 compatible = "qcom,sm8650-smmu-500", "qcom,smmu-500", "arm,mmu-500";
4959 #iommu-cells = <2>;
4960 #global-interrupts = <1>;
4962 dma-coherent;
4965 intc: interrupt-controller@17100000 {
4966 compatible = "arm,gic-v3";
4972 #interrupt-cells = <3>;
4973 interrupt-controller;
4975 #redistributor-regions = <1>;
4976 redistributor-stride = <0 0x40000>;
4978 #address-cells = <2>;
4979 #size-cells = <2>;
4982 gic_its: msi-controller@17140000 {
4983 compatible = "arm,gic-v3-its";
4986 msi-controller;
4987 #msi-cells = <1>;
4992 compatible = "arm,armv7-timer-mem";
4996 #address-cells = <1>;
4997 #size-cells = <1>;
5006 frame-number = <0>;
5014 frame-number = <1>;
5024 frame-number = <2>;
5034 frame-number = <3>;
5044 frame-number = <4>;
5054 frame-number = <5>;
5064 frame-number = <6>;
5071 compatible = "qcom,rpmh-rsc";
5076 reg-names = "drv-0",
5077 "drv-1",
5078 "drv-2";
5084 power-domains = <&cluster_pd>;
5086 qcom,tcs-offset = <0xd00>;
5087 qcom,drv-id = <2>;
5088 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
5093 apps_bcm_voter: bcm-voter {
5094 compatible = "qcom,bcm-voter";
5097 rpmhcc: clock-controller {
5098 compatible = "qcom,sm8650-rpmh-clk";
5101 clock-names = "xo";
5103 #clock-cells = <1>;
5106 rpmhpd: power-controller {
5107 compatible = "qcom,sm8650-rpmhpd";
5109 operating-points-v2 = <&rpmhpd_opp_table>;
5111 #power-domain-cells = <1>;
5113 rpmhpd_opp_table: opp-table {
5114 compatible = "operating-points-v2";
5116 rpmhpd_opp_ret: opp-16 {
5117 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5120 rpmhpd_opp_min_svs: opp-48 {
5121 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5124 rpmhpd_opp_low_svs_d2: opp-52 {
5125 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
5128 rpmhpd_opp_low_svs_d1: opp-56 {
5129 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
5132 rpmhpd_opp_low_svs_d0: opp-60 {
5133 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
5136 rpmhpd_opp_low_svs: opp-64 {
5137 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5140 rpmhpd_opp_low_svs_l1: opp-80 {
5141 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
5144 rpmhpd_opp_svs: opp-128 {
5145 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5148 rpmhpd_opp_svs_l0: opp-144 {
5149 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
5152 rpmhpd_opp_svs_l1: opp-192 {
5153 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5156 rpmhpd_opp_nom: opp-256 {
5157 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5160 rpmhpd_opp_nom_l1: opp-320 {
5161 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5164 rpmhpd_opp_nom_l2: opp-336 {
5165 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5168 rpmhpd_opp_turbo: opp-384 {
5169 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5172 rpmhpd_opp_turbo_l1: opp-416 {
5173 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5180 compatible = "qcom,sm8650-cpufreq-epss", "qcom,cpufreq-epss";
5185 reg-names = "freq-domain0",
5186 "freq-domain1",
5187 "freq-domain2",
5188 "freq-domain3";
5194 interrupt-names = "dcvsh-irq-0",
5195 "dcvsh-irq-1",
5196 "dcvsh-irq-2",
5197 "dcvsh-irq-3";
5200 clock-names = "xo", "alternate";
5202 #freq-domain-cells = <1>;
5203 #clock-cells = <1>;
5207 compatible = "qcom,sm8650-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
5215 operating-points-v2 = <&llcc_bwmon_opp_table>;
5217 llcc_bwmon_opp_table: opp-table {
5218 compatible = "operating-points-v2";
5220 opp-0 {
5221 opp-peak-kBps = <2086000>;
5224 opp-1 {
5225 opp-peak-kBps = <2929000>;
5228 opp-2 {
5229 opp-peak-kBps = <5931000>;
5232 opp-3 {
5233 opp-peak-kBps = <6515000>;
5236 opp-4 {
5237 opp-peak-kBps = <7980000>;
5240 opp-5 {
5241 opp-peak-kBps = <10437000>;
5244 opp-6 {
5245 opp-peak-kBps = <12157000>;
5248 opp-7 {
5249 opp-peak-kBps = <14060000>;
5252 opp-8 {
5253 opp-peak-kBps = <16113000>;
5259 compatible = "qcom,sm8650-cpu-bwmon", "qcom,sdm845-bwmon";
5267 operating-points-v2 = <&cpu_bwmon_opp_table>;
5269 cpu_bwmon_opp_table: opp-table {
5270 compatible = "operating-points-v2";
5272 opp-0 {
5273 opp-peak-kBps = <4577000>;
5276 opp-1 {
5277 opp-peak-kBps = <7110000>;
5280 opp-2 {
5281 opp-peak-kBps = <9155000>;
5284 opp-3 {
5285 opp-peak-kBps = <12298000>;
5288 opp-4 {
5289 opp-peak-kBps = <14236000>;
5292 opp-5 {
5293 opp-peak-kBps = <16265000>;
5299 compatible = "qcom,sm8650-gem-noc";
5302 qcom,bcm-voters = <&apps_bcm_voter>;
5304 #interconnect-cells = <2>;
5307 system-cache-controller@25000000 {
5308 compatible = "qcom,sm8650-llcc";
5315 reg-names = "llcc0_base",
5326 compatible = "qcom,sm8650-adsp-pas";
5329 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
5334 interrupt-names = "wdog",
5338 "stop-ack";
5341 clock-names = "xo";
5346 power-domains = <&rpmhpd RPMHPD_LCX>,
5348 power-domain-names = "lcx",
5351 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
5355 qcom,smem-states = <&smp2p_adsp_out 0>;
5356 qcom,smem-state-names = "stop";
5360 remoteproc_adsp_glink: glink-edge {
5361 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
5368 qcom,remote-pid = <2>;
5375 qcom,glink-channels = "fastrpcglink-apps-dsp";
5379 qcom,non-secure-domain;
5381 #address-cells = <1>;
5382 #size-cells = <0>;
5384 compute-cb@3 {
5385 compatible = "qcom,fastrpc-compute-cb";
5390 dma-coherent;
5393 compute-cb@4 {
5394 compatible = "qcom,fastrpc-compute-cb";
5399 dma-coherent;
5402 compute-cb@5 {
5403 compatible = "qcom,fastrpc-compute-cb";
5408 dma-coherent;
5411 compute-cb@6 {
5412 compatible = "qcom,fastrpc-compute-cb";
5417 dma-coherent;
5420 compute-cb@7 {
5421 compatible = "qcom,fastrpc-compute-cb";
5427 dma-coherent;
5433 qcom,glink-channels = "adsp_apps";
5436 #address-cells = <1>;
5437 #size-cells = <0>;
5442 #sound-dai-cells = <0>;
5443 qcom,protection-domain = "avs/audio",
5447 compatible = "qcom,q6apm-lpass-dais";
5448 #sound-dai-cells = <1>;
5452 compatible = "qcom,q6apm-dais";
5461 qcom,protection-domain = "avs/audio",
5464 q6prmcc: clock-controller {
5465 compatible = "qcom,q6prm-lpass-clocks";
5466 #clock-cells = <2>;
5474 compatible = "qcom,sm8650-nsp-noc";
5477 qcom,bcm-voters = <&apps_bcm_voter>;
5479 #interconnect-cells = <2>;
5483 compatible = "qcom,sm8650-cdsp-pas";
5486 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
5491 interrupt-names = "wdog",
5495 "stop-ack";
5498 clock-names = "xo";
5503 power-domains = <&rpmhpd RPMHPD_CX>,
5506 power-domain-names = "cx",
5510 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>, <&global_sync_mem>;
5514 qcom,smem-states = <&smp2p_cdsp_out 0>;
5515 qcom,smem-state-names = "stop";
5519 glink-edge {
5520 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
5527 qcom,remote-pid = <5>;
5534 qcom,glink-channels = "fastrpcglink-apps-dsp";
5538 qcom,non-secure-domain;
5540 #address-cells = <1>;
5541 #size-cells = <0>;
5543 compute-cb@1 {
5544 compatible = "qcom,fastrpc-compute-cb";
5550 dma-coherent;
5553 compute-cb@2 {
5554 compatible = "qcom,fastrpc-compute-cb";
5560 dma-coherent;
5563 compute-cb@3 {
5564 compatible = "qcom,fastrpc-compute-cb";
5570 dma-coherent;
5573 compute-cb@4 {
5574 compatible = "qcom,fastrpc-compute-cb";
5580 dma-coherent;
5583 compute-cb@5 {
5584 compatible = "qcom,fastrpc-compute-cb";
5590 dma-coherent;
5593 compute-cb@6 {
5594 compatible = "qcom,fastrpc-compute-cb";
5600 dma-coherent;
5603 compute-cb@7 {
5604 compatible = "qcom,fastrpc-compute-cb";
5610 dma-coherent;
5613 compute-cb@8 {
5614 compatible = "qcom,fastrpc-compute-cb";
5620 dma-coherent;
5625 compute-cb@10 {
5626 compatible = "qcom,fastrpc-compute-cb";
5632 dma-coherent;
5635 compute-cb@11 {
5636 compatible = "qcom,fastrpc-compute-cb";
5642 dma-coherent;
5645 compute-cb@12 {
5646 compatible = "qcom,fastrpc-compute-cb";
5652 dma-coherent;
5659 thermal-zones {
5660 aoss0-thermal {
5661 thermal-sensors = <&tsens0 0>;
5664 trip-point0 {
5670 aoss0-critical {
5678 cpuss0-thermal {
5679 thermal-sensors = <&tsens0 1>;
5682 trip-point0 {
5688 cpuss0-critical {
5696 cpuss1-thermal {
5697 thermal-sensors = <&tsens0 2>;
5700 trip-point0 {
5706 cpuss1-critical {
5714 cpuss2-thermal {
5715 thermal-sensors = <&tsens0 3>;
5718 trip-point0 {
5724 cpuss2-critical {
5732 cpuss3-thermal {
5733 thermal-sensors = <&tsens0 4>;
5736 trip-point0 {
5742 cpuss3-critical {
5750 cpu2-top-thermal {
5751 thermal-sensors = <&tsens0 5>;
5754 trip-point0 {
5760 trip-point1 {
5766 cpu2-critical {
5774 cpu2-bottom-thermal {
5775 thermal-sensors = <&tsens0 6>;
5778 trip-point0 {
5784 trip-point1 {
5790 cpu2-critical {
5798 cpu3-top-thermal {
5799 thermal-sensors = <&tsens0 7>;
5802 trip-point0 {
5808 trip-point1 {
5814 cpu3-critical {
5822 cpu3-bottom-thermal {
5823 thermal-sensors = <&tsens0 8>;
5826 trip-point0 {
5832 trip-point1 {
5838 cpu3-critical {
5846 cpu4-top-thermal {
5847 thermal-sensors = <&tsens0 9>;
5850 trip-point0 {
5856 trip-point1 {
5862 cpu4-critical {
5870 cpu4-bottom-thermal {
5871 thermal-sensors = <&tsens0 10>;
5874 trip-point0 {
5880 trip-point1 {
5886 cpu4-critical {
5894 cpu5-top-thermal {
5895 thermal-sensors = <&tsens0 11>;
5898 trip-point0 {
5904 trip-point1 {
5910 cpu5-critical {
5918 cpu5-bottom-thermal {
5919 thermal-sensors = <&tsens0 12>;
5922 trip-point0 {
5928 trip-point1 {
5934 cpu5-critical {
5942 cpu6-top-thermal {
5943 thermal-sensors = <&tsens0 13>;
5946 trip-point0 {
5952 trip-point1 {
5958 cpu6-critical {
5966 cpu6-bottom-thermal {
5967 thermal-sensors = <&tsens0 14>;
5970 trip-point0 {
5976 trip-point1 {
5982 cpu6-critical {
5990 aoss1-thermal {
5991 thermal-sensors = <&tsens1 0>;
5994 trip-point0 {
6000 aoss1-critical {
6008 cpu7-top-thermal {
6009 thermal-sensors = <&tsens1 1>;
6012 trip-point0 {
6018 trip-point1 {
6024 cpu7-critical {
6032 cpu7-middle-thermal {
6033 thermal-sensors = <&tsens1 2>;
6036 trip-point0 {
6042 trip-point1 {
6048 cpu7-critical {
6056 cpu7-bottom-thermal {
6057 thermal-sensors = <&tsens1 3>;
6060 trip-point0 {
6066 trip-point1 {
6072 cpu7-critical {
6080 cpu0-thermal {
6081 thermal-sensors = <&tsens1 4>;
6084 trip-point0 {
6090 trip-point1 {
6096 cpu0-critical {
6104 cpu1-thermal {
6105 thermal-sensors = <&tsens1 5>;
6108 trip-point0 {
6114 trip-point1 {
6120 cpu1-critical {
6128 nsphvx0-thermal {
6129 polling-delay-passive = <10>;
6131 thermal-sensors = <&tsens2 6>;
6134 trip-point0 {
6140 nsphvx1-critical {
6148 nsphvx1-thermal {
6149 polling-delay-passive = <10>;
6151 thermal-sensors = <&tsens2 7>;
6154 trip-point0 {
6160 nsphvx1-critical {
6168 nsphmx0-thermal {
6169 polling-delay-passive = <10>;
6171 thermal-sensors = <&tsens2 8>;
6174 trip-point0 {
6180 nsphmx0-critical {
6188 nsphmx1-thermal {
6189 polling-delay-passive = <10>;
6191 thermal-sensors = <&tsens2 9>;
6194 trip-point0 {
6200 nsphmx1-critical {
6208 nsphmx2-thermal {
6209 polling-delay-passive = <10>;
6211 thermal-sensors = <&tsens2 10>;
6214 trip-point0 {
6220 nsphmx2-critical {
6228 nsphmx3-thermal {
6229 polling-delay-passive = <10>;
6231 thermal-sensors = <&tsens2 11>;
6234 trip-point0 {
6240 nsphmx3-critical {
6248 video-thermal {
6249 polling-delay-passive = <10>;
6251 thermal-sensors = <&tsens1 12>;
6254 trip-point0 {
6260 video-critical {
6268 ddr-thermal {
6269 polling-delay-passive = <10>;
6271 thermal-sensors = <&tsens1 13>;
6274 trip-point0 {
6280 ddr-critical {
6288 camera0-thermal {
6289 thermal-sensors = <&tsens1 14>;
6292 trip-point0 {
6298 camera0-critical {
6306 camera1-thermal {
6307 thermal-sensors = <&tsens1 15>;
6310 trip-point0 {
6316 camera1-critical {
6324 aoss2-thermal {
6325 thermal-sensors = <&tsens2 0>;
6328 trip-point0 {
6334 aoss2-critical {
6342 gpuss0-thermal {
6343 polling-delay-passive = <10>;
6345 thermal-sensors = <&tsens2 1>;
6347 cooling-maps {
6350 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6355 gpu0_alert0: trip-point0 {
6361 trip-point1 {
6367 trip-point2 {
6375 gpuss1-thermal {
6376 polling-delay-passive = <10>;
6378 thermal-sensors = <&tsens2 2>;
6380 cooling-maps {
6383 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6388 gpu1_alert0: trip-point0 {
6394 trip-point1 {
6400 trip-point2 {
6408 gpuss2-thermal {
6409 polling-delay-passive = <10>;
6411 thermal-sensors = <&tsens2 3>;
6413 cooling-maps {
6416 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6421 gpu2_alert0: trip-point0 {
6427 trip-point1 {
6433 trip-point2 {
6441 gpuss3-thermal {
6442 polling-delay-passive = <10>;
6444 thermal-sensors = <&tsens2 4>;
6446 cooling-maps {
6449 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6454 gpu3_alert0: trip-point0 {
6460 trip-point1 {
6466 trip-point2 {
6474 gpuss4-thermal {
6475 polling-delay-passive = <10>;
6477 thermal-sensors = <&tsens2 5>;
6479 cooling-maps {
6482 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6487 gpu4_alert0: trip-point0 {
6493 trip-point1 {
6499 trip-point2 {
6507 gpuss5-thermal {
6508 polling-delay-passive = <10>;
6510 thermal-sensors = <&tsens2 6>;
6512 cooling-maps {
6515 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6520 gpu5_alert0: trip-point0 {
6526 trip-point1 {
6532 trip-point2 {
6540 gpuss6-thermal {
6541 polling-delay-passive = <10>;
6543 thermal-sensors = <&tsens2 7>;
6545 cooling-maps {
6548 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6553 gpu6_alert0: trip-point0 {
6559 trip-point1 {
6565 trip-point2 {
6573 gpuss7-thermal {
6574 polling-delay-passive = <10>;
6576 thermal-sensors = <&tsens2 8>;
6578 cooling-maps {
6581 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6586 gpu7_alert0: trip-point0 {
6592 trip-point1 {
6598 trip-point2 {
6606 modem0-thermal {
6607 thermal-sensors = <&tsens2 9>;
6610 trip-point0 {
6616 modem0-critical {
6624 modem1-thermal {
6625 thermal-sensors = <&tsens2 10>;
6628 trip-point0 {
6634 modem1-critical {
6642 modem2-thermal {
6643 thermal-sensors = <&tsens2 11>;
6646 trip-point0 {
6652 modem2-critical {
6660 modem3-thermal {
6661 thermal-sensors = <&tsens2 12>;
6664 trip-point0 {
6670 modem3-critical {
6680 compatible = "arm,armv8-timer";