Lines Matching +full:pcie +full:- +full:sm8150
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm8650-camcc.h>
8 #include <dt-bindings/clock/qcom,sm8650-dispcc.h>
9 #include <dt-bindings/clock/qcom,sm8650-gcc.h>
10 #include <dt-bindings/clock/qcom,sm8650-gpucc.h>
11 #include <dt-bindings/clock/qcom,sm8650-tcsr.h>
12 #include <dt-bindings/clock/qcom,sm8650-videocc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/interconnect/qcom,icc.h>
17 #include <dt-bindings/interconnect/qcom,sm8650-rpmh.h>
18 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/mailbox/qcom-ipcc.h>
20 #include <dt-bindings/phy/phy-qcom-qmp.h>
21 #include <dt-bindings/power/qcom,rpmhpd.h>
22 #include <dt-bindings/power/qcom-rpmpd.h>
23 #include <dt-bindings/reset/qcom,sm8650-gpucc.h>
24 #include <dt-bindings/soc/qcom,gpr.h>
25 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
26 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
27 #include <dt-bindings/thermal/thermal.h>
30 interrupt-parent = <&intc>;
32 #address-cells = <2>;
33 #size-cells = <2>;
38 xo_board: xo-board {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
43 sleep_clk: sleep-clk {
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
48 bi_tcxo_div2: bi-tcxo-div2-clk {
49 compatible = "fixed-factor-clock";
50 #clock-cells = <0>;
53 clock-mult = <1>;
54 clock-div = <2>;
57 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
58 compatible = "fixed-factor-clock";
59 #clock-cells = <0>;
62 clock-mult = <1>;
63 clock-div = <2>;
68 #address-cells = <2>;
69 #size-cells = <0>;
73 compatible = "arm,cortex-a520";
78 power-domains = <&cpu_pd0>;
79 power-domain-names = "psci";
81 enable-method = "psci";
82 next-level-cache = <&l2_0>;
83 capacity-dmips-mhz = <1024>;
84 dynamic-power-coefficient = <100>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
88 #cooling-cells = <2>;
90 l2_0: l2-cache {
92 cache-level = <2>;
93 cache-unified;
94 next-level-cache = <&l3_0>;
96 l3_0: l3-cache {
98 cache-level = <3>;
99 cache-unified;
106 compatible = "arm,cortex-a520";
111 power-domains = <&cpu_pd1>;
112 power-domain-names = "psci";
114 enable-method = "psci";
115 next-level-cache = <&l2_0>;
116 capacity-dmips-mhz = <1024>;
117 dynamic-power-coefficient = <100>;
119 qcom,freq-domain = <&cpufreq_hw 0>;
121 #cooling-cells = <2>;
126 compatible = "arm,cortex-a720";
131 power-domains = <&cpu_pd2>;
132 power-domain-names = "psci";
134 enable-method = "psci";
135 next-level-cache = <&l2_200>;
136 capacity-dmips-mhz = <1792>;
137 dynamic-power-coefficient = <238>;
139 qcom,freq-domain = <&cpufreq_hw 3>;
141 #cooling-cells = <2>;
143 l2_200: l2-cache {
145 cache-level = <2>;
146 cache-unified;
147 next-level-cache = <&l3_0>;
153 compatible = "arm,cortex-a720";
158 power-domains = <&cpu_pd3>;
159 power-domain-names = "psci";
161 enable-method = "psci";
162 next-level-cache = <&l2_200>;
163 capacity-dmips-mhz = <1792>;
164 dynamic-power-coefficient = <238>;
166 qcom,freq-domain = <&cpufreq_hw 3>;
168 #cooling-cells = <2>;
173 compatible = "arm,cortex-a720";
178 power-domains = <&cpu_pd4>;
179 power-domain-names = "psci";
181 enable-method = "psci";
182 next-level-cache = <&l2_400>;
183 capacity-dmips-mhz = <1792>;
184 dynamic-power-coefficient = <238>;
186 qcom,freq-domain = <&cpufreq_hw 3>;
188 #cooling-cells = <2>;
190 l2_400: l2-cache {
192 cache-level = <2>;
193 cache-unified;
194 next-level-cache = <&l3_0>;
200 compatible = "arm,cortex-a720";
205 power-domains = <&cpu_pd5>;
206 power-domain-names = "psci";
208 enable-method = "psci";
209 next-level-cache = <&l2_500>;
210 capacity-dmips-mhz = <1792>;
211 dynamic-power-coefficient = <238>;
213 qcom,freq-domain = <&cpufreq_hw 1>;
215 #cooling-cells = <2>;
217 l2_500: l2-cache {
219 cache-level = <2>;
220 cache-unified;
221 next-level-cache = <&l3_0>;
227 compatible = "arm,cortex-a720";
232 power-domains = <&cpu_pd6>;
233 power-domain-names = "psci";
235 enable-method = "psci";
236 next-level-cache = <&l2_600>;
237 capacity-dmips-mhz = <1792>;
238 dynamic-power-coefficient = <238>;
240 qcom,freq-domain = <&cpufreq_hw 1>;
242 #cooling-cells = <2>;
244 l2_600: l2-cache {
246 cache-level = <2>;
247 cache-unified;
248 next-level-cache = <&l3_0>;
254 compatible = "arm,cortex-x4";
259 power-domains = <&cpu_pd7>;
260 power-domain-names = "psci";
262 enable-method = "psci";
263 next-level-cache = <&l2_700>;
264 capacity-dmips-mhz = <1894>;
265 dynamic-power-coefficient = <588>;
267 qcom,freq-domain = <&cpufreq_hw 2>;
269 #cooling-cells = <2>;
271 l2_700: l2-cache {
273 cache-level = <2>;
274 cache-unified;
275 next-level-cache = <&l3_0>;
279 cpu-map {
315 idle-states {
316 entry-method = "psci";
318 silver_cpu_sleep_0: cpu-sleep-0-0 {
319 compatible = "arm,idle-state";
320 idle-state-name = "silver-rail-power-collapse";
321 arm,psci-suspend-param = <0x40000004>;
322 entry-latency-us = <550>;
323 exit-latency-us = <750>;
324 min-residency-us = <6700>;
325 local-timer-stop;
328 gold_cpu_sleep_0: cpu-sleep-1-0 {
329 compatible = "arm,idle-state";
330 idle-state-name = "gold-rail-power-collapse";
331 arm,psci-suspend-param = <0x40000004>;
332 entry-latency-us = <600>;
333 exit-latency-us = <1300>;
334 min-residency-us = <8136>;
335 local-timer-stop;
338 gold_plus_cpu_sleep_0: cpu-sleep-2-0 {
339 compatible = "arm,idle-state";
340 idle-state-name = "gold-plus-rail-power-collapse";
341 arm,psci-suspend-param = <0x40000004>;
342 entry-latency-us = <500>;
343 exit-latency-us = <1350>;
344 min-residency-us = <7480>;
345 local-timer-stop;
349 domain-idle-states {
350 cluster_sleep_0: cluster-sleep-0 {
351 compatible = "domain-idle-state";
352 arm,psci-suspend-param = <0x41000044>;
353 entry-latency-us = <750>;
354 exit-latency-us = <2350>;
355 min-residency-us = <9144>;
358 cluster_sleep_1: cluster-sleep-1 {
359 compatible = "domain-idle-state";
360 arm,psci-suspend-param = <0x4100c344>;
361 entry-latency-us = <2800>;
362 exit-latency-us = <4400>;
363 min-residency-us = <10150>;
369 compatible = "arm,embedded-trace-extension";
373 out-ports {
376 remote-endpoint = <&funnel_ete_in_ete0>;
382 funnel-ete {
383 compatible = "arm,coresight-static-funnel";
385 in-ports {
388 remote-endpoint = <&ete0_out_funnel_ete>;
393 out-ports {
396 remote-endpoint = <&funnel_apss_in_funnel_ete>;
404 compatible = "qcom,scm-sm8650", "qcom,scm";
405 qcom,dload-mode = <&tcsr 0x19000>;
411 clk_virt: interconnect-0 {
412 compatible = "qcom,sm8650-clk-virt";
413 #interconnect-cells = <2>;
414 qcom,bcm-voters = <&apps_bcm_voter>;
417 mc_virt: interconnect-1 {
418 compatible = "qcom,sm8650-mc-virt";
419 #interconnect-cells = <2>;
420 qcom,bcm-voters = <&apps_bcm_voter>;
429 pmu-a520 {
430 compatible = "arm,cortex-a520-pmu";
434 pmu-a720 {
435 compatible = "arm,cortex-a720-pmu";
439 pmu-x4 {
440 compatible = "arm,cortex-x4-pmu";
445 compatible = "arm,psci-1.0";
448 cpu_pd0: power-domain-cpu0 {
449 #power-domain-cells = <0>;
450 power-domains = <&cluster_pd>;
451 domain-idle-states = <&silver_cpu_sleep_0>;
454 cpu_pd1: power-domain-cpu1 {
455 #power-domain-cells = <0>;
456 power-domains = <&cluster_pd>;
457 domain-idle-states = <&silver_cpu_sleep_0>;
460 cpu_pd2: power-domain-cpu2 {
461 #power-domain-cells = <0>;
462 power-domains = <&cluster_pd>;
463 domain-idle-states = <&silver_cpu_sleep_0>;
466 cpu_pd3: power-domain-cpu3 {
467 #power-domain-cells = <0>;
468 power-domains = <&cluster_pd>;
469 domain-idle-states = <&gold_cpu_sleep_0>;
472 cpu_pd4: power-domain-cpu4 {
473 #power-domain-cells = <0>;
474 power-domains = <&cluster_pd>;
475 domain-idle-states = <&gold_cpu_sleep_0>;
478 cpu_pd5: power-domain-cpu5 {
479 #power-domain-cells = <0>;
480 power-domains = <&cluster_pd>;
481 domain-idle-states = <&gold_cpu_sleep_0>;
484 cpu_pd6: power-domain-cpu6 {
485 #power-domain-cells = <0>;
486 power-domains = <&cluster_pd>;
487 domain-idle-states = <&gold_cpu_sleep_0>;
490 cpu_pd7: power-domain-cpu7 {
491 #power-domain-cells = <0>;
492 power-domains = <&cluster_pd>;
493 domain-idle-states = <&gold_plus_cpu_sleep_0>;
496 cluster_pd: power-domain-cluster {
497 #power-domain-cells = <0>;
498 domain-idle-states = <&cluster_sleep_0>,
503 reserved_memory: reserved-memory {
504 #address-cells = <2>;
505 #size-cells = <2>;
510 no-map;
513 cpusys_vm_mem: cpusys-vm@80e00000 {
515 no-map;
519 xbl_dt_log_merged_mem: xbl-dt-log-merged@81a00000 {
521 no-map;
524 aop_cmd_db_mem: aop-cmd-db@81c60000 {
525 compatible = "qcom,cmd-db";
527 no-map;
531 aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 {
533 no-map;
542 no-map;
545 adsp_mhi_mem: adsp-mhi@81f00000 {
547 no-map;
552 no-map;
555 global_sync_mem: global-sync@82600000 {
557 no-map;
560 tz_stat_mem: tz-stat@82700000 {
562 no-map;
567 no-map;
570 qlink_logging_mem: qlink-logging@84800000 {
572 no-map;
575 mpss_dsm_mem: mpss-dsm@86b00000 {
577 no-map;
580 mpss_dsm_mem_2: mpss-dsm-2@8b400000 {
582 no-map;
587 no-map;
590 q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 {
592 no-map;
595 ipa_fw_mem: ipa-fw@9b080000 {
597 no-map;
600 ipa_gsi_mem: ipa-gsi@9b090000 {
602 no-map;
605 gpu_micro_code_mem: gpu-micro-code@9b09a000 {
607 no-map;
612 no-map;
616 spu_tz_shared_mem: spu-tz-shared@9b280000 {
618 no-map;
622 spu_modem_shared_mem: spu-modem-shared@9b2e0000 {
624 no-map;
629 no-map;
634 no-map;
639 no-map;
644 no-map;
647 q6_cdsp_dtb_mem: q6-cdsp-dtb@9de00000 {
649 no-map;
652 q6_adsp_dtb_mem: q6-adsp-dtb@9de80000 {
654 no-map;
659 no-map;
663 compatible = "qcom,rmtfs-mem";
665 no-map;
667 qcom,client-id = <1>;
672 tz_merged_mem: tz-merged@d8000000 {
674 no-map;
677 hwfence_shbuf: hwfence-shbuf@e6440000 {
679 no-map;
682 trust_ui_vm_mem: trust-ui-vm@f3800000 {
684 no-map;
687 oem_vm_mem: oem-vm@f7c00000 {
689 no-map;
692 llcc_lpi_mem: llcc-lpi@ff800000 {
694 no-map;
698 smp2p-adsp {
701 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
709 qcom,local-pid = <0>;
710 qcom,remote-pid = <2>;
712 smp2p_adsp_out: master-kernel {
713 qcom,entry-name = "master-kernel";
714 #qcom,smem-state-cells = <1>;
717 smp2p_adsp_in: slave-kernel {
718 qcom,entry-name = "slave-kernel";
719 interrupt-controller;
720 #interrupt-cells = <2>;
724 smp2p-cdsp {
727 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
735 qcom,local-pid = <0>;
736 qcom,remote-pid = <5>;
738 smp2p_cdsp_out: master-kernel {
739 qcom,entry-name = "master-kernel";
740 #qcom,smem-state-cells = <1>;
743 smp2p_cdsp_in: slave-kernel {
744 qcom,entry-name = "slave-kernel";
745 interrupt-controller;
746 #interrupt-cells = <2>;
750 smp2p-modem {
753 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
761 qcom,local-pid = <0>;
762 qcom,remote-pid = <1>;
764 smp2p_modem_out: master-kernel {
765 qcom,entry-name = "master-kernel";
766 #qcom,smem-state-cells = <1>;
769 smp2p_modem_in: slave-kernel {
770 qcom,entry-name = "slave-kernel";
771 interrupt-controller;
772 #interrupt-cells = <2>;
775 ipa_smp2p_out: ipa-ap-to-modem {
776 qcom,entry-name = "ipa";
777 #qcom,smem-state-cells = <1>;
780 ipa_smp2p_in: ipa-modem-to-ap {
781 qcom,entry-name = "ipa";
782 interrupt-controller;
783 #interrupt-cells = <2>;
788 compatible = "simple-bus";
790 #address-cells = <2>;
791 #size-cells = <2>;
792 dma-ranges = <0 0 0 0 0x10 0>;
795 gcc: clock-controller@100000 {
796 compatible = "qcom,sm8650-gcc";
810 #clock-cells = <1>;
811 #reset-cells = <1>;
812 #power-domain-cells = <1>;
816 compatible = "qcom,sm8650-ipcc", "qcom,ipcc";
820 interrupt-controller;
821 #interrupt-cells = <3>;
823 #mbox-cells = <2>;
826 gpi_dma2: dma-controller@800000 {
827 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma";
843 dma-channels = <12>;
844 dma-channel-mask = <0x3f>;
845 #dma-cells = <3>;
849 dma-coherent;
855 compatible = "qcom,geni-se-qup";
860 clock-names = "m-ahb",
861 "s-ahb";
865 dma-coherent;
867 #address-cells = <2>;
868 #size-cells = <2>;
874 compatible = "qcom,geni-i2c";
880 clock-names = "se";
888 interconnect-names = "qup-core",
889 "qup-config",
890 "qup-memory";
894 dma-names = "tx",
897 pinctrl-0 = <&qup_i2c8_data_clk>;
898 pinctrl-names = "default";
900 #address-cells = <1>;
901 #size-cells = <0>;
907 compatible = "qcom,geni-spi";
913 clock-names = "se";
921 interconnect-names = "qup-core",
922 "qup-config",
923 "qup-memory";
927 dma-names = "tx",
930 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
931 pinctrl-names = "default";
933 #address-cells = <1>;
934 #size-cells = <0>;
940 compatible = "qcom,geni-i2c";
946 clock-names = "se";
954 interconnect-names = "qup-core",
955 "qup-config",
956 "qup-memory";
960 dma-names = "tx",
963 pinctrl-0 = <&qup_i2c9_data_clk>;
964 pinctrl-names = "default";
966 #address-cells = <1>;
967 #size-cells = <0>;
973 compatible = "qcom,geni-spi";
979 clock-names = "se";
987 interconnect-names = "qup-core",
988 "qup-config",
989 "qup-memory";
993 dma-names = "tx",
996 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
997 pinctrl-names = "default";
999 #address-cells = <1>;
1000 #size-cells = <0>;
1006 compatible = "qcom,geni-i2c";
1012 clock-names = "se";
1020 interconnect-names = "qup-core",
1021 "qup-config",
1022 "qup-memory";
1026 dma-names = "tx",
1029 pinctrl-0 = <&qup_i2c10_data_clk>;
1030 pinctrl-names = "default";
1032 #address-cells = <1>;
1033 #size-cells = <0>;
1039 compatible = "qcom,geni-spi";
1045 clock-names = "se";
1053 interconnect-names = "qup-core",
1054 "qup-config",
1055 "qup-memory";
1059 dma-names = "tx",
1062 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1063 pinctrl-names = "default";
1065 #address-cells = <1>;
1066 #size-cells = <0>;
1072 compatible = "qcom,geni-i2c";
1078 clock-names = "se";
1086 interconnect-names = "qup-core",
1087 "qup-config",
1088 "qup-memory";
1092 dma-names = "tx",
1095 pinctrl-0 = <&qup_i2c11_data_clk>;
1096 pinctrl-names = "default";
1098 #address-cells = <1>;
1099 #size-cells = <0>;
1105 compatible = "qcom,geni-spi";
1111 clock-names = "se";
1119 interconnect-names = "qup-core",
1120 "qup-config",
1121 "qup-memory";
1125 dma-names = "tx",
1128 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1129 pinctrl-names = "default";
1131 #address-cells = <1>;
1132 #size-cells = <0>;
1138 compatible = "qcom,geni-i2c";
1144 clock-names = "se";
1152 interconnect-names = "qup-core",
1153 "qup-config",
1154 "qup-memory";
1158 dma-names = "tx",
1161 pinctrl-0 = <&qup_i2c12_data_clk>;
1162 pinctrl-names = "default";
1164 #address-cells = <1>;
1165 #size-cells = <0>;
1171 compatible = "qcom,geni-spi";
1177 clock-names = "se";
1185 interconnect-names = "qup-core",
1186 "qup-config",
1187 "qup-memory";
1191 dma-names = "tx",
1194 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1195 pinctrl-names = "default";
1197 #address-cells = <1>;
1198 #size-cells = <0>;
1204 compatible = "qcom,geni-i2c";
1210 clock-names = "se";
1218 interconnect-names = "qup-core",
1219 "qup-config",
1220 "qup-memory";
1224 dma-names = "tx",
1227 pinctrl-0 = <&qup_i2c13_data_clk>;
1228 pinctrl-names = "default";
1230 #address-cells = <1>;
1231 #size-cells = <0>;
1237 compatible = "qcom,geni-spi";
1243 clock-names = "se";
1251 interconnect-names = "qup-core",
1252 "qup-config",
1253 "qup-memory";
1257 dma-names = "tx",
1260 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1261 pinctrl-names = "default";
1263 #address-cells = <1>;
1264 #size-cells = <0>;
1270 compatible = "qcom,geni-uart";
1276 clock-names = "se";
1282 interconnect-names = "qup-core",
1283 "qup-config";
1285 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
1286 pinctrl-names = "default";
1292 compatible = "qcom,geni-debug-uart";
1298 clock-names = "se";
1304 interconnect-names = "qup-core",
1305 "qup-config";
1307 pinctrl-0 = <&qup_uart15_default>;
1308 pinctrl-names = "default";
1315 compatible = "qcom,geni-se-i2c-master-hub";
1319 clock-names = "s-ahb";
1321 #address-cells = <2>;
1322 #size-cells = <2>;
1328 compatible = "qcom,geni-i2c-master-hub";
1335 clock-names = "se",
1342 interconnect-names = "qup-core",
1343 "qup-config";
1345 pinctrl-0 = <&hub_i2c0_data_clk>;
1346 pinctrl-names = "default";
1348 #address-cells = <1>;
1349 #size-cells = <0>;
1355 compatible = "qcom,geni-i2c-master-hub";
1362 clock-names = "se",
1369 interconnect-names = "qup-core",
1370 "qup-config";
1372 pinctrl-0 = <&hub_i2c1_data_clk>;
1373 pinctrl-names = "default";
1375 #address-cells = <1>;
1376 #size-cells = <0>;
1382 compatible = "qcom,geni-i2c-master-hub";
1389 clock-names = "se",
1396 interconnect-names = "qup-core",
1397 "qup-config";
1399 pinctrl-0 = <&hub_i2c2_data_clk>;
1400 pinctrl-names = "default";
1402 #address-cells = <1>;
1403 #size-cells = <0>;
1409 compatible = "qcom,geni-i2c-master-hub";
1416 clock-names = "se",
1423 interconnect-names = "qup-core",
1424 "qup-config";
1426 pinctrl-0 = <&hub_i2c3_data_clk>;
1427 pinctrl-names = "default";
1429 #address-cells = <1>;
1430 #size-cells = <0>;
1436 compatible = "qcom,geni-i2c-master-hub";
1443 clock-names = "se",
1450 interconnect-names = "qup-core",
1451 "qup-config";
1453 pinctrl-0 = <&hub_i2c4_data_clk>;
1454 pinctrl-names = "default";
1456 #address-cells = <1>;
1457 #size-cells = <0>;
1463 compatible = "qcom,geni-i2c-master-hub";
1470 clock-names = "se",
1477 interconnect-names = "qup-core",
1478 "qup-config";
1480 pinctrl-0 = <&hub_i2c5_data_clk>;
1481 pinctrl-names = "default";
1483 #address-cells = <1>;
1484 #size-cells = <0>;
1490 compatible = "qcom,geni-i2c-master-hub";
1497 clock-names = "se",
1504 interconnect-names = "qup-core",
1505 "qup-config";
1507 pinctrl-0 = <&hub_i2c6_data_clk>;
1508 pinctrl-names = "default";
1510 #address-cells = <1>;
1511 #size-cells = <0>;
1517 compatible = "qcom,geni-i2c-master-hub";
1524 clock-names = "se",
1531 interconnect-names = "qup-core",
1532 "qup-config";
1534 pinctrl-0 = <&hub_i2c7_data_clk>;
1535 pinctrl-names = "default";
1537 #address-cells = <1>;
1538 #size-cells = <0>;
1544 compatible = "qcom,geni-i2c-master-hub";
1551 clock-names = "se",
1558 interconnect-names = "qup-core",
1559 "qup-config";
1561 pinctrl-0 = <&hub_i2c8_data_clk>;
1562 pinctrl-names = "default";
1564 #address-cells = <1>;
1565 #size-cells = <0>;
1571 compatible = "qcom,geni-i2c-master-hub";
1578 clock-names = "se",
1585 interconnect-names = "qup-core",
1586 "qup-config";
1588 pinctrl-0 = <&hub_i2c9_data_clk>;
1589 pinctrl-names = "default";
1591 #address-cells = <1>;
1592 #size-cells = <0>;
1598 gpi_dma1: dma-controller@a00000 {
1599 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma";
1615 dma-channels = <12>;
1616 dma-channel-mask = <0xc>;
1617 #dma-cells = <3>;
1620 dma-coherent;
1626 compatible = "qcom,geni-se-qup";
1631 clock-names = "m-ahb",
1632 "s-ahb";
1636 interconnect-names = "qup-core";
1640 dma-coherent;
1642 #address-cells = <2>;
1643 #size-cells = <2>;
1649 compatible = "qcom,geni-i2c";
1655 clock-names = "se";
1663 interconnect-names = "qup-core",
1664 "qup-config",
1665 "qup-memory";
1669 dma-names = "tx",
1672 pinctrl-0 = <&qup_i2c0_data_clk>;
1673 pinctrl-names = "default";
1675 #address-cells = <1>;
1676 #size-cells = <0>;
1682 compatible = "qcom,geni-spi";
1688 clock-names = "se";
1696 interconnect-names = "qup-core",
1697 "qup-config",
1698 "qup-memory";
1702 dma-names = "tx",
1705 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1706 pinctrl-names = "default";
1708 #address-cells = <1>;
1709 #size-cells = <0>;
1715 compatible = "qcom,geni-i2c";
1721 clock-names = "se";
1729 interconnect-names = "qup-core",
1730 "qup-config",
1731 "qup-memory";
1735 dma-names = "tx",
1738 pinctrl-0 = <&qup_i2c1_data_clk>;
1739 pinctrl-names = "default";
1741 #address-cells = <1>;
1742 #size-cells = <0>;
1748 compatible = "qcom,geni-spi";
1754 clock-names = "se";
1762 interconnect-names = "qup-core",
1763 "qup-config",
1764 "qup-memory";
1768 dma-names = "tx",
1771 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1772 pinctrl-names = "default";
1774 #address-cells = <1>;
1775 #size-cells = <0>;
1781 compatible = "qcom,geni-i2c";
1787 clock-names = "se";
1795 interconnect-names = "qup-core",
1796 "qup-config",
1797 "qup-memory";
1801 dma-names = "tx",
1804 pinctrl-0 = <&qup_i2c2_data_clk>;
1805 pinctrl-names = "default";
1807 #address-cells = <1>;
1808 #size-cells = <0>;
1814 compatible = "qcom,geni-spi";
1820 clock-names = "se";
1828 interconnect-names = "qup-core",
1829 "qup-config",
1830 "qup-memory";
1834 dma-names = "tx",
1837 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1838 pinctrl-names = "default";
1840 #address-cells = <1>;
1841 #size-cells = <0>;
1847 compatible = "qcom,geni-i2c";
1853 clock-names = "se";
1861 interconnect-names = "qup-core",
1862 "qup-config",
1863 "qup-memory";
1867 dma-names = "tx",
1870 pinctrl-0 = <&qup_i2c3_data_clk>;
1871 pinctrl-names = "default";
1873 #address-cells = <1>;
1874 #size-cells = <0>;
1880 compatible = "qcom,geni-spi";
1886 clock-names = "se";
1894 interconnect-names = "qup-core",
1895 "qup-config",
1896 "qup-memory";
1900 dma-names = "tx",
1903 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1904 pinctrl-names = "default";
1906 #address-cells = <1>;
1907 #size-cells = <0>;
1913 compatible = "qcom,geni-i2c";
1919 clock-names = "se";
1927 interconnect-names = "qup-core",
1928 "qup-config",
1929 "qup-memory";
1933 dma-names = "tx",
1936 pinctrl-0 = <&qup_i2c4_data_clk>;
1937 pinctrl-names = "default";
1939 #address-cells = <1>;
1940 #size-cells = <0>;
1946 compatible = "qcom,geni-spi";
1952 clock-names = "se";
1960 interconnect-names = "qup-core",
1961 "qup-config",
1962 "qup-memory";
1966 dma-names = "tx",
1969 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1970 pinctrl-names = "default";
1972 #address-cells = <1>;
1973 #size-cells = <0>;
1979 compatible = "qcom,geni-i2c";
1985 clock-names = "se";
1993 interconnect-names = "qup-core",
1994 "qup-config",
1995 "qup-memory";
1999 dma-names = "tx",
2002 pinctrl-0 = <&qup_i2c5_data_clk>;
2003 pinctrl-names = "default";
2005 #address-cells = <1>;
2006 #size-cells = <0>;
2012 compatible = "qcom,geni-spi";
2018 clock-names = "se";
2026 interconnect-names = "qup-core",
2027 "qup-config",
2028 "qup-memory";
2032 dma-names = "tx",
2035 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
2036 pinctrl-names = "default";
2038 #address-cells = <1>;
2039 #size-cells = <0>;
2045 compatible = "qcom,geni-i2c";
2051 clock-names = "se";
2059 interconnect-names = "qup-core",
2060 "qup-config",
2061 "qup-memory";
2065 dma-names = "tx",
2068 pinctrl-0 = <&qup_i2c6_data_clk>;
2069 pinctrl-names = "default";
2071 #address-cells = <1>;
2072 #size-cells = <0>;
2078 compatible = "qcom,geni-spi";
2084 clock-names = "se";
2092 interconnect-names = "qup-core",
2093 "qup-config",
2094 "qup-memory";
2098 dma-names = "tx",
2101 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
2102 pinctrl-names = "default";
2104 #address-cells = <1>;
2105 #size-cells = <0>;
2111 compatible = "qcom,geni-i2c";
2117 clock-names = "se";
2125 interconnect-names = "qup-core",
2126 "qup-config",
2127 "qup-memory";
2131 dma-names = "tx",
2134 pinctrl-0 = <&qup_i2c7_data_clk>;
2135 pinctrl-names = "default";
2137 #address-cells = <1>;
2138 #size-cells = <0>;
2144 compatible = "qcom,geni-spi";
2150 clock-names = "se";
2158 interconnect-names = "qup-core",
2159 "qup-config",
2160 "qup-memory";
2164 dma-names = "tx",
2167 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
2168 pinctrl-names = "default";
2170 #address-cells = <1>;
2171 #size-cells = <0>;
2178 compatible = "qcom,sm8650-cnoc-main";
2181 qcom,bcm-voters = <&apps_bcm_voter>;
2183 #interconnect-cells = <2>;
2187 compatible = "qcom,sm8650-config-noc";
2190 qcom,bcm-voters = <&apps_bcm_voter>;
2192 #interconnect-cells = <2>;
2196 compatible = "qcom,sm8650-system-noc";
2199 qcom,bcm-voters = <&apps_bcm_voter>;
2201 #interconnect-cells = <2>;
2205 compatible = "qcom,sm8650-pcie-anoc";
2211 qcom,bcm-voters = <&apps_bcm_voter>;
2213 #interconnect-cells = <2>;
2217 compatible = "qcom,sm8650-aggre1-noc";
2223 qcom,bcm-voters = <&apps_bcm_voter>;
2225 #interconnect-cells = <2>;
2229 compatible = "qcom,sm8650-aggre2-noc";
2234 qcom,bcm-voters = <&apps_bcm_voter>;
2236 #interconnect-cells = <2>;
2240 compatible = "qcom,sm8650-mmss-noc";
2243 qcom,bcm-voters = <&apps_bcm_voter>;
2245 #interconnect-cells = <2>;
2249 compatible = "qcom,sm8650-trng", "qcom,trng";
2253 pcie0: pcie@1c00000 {
2255 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550";
2261 reg-names = "parf", "dbi", "elbi", "atu", "config";
2272 interrupt-names = "msi0",
2290 clock-names = "aux",
2300 reset-names = "pci";
2306 interconnect-names = "pcie-mem",
2307 "cpu-pcie";
2309 power-domains = <&gcc PCIE_0_GDSC>;
2311 iommu-map = <0 &apps_smmu 0x1400 0x1>,
2314 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
2318 interrupt-map-mask = <0 0 0 0x7>;
2319 #interrupt-cells = <1>;
2321 msi-map = <0x0 &gic_its 0x1400 0x1>,
2323 msi-map-mask = <0xff00>;
2325 linux,pci-domain = <0>;
2326 num-lanes = <2>;
2327 bus-range = <0 0xff>;
2330 phy-names = "pciephy";
2332 #address-cells = <3>;
2333 #size-cells = <2>;
2337 dma-coherent;
2341 pcieport0: pcie@0 {
2344 bus-range = <0x01 0xff>;
2346 #address-cells = <3>;
2347 #size-cells = <2>;
2353 compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy";
2361 clock-names = "aux",
2367 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
2368 assigned-clock-rates = <100000000>;
2371 reset-names = "phy";
2373 power-domains = <&gcc PCIE_0_PHY_GDSC>;
2375 #clock-cells = <0>;
2376 clock-output-names = "pcie0_pipe_clk";
2378 #phy-cells = <0>;
2383 pcie1: pcie@1c08000 {
2385 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550";
2391 reg-names = "parf",
2406 interrupt-names = "msi0",
2424 clock-names = "aux",
2433 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2434 assigned-clock-rates = <19200000>;
2438 reset-names = "pci",
2445 interconnect-names = "pcie-mem",
2446 "cpu-pcie";
2448 power-domains = <&gcc PCIE_1_GDSC>;
2450 iommu-map = <0 &apps_smmu 0x1480 0x1>,
2453 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2457 interrupt-map-mask = <0 0 0 0x7>;
2458 #interrupt-cells = <1>;
2460 msi-map = <0x0 &gic_its 0x1480 0x1>,
2462 msi-map-mask = <0xff00>;
2464 linux,pci-domain = <1>;
2465 num-lanes = <2>;
2466 bus-range = <0 0xff>;
2469 phy-names = "pciephy";
2471 dma-coherent;
2473 #address-cells = <3>;
2474 #size-cells = <2>;
2480 pcie@0 {
2483 bus-range = <0x01 0xff>;
2485 #address-cells = <3>;
2486 #size-cells = <2>;
2492 compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy";
2500 clock-names = "aux",
2506 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2507 assigned-clock-rates = <100000000>;
2511 reset-names = "phy",
2514 power-domains = <&gcc PCIE_1_PHY_GDSC>;
2516 #clock-cells = <1>;
2517 clock-output-names = "pcie1_pipe_clk";
2519 #phy-cells = <0>;
2524 cryptobam: dma-controller@1dc4000 {
2525 compatible = "qcom,bam-v1.7.0";
2530 #dma-cells = <1>;
2536 qcom,controlled-remotely;
2540 compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce";
2545 interconnect-names = "memory";
2548 dma-names = "rx", "tx";
2555 compatible = "qcom,sm8650-qmp-ufs-phy";
2561 clock-names = "ref",
2566 reset-names = "ufsphy";
2568 power-domains = <&gcc UFS_MEM_PHY_GDSC>;
2570 #clock-cells = <1>;
2571 #phy-cells = <0>;
2577 compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
2590 clock-names = "core_clk",
2598 freq-table-hz = <100000000 403000000>,
2608 reset-names = "rst";
2614 interconnect-names = "ufs-ddr",
2615 "cpu-ufs";
2617 power-domains = <&gcc UFS_PHY_GDSC>;
2618 required-opps = <&rpmhpd_opp_nom>;
2622 lanes-per-direction = <2>;
2626 phy-names = "ufsphy";
2628 #reset-cells = <1>;
2634 compatible = "qcom,sm8650-inline-crypto-engine",
2635 "qcom,inline-crypto-engine";
2642 compatible = "qcom,tcsr-mutex";
2645 #hwlock-cells = <1>;
2648 tcsr: clock-controller@1fc0000 {
2649 compatible = "qcom,sm8650-tcsr", "syscon";
2654 #clock-cells = <1>;
2655 #reset-cells = <1>;
2659 compatible = "qcom,adreno-43051401", "qcom,adreno";
2663 reg-names = "kgsl_3d0_reg_memory",
2672 operating-points-v2 = <&gpu_opp_table>;
2675 #cooling-cells = <2>;
2679 interconnect-names = "gfx-mem";
2683 zap-shader {
2684 memory-region = <&gpu_micro_code_mem>;
2688 gpu_opp_table: opp-table {
2689 compatible = "operating-points-v2";
2691 opp-231000000 {
2692 opp-hz = /bits/ 64 <231000000>;
2693 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
2694 opp-peak-kBps = <2136718>;
2697 opp-310000000 {
2698 opp-hz = /bits/ 64 <310000000>;
2699 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2700 opp-peak-kBps = <2136718>;
2703 opp-366000000 {
2704 opp-hz = /bits/ 64 <366000000>;
2705 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
2706 opp-peak-kBps = <6074218>;
2709 opp-422000000 {
2710 opp-hz = /bits/ 64 <422000000>;
2711 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2712 opp-peak-kBps = <8171875>;
2715 opp-500000000 {
2716 opp-hz = /bits/ 64 <500000000>;
2717 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
2718 opp-peak-kBps = <8171875>;
2721 opp-578000000 {
2722 opp-hz = /bits/ 64 <578000000>;
2723 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2724 opp-peak-kBps = <8171875>;
2727 opp-629000000 {
2728 opp-hz = /bits/ 64 <629000000>;
2729 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2730 opp-peak-kBps = <10687500>;
2733 opp-680000000 {
2734 opp-hz = /bits/ 64 <680000000>;
2735 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2736 opp-peak-kBps = <12449218>;
2739 opp-720000000 {
2740 opp-hz = /bits/ 64 <720000000>;
2741 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2742 opp-peak-kBps = <12449218>;
2745 opp-770000000 {
2746 opp-hz = /bits/ 64 <770000000>;
2747 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2748 opp-peak-kBps = <12449218>;
2751 opp-834000000 {
2752 opp-hz = /bits/ 64 <834000000>;
2753 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2754 opp-peak-kBps = <14398437>;
2760 compatible = "qcom,adreno-gmu-750.1", "qcom,adreno-gmu";
2764 reg-names = "gmu", "rscc", "gmu_pdc";
2768 interrupt-names = "hfi", "gmu";
2777 clock-names = "ahb",
2785 power-domains = <&gpucc GPU_CX_GDSC>,
2787 power-domain-names = "cx",
2794 operating-points-v2 = <&gmu_opp_table>;
2796 gmu_opp_table: opp-table {
2797 compatible = "operating-points-v2";
2799 opp-260000000 {
2800 opp-hz = /bits/ 64 <260000000>;
2801 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2804 opp-625000000 {
2805 opp-hz = /bits/ 64 <625000000>;
2806 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2811 gpucc: clock-controller@3d90000 {
2812 compatible = "qcom,sm8650-gpucc";
2819 #clock-cells = <1>;
2820 #reset-cells = <1>;
2821 #power-domain-cells = <1>;
2825 compatible = "qcom,sm8650-smmu-500", "qcom,adreno-smmu",
2826 "qcom,smmu-500", "arm,mmu-500";
2828 #iommu-cells = <2>;
2829 #global-interrupts = <1>;
2860 clock-names = "hlos",
2864 power-domains = <&gpucc GPU_CX_GDSC>;
2865 dma-coherent;
2869 compatible = "qcom,sm8650-ipa", "qcom,sm8550-ipa";
2876 reg-names = "ipa-reg",
2877 "ipa-shared",
2880 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
2884 interrupt-names = "ipa",
2886 "ipa-clock-query",
2887 "ipa-setup-ready";
2890 clock-names = "core";
2894 interconnect-names = "memory",
2899 qcom,smem-states = <&ipa_smp2p_out 0>,
2901 qcom,smem-state-names = "ipa-clock-enabled-valid",
2902 "ipa-clock-enabled";
2908 compatible = "qcom,sm8650-mpss-pas";
2911 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2917 interrupt-names = "wdog",
2921 "stop-ack",
2922 "shutdown-ack";
2925 clock-names = "xo";
2930 power-domains = <&rpmhpd RPMHPD_CX>,
2932 power-domain-names = "cx",
2935 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>,
2941 qcom,smem-states = <&smp2p_modem_out 0>;
2942 qcom,smem-state-names = "stop";
2946 glink-edge {
2947 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2954 qcom,remote-pid = <1>;
2961 compatible = "qcom,sm8650-adsp-pas";
2964 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2969 interrupt-names = "wdog",
2973 "stop-ack";
2976 clock-names = "xo";
2981 power-domains = <&rpmhpd RPMHPD_LCX>,
2983 power-domain-names = "lcx",
2986 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
2990 qcom,smem-states = <&smp2p_adsp_out 0>;
2991 qcom,smem-state-names = "stop";
2995 remoteproc_adsp_glink: glink-edge {
2996 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
3003 qcom,remote-pid = <2>;
3010 qcom,glink-channels = "fastrpcglink-apps-dsp";
3014 qcom,non-secure-domain;
3016 #address-cells = <1>;
3017 #size-cells = <0>;
3019 compute-cb@3 {
3020 compatible = "qcom,fastrpc-compute-cb";
3025 dma-coherent;
3028 compute-cb@4 {
3029 compatible = "qcom,fastrpc-compute-cb";
3034 dma-coherent;
3037 compute-cb@5 {
3038 compatible = "qcom,fastrpc-compute-cb";
3043 dma-coherent;
3046 compute-cb@6 {
3047 compatible = "qcom,fastrpc-compute-cb";
3052 dma-coherent;
3055 compute-cb@7 {
3056 compatible = "qcom,fastrpc-compute-cb";
3062 dma-coherent;
3068 qcom,glink-channels = "adsp_apps";
3071 #address-cells = <1>;
3072 #size-cells = <0>;
3077 #sound-dai-cells = <0>;
3078 qcom,protection-domain = "avs/audio",
3082 compatible = "qcom,q6apm-lpass-dais";
3083 #sound-dai-cells = <1>;
3087 compatible = "qcom,q6apm-dais";
3096 qcom,protection-domain = "avs/audio",
3099 q6prmcc: clock-controller {
3100 compatible = "qcom,q6prm-lpass-clocks";
3101 #clock-cells = <2>;
3109 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
3115 clock-names = "mclk",
3120 #clock-cells = <0>;
3121 clock-output-names = "wsa2-mclk";
3122 #sound-dai-cells = <1>;
3126 compatible = "qcom,soundwire-v2.0.0";
3130 clock-names = "iface";
3133 pinctrl-0 = <&wsa2_swr_active>;
3134 pinctrl-names = "default";
3136 qcom,din-ports = <4>;
3137 qcom,dout-ports = <9>;
3139 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
3140 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
3141 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3142 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3143 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3144 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
3145 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
3146 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3147 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3149 #address-cells = <2>;
3150 #size-cells = <0>;
3151 #sound-dai-cells = <1>;
3156 compatible = "qcom,sm8650-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro";
3162 clock-names = "mclk",
3167 #clock-cells = <0>;
3168 clock-output-names = "mclk";
3169 #sound-dai-cells = <1>;
3173 compatible = "qcom,soundwire-v2.0.0";
3177 clock-names = "iface";
3180 pinctrl-0 = <&rx_swr_active>;
3181 pinctrl-names = "default";
3183 qcom,din-ports = <0>;
3184 qcom,dout-ports = <11>;
3186 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x03 0xff 0xff 0x31 0xff 0xff 0xff>;
3187 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x09 0x01 0xff 0xff 0x00 0xff 0xff 0xff>;
3188 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>;
3189 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0xff 0xff 0x00 0xff 0xff 0xff>;
3190 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0xff 0xff 0x0f 0xff 0xff 0xff>;
3191 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0x18 0xff 0xff 0xff>;
3192 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff 0xff 0x01 0xff 0xff 0xff>;
3193 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0x01 0x03 0xff 0xff 0x00 0xff 0xff 0xff>;
3194 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0xff 0xff 0xff>;
3196 #address-cells = <2>;
3197 #size-cells = <0>;
3198 #sound-dai-cells = <1>;
3203 compatible = "qcom,sm8650-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro";
3209 clock-names = "mclk",
3214 #clock-cells = <0>;
3215 clock-output-names = "mclk";
3216 #sound-dai-cells = <1>;
3220 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
3226 clock-names = "mclk",
3231 #clock-cells = <0>;
3232 clock-output-names = "mclk";
3233 #sound-dai-cells = <1>;
3237 compatible = "qcom,soundwire-v2.0.0";
3241 clock-names = "iface";
3244 pinctrl-0 = <&wsa_swr_active>;
3245 pinctrl-names = "default";
3247 qcom,din-ports = <4>;
3248 qcom,dout-ports = <9>;
3250 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
3251 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
3252 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3253 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3254 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3255 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
3256 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
3257 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3258 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3260 #address-cells = <2>;
3261 #size-cells = <0>;
3262 #sound-dai-cells = <1>;
3267 compatible = "qcom,soundwire-v2.0.0";
3271 interrupt-names = "core", "wakeup";
3273 clock-names = "iface";
3276 pinctrl-0 = <&tx_swr_active>;
3277 pinctrl-names = "default";
3279 qcom,din-ports = <4>;
3280 qcom,dout-ports = <0>;
3282 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
3283 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
3284 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
3285 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
3286 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
3287 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
3288 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
3289 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
3290 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
3292 #address-cells = <2>;
3293 #size-cells = <0>;
3294 #sound-dai-cells = <1>;
3299 compatible = "qcom,sm8650-lpass-va-macro", "qcom,sm8550-lpass-va-macro";
3304 clock-names = "mclk",
3308 #clock-cells = <0>;
3309 clock-output-names = "fsgen";
3310 #sound-dai-cells = <1>;
3314 compatible = "qcom,sm8650-lpass-lpi-pinctrl";
3319 clock-names = "core", "audio";
3321 gpio-controller;
3322 #gpio-cells = <2>;
3323 gpio-ranges = <&lpass_tlmm 0 0 23>;
3325 tx_swr_active: tx-swr-active-state {
3326 clk-pins {
3329 drive-strength = <2>;
3330 slew-rate = <1>;
3331 bias-disable;
3334 data-pins {
3337 drive-strength = <2>;
3338 slew-rate = <1>;
3339 bias-bus-hold;
3343 rx_swr_active: rx-swr-active-state {
3344 clk-pins {
3347 drive-strength = <2>;
3348 slew-rate = <1>;
3349 bias-disable;
3352 data-pins {
3355 drive-strength = <2>;
3356 slew-rate = <1>;
3357 bias-bus-hold;
3361 dmic01_default: dmic01-default-state {
3362 clk-pins {
3365 drive-strength = <8>;
3366 output-high;
3369 data-pins {
3372 drive-strength = <8>;
3373 input-enable;
3377 dmic23_default: dmic23-default-state {
3378 clk-pins {
3381 drive-strength = <8>;
3382 output-high;
3385 data-pins {
3388 drive-strength = <8>;
3389 input-enable;
3393 wsa_swr_active: wsa-swr-active-state {
3394 clk-pins {
3397 drive-strength = <2>;
3398 slew-rate = <1>;
3399 bias-disable;
3402 data-pins {
3405 drive-strength = <2>;
3406 slew-rate = <1>;
3407 bias-bus-hold;
3411 wsa2_swr_active: wsa2-swr-active-state {
3412 clk-pins {
3415 drive-strength = <2>;
3416 slew-rate = <1>;
3417 bias-disable;
3420 data-pins {
3423 drive-strength = <2>;
3424 slew-rate = <1>;
3425 bias-bus-hold;
3431 compatible = "qcom,sm8650-lpass-lpiaon-noc";
3434 #interconnect-cells = <2>;
3436 qcom,bcm-voters = <&apps_bcm_voter>;
3440 compatible = "qcom,sm8650-lpass-lpicx-noc";
3443 #interconnect-cells = <2>;
3445 qcom,bcm-voters = <&apps_bcm_voter>;
3449 compatible = "qcom,sm8650-lpass-ag-noc";
3452 #interconnect-cells = <2>;
3454 qcom,bcm-voters = <&apps_bcm_voter>;
3458 compatible = "qcom,sm8650-sdhci", "qcom,sdhci-msm-v5";
3463 interrupt-names = "hc_irq",
3469 clock-names = "iface",
3477 interconnect-names = "sdhc-ddr",
3478 "cpu-sdhc";
3480 power-domains = <&rpmhpd RPMHPD_CX>;
3481 operating-points-v2 = <&sdhc2_opp_table>;
3485 bus-width = <4>;
3487 /* Forbid SDR104/SDR50 - broken hw! */
3488 sdhci-caps-mask = <0x3 0>;
3490 qcom,dll-config = <0x0007642c>;
3491 qcom,ddr-config = <0x80040868>;
3493 dma-coherent;
3497 sdhc2_opp_table: opp-table {
3498 compatible = "operating-points-v2";
3500 opp-19200000 {
3501 opp-hz = /bits/ 64 <19200000>;
3502 required-opps = <&rpmhpd_opp_min_svs>;
3505 opp-50000000 {
3506 opp-hz = /bits/ 64 <50000000>;
3507 required-opps = <&rpmhpd_opp_low_svs>;
3510 opp-100000000 {
3511 opp-hz = /bits/ 64 <100000000>;
3512 required-opps = <&rpmhpd_opp_svs>;
3515 opp-202000000 {
3516 opp-hz = /bits/ 64 <202000000>;
3517 required-opps = <&rpmhpd_opp_svs_l1>;
3522 videocc: clock-controller@aaf0000 {
3523 compatible = "qcom,sm8650-videocc";
3527 power-domains = <&rpmhpd RPMHPD_MMCX>;
3528 #clock-cells = <1>;
3529 #reset-cells = <1>;
3530 #power-domain-cells = <1>;
3534 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
3537 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
3541 clock-names = "camnoc_axi",
3544 pinctrl-0 = <&cci0_0_default &cci0_1_default>;
3545 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
3546 pinctrl-names = "default", "sleep";
3548 #address-cells = <1>;
3549 #size-cells = <0>;
3551 cci0_i2c0: i2c-bus@0 {
3553 clock-frequency = <1000000>;
3554 #address-cells = <1>;
3555 #size-cells = <0>;
3558 cci0_i2c1: i2c-bus@1 {
3560 clock-frequency = <1000000>;
3561 #address-cells = <1>;
3562 #size-cells = <0>;
3567 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
3570 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
3574 clock-names = "camnoc_axi",
3577 pinctrl-0 = <&cci1_0_default &cci1_1_default>;
3578 pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>;
3579 pinctrl-names = "default", "sleep";
3581 #address-cells = <1>;
3582 #size-cells = <0>;
3584 cci1_i2c0: i2c-bus@0 {
3586 clock-frequency = <1000000>;
3587 #address-cells = <1>;
3588 #size-cells = <0>;
3591 cci1_i2c1: i2c-bus@1 {
3593 clock-frequency = <1000000>;
3594 #address-cells = <1>;
3595 #size-cells = <0>;
3600 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
3603 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
3607 clock-names = "camnoc_axi",
3610 pinctrl-0 = <&cci2_0_default &cci2_1_default>;
3611 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>;
3612 pinctrl-names = "default", "sleep";
3614 #address-cells = <1>;
3615 #size-cells = <0>;
3617 cci2_i2c0: i2c-bus@0 {
3619 clock-frequency = <1000000>;
3620 #address-cells = <1>;
3621 #size-cells = <0>;
3624 cci2_i2c1: i2c-bus@1 {
3626 clock-frequency = <1000000>;
3627 #address-cells = <1>;
3628 #size-cells = <0>;
3632 camcc: clock-controller@ade0000 {
3633 compatible = "qcom,sm8650-camcc";
3639 power-domains = <&rpmhpd RPMHPD_MMCX>;
3640 #clock-cells = <1>;
3641 #reset-cells = <1>;
3642 #power-domain-cells = <1>;
3645 mdss: display-subsystem@ae00000 {
3646 compatible = "qcom,sm8650-mdss";
3648 reg-names = "mdss";
3660 interconnect-names = "mdp0-mem";
3662 power-domains = <&dispcc MDSS_GDSC>;
3666 interrupt-controller;
3667 #interrupt-cells = <1>;
3669 #address-cells = <2>;
3670 #size-cells = <2>;
3675 mdss_mdp: display-controller@ae01000 {
3676 compatible = "qcom,sm8650-dpu";
3679 reg-names = "mdp",
3682 interrupts-extended = <&mdss 0>;
3689 clock-names = "nrt_bus",
3695 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3696 assigned-clock-rates = <19200000>;
3698 operating-points-v2 = <&mdp_opp_table>;
3700 power-domains = <&rpmhpd RPMHPD_MMCX>;
3703 #address-cells = <1>;
3704 #size-cells = <0>;
3710 remote-endpoint = <&mdss_dsi0_in>;
3718 remote-endpoint = <&mdss_dsi1_in>;
3726 remote-endpoint = <&mdss_dp0_in>;
3731 mdp_opp_table: opp-table {
3732 compatible = "operating-points-v2";
3734 opp-200000000 {
3735 opp-hz = /bits/ 64 <200000000>;
3736 required-opps = <&rpmhpd_opp_low_svs>;
3739 opp-325000000 {
3740 opp-hz = /bits/ 64 <325000000>;
3741 required-opps = <&rpmhpd_opp_svs>;
3744 opp-375000000 {
3745 opp-hz = /bits/ 64 <375000000>;
3746 required-opps = <&rpmhpd_opp_svs_l1>;
3749 opp-514000000 {
3750 opp-hz = /bits/ 64 <514000000>;
3751 required-opps = <&rpmhpd_opp_nom>;
3757 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3759 reg-names = "dsi_ctrl";
3761 interrupts-extended = <&mdss 4>;
3769 clock-names = "byte",
3776 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
3778 assigned-clock-parents = <&mdss_dsi0_phy 0>,
3781 operating-points-v2 = <&mdss_dsi_opp_table>;
3783 power-domains = <&rpmhpd RPMHPD_MMCX>;
3786 phy-names = "dsi";
3788 #address-cells = <1>;
3789 #size-cells = <0>;
3794 #address-cells = <1>;
3795 #size-cells = <0>;
3801 remote-endpoint = <&dpu_intf1_out>;
3813 mdss_dsi_opp_table: opp-table {
3814 compatible = "operating-points-v2";
3816 opp-187500000 {
3817 opp-hz = /bits/ 64 <187500000>;
3818 required-opps = <&rpmhpd_opp_low_svs>;
3821 opp-300000000 {
3822 opp-hz = /bits/ 64 <300000000>;
3823 required-opps = <&rpmhpd_opp_svs>;
3826 opp-358000000 {
3827 opp-hz = /bits/ 64 <358000000>;
3828 required-opps = <&rpmhpd_opp_svs_l1>;
3834 compatible = "qcom,sm8650-dsi-phy-4nm";
3838 reg-names = "dsi_phy",
3844 clock-names = "iface",
3847 #clock-cells = <1>;
3848 #phy-cells = <0>;
3854 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3856 reg-names = "dsi_ctrl";
3858 interrupts-extended = <&mdss 5>;
3866 clock-names = "byte",
3873 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
3875 assigned-clock-parents = <&mdss_dsi1_phy 0>,
3878 operating-points-v2 = <&mdss_dsi_opp_table>;
3880 power-domains = <&rpmhpd RPMHPD_MMCX>;
3883 phy-names = "dsi";
3885 #address-cells = <1>;
3886 #size-cells = <0>;
3891 #address-cells = <1>;
3892 #size-cells = <0>;
3898 remote-endpoint = <&dpu_intf2_out>;
3912 compatible = "qcom,sm8650-dsi-phy-4nm";
3916 reg-names = "dsi_phy",
3922 clock-names = "iface",
3925 #clock-cells = <1>;
3926 #phy-cells = <0>;
3931 mdss_dp0: displayport-controller@af54000 {
3932 compatible = "qcom,sm8650-dp";
3939 interrupts-extended = <&mdss 12>;
3946 clock-names = "core_iface",
3952 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
3954 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3957 operating-points-v2 = <&dp_opp_table>;
3959 power-domains = <&rpmhpd RPMHPD_MMCX>;
3962 phy-names = "dp";
3964 #sound-dai-cells = <0>;
3968 dp_opp_table: opp-table {
3969 compatible = "operating-points-v2";
3971 opp-162000000 {
3972 opp-hz = /bits/ 64 <162000000>;
3973 required-opps = <&rpmhpd_opp_low_svs_d1>;
3976 opp-270000000 {
3977 opp-hz = /bits/ 64 <270000000>;
3978 required-opps = <&rpmhpd_opp_low_svs>;
3981 opp-540000000 {
3982 opp-hz = /bits/ 64 <540000000>;
3983 required-opps = <&rpmhpd_opp_svs_l1>;
3986 opp-810000000 {
3987 opp-hz = /bits/ 64 <810000000>;
3988 required-opps = <&rpmhpd_opp_nom>;
3993 #address-cells = <1>;
3994 #size-cells = <0>;
4000 remote-endpoint = <&dpu_intf0_out>;
4008 remote-endpoint = <&usb_dp_qmpphy_dp_in>;
4015 dispcc: clock-controller@af00000 {
4016 compatible = "qcom,sm8650-dispcc";
4036 power-domains = <&rpmhpd RPMHPD_MMCX>;
4037 required-opps = <&rpmhpd_opp_low_svs>;
4039 #clock-cells = <1>;
4040 #reset-cells = <1>;
4041 #power-domain-cells = <1>;
4045 compatible = "qcom,sm8650-snps-eusb2-phy",
4046 "qcom,sm8550-snps-eusb2-phy";
4050 clock-names = "ref";
4054 #phy-cells = <0>;
4060 compatible = "qcom,sm8650-qmp-usb3-dp-phy";
4067 clock-names = "aux",
4074 reset-names = "phy",
4077 power-domains = <&gcc USB3_PHY_GDSC>;
4079 #clock-cells = <1>;
4080 #phy-cells = <1>;
4082 orientation-switch;
4087 #address-cells = <1>;
4088 #size-cells = <0>;
4101 remote-endpoint = <&usb_1_dwc3_ss>;
4109 remote-endpoint = <&mdss_dp0_out>;
4116 compatible = "qcom,sm8650-dwc3", "qcom,dwc3";
4119 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4124 interrupt-names = "pwr_event",
4136 clock-names = "cfg_noc",
4143 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4145 assigned-clock-rates = <19200000>, <200000000>;
4149 power-domains = <&gcc USB30_PRIM_GDSC>;
4150 required-opps = <&rpmhpd_opp_nom>;
4152 #address-cells = <2>;
4153 #size-cells = <2>;
4168 phy-names = "usb2-phy",
4169 "usb3-phy";
4171 snps,hird-threshold = /bits/ 8 <0x0>;
4172 snps,usb2-gadget-lpm-disable;
4175 snps,dis-u1-entry-quirk;
4176 snps,dis-u2-entry-quirk;
4177 snps,is-utmi-l1-suspend;
4179 snps,usb2-lpm-disable;
4180 snps,has-lpm-erratum;
4181 tx-fifo-resize;
4183 dma-coherent;
4186 #address-cells = <1>;
4187 #size-cells = <0>;
4200 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
4207 pdc: interrupt-controller@b220000 {
4208 compatible = "qcom,sm8650-pdc", "qcom,pdc";
4211 interrupt-parent = <&intc>;
4213 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
4217 #interrupt-cells = <2>;
4218 interrupt-controller;
4221 tsens0: thermal-sensor@c228000 {
4222 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2";
4228 interrupt-names = "uplow",
4233 #thermal-sensor-cells = <1>;
4236 tsens1: thermal-sensor@c229000 {
4237 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2";
4243 interrupt-names = "uplow",
4248 #thermal-sensor-cells = <1>;
4251 tsens2: thermal-sensor@c22a000 {
4252 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2";
4258 interrupt-names = "uplow",
4263 #thermal-sensor-cells = <1>;
4266 aoss_qmp: power-management@c300000 {
4267 compatible = "qcom,sm8650-aoss-qmp", "qcom,aoss-qmp";
4270 interrupt-parent = <&ipcc>;
4271 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
4276 #clock-cells = <0>;
4280 compatible = "qcom,rpmh-stats";
4285 compatible = "qcom,spmi-pmic-arb";
4291 reg-names = "core",
4297 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4298 interrupt-names = "periph_irq";
4302 qcom,bus-id = <0>;
4304 interrupt-controller;
4305 #interrupt-cells = <4>;
4307 #address-cells = <2>;
4308 #size-cells = <0>;
4312 compatible = "qcom,sm8650-tlmm";
4317 gpio-controller;
4318 #gpio-cells = <2>;
4320 interrupt-controller;
4321 #interrupt-cells = <2>;
4323 gpio-ranges = <&tlmm 0 0 211>;
4325 wakeup-parent = <&pdc>;
4327 cci0_0_default: cci0-0-default-state {
4328 sda-pins {
4331 drive-strength = <2>;
4332 bias-pull-up = <2200>;
4335 scl-pins {
4338 drive-strength = <2>;
4339 bias-pull-up = <2200>;
4343 cci0_0_sleep: cci0-0-sleep-state {
4344 sda-pins {
4347 drive-strength = <2>;
4348 bias-pull-down;
4351 scl-pins {
4354 drive-strength = <2>;
4355 bias-pull-down;
4359 cci0_1_default: cci0-1-default-state {
4360 sda-pins {
4363 drive-strength = <2>;
4364 bias-pull-up = <2200>;
4367 scl-pins {
4370 drive-strength = <2>;
4371 bias-pull-up = <2200>;
4375 cci0_1_sleep: cci0-1-sleep-state {
4376 sda-pins {
4379 drive-strength = <2>;
4380 bias-pull-down;
4383 scl-pins {
4386 drive-strength = <2>;
4387 bias-pull-down;
4391 cci1_0_default: cci1-0-default-state {
4392 sda-pins {
4395 drive-strength = <2>;
4396 bias-pull-up = <2200>;
4399 scl-pins {
4402 drive-strength = <2>;
4403 bias-pull-up = <2200>;
4407 cci1_0_sleep: cci1-0-sleep-state {
4408 sda-pins {
4411 drive-strength = <2>;
4412 bias-pull-down;
4415 scl-pins {
4418 drive-strength = <2>;
4419 bias-pull-down;
4423 cci1_1_default: cci1-1-default-state {
4424 sda-pins {
4427 drive-strength = <2>;
4428 bias-pull-up = <2200>;
4431 scl-pins {
4434 drive-strength = <2>;
4435 bias-pull-up = <2200>;
4439 cci1_1_sleep: cci1-1-sleep-state {
4440 sda-pins {
4443 drive-strength = <2>;
4444 bias-pull-down;
4447 scl-pins {
4450 drive-strength = <2>;
4451 bias-pull-down;
4455 cci2_0_default: cci2-0-default-state {
4456 sda-pins {
4459 drive-strength = <2>;
4460 bias-pull-up = <2200>;
4463 scl-pins {
4466 drive-strength = <2>;
4467 bias-pull-up = <2200>;
4471 cci2_0_sleep: cci2-0-sleep-state {
4472 sda-pins {
4475 drive-strength = <2>;
4476 bias-pull-down;
4479 scl-pins {
4482 drive-strength = <2>;
4483 bias-pull-down;
4487 cci2_1_default: cci2-1-default-state {
4488 sda-pins {
4491 drive-strength = <2>;
4492 bias-pull-up = <2200>;
4495 scl-pins {
4498 drive-strength = <2>;
4499 bias-pull-up = <2200>;
4503 cci2_1_sleep: cci2-1-sleep-state {
4504 sda-pins {
4507 drive-strength = <2>;
4508 bias-pull-down;
4511 scl-pins {
4514 drive-strength = <2>;
4515 bias-pull-down;
4519 hub_i2c0_data_clk: hub-i2c0-data-clk-state {
4523 drive-strength = <2>;
4524 bias-pull-up;
4527 hub_i2c1_data_clk: hub-i2c1-data-clk-state {
4531 drive-strength = <2>;
4532 bias-pull-up;
4535 hub_i2c2_data_clk: hub-i2c2-data-clk-state {
4539 drive-strength = <2>;
4540 bias-pull-up;
4543 hub_i2c3_data_clk: hub-i2c3-data-clk-state {
4547 drive-strength = <2>;
4548 bias-pull-up;
4551 hub_i2c4_data_clk: hub-i2c4-data-clk-state {
4555 drive-strength = <2>;
4556 bias-pull-up;
4559 hub_i2c5_data_clk: hub-i2c5-data-clk-state {
4563 drive-strength = <2>;
4564 bias-pull-up;
4567 hub_i2c6_data_clk: hub-i2c6-data-clk-state {
4571 drive-strength = <2>;
4572 bias-pull-up;
4575 hub_i2c7_data_clk: hub-i2c7-data-clk-state {
4579 drive-strength = <2>;
4580 bias-pull-up;
4583 hub_i2c8_data_clk: hub-i2c8-data-clk-state {
4587 drive-strength = <2>;
4588 bias-pull-up;
4591 hub_i2c9_data_clk: hub-i2c9-data-clk-state {
4595 drive-strength = <2>;
4596 bias-pull-up;
4599 pcie0_default_state: pcie0-default-state {
4600 perst-pins {
4603 drive-strength = <2>;
4604 bias-pull-down;
4607 clkreq-pins {
4610 drive-strength = <2>;
4611 bias-pull-up;
4614 wake-pins {
4617 drive-strength = <2>;
4618 bias-pull-up;
4622 pcie1_default_state: pcie1-default-state {
4623 perst-pins {
4626 drive-strength = <2>;
4627 bias-pull-down;
4630 clkreq-pins {
4633 drive-strength = <2>;
4634 bias-pull-up;
4637 wake-pins {
4640 drive-strength = <2>;
4641 bias-pull-up;
4645 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
4649 drive-strength = <2>;
4650 bias-pull-up;
4653 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
4657 drive-strength = <2>;
4658 bias-pull-up;
4661 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
4665 drive-strength = <2>;
4666 bias-pull-up;
4669 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
4673 drive-strength = <2>;
4674 bias-pull-up;
4677 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
4681 drive-strength = <2>;
4682 bias-pull-up;
4685 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
4689 drive-strength = <2>;
4690 bias-pull-up;
4693 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
4697 drive-strength = <2>;
4698 bias-pull-up;
4701 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
4705 drive-strength = <2>;
4706 bias-pull-up;
4709 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
4713 drive-strength = <2>;
4714 bias-pull-up;
4717 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
4721 drive-strength = <2>;
4722 bias-pull-up;
4725 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
4729 drive-strength = <2>;
4730 bias-pull-up;
4733 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
4737 drive-strength = <2>;
4738 bias-pull-up;
4741 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
4745 drive-strength = <2>;
4746 bias-pull-up;
4749 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
4753 drive-strength = <2>;
4754 bias-pull-up;
4757 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
4761 drive-strength = <2>;
4762 bias-pull-up;
4765 qup_spi0_cs: qup-spi0-cs-state {
4768 drive-strength = <6>;
4769 bias-disable;
4772 qup_spi0_data_clk: qup-spi0-data-clk-state {
4776 drive-strength = <6>;
4777 bias-disable;
4780 qup_spi1_cs: qup-spi1-cs-state {
4783 drive-strength = <6>;
4784 bias-disable;
4787 qup_spi1_data_clk: qup-spi1-data-clk-state {
4791 drive-strength = <6>;
4792 bias-disable;
4795 qup_spi2_cs: qup-spi2-cs-state {
4798 drive-strength = <6>;
4799 bias-disable;
4802 qup_spi2_data_clk: qup-spi2-data-clk-state {
4806 drive-strength = <6>;
4807 bias-disable;
4810 qup_spi3_cs: qup-spi3-cs-state {
4813 drive-strength = <6>;
4814 bias-disable;
4817 qup_spi3_data_clk: qup-spi3-data-clk-state {
4821 drive-strength = <6>;
4822 bias-disable;
4825 qup_spi4_cs: qup-spi4-cs-state {
4828 drive-strength = <6>;
4829 bias-disable;
4832 qup_spi4_data_clk: qup-spi4-data-clk-state {
4836 drive-strength = <6>;
4837 bias-disable;
4840 qup_spi5_cs: qup-spi5-cs-state {
4843 drive-strength = <6>;
4844 bias-disable;
4847 qup_spi5_data_clk: qup-spi5-data-clk-state {
4851 drive-strength = <6>;
4852 bias-disable;
4855 qup_spi6_cs: qup-spi6-cs-state {
4858 drive-strength = <6>;
4859 bias-disable;
4862 qup_spi6_data_clk: qup-spi6-data-clk-state {
4866 drive-strength = <6>;
4867 bias-disable;
4870 qup_spi7_cs: qup-spi7-cs-state {
4873 drive-strength = <6>;
4874 bias-disable;
4877 qup_spi7_data_clk: qup-spi7-data-clk-state {
4881 drive-strength = <6>;
4882 bias-disable;
4885 qup_spi8_cs: qup-spi8-cs-state {
4888 drive-strength = <6>;
4889 bias-disable;
4892 qup_spi8_data_clk: qup-spi8-data-clk-state {
4896 drive-strength = <6>;
4897 bias-disable;
4900 qup_spi9_cs: qup-spi9-cs-state {
4903 drive-strength = <6>;
4904 bias-disable;
4907 qup_spi9_data_clk: qup-spi9-data-clk-state {
4911 drive-strength = <6>;
4912 bias-disable;
4915 qup_spi10_cs: qup-spi10-cs-state {
4918 drive-strength = <6>;
4919 bias-disable;
4922 qup_spi10_data_clk: qup-spi10-data-clk-state {
4926 drive-strength = <6>;
4927 bias-disable;
4930 qup_spi11_cs: qup-spi11-cs-state {
4933 drive-strength = <6>;
4934 bias-disable;
4937 qup_spi11_data_clk: qup-spi11-data-clk-state {
4941 drive-strength = <6>;
4942 bias-disable;
4945 qup_spi12_cs: qup-spi12-cs-state {
4948 drive-strength = <6>;
4949 bias-disable;
4952 qup_spi12_data_clk: qup-spi12-data-clk-state {
4956 drive-strength = <6>;
4957 bias-disable;
4960 qup_spi13_cs: qup-spi13-cs-state {
4963 drive-strength = <6>;
4964 bias-disable;
4967 qup_spi13_data_clk: qup-spi13-data-clk-state {
4971 drive-strength = <6>;
4972 bias-disable;
4975 qup_spi14_cs: qup-spi14-cs-state {
4978 drive-strength = <6>;
4979 bias-disable;
4982 qup_spi14_data_clk: qup-spi14-data-clk-state {
4986 drive-strength = <6>;
4987 bias-disable;
4990 qup_uart14_default: qup-uart14-default-state {
4994 drive-strength = <2>;
4995 bias-pull-up;
4998 qup_uart14_cts_rts: qup-uart14-cts-rts-state {
5002 drive-strength = <2>;
5003 bias-pull-down;
5006 qup_uart15_default: qup-uart15-default-state {
5010 drive-strength = <2>;
5011 bias-disable;
5014 sdc2_sleep: sdc2-sleep-state {
5015 clk-pins {
5017 drive-strength = <2>;
5018 bias-disable;
5021 cmd-pins {
5023 drive-strength = <2>;
5024 bias-pull-up;
5027 data-pins {
5029 drive-strength = <2>;
5030 bias-pull-up;
5034 sdc2_default: sdc2-default-state {
5035 clk-pins {
5037 drive-strength = <16>;
5038 bias-disable;
5041 cmd-pins {
5043 drive-strength = <10>;
5044 bias-pull-up;
5047 data-pins {
5049 drive-strength = <10>;
5050 bias-pull-up;
5056 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
5061 clock-names = "apb_pclk";
5063 in-ports {
5064 #address-cells = <1>;
5065 #size-cells = <0>;
5071 remote-endpoint = <&funnel_apss_out_funnel_in1>;
5076 out-ports {
5079 remote-endpoint = <&funnel_qdss_in_funnel_in1>;
5086 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
5091 clock-names = "apb_pclk";
5093 in-ports {
5094 #address-cells = <1>;
5095 #size-cells = <0>;
5101 remote-endpoint = <&funnel_in1_out_funnel_qdss>;
5106 out-ports {
5109 remote-endpoint = <&funnel_aoss_in_funnel_qdss>;
5116 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
5121 clock-names = "apb_pclk";
5123 in-ports {
5124 #address-cells = <1>;
5125 #size-cells = <0>;
5131 remote-endpoint = <&funnel_qdss_out_funnel_aoss>;
5136 out-ports {
5139 remote-endpoint = <&tmc_etf_in_funnel_aoss>;
5146 compatible = "arm,coresight-tmc", "arm,primecell";
5151 clock-names = "apb_pclk";
5153 in-ports {
5156 remote-endpoint = <&funnel_aoss_out_tmc_etf>;
5163 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
5168 clock-names = "apb_pclk";
5170 in-ports {
5173 remote-endpoint = <&funnel_ete_out_funnel_apss>;
5178 out-ports {
5181 remote-endpoint = <&funnel_in1_in_funnel_apss>;
5188 compatible = "qcom,sm8650-smmu-500", "qcom,smmu-500", "arm,mmu-500";
5289 #iommu-cells = <2>;
5290 #global-interrupts = <1>;
5292 dma-coherent;
5295 intc: interrupt-controller@17100000 {
5296 compatible = "arm,gic-v3";
5302 #interrupt-cells = <3>;
5303 interrupt-controller;
5305 #redistributor-regions = <1>;
5306 redistributor-stride = <0 0x40000>;
5308 #address-cells = <2>;
5309 #size-cells = <2>;
5312 gic_its: msi-controller@17140000 {
5313 compatible = "arm,gic-v3-its";
5316 msi-controller;
5317 #msi-cells = <1>;
5322 compatible = "arm,armv7-timer-mem";
5326 #address-cells = <1>;
5327 #size-cells = <1>;
5336 frame-number = <0>;
5344 frame-number = <1>;
5354 frame-number = <2>;
5364 frame-number = <3>;
5374 frame-number = <4>;
5384 frame-number = <5>;
5394 frame-number = <6>;
5401 compatible = "qcom,rpmh-rsc";
5406 reg-names = "drv-0",
5407 "drv-1",
5408 "drv-2";
5414 power-domains = <&cluster_pd>;
5416 qcom,tcs-offset = <0xd00>;
5417 qcom,drv-id = <2>;
5418 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
5423 apps_bcm_voter: bcm-voter {
5424 compatible = "qcom,bcm-voter";
5427 rpmhcc: clock-controller {
5428 compatible = "qcom,sm8650-rpmh-clk";
5431 clock-names = "xo";
5433 #clock-cells = <1>;
5436 rpmhpd: power-controller {
5437 compatible = "qcom,sm8650-rpmhpd";
5439 operating-points-v2 = <&rpmhpd_opp_table>;
5441 #power-domain-cells = <1>;
5443 rpmhpd_opp_table: opp-table {
5444 compatible = "operating-points-v2";
5446 rpmhpd_opp_ret: opp-16 {
5447 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5450 rpmhpd_opp_min_svs: opp-48 {
5451 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5454 rpmhpd_opp_low_svs_d2: opp-52 {
5455 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
5458 rpmhpd_opp_low_svs_d1: opp-56 {
5459 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
5462 rpmhpd_opp_low_svs_d0: opp-60 {
5463 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
5466 rpmhpd_opp_low_svs: opp-64 {
5467 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5470 rpmhpd_opp_low_svs_l1: opp-80 {
5471 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
5474 rpmhpd_opp_svs: opp-128 {
5475 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5478 rpmhpd_opp_svs_l0: opp-144 {
5479 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
5482 rpmhpd_opp_svs_l1: opp-192 {
5483 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5486 rpmhpd_opp_nom: opp-256 {
5487 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5490 rpmhpd_opp_nom_l1: opp-320 {
5491 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5494 rpmhpd_opp_nom_l2: opp-336 {
5495 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5498 rpmhpd_opp_turbo: opp-384 {
5499 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5502 rpmhpd_opp_turbo_l1: opp-416 {
5503 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5510 compatible = "qcom,sm8650-cpufreq-epss", "qcom,cpufreq-epss";
5515 reg-names = "freq-domain0",
5516 "freq-domain1",
5517 "freq-domain2",
5518 "freq-domain3";
5524 interrupt-names = "dcvsh-irq-0",
5525 "dcvsh-irq-1",
5526 "dcvsh-irq-2",
5527 "dcvsh-irq-3";
5530 clock-names = "xo", "alternate";
5532 #freq-domain-cells = <1>;
5533 #clock-cells = <1>;
5537 compatible = "qcom,sm8650-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
5545 operating-points-v2 = <&llcc_bwmon_opp_table>;
5547 llcc_bwmon_opp_table: opp-table {
5548 compatible = "operating-points-v2";
5550 opp-0 {
5551 opp-peak-kBps = <2086000>;
5554 opp-1 {
5555 opp-peak-kBps = <2929000>;
5558 opp-2 {
5559 opp-peak-kBps = <5931000>;
5562 opp-3 {
5563 opp-peak-kBps = <6515000>;
5566 opp-4 {
5567 opp-peak-kBps = <7980000>;
5570 opp-5 {
5571 opp-peak-kBps = <10437000>;
5574 opp-6 {
5575 opp-peak-kBps = <12157000>;
5578 opp-7 {
5579 opp-peak-kBps = <14060000>;
5582 opp-8 {
5583 opp-peak-kBps = <16113000>;
5589 compatible = "qcom,sm8650-cpu-bwmon", "qcom,sdm845-bwmon";
5597 operating-points-v2 = <&cpu_bwmon_opp_table>;
5599 cpu_bwmon_opp_table: opp-table {
5600 compatible = "operating-points-v2";
5602 opp-0 {
5603 opp-peak-kBps = <4577000>;
5606 opp-1 {
5607 opp-peak-kBps = <7110000>;
5610 opp-2 {
5611 opp-peak-kBps = <9155000>;
5614 opp-3 {
5615 opp-peak-kBps = <12298000>;
5618 opp-4 {
5619 opp-peak-kBps = <14236000>;
5622 opp-5 {
5623 opp-peak-kBps = <16265000>;
5629 compatible = "qcom,sm8650-gem-noc";
5632 qcom,bcm-voters = <&apps_bcm_voter>;
5634 #interconnect-cells = <2>;
5637 system-cache-controller@25000000 {
5638 compatible = "qcom,sm8650-llcc";
5645 reg-names = "llcc0_base",
5656 compatible = "qcom,sm8650-nsp-noc";
5659 qcom,bcm-voters = <&apps_bcm_voter>;
5661 #interconnect-cells = <2>;
5665 compatible = "qcom,sm8650-cdsp-pas";
5668 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
5673 interrupt-names = "wdog",
5677 "stop-ack";
5680 clock-names = "xo";
5685 power-domains = <&rpmhpd RPMHPD_CX>,
5688 power-domain-names = "cx",
5692 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>, <&global_sync_mem>;
5696 qcom,smem-states = <&smp2p_cdsp_out 0>;
5697 qcom,smem-state-names = "stop";
5701 glink-edge {
5702 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
5709 qcom,remote-pid = <5>;
5716 qcom,glink-channels = "fastrpcglink-apps-dsp";
5720 qcom,non-secure-domain;
5722 #address-cells = <1>;
5723 #size-cells = <0>;
5725 compute-cb@1 {
5726 compatible = "qcom,fastrpc-compute-cb";
5732 dma-coherent;
5735 compute-cb@2 {
5736 compatible = "qcom,fastrpc-compute-cb";
5742 dma-coherent;
5745 compute-cb@3 {
5746 compatible = "qcom,fastrpc-compute-cb";
5752 dma-coherent;
5755 compute-cb@4 {
5756 compatible = "qcom,fastrpc-compute-cb";
5762 dma-coherent;
5765 compute-cb@5 {
5766 compatible = "qcom,fastrpc-compute-cb";
5772 dma-coherent;
5775 compute-cb@6 {
5776 compatible = "qcom,fastrpc-compute-cb";
5782 dma-coherent;
5785 compute-cb@7 {
5786 compatible = "qcom,fastrpc-compute-cb";
5792 dma-coherent;
5795 compute-cb@8 {
5796 compatible = "qcom,fastrpc-compute-cb";
5802 dma-coherent;
5807 compute-cb@12 {
5808 compatible = "qcom,fastrpc-compute-cb";
5814 dma-coherent;
5817 compute-cb@13 {
5818 compatible = "qcom,fastrpc-compute-cb";
5824 dma-coherent;
5827 compute-cb@14 {
5828 compatible = "qcom,fastrpc-compute-cb";
5834 dma-coherent;
5841 thermal-zones {
5842 aoss0-thermal {
5843 thermal-sensors = <&tsens0 0>;
5846 trip-point0 {
5852 aoss0-critical {
5860 cpuss0-thermal {
5861 thermal-sensors = <&tsens0 1>;
5864 trip-point0 {
5870 cpuss0-critical {
5878 cpuss1-thermal {
5879 thermal-sensors = <&tsens0 2>;
5882 trip-point0 {
5888 cpuss1-critical {
5896 cpuss2-thermal {
5897 thermal-sensors = <&tsens0 3>;
5900 trip-point0 {
5906 cpuss2-critical {
5914 cpuss3-thermal {
5915 thermal-sensors = <&tsens0 4>;
5918 trip-point0 {
5924 cpuss3-critical {
5932 cpu2-top-thermal {
5933 thermal-sensors = <&tsens0 5>;
5936 trip-point0 {
5942 trip-point1 {
5948 cpu2-critical {
5956 cpu2-bottom-thermal {
5957 thermal-sensors = <&tsens0 6>;
5960 trip-point0 {
5966 trip-point1 {
5972 cpu2-critical {
5980 cpu3-top-thermal {
5981 thermal-sensors = <&tsens0 7>;
5984 trip-point0 {
5990 trip-point1 {
5996 cpu3-critical {
6004 cpu3-bottom-thermal {
6005 thermal-sensors = <&tsens0 8>;
6008 trip-point0 {
6014 trip-point1 {
6020 cpu3-critical {
6028 cpu4-top-thermal {
6029 thermal-sensors = <&tsens0 9>;
6032 trip-point0 {
6038 trip-point1 {
6044 cpu4-critical {
6052 cpu4-bottom-thermal {
6053 thermal-sensors = <&tsens0 10>;
6056 trip-point0 {
6062 trip-point1 {
6068 cpu4-critical {
6076 cpu5-top-thermal {
6077 thermal-sensors = <&tsens0 11>;
6080 trip-point0 {
6086 trip-point1 {
6092 cpu5-critical {
6100 cpu5-bottom-thermal {
6101 thermal-sensors = <&tsens0 12>;
6104 trip-point0 {
6110 trip-point1 {
6116 cpu5-critical {
6124 cpu6-top-thermal {
6125 thermal-sensors = <&tsens0 13>;
6128 trip-point0 {
6134 trip-point1 {
6140 cpu6-critical {
6148 cpu6-bottom-thermal {
6149 thermal-sensors = <&tsens0 14>;
6152 trip-point0 {
6158 trip-point1 {
6164 cpu6-critical {
6172 aoss1-thermal {
6173 thermal-sensors = <&tsens1 0>;
6176 trip-point0 {
6182 aoss1-critical {
6190 cpu7-top-thermal {
6191 thermal-sensors = <&tsens1 1>;
6194 trip-point0 {
6200 trip-point1 {
6206 cpu7-critical {
6214 cpu7-middle-thermal {
6215 thermal-sensors = <&tsens1 2>;
6218 trip-point0 {
6224 trip-point1 {
6230 cpu7-critical {
6238 cpu7-bottom-thermal {
6239 thermal-sensors = <&tsens1 3>;
6242 trip-point0 {
6248 trip-point1 {
6254 cpu7-critical {
6262 cpu0-thermal {
6263 thermal-sensors = <&tsens1 4>;
6266 trip-point0 {
6272 trip-point1 {
6278 cpu0-critical {
6286 cpu1-thermal {
6287 thermal-sensors = <&tsens1 5>;
6290 trip-point0 {
6296 trip-point1 {
6302 cpu1-critical {
6310 nsphvx0-thermal {
6311 polling-delay-passive = <10>;
6313 thermal-sensors = <&tsens2 6>;
6316 trip-point0 {
6322 nsphvx1-critical {
6330 nsphvx1-thermal {
6331 polling-delay-passive = <10>;
6333 thermal-sensors = <&tsens2 7>;
6336 trip-point0 {
6342 nsphvx1-critical {
6350 nsphmx0-thermal {
6351 polling-delay-passive = <10>;
6353 thermal-sensors = <&tsens2 8>;
6356 trip-point0 {
6362 nsphmx0-critical {
6370 nsphmx1-thermal {
6371 polling-delay-passive = <10>;
6373 thermal-sensors = <&tsens2 9>;
6376 trip-point0 {
6382 nsphmx1-critical {
6390 nsphmx2-thermal {
6391 polling-delay-passive = <10>;
6393 thermal-sensors = <&tsens2 10>;
6396 trip-point0 {
6402 nsphmx2-critical {
6410 nsphmx3-thermal {
6411 polling-delay-passive = <10>;
6413 thermal-sensors = <&tsens2 11>;
6416 trip-point0 {
6422 nsphmx3-critical {
6430 video-thermal {
6431 polling-delay-passive = <10>;
6433 thermal-sensors = <&tsens1 12>;
6436 trip-point0 {
6442 video-critical {
6450 ddr-thermal {
6451 polling-delay-passive = <10>;
6453 thermal-sensors = <&tsens1 13>;
6456 trip-point0 {
6462 ddr-critical {
6470 camera0-thermal {
6471 thermal-sensors = <&tsens1 14>;
6474 trip-point0 {
6480 camera0-critical {
6488 camera1-thermal {
6489 thermal-sensors = <&tsens1 15>;
6492 trip-point0 {
6498 camera1-critical {
6506 aoss2-thermal {
6507 thermal-sensors = <&tsens2 0>;
6510 trip-point0 {
6516 aoss2-critical {
6524 gpuss0-thermal {
6525 polling-delay-passive = <10>;
6527 thermal-sensors = <&tsens2 1>;
6529 cooling-maps {
6532 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6537 gpu0_alert0: trip-point0 {
6543 trip-point1 {
6549 trip-point2 {
6557 gpuss1-thermal {
6558 polling-delay-passive = <10>;
6560 thermal-sensors = <&tsens2 2>;
6562 cooling-maps {
6565 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6570 gpu1_alert0: trip-point0 {
6576 trip-point1 {
6582 trip-point2 {
6590 gpuss2-thermal {
6591 polling-delay-passive = <10>;
6593 thermal-sensors = <&tsens2 3>;
6595 cooling-maps {
6598 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6603 gpu2_alert0: trip-point0 {
6609 trip-point1 {
6615 trip-point2 {
6623 gpuss3-thermal {
6624 polling-delay-passive = <10>;
6626 thermal-sensors = <&tsens2 4>;
6628 cooling-maps {
6631 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6636 gpu3_alert0: trip-point0 {
6642 trip-point1 {
6648 trip-point2 {
6656 gpuss4-thermal {
6657 polling-delay-passive = <10>;
6659 thermal-sensors = <&tsens2 5>;
6661 cooling-maps {
6664 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6669 gpu4_alert0: trip-point0 {
6675 trip-point1 {
6681 trip-point2 {
6689 gpuss5-thermal {
6690 polling-delay-passive = <10>;
6692 thermal-sensors = <&tsens2 6>;
6694 cooling-maps {
6697 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6702 gpu5_alert0: trip-point0 {
6708 trip-point1 {
6714 trip-point2 {
6722 gpuss6-thermal {
6723 polling-delay-passive = <10>;
6725 thermal-sensors = <&tsens2 7>;
6727 cooling-maps {
6730 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6735 gpu6_alert0: trip-point0 {
6741 trip-point1 {
6747 trip-point2 {
6755 gpuss7-thermal {
6756 polling-delay-passive = <10>;
6758 thermal-sensors = <&tsens2 8>;
6760 cooling-maps {
6763 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6768 gpu7_alert0: trip-point0 {
6774 trip-point1 {
6780 trip-point2 {
6788 modem0-thermal {
6789 thermal-sensors = <&tsens2 9>;
6792 trip-point0 {
6798 modem0-critical {
6806 modem1-thermal {
6807 thermal-sensors = <&tsens2 10>;
6810 trip-point0 {
6816 modem1-critical {
6824 modem2-thermal {
6825 thermal-sensors = <&tsens2 11>;
6828 trip-point0 {
6834 modem2-critical {
6842 modem3-thermal {
6843 thermal-sensors = <&tsens2 12>;
6846 trip-point0 {
6852 modem3-critical {
6862 compatible = "arm,armv8-timer";