Lines Matching +full:opp +full:- +full:810000000
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
7 #include <dt-bindings/clock/qcom,rpmh.h>
8 #include <dt-bindings/clock/qcom,sm8650-camcc.h>
9 #include <dt-bindings/clock/qcom,sm8650-dispcc.h>
10 #include <dt-bindings/clock/qcom,sm8650-gcc.h>
11 #include <dt-bindings/clock/qcom,sm8650-gpucc.h>
12 #include <dt-bindings/clock/qcom,sm8650-tcsr.h>
13 #include <dt-bindings/clock/qcom,sm8650-videocc.h>
14 #include <dt-bindings/dma/qcom-gpi.h>
15 #include <dt-bindings/firmware/qcom,scm.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interconnect/qcom,icc.h>
18 #include <dt-bindings/interconnect/qcom,sm8650-rpmh.h>
19 #include <dt-bindings/interconnect/qcom,osm-l3.h>
20 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 #include <dt-bindings/mailbox/qcom-ipcc.h>
22 #include <dt-bindings/phy/phy-qcom-qmp.h>
23 #include <dt-bindings/power/qcom,rpmhpd.h>
24 #include <dt-bindings/power/qcom-rpmpd.h>
25 #include <dt-bindings/reset/qcom,sm8650-gpucc.h>
26 #include <dt-bindings/soc/qcom,gpr.h>
27 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
28 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
29 #include <dt-bindings/thermal/thermal.h>
32 interrupt-parent = <&intc>;
34 #address-cells = <2>;
35 #size-cells = <2>;
40 xo_board: xo-board {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
45 sleep_clk: sleep-clk {
46 compatible = "fixed-clock";
47 #clock-cells = <0>;
50 bi_tcxo_div2: bi-tcxo-div2-clk {
51 compatible = "fixed-factor-clock";
52 #clock-cells = <0>;
55 clock-mult = <1>;
56 clock-div = <2>;
59 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
60 compatible = "fixed-factor-clock";
61 #clock-cells = <0>;
64 clock-mult = <1>;
65 clock-div = <2>;
70 #address-cells = <2>;
71 #size-cells = <0>;
75 compatible = "arm,cortex-a520";
80 power-domains = <&cpu_pd0>;
81 power-domain-names = "psci";
83 enable-method = "psci";
84 next-level-cache = <&l2_0>;
85 capacity-dmips-mhz = <1024>;
86 dynamic-power-coefficient = <100>;
88 qcom,freq-domain = <&cpufreq_hw 0>;
90 operating-points-v2 = <&cpu0_opp_table>;
99 #cooling-cells = <2>;
101 l2_0: l2-cache {
103 cache-level = <2>;
104 cache-unified;
105 next-level-cache = <&l3_0>;
107 l3_0: l3-cache {
109 cache-level = <3>;
110 cache-unified;
117 compatible = "arm,cortex-a520";
122 power-domains = <&cpu_pd1>;
123 power-domain-names = "psci";
125 enable-method = "psci";
126 next-level-cache = <&l2_0>;
127 capacity-dmips-mhz = <1024>;
128 dynamic-power-coefficient = <100>;
130 qcom,freq-domain = <&cpufreq_hw 0>;
132 operating-points-v2 = <&cpu0_opp_table>;
141 #cooling-cells = <2>;
146 compatible = "arm,cortex-a720";
151 power-domains = <&cpu_pd2>;
152 power-domain-names = "psci";
154 enable-method = "psci";
155 next-level-cache = <&l2_200>;
156 capacity-dmips-mhz = <1792>;
157 dynamic-power-coefficient = <238>;
159 qcom,freq-domain = <&cpufreq_hw 3>;
161 operating-points-v2 = <&cpu2_opp_table>;
170 #cooling-cells = <2>;
172 l2_200: l2-cache {
174 cache-level = <2>;
175 cache-unified;
176 next-level-cache = <&l3_0>;
182 compatible = "arm,cortex-a720";
187 power-domains = <&cpu_pd3>;
188 power-domain-names = "psci";
190 enable-method = "psci";
191 next-level-cache = <&l2_300>;
192 capacity-dmips-mhz = <1792>;
193 dynamic-power-coefficient = <238>;
195 qcom,freq-domain = <&cpufreq_hw 3>;
197 operating-points-v2 = <&cpu2_opp_table>;
206 #cooling-cells = <2>;
208 l2_300: l2-cache {
210 cache-level = <2>;
211 cache-unified;
212 next-level-cache = <&l3_0>;
218 compatible = "arm,cortex-a720";
223 power-domains = <&cpu_pd4>;
224 power-domain-names = "psci";
226 enable-method = "psci";
227 next-level-cache = <&l2_400>;
228 capacity-dmips-mhz = <1792>;
229 dynamic-power-coefficient = <238>;
231 qcom,freq-domain = <&cpufreq_hw 3>;
233 operating-points-v2 = <&cpu2_opp_table>;
242 #cooling-cells = <2>;
244 l2_400: l2-cache {
246 cache-level = <2>;
247 cache-unified;
248 next-level-cache = <&l3_0>;
254 compatible = "arm,cortex-a720";
259 power-domains = <&cpu_pd5>;
260 power-domain-names = "psci";
262 enable-method = "psci";
263 next-level-cache = <&l2_500>;
264 capacity-dmips-mhz = <1792>;
265 dynamic-power-coefficient = <238>;
267 qcom,freq-domain = <&cpufreq_hw 1>;
269 operating-points-v2 = <&cpu5_opp_table>;
278 #cooling-cells = <2>;
280 l2_500: l2-cache {
282 cache-level = <2>;
283 cache-unified;
284 next-level-cache = <&l3_0>;
290 compatible = "arm,cortex-a720";
295 power-domains = <&cpu_pd6>;
296 power-domain-names = "psci";
298 enable-method = "psci";
299 next-level-cache = <&l2_600>;
300 capacity-dmips-mhz = <1792>;
301 dynamic-power-coefficient = <238>;
303 qcom,freq-domain = <&cpufreq_hw 1>;
305 operating-points-v2 = <&cpu5_opp_table>;
314 #cooling-cells = <2>;
316 l2_600: l2-cache {
318 cache-level = <2>;
319 cache-unified;
320 next-level-cache = <&l3_0>;
326 compatible = "arm,cortex-x4";
331 power-domains = <&cpu_pd7>;
332 power-domain-names = "psci";
334 enable-method = "psci";
335 next-level-cache = <&l2_700>;
336 capacity-dmips-mhz = <1894>;
337 dynamic-power-coefficient = <588>;
339 qcom,freq-domain = <&cpufreq_hw 2>;
341 operating-points-v2 = <&cpu7_opp_table>;
350 #cooling-cells = <2>;
352 l2_700: l2-cache {
354 cache-level = <2>;
355 cache-unified;
356 next-level-cache = <&l3_0>;
360 cpu-map {
396 idle-states {
397 entry-method = "psci";
399 silver_cpu_sleep_0: cpu-sleep-0-0 {
400 compatible = "arm,idle-state";
401 idle-state-name = "silver-rail-power-collapse";
402 arm,psci-suspend-param = <0x40000004>;
403 entry-latency-us = <550>;
404 exit-latency-us = <750>;
405 min-residency-us = <6700>;
406 local-timer-stop;
409 gold_cpu_sleep_0: cpu-sleep-1-0 {
410 compatible = "arm,idle-state";
411 idle-state-name = "gold-rail-power-collapse";
412 arm,psci-suspend-param = <0x40000004>;
413 entry-latency-us = <600>;
414 exit-latency-us = <1300>;
415 min-residency-us = <8136>;
416 local-timer-stop;
419 gold_plus_cpu_sleep_0: cpu-sleep-2-0 {
420 compatible = "arm,idle-state";
421 idle-state-name = "gold-plus-rail-power-collapse";
422 arm,psci-suspend-param = <0x40000004>;
423 entry-latency-us = <500>;
424 exit-latency-us = <1350>;
425 min-residency-us = <7480>;
426 local-timer-stop;
430 domain-idle-states {
431 cluster_sleep_0: cluster-sleep-0 {
432 compatible = "domain-idle-state";
433 arm,psci-suspend-param = <0x41000044>;
434 entry-latency-us = <750>;
435 exit-latency-us = <2350>;
436 min-residency-us = <9144>;
439 cluster_sleep_1: cluster-sleep-1 {
440 compatible = "domain-idle-state";
441 arm,psci-suspend-param = <0x4100c344>;
442 entry-latency-us = <2800>;
443 exit-latency-us = <4400>;
444 min-residency-us = <10150>;
449 ete-0 {
450 compatible = "arm,embedded-trace-extension";
454 out-ports {
457 remote-endpoint = <&funnel_ete_in_ete0>;
463 ete-1 {
464 compatible = "arm,embedded-trace-extension";
468 out-ports {
471 remote-endpoint = <&funnel_ete_in_ete1>;
477 ete-2 {
478 compatible = "arm,embedded-trace-extension";
482 out-ports {
485 remote-endpoint = <&funnel_ete_in_ete2>;
491 ete-3 {
492 compatible = "arm,embedded-trace-extension";
496 out-ports {
499 remote-endpoint = <&funnel_ete_in_ete3>;
505 ete-4 {
506 compatible = "arm,embedded-trace-extension";
510 out-ports {
513 remote-endpoint = <&funnel_ete_in_ete4>;
519 ete-5 {
520 compatible = "arm,embedded-trace-extension";
524 out-ports {
527 remote-endpoint = <&funnel_ete_in_ete5>;
533 ete-6 {
534 compatible = "arm,embedded-trace-extension";
538 out-ports {
541 remote-endpoint = <&funnel_ete_in_ete6>;
547 ete-7 {
548 compatible = "arm,embedded-trace-extension";
552 out-ports {
555 remote-endpoint = <&funnel_ete_in_ete7>;
561 funnel-ete {
562 compatible = "arm,coresight-static-funnel";
564 in-ports {
565 #address-cells = <1>;
566 #size-cells = <0>;
572 remote-endpoint = <&ete0_out_funnel_ete>;
580 remote-endpoint = <&ete1_out_funnel_ete>;
588 remote-endpoint = <&ete2_out_funnel_ete>;
596 remote-endpoint = <&ete3_out_funnel_ete>;
604 remote-endpoint = <&ete4_out_funnel_ete>;
612 remote-endpoint = <&ete5_out_funnel_ete>;
620 remote-endpoint = <&ete6_out_funnel_ete>;
628 remote-endpoint = <&ete7_out_funnel_ete>;
633 out-ports {
636 remote-endpoint = <&funnel_apss_in_funnel_ete>;
644 compatible = "qcom,scm-sm8650", "qcom,scm";
645 qcom,dload-mode = <&tcsr 0x19000>;
651 clk_virt: interconnect-0 {
652 compatible = "qcom,sm8650-clk-virt";
653 #interconnect-cells = <2>;
654 qcom,bcm-voters = <&apps_bcm_voter>;
657 mc_virt: interconnect-1 {
658 compatible = "qcom,sm8650-mc-virt";
659 #interconnect-cells = <2>;
660 qcom,bcm-voters = <&apps_bcm_voter>;
663 qup_opp_table_100mhz: opp-table-qup100mhz {
664 compatible = "operating-points-v2";
666 opp-75000000 {
667 opp-hz = /bits/ 64 <75000000>;
668 required-opps = <&rpmhpd_opp_low_svs>;
671 opp-100000000 {
672 opp-hz = /bits/ 64 <100000000>;
673 required-opps = <&rpmhpd_opp_svs>;
677 qup_opp_table_120mhz: opp-table-qup120mhz {
678 compatible = "operating-points-v2";
680 opp-75000000 {
681 opp-hz = /bits/ 64 <75000000>;
682 required-opps = <&rpmhpd_opp_low_svs>;
685 opp-120000000 {
686 opp-hz = /bits/ 64 <120000000>;
687 required-opps = <&rpmhpd_opp_svs>;
691 qup_opp_table_128mhz: opp-table-qup128mhz {
692 compatible = "operating-points-v2";
694 opp-75000000 {
695 opp-hz = /bits/ 64 <75000000>;
696 required-opps = <&rpmhpd_opp_low_svs>;
699 opp-128000000 {
700 opp-hz = /bits/ 64 <128000000>;
701 required-opps = <&rpmhpd_opp_svs>;
705 qup_opp_table_240mhz: opp-table-qup240mhz {
706 compatible = "operating-points-v2";
708 opp-150000000 {
709 opp-hz = /bits/ 64 <150000000>;
710 required-opps = <&rpmhpd_opp_low_svs>;
713 opp-240000000 {
714 opp-hz = /bits/ 64 <240000000>;
715 required-opps = <&rpmhpd_opp_svs>;
725 cpu0_opp_table: opp-table-cpu0 {
726 compatible = "operating-points-v2";
727 opp-shared;
729 opp-307200000 {
730 opp-hz = /bits/ 64 <307200000>;
731 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
734 opp-364800000 {
735 opp-hz = /bits/ 64 <364800000>;
736 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
739 opp-460800000 {
740 opp-hz = /bits/ 64 <460800000>;
741 opp-peak-kBps = <(300000 * 16) (547000 * 4) (384000 * 32)>;
744 opp-556800000 {
745 opp-hz = /bits/ 64 <556800000>;
746 opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
749 opp-672000000 {
750 opp-hz = /bits/ 64 <672000000>;
751 opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
754 opp-787200000 {
755 opp-hz = /bits/ 64 <787200000>;
756 opp-peak-kBps = <(300000 * 16) (547000 * 4) (729600 * 32)>;
759 opp-902400000 {
760 opp-hz = /bits/ 64 <902400000>;
761 opp-peak-kBps = <(300000 * 16) (547000 * 4) (844800 * 32)>;
764 opp-1017600000 {
765 opp-hz = /bits/ 64 <1017600000>;
766 opp-peak-kBps = <(466000 * 16) (547000 * 4) (940800 * 32)>;
769 opp-1132800000 {
770 opp-hz = /bits/ 64 <1132800000>;
771 opp-peak-kBps = <(466000 * 16) (547000 * 4) (1036800 * 32)>;
774 opp-1248000000 {
775 opp-hz = /bits/ 64 <1248000000>;
776 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1132800 * 32)>;
779 opp-1344000000 {
780 opp-hz = /bits/ 64 <1344000000>;
781 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1248000 * 32)>;
784 opp-1440000000 {
785 opp-hz = /bits/ 64 <1440000000>;
786 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1248000 * 32)>;
789 opp-1459200000 {
790 opp-hz = /bits/ 64 <1459200000>;
791 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1248000 * 32)>;
794 opp-1536000000 {
795 opp-hz = /bits/ 64 <1536000000>;
796 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1440000 * 32)>;
799 opp-1574400000 {
800 opp-hz = /bits/ 64 <1574400000>;
801 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1440000 * 32)>;
804 opp-1651200000 {
805 opp-hz = /bits/ 64 <1651200000>;
806 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1440000 * 32)>;
809 opp-1689600000 {
810 opp-hz = /bits/ 64 <1689600000>;
811 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1440000 * 32)>;
814 opp-1747200000 {
815 opp-hz = /bits/ 64 <1747200000>;
816 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1440000 * 32)>;
819 opp-1804800000 {
820 opp-hz = /bits/ 64 <1804800000>;
821 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1555200 * 32)>;
824 opp-1843200000 {
825 opp-hz = /bits/ 64 <1843200000>;
826 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1555200 * 32)>;
829 opp-1920000000 {
830 opp-hz = /bits/ 64 <1920000000>;
831 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1651200 * 32)>;
834 opp-1939200000 {
835 opp-hz = /bits/ 64 <1939200000>;
836 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1651200 * 32)>;
839 opp-2035200000 {
840 opp-hz = /bits/ 64 <2035200000>;
841 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1843200 * 32)>;
844 opp-2150400000 {
845 opp-hz = /bits/ 64 <2150400000>;
846 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1843200 * 32)>;
849 opp-2265600000 {
850 opp-hz = /bits/ 64 <2265600000>;
851 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (2035200 * 32)>;
855 cpu2_opp_table: opp-table-cpu2 {
856 compatible = "operating-points-v2";
857 opp-shared;
859 opp-460800000 {
860 opp-hz = /bits/ 64 <460800000>;
861 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
864 opp-499200000 {
865 opp-hz = /bits/ 64 <499200000>;
866 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
869 opp-576000000 {
870 opp-hz = /bits/ 64 <576000000>;
871 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
874 opp-614400000 {
875 opp-hz = /bits/ 64 <614400000>;
876 opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
879 opp-691200000 {
880 opp-hz = /bits/ 64 <691200000>;
881 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
884 opp-729600000 {
885 opp-hz = /bits/ 64 <729600000>;
886 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
889 opp-806400000 {
890 opp-hz = /bits/ 64 <806400000>;
891 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
894 opp-844800000 {
895 opp-hz = /bits/ 64 <844800000>;
896 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
899 opp-902400000 {
900 opp-hz = /bits/ 64 <902400000>;
901 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
904 opp-960000000 {
905 opp-hz = /bits/ 64 <960000000>;
906 opp-peak-kBps = <(466000 * 16) (768000 * 4) (844800 * 32)>;
909 opp-1036800000 {
910 opp-hz = /bits/ 64 <1036800000>;
911 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
914 opp-1075200000 {
915 opp-hz = /bits/ 64 <1075200000>;
916 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
919 opp-1152000000 {
920 opp-hz = /bits/ 64 <1152000000>;
921 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
924 opp-1190400000 {
925 opp-hz = /bits/ 64 <1190400000>;
926 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (1036800 * 32)>;
929 opp-1267200000 {
930 opp-hz = /bits/ 64 <1267200000>;
931 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
934 opp-1286400000 {
935 opp-hz = /bits/ 64 <1286400000>;
936 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
939 opp-1382400000 {
940 opp-hz = /bits/ 64 <1382400000>;
941 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
944 opp-1401600000 {
945 opp-hz = /bits/ 64 <1401600000>;
946 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1248000 * 32)>;
949 opp-1497600000 {
950 opp-hz = /bits/ 64 <1497600000>;
951 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
954 opp-1612800000 {
955 opp-hz = /bits/ 64 <1612800000>;
956 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
959 opp-1708800000 {
960 opp-hz = /bits/ 64 <1708800000>;
961 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
964 opp-1728000000 {
965 opp-hz = /bits/ 64 <1728000000>;
966 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
969 opp-1824000000 {
970 opp-hz = /bits/ 64 <1824000000>;
971 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
974 opp-1843200000 {
975 opp-hz = /bits/ 64 <1843200000>;
976 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
979 opp-1920000000 {
980 opp-hz = /bits/ 64 <1920000000>;
981 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1440000 * 32)>;
984 opp-1958400000 {
985 opp-hz = /bits/ 64 <1958400000>;
986 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
989 opp-2035200000 {
990 opp-hz = /bits/ 64 <2035200000>;
991 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
994 opp-2073600000 {
995 opp-hz = /bits/ 64 <2073600000>;
996 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
999 opp-2131200000 {
1000 opp-hz = /bits/ 64 <2131200000>;
1001 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1004 opp-2188800000 {
1005 opp-hz = /bits/ 64 <2188800000>;
1006 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1009 opp-2246400000 {
1010 opp-hz = /bits/ 64 <2246400000>;
1011 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1014 opp-2304000000 {
1015 opp-hz = /bits/ 64 <2304000000>;
1016 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1019 opp-2323200000 {
1020 opp-hz = /bits/ 64 <2323200000>;
1021 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1024 opp-2380800000 {
1025 opp-hz = /bits/ 64 <2380800000>;
1026 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1029 opp-2400000000 {
1030 opp-hz = /bits/ 64 <2400000000>;
1031 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1034 opp-2438400000 {
1035 opp-hz = /bits/ 64 <2438400000>;
1036 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1039 opp-2515200000 {
1040 opp-hz = /bits/ 64 <2515200000>;
1041 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1044 opp-2572800000 {
1045 opp-hz = /bits/ 64 <2572800000>;
1046 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>;
1049 opp-2630400000 {
1050 opp-hz = /bits/ 64 <2630400000>;
1051 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>;
1054 opp-2707200000 {
1055 opp-hz = /bits/ 64 <2707200000>;
1056 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>;
1059 opp-2764800000 {
1060 opp-hz = /bits/ 64 <2764800000>;
1061 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1843200 * 32)>;
1064 opp-2841600000 {
1065 opp-hz = /bits/ 64 <2841600000>;
1066 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
1069 opp-2899200000 {
1070 opp-hz = /bits/ 64 <2899200000>;
1071 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
1074 opp-2956800000 {
1075 opp-hz = /bits/ 64 <2956800000>;
1076 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
1079 opp-3014400000 {
1080 opp-hz = /bits/ 64 <3014400000>;
1081 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
1084 opp-3072000000 {
1085 opp-hz = /bits/ 64 <3072000000>;
1086 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
1089 opp-3148800000 {
1090 opp-hz = /bits/ 64 <3148800000>;
1091 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>;
1095 cpu5_opp_table: opp-table-cpu5 {
1096 compatible = "operating-points-v2";
1097 opp-shared;
1099 opp-460800000 {
1100 opp-hz = /bits/ 64 <460800000>;
1101 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
1104 opp-499200000 {
1105 opp-hz = /bits/ 64 <499200000>;
1106 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
1109 opp-576000000 {
1110 opp-hz = /bits/ 64 <576000000>;
1111 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
1114 opp-614400000 {
1115 opp-hz = /bits/ 64 <614400000>;
1116 opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
1119 opp-691200000 {
1120 opp-hz = /bits/ 64 <691200000>;
1121 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
1124 opp-729600000 {
1125 opp-hz = /bits/ 64 <729600000>;
1126 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
1129 opp-806400000 {
1130 opp-hz = /bits/ 64 <806400000>;
1131 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
1134 opp-844800000 {
1135 opp-hz = /bits/ 64 <844800000>;
1136 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
1139 opp-902400000 {
1140 opp-hz = /bits/ 64 <902400000>;
1141 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
1144 opp-960000000 {
1145 opp-hz = /bits/ 64 <960000000>;
1146 opp-peak-kBps = <(466000 * 16) (768000 * 4) (844800 * 32)>;
1149 opp-1036800000 {
1150 opp-hz = /bits/ 64 <1036800000>;
1151 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
1154 opp-1075200000 {
1155 opp-hz = /bits/ 64 <1075200000>;
1156 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
1159 opp-1152000000 {
1160 opp-hz = /bits/ 64 <1152000000>;
1161 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
1164 opp-1190400000 {
1165 opp-hz = /bits/ 64 <1190400000>;
1166 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (1036800 * 32)>;
1169 opp-1267200000 {
1170 opp-hz = /bits/ 64 <1267200000>;
1171 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
1174 opp-1286400000 {
1175 opp-hz = /bits/ 64 <1286400000>;
1176 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
1179 opp-1382400000 {
1180 opp-hz = /bits/ 64 <1382400000>;
1181 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
1184 opp-1401600000 {
1185 opp-hz = /bits/ 64 <1401600000>;
1186 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1248000 * 32)>;
1189 opp-1497600000 {
1190 opp-hz = /bits/ 64 <1497600000>;
1191 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
1194 opp-1612800000 {
1195 opp-hz = /bits/ 64 <1612800000>;
1196 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
1199 opp-1708800000 {
1200 opp-hz = /bits/ 64 <1708800000>;
1201 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
1204 opp-1728000000 {
1205 opp-hz = /bits/ 64 <1728000000>;
1206 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
1209 opp-1824000000 {
1210 opp-hz = /bits/ 64 <1824000000>;
1211 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
1214 opp-1843200000 {
1215 opp-hz = /bits/ 64 <1843200000>;
1216 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
1219 opp-1920000000 {
1220 opp-hz = /bits/ 64 <1920000000>;
1221 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1440000 * 32)>;
1224 opp-1958400000 {
1225 opp-hz = /bits/ 64 <1958400000>;
1226 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1229 opp-2035200000 {
1230 opp-hz = /bits/ 64 <2035200000>;
1231 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1234 opp-2073600000 {
1235 opp-hz = /bits/ 64 <2073600000>;
1236 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1239 opp-2131200000 {
1240 opp-hz = /bits/ 64 <2131200000>;
1241 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1244 opp-2188800000 {
1245 opp-hz = /bits/ 64 <2188800000>;
1246 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1249 opp-2246400000 {
1250 opp-hz = /bits/ 64 <2246400000>;
1251 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1254 opp-2304000000 {
1255 opp-hz = /bits/ 64 <2304000000>;
1256 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1259 opp-2323200000 {
1260 opp-hz = /bits/ 64 <2323200000>;
1261 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1264 opp-2380800000 {
1265 opp-hz = /bits/ 64 <2380800000>;
1266 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1269 opp-2400000000 {
1270 opp-hz = /bits/ 64 <2400000000>;
1271 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1274 opp-2438400000 {
1275 opp-hz = /bits/ 64 <2438400000>;
1276 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1279 opp-2515200000 {
1280 opp-hz = /bits/ 64 <2515200000>;
1281 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1284 opp-2572800000 {
1285 opp-hz = /bits/ 64 <2572800000>;
1286 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>;
1289 opp-2630400000 {
1290 opp-hz = /bits/ 64 <2630400000>;
1291 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>;
1294 opp-2707200000 {
1295 opp-hz = /bits/ 64 <2707200000>;
1296 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>;
1299 opp-2764800000 {
1300 opp-hz = /bits/ 64 <2764800000>;
1301 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1843200 * 32)>;
1304 opp-2841600000 {
1305 opp-hz = /bits/ 64 <2841600000>;
1306 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
1309 opp-2899200000 {
1310 opp-hz = /bits/ 64 <2899200000>;
1311 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
1314 opp-2956800000 {
1315 opp-hz = /bits/ 64 <2956800000>;
1316 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
1319 opp-3014400000 {
1320 opp-hz = /bits/ 64 <3014400000>;
1321 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
1324 opp-3072000000 {
1325 opp-hz = /bits/ 64 <3072000000>;
1326 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
1329 opp-3148800000 {
1330 opp-hz = /bits/ 64 <3148800000>;
1331 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>;
1335 cpu7_opp_table: opp-table-cpu7 {
1336 compatible = "operating-points-v2";
1337 opp-shared;
1339 opp-480000000 {
1340 opp-hz = /bits/ 64 <480000000>;
1341 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
1344 opp-499200000 {
1345 opp-hz = /bits/ 64 <499200000>;
1346 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
1349 opp-576000000 {
1350 opp-hz = /bits/ 64 <576000000>;
1351 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
1354 opp-614400000 {
1355 opp-hz = /bits/ 64 <614400000>;
1356 opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
1359 opp-672000000 {
1360 opp-hz = /bits/ 64 <672000000>;
1361 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
1364 opp-729600000 {
1365 opp-hz = /bits/ 64 <729600000>;
1366 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
1369 opp-787200000 {
1370 opp-hz = /bits/ 64 <787200000>;
1371 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
1374 opp-844800000 {
1375 opp-hz = /bits/ 64 <844800000>;
1376 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
1379 opp-902400000 {
1380 opp-hz = /bits/ 64 <902400000>;
1381 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
1384 opp-940800000 {
1385 opp-hz = /bits/ 64 <940800000>;
1386 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
1389 opp-1017600000 {
1390 opp-hz = /bits/ 64 <1017600000>;
1391 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
1394 opp-1075200000 {
1395 opp-hz = /bits/ 64 <1075200000>;
1396 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
1399 opp-1132800000 {
1400 opp-hz = /bits/ 64 <1132800000>;
1401 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
1404 opp-1190400000 {
1405 opp-hz = /bits/ 64 <1190400000>;
1406 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (1036800 * 32)>;
1409 opp-1248000000 {
1410 opp-hz = /bits/ 64 <1248000000>;
1411 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
1414 opp-1305600000 {
1415 opp-hz = /bits/ 64 <1305600000>;
1416 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
1419 opp-1363200000 {
1420 opp-hz = /bits/ 64 <1363200000>;
1421 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
1424 opp-1420800000 {
1425 opp-hz = /bits/ 64 <1420800000>;
1426 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1248000 * 32)>;
1429 opp-1478400000 {
1430 opp-hz = /bits/ 64 <1478400000>;
1431 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
1434 opp-1555200000 {
1435 opp-hz = /bits/ 64 <1555200000>;
1436 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
1439 opp-1593600000 {
1440 opp-hz = /bits/ 64 <1593600000>;
1441 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
1444 opp-1670400000 {
1445 opp-hz = /bits/ 64 <1670400000>;
1446 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
1449 opp-1708800000 {
1450 opp-hz = /bits/ 64 <1708800000>;
1451 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
1454 opp-1804800000 {
1455 opp-hz = /bits/ 64 <1804800000>;
1456 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
1459 opp-1824000000 {
1460 opp-hz = /bits/ 64 <1824000000>;
1461 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
1464 opp-1939200000 {
1465 opp-hz = /bits/ 64 <1939200000>;
1466 opp-peak-kBps = <(806000 * 16) (3686000 * 4) (1440000 * 32)>;
1469 opp-2035200000 {
1470 opp-hz = /bits/ 64 <2035200000>;
1471 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1474 opp-2073600000 {
1475 opp-hz = /bits/ 64 <2073600000>;
1476 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1479 opp-2112000000 {
1480 opp-hz = /bits/ 64 <2112000000>;
1481 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1484 opp-2169600000 {
1485 opp-hz = /bits/ 64 <2169600000>;
1486 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1489 opp-2208000000 {
1490 opp-hz = /bits/ 64 <2208000000>;
1491 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1494 opp-2246400000 {
1495 opp-hz = /bits/ 64 <2246400000>;
1496 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1499 opp-2304000000 {
1500 opp-hz = /bits/ 64 <2304000000>;
1501 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1504 opp-2342400000 {
1505 opp-hz = /bits/ 64 <2342400000>;
1506 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1509 opp-2380800000 {
1510 opp-hz = /bits/ 64 <2380800000>;
1511 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1514 opp-2438400000 {
1515 opp-hz = /bits/ 64 <2438400000>;
1516 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1519 opp-2457600000 {
1520 opp-hz = /bits/ 64 <2457600000>;
1521 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1524 opp-2496000000 {
1525 opp-hz = /bits/ 64 <2496000000>;
1526 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1529 opp-2553600000 {
1530 opp-hz = /bits/ 64 <2553600000>;
1531 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
1534 opp-2630400000 {
1535 opp-hz = /bits/ 64 <2630400000>;
1536 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>;
1539 opp-2688000000 {
1540 opp-hz = /bits/ 64 <2688000000>;
1541 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>;
1544 opp-2745600000 {
1545 opp-hz = /bits/ 64 <2745600000>;
1546 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1843200 * 32)>;
1549 opp-2803200000 {
1550 opp-hz = /bits/ 64 <2803200000>;
1551 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
1554 opp-2880000000 {
1555 opp-hz = /bits/ 64 <2880000000>;
1556 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
1559 opp-2937600000 {
1560 opp-hz = /bits/ 64 <2937600000>;
1561 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
1564 opp-2995200000 {
1565 opp-hz = /bits/ 64 <2995200000>;
1566 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
1569 opp-3052800000 {
1570 opp-hz = /bits/ 64 <3052800000>;
1571 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
1574 opp-3187200000 {
1575 opp-hz = /bits/ 64 <3187200000>;
1576 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>;
1579 opp-3302400000 {
1580 opp-hz = /bits/ 64 <3302400000>;
1581 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>;
1585 pmu-a520 {
1586 compatible = "arm,cortex-a520-pmu";
1590 pmu-a720 {
1591 compatible = "arm,cortex-a720-pmu";
1595 pmu-x4 {
1596 compatible = "arm,cortex-x4-pmu";
1601 compatible = "arm,psci-1.0";
1604 cpu_pd0: power-domain-cpu0 {
1605 #power-domain-cells = <0>;
1606 power-domains = <&cluster_pd>;
1607 domain-idle-states = <&silver_cpu_sleep_0>;
1610 cpu_pd1: power-domain-cpu1 {
1611 #power-domain-cells = <0>;
1612 power-domains = <&cluster_pd>;
1613 domain-idle-states = <&silver_cpu_sleep_0>;
1616 cpu_pd2: power-domain-cpu2 {
1617 #power-domain-cells = <0>;
1618 power-domains = <&cluster_pd>;
1619 domain-idle-states = <&gold_cpu_sleep_0>;
1622 cpu_pd3: power-domain-cpu3 {
1623 #power-domain-cells = <0>;
1624 power-domains = <&cluster_pd>;
1625 domain-idle-states = <&gold_cpu_sleep_0>;
1628 cpu_pd4: power-domain-cpu4 {
1629 #power-domain-cells = <0>;
1630 power-domains = <&cluster_pd>;
1631 domain-idle-states = <&gold_cpu_sleep_0>;
1634 cpu_pd5: power-domain-cpu5 {
1635 #power-domain-cells = <0>;
1636 power-domains = <&cluster_pd>;
1637 domain-idle-states = <&gold_cpu_sleep_0>;
1640 cpu_pd6: power-domain-cpu6 {
1641 #power-domain-cells = <0>;
1642 power-domains = <&cluster_pd>;
1643 domain-idle-states = <&gold_cpu_sleep_0>;
1646 cpu_pd7: power-domain-cpu7 {
1647 #power-domain-cells = <0>;
1648 power-domains = <&cluster_pd>;
1649 domain-idle-states = <&gold_plus_cpu_sleep_0>;
1652 cluster_pd: power-domain-cluster {
1653 #power-domain-cells = <0>;
1654 domain-idle-states = <&cluster_sleep_0>,
1659 reserved_memory: reserved-memory {
1660 #address-cells = <2>;
1661 #size-cells = <2>;
1666 no-map;
1669 cpusys_vm_mem: cpusys-vm@80e00000 {
1671 no-map;
1675 xbl_dt_log_merged_mem: xbl-dt-log-merged@81a00000 {
1677 no-map;
1680 aop_cmd_db_mem: aop-cmd-db@81c60000 {
1681 compatible = "qcom,cmd-db";
1683 no-map;
1687 aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 {
1689 no-map;
1698 no-map;
1701 adsp_mhi_mem: adsp-mhi@81f00000 {
1703 no-map;
1708 no-map;
1711 global_sync_mem: global-sync@82600000 {
1713 no-map;
1716 tz_stat_mem: tz-stat@82700000 {
1718 no-map;
1723 no-map;
1726 qlink_logging_mem: qlink-logging@84800000 {
1728 no-map;
1731 mpss_dsm_mem: mpss-dsm@86b00000 {
1733 no-map;
1736 mpss_dsm_mem_2: mpss-dsm-2@8b400000 {
1738 no-map;
1743 no-map;
1746 q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 {
1748 no-map;
1751 ipa_fw_mem: ipa-fw@9b080000 {
1753 no-map;
1756 ipa_gsi_mem: ipa-gsi@9b090000 {
1758 no-map;
1761 gpu_micro_code_mem: gpu-micro-code@9b09a000 {
1763 no-map;
1768 no-map;
1772 spu_tz_shared_mem: spu-tz-shared@9b280000 {
1774 no-map;
1778 spu_modem_shared_mem: spu-modem-shared@9b2e0000 {
1780 no-map;
1785 no-map;
1790 no-map;
1795 no-map;
1800 no-map;
1803 q6_cdsp_dtb_mem: q6-cdsp-dtb@9de00000 {
1805 no-map;
1808 q6_adsp_dtb_mem: q6-adsp-dtb@9de80000 {
1810 no-map;
1815 no-map;
1819 compatible = "qcom,rmtfs-mem";
1821 no-map;
1823 qcom,client-id = <1>;
1828 tz_merged_mem: tz-merged@d8000000 {
1830 no-map;
1833 hwfence_shbuf: hwfence-shbuf@e6440000 {
1835 no-map;
1838 trust_ui_vm_mem: trust-ui-vm@f3800000 {
1840 no-map;
1843 oem_vm_mem: oem-vm@f7c00000 {
1845 no-map;
1848 llcc_lpi_mem: llcc-lpi@ff800000 {
1850 no-map;
1854 smp2p-adsp {
1857 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
1865 qcom,local-pid = <0>;
1866 qcom,remote-pid = <2>;
1868 smp2p_adsp_out: master-kernel {
1869 qcom,entry-name = "master-kernel";
1870 #qcom,smem-state-cells = <1>;
1873 smp2p_adsp_in: slave-kernel {
1874 qcom,entry-name = "slave-kernel";
1875 interrupt-controller;
1876 #interrupt-cells = <2>;
1880 smp2p-cdsp {
1883 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
1891 qcom,local-pid = <0>;
1892 qcom,remote-pid = <5>;
1894 smp2p_cdsp_out: master-kernel {
1895 qcom,entry-name = "master-kernel";
1896 #qcom,smem-state-cells = <1>;
1899 smp2p_cdsp_in: slave-kernel {
1900 qcom,entry-name = "slave-kernel";
1901 interrupt-controller;
1902 #interrupt-cells = <2>;
1906 smp2p-modem {
1909 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
1917 qcom,local-pid = <0>;
1918 qcom,remote-pid = <1>;
1920 smp2p_modem_out: master-kernel {
1921 qcom,entry-name = "master-kernel";
1922 #qcom,smem-state-cells = <1>;
1925 smp2p_modem_in: slave-kernel {
1926 qcom,entry-name = "slave-kernel";
1927 interrupt-controller;
1928 #interrupt-cells = <2>;
1931 ipa_smp2p_out: ipa-ap-to-modem {
1932 qcom,entry-name = "ipa";
1933 #qcom,smem-state-cells = <1>;
1936 ipa_smp2p_in: ipa-modem-to-ap {
1937 qcom,entry-name = "ipa";
1938 interrupt-controller;
1939 #interrupt-cells = <2>;
1944 compatible = "simple-bus";
1946 #address-cells = <2>;
1947 #size-cells = <2>;
1948 dma-ranges = <0 0 0 0 0x10 0>;
1951 gcc: clock-controller@100000 {
1952 compatible = "qcom,sm8650-gcc";
1966 #clock-cells = <1>;
1967 #reset-cells = <1>;
1968 #power-domain-cells = <1>;
1972 compatible = "qcom,sm8650-ipcc", "qcom,ipcc";
1976 interrupt-controller;
1977 #interrupt-cells = <3>;
1979 #mbox-cells = <2>;
1982 gpi_dma2: dma-controller@800000 {
1983 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma";
1999 dma-channels = <12>;
2000 dma-channel-mask = <0x3f>;
2001 #dma-cells = <3>;
2005 dma-coherent;
2011 compatible = "qcom,geni-se-qup";
2016 clock-names = "m-ahb",
2017 "s-ahb";
2021 dma-coherent;
2023 #address-cells = <2>;
2024 #size-cells = <2>;
2030 compatible = "qcom,geni-i2c";
2036 clock-names = "se";
2044 interconnect-names = "qup-core",
2045 "qup-config",
2046 "qup-memory";
2048 power-domains = <&rpmhpd RPMHPD_CX>;
2050 operating-points-v2 = <&qup_opp_table_120mhz>;
2054 dma-names = "tx",
2057 pinctrl-0 = <&qup_i2c8_data_clk>;
2058 pinctrl-names = "default";
2060 #address-cells = <1>;
2061 #size-cells = <0>;
2067 compatible = "qcom,geni-spi";
2073 clock-names = "se";
2081 interconnect-names = "qup-core",
2082 "qup-config",
2083 "qup-memory";
2085 power-domains = <&rpmhpd RPMHPD_CX>;
2087 operating-points-v2 = <&qup_opp_table_100mhz>;
2091 dma-names = "tx",
2094 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
2095 pinctrl-names = "default";
2097 #address-cells = <1>;
2098 #size-cells = <0>;
2104 compatible = "qcom,geni-i2c";
2110 clock-names = "se";
2118 interconnect-names = "qup-core",
2119 "qup-config",
2120 "qup-memory";
2122 power-domains = <&rpmhpd RPMHPD_CX>;
2124 operating-points-v2 = <&qup_opp_table_120mhz>;
2128 dma-names = "tx",
2131 pinctrl-0 = <&qup_i2c9_data_clk>;
2132 pinctrl-names = "default";
2134 #address-cells = <1>;
2135 #size-cells = <0>;
2141 compatible = "qcom,geni-spi";
2147 clock-names = "se";
2155 interconnect-names = "qup-core",
2156 "qup-config",
2157 "qup-memory";
2159 power-domains = <&rpmhpd RPMHPD_CX>;
2161 operating-points-v2 = <&qup_opp_table_120mhz>;
2165 dma-names = "tx",
2168 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
2169 pinctrl-names = "default";
2171 #address-cells = <1>;
2172 #size-cells = <0>;
2178 compatible = "qcom,geni-i2c";
2184 clock-names = "se";
2192 interconnect-names = "qup-core",
2193 "qup-config",
2194 "qup-memory";
2196 power-domains = <&rpmhpd RPMHPD_CX>;
2198 operating-points-v2 = <&qup_opp_table_120mhz>;
2202 dma-names = "tx",
2205 pinctrl-0 = <&qup_i2c10_data_clk>;
2206 pinctrl-names = "default";
2208 #address-cells = <1>;
2209 #size-cells = <0>;
2215 compatible = "qcom,geni-spi";
2221 clock-names = "se";
2229 interconnect-names = "qup-core",
2230 "qup-config",
2231 "qup-memory";
2233 power-domains = <&rpmhpd RPMHPD_CX>;
2235 operating-points-v2 = <&qup_opp_table_120mhz>;
2239 dma-names = "tx",
2242 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
2243 pinctrl-names = "default";
2245 #address-cells = <1>;
2246 #size-cells = <0>;
2252 compatible = "qcom,geni-i2c";
2258 clock-names = "se";
2266 interconnect-names = "qup-core",
2267 "qup-config",
2268 "qup-memory";
2270 power-domains = <&rpmhpd RPMHPD_CX>;
2272 operating-points-v2 = <&qup_opp_table_120mhz>;
2276 dma-names = "tx",
2279 pinctrl-0 = <&qup_i2c11_data_clk>;
2280 pinctrl-names = "default";
2282 #address-cells = <1>;
2283 #size-cells = <0>;
2289 compatible = "qcom,geni-spi";
2295 clock-names = "se";
2303 interconnect-names = "qup-core",
2304 "qup-config",
2305 "qup-memory";
2307 power-domains = <&rpmhpd RPMHPD_CX>;
2309 operating-points-v2 = <&qup_opp_table_120mhz>;
2313 dma-names = "tx",
2316 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
2317 pinctrl-names = "default";
2319 #address-cells = <1>;
2320 #size-cells = <0>;
2326 compatible = "qcom,geni-i2c";
2332 clock-names = "se";
2340 interconnect-names = "qup-core",
2341 "qup-config",
2342 "qup-memory";
2344 power-domains = <&rpmhpd RPMHPD_CX>;
2346 operating-points-v2 = <&qup_opp_table_100mhz>;
2350 dma-names = "tx",
2353 pinctrl-0 = <&qup_i2c12_data_clk>;
2354 pinctrl-names = "default";
2356 #address-cells = <1>;
2357 #size-cells = <0>;
2363 compatible = "qcom,geni-spi";
2369 clock-names = "se";
2377 interconnect-names = "qup-core",
2378 "qup-config",
2379 "qup-memory";
2381 power-domains = <&rpmhpd RPMHPD_CX>;
2383 operating-points-v2 = <&qup_opp_table_100mhz>;
2387 dma-names = "tx",
2390 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
2391 pinctrl-names = "default";
2393 #address-cells = <1>;
2394 #size-cells = <0>;
2400 compatible = "qcom,geni-i2c";
2406 clock-names = "se";
2414 interconnect-names = "qup-core",
2415 "qup-config",
2416 "qup-memory";
2418 power-domains = <&rpmhpd RPMHPD_CX>;
2420 operating-points-v2 = <&qup_opp_table_100mhz>;
2424 dma-names = "tx",
2427 pinctrl-0 = <&qup_i2c13_data_clk>;
2428 pinctrl-names = "default";
2430 #address-cells = <1>;
2431 #size-cells = <0>;
2437 compatible = "qcom,geni-spi";
2443 clock-names = "se";
2451 interconnect-names = "qup-core",
2452 "qup-config",
2453 "qup-memory";
2455 power-domains = <&rpmhpd RPMHPD_CX>;
2457 operating-points-v2 = <&qup_opp_table_100mhz>;
2461 dma-names = "tx",
2464 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
2465 pinctrl-names = "default";
2467 #address-cells = <1>;
2468 #size-cells = <0>;
2474 compatible = "qcom,geni-uart";
2480 clock-names = "se";
2486 interconnect-names = "qup-core",
2487 "qup-config";
2489 power-domains = <&rpmhpd RPMHPD_CX>;
2491 operating-points-v2 = <&qup_opp_table_128mhz>;
2493 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
2494 pinctrl-names = "default";
2500 compatible = "qcom,geni-debug-uart";
2506 clock-names = "se";
2512 interconnect-names = "qup-core",
2513 "qup-config";
2515 power-domains = <&rpmhpd RPMHPD_CX>;
2517 operating-points-v2 = <&qup_opp_table_100mhz>;
2519 pinctrl-0 = <&qup_uart15_default>;
2520 pinctrl-names = "default";
2527 compatible = "qcom,geni-se-i2c-master-hub";
2531 clock-names = "s-ahb";
2533 #address-cells = <2>;
2534 #size-cells = <2>;
2540 compatible = "qcom,geni-i2c-master-hub";
2547 clock-names = "se",
2554 interconnect-names = "qup-core",
2555 "qup-config";
2557 power-domains = <&rpmhpd RPMHPD_CX>;
2559 required-opps = <&rpmhpd_opp_low_svs>;
2561 pinctrl-0 = <&hub_i2c0_data_clk>;
2562 pinctrl-names = "default";
2564 #address-cells = <1>;
2565 #size-cells = <0>;
2571 compatible = "qcom,geni-i2c-master-hub";
2578 clock-names = "se",
2585 interconnect-names = "qup-core",
2586 "qup-config";
2588 power-domains = <&rpmhpd RPMHPD_CX>;
2590 required-opps = <&rpmhpd_opp_low_svs>;
2592 pinctrl-0 = <&hub_i2c1_data_clk>;
2593 pinctrl-names = "default";
2595 #address-cells = <1>;
2596 #size-cells = <0>;
2602 compatible = "qcom,geni-i2c-master-hub";
2609 clock-names = "se",
2616 interconnect-names = "qup-core",
2617 "qup-config";
2619 power-domains = <&rpmhpd RPMHPD_CX>;
2621 required-opps = <&rpmhpd_opp_low_svs>;
2623 pinctrl-0 = <&hub_i2c2_data_clk>;
2624 pinctrl-names = "default";
2626 #address-cells = <1>;
2627 #size-cells = <0>;
2633 compatible = "qcom,geni-i2c-master-hub";
2640 clock-names = "se",
2647 interconnect-names = "qup-core",
2648 "qup-config";
2650 power-domains = <&rpmhpd RPMHPD_CX>;
2652 required-opps = <&rpmhpd_opp_low_svs>;
2654 pinctrl-0 = <&hub_i2c3_data_clk>;
2655 pinctrl-names = "default";
2657 #address-cells = <1>;
2658 #size-cells = <0>;
2664 compatible = "qcom,geni-i2c-master-hub";
2671 clock-names = "se",
2678 interconnect-names = "qup-core",
2679 "qup-config";
2681 power-domains = <&rpmhpd RPMHPD_CX>;
2683 required-opps = <&rpmhpd_opp_low_svs>;
2685 pinctrl-0 = <&hub_i2c4_data_clk>;
2686 pinctrl-names = "default";
2688 #address-cells = <1>;
2689 #size-cells = <0>;
2695 compatible = "qcom,geni-i2c-master-hub";
2702 clock-names = "se",
2709 interconnect-names = "qup-core",
2710 "qup-config";
2712 power-domains = <&rpmhpd RPMHPD_CX>;
2714 required-opps = <&rpmhpd_opp_low_svs>;
2716 pinctrl-0 = <&hub_i2c5_data_clk>;
2717 pinctrl-names = "default";
2719 #address-cells = <1>;
2720 #size-cells = <0>;
2726 compatible = "qcom,geni-i2c-master-hub";
2733 clock-names = "se",
2740 interconnect-names = "qup-core",
2741 "qup-config";
2743 power-domains = <&rpmhpd RPMHPD_CX>;
2745 required-opps = <&rpmhpd_opp_low_svs>;
2747 pinctrl-0 = <&hub_i2c6_data_clk>;
2748 pinctrl-names = "default";
2750 #address-cells = <1>;
2751 #size-cells = <0>;
2757 compatible = "qcom,geni-i2c-master-hub";
2764 clock-names = "se",
2771 interconnect-names = "qup-core",
2772 "qup-config";
2774 power-domains = <&rpmhpd RPMHPD_CX>;
2776 required-opps = <&rpmhpd_opp_low_svs>;
2778 pinctrl-0 = <&hub_i2c7_data_clk>;
2779 pinctrl-names = "default";
2781 #address-cells = <1>;
2782 #size-cells = <0>;
2788 compatible = "qcom,geni-i2c-master-hub";
2795 clock-names = "se",
2802 interconnect-names = "qup-core",
2803 "qup-config";
2805 power-domains = <&rpmhpd RPMHPD_CX>;
2807 required-opps = <&rpmhpd_opp_low_svs>;
2809 pinctrl-0 = <&hub_i2c8_data_clk>;
2810 pinctrl-names = "default";
2812 #address-cells = <1>;
2813 #size-cells = <0>;
2819 compatible = "qcom,geni-i2c-master-hub";
2826 clock-names = "se",
2833 interconnect-names = "qup-core",
2834 "qup-config";
2836 power-domains = <&rpmhpd RPMHPD_CX>;
2838 required-opps = <&rpmhpd_opp_low_svs>;
2840 pinctrl-0 = <&hub_i2c9_data_clk>;
2841 pinctrl-names = "default";
2843 #address-cells = <1>;
2844 #size-cells = <0>;
2850 gpi_dma1: dma-controller@a00000 {
2851 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma";
2867 dma-channels = <12>;
2868 dma-channel-mask = <0xc>;
2869 #dma-cells = <3>;
2872 dma-coherent;
2878 compatible = "qcom,geni-se-qup";
2883 clock-names = "m-ahb",
2884 "s-ahb";
2888 interconnect-names = "qup-core";
2892 dma-coherent;
2894 #address-cells = <2>;
2895 #size-cells = <2>;
2901 compatible = "qcom,geni-i2c";
2907 clock-names = "se";
2915 interconnect-names = "qup-core",
2916 "qup-config",
2917 "qup-memory";
2919 power-domains = <&rpmhpd RPMHPD_CX>;
2921 operating-points-v2 = <&qup_opp_table_120mhz>;
2925 dma-names = "tx",
2928 pinctrl-0 = <&qup_i2c0_data_clk>;
2929 pinctrl-names = "default";
2931 #address-cells = <1>;
2932 #size-cells = <0>;
2938 compatible = "qcom,geni-spi";
2944 clock-names = "se";
2952 interconnect-names = "qup-core",
2953 "qup-config",
2954 "qup-memory";
2956 power-domains = <&rpmhpd RPMHPD_CX>;
2958 operating-points-v2 = <&qup_opp_table_120mhz>;
2962 dma-names = "tx",
2965 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
2966 pinctrl-names = "default";
2968 #address-cells = <1>;
2969 #size-cells = <0>;
2975 compatible = "qcom,geni-i2c";
2981 clock-names = "se";
2989 interconnect-names = "qup-core",
2990 "qup-config",
2991 "qup-memory";
2993 power-domains = <&rpmhpd RPMHPD_CX>;
2995 operating-points-v2 = <&qup_opp_table_120mhz>;
2999 dma-names = "tx",
3002 pinctrl-0 = <&qup_i2c1_data_clk>;
3003 pinctrl-names = "default";
3005 #address-cells = <1>;
3006 #size-cells = <0>;
3012 compatible = "qcom,geni-spi";
3018 clock-names = "se";
3026 interconnect-names = "qup-core",
3027 "qup-config",
3028 "qup-memory";
3030 power-domains = <&rpmhpd RPMHPD_CX>;
3032 operating-points-v2 = <&qup_opp_table_120mhz>;
3036 dma-names = "tx",
3039 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
3040 pinctrl-names = "default";
3042 #address-cells = <1>;
3043 #size-cells = <0>;
3049 compatible = "qcom,geni-i2c";
3055 clock-names = "se";
3063 interconnect-names = "qup-core",
3064 "qup-config",
3065 "qup-memory";
3067 power-domains = <&rpmhpd RPMHPD_CX>;
3069 operating-points-v2 = <&qup_opp_table_240mhz>;
3073 dma-names = "tx",
3076 pinctrl-0 = <&qup_i2c2_data_clk>;
3077 pinctrl-names = "default";
3079 #address-cells = <1>;
3080 #size-cells = <0>;
3086 compatible = "qcom,geni-spi";
3092 clock-names = "se";
3100 interconnect-names = "qup-core",
3101 "qup-config",
3102 "qup-memory";
3104 power-domains = <&rpmhpd RPMHPD_CX>;
3106 operating-points-v2 = <&qup_opp_table_240mhz>;
3110 dma-names = "tx",
3113 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
3114 pinctrl-names = "default";
3116 #address-cells = <1>;
3117 #size-cells = <0>;
3123 compatible = "qcom,geni-i2c";
3129 clock-names = "se";
3137 interconnect-names = "qup-core",
3138 "qup-config",
3139 "qup-memory";
3141 power-domains = <&rpmhpd RPMHPD_CX>;
3143 operating-points-v2 = <&qup_opp_table_100mhz>;
3147 dma-names = "tx",
3150 pinctrl-0 = <&qup_i2c3_data_clk>;
3151 pinctrl-names = "default";
3153 #address-cells = <1>;
3154 #size-cells = <0>;
3160 compatible = "qcom,geni-spi";
3166 clock-names = "se";
3174 interconnect-names = "qup-core",
3175 "qup-config",
3176 "qup-memory";
3178 power-domains = <&rpmhpd RPMHPD_CX>;
3180 operating-points-v2 = <&qup_opp_table_100mhz>;
3184 dma-names = "tx",
3187 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
3188 pinctrl-names = "default";
3190 #address-cells = <1>;
3191 #size-cells = <0>;
3197 compatible = "qcom,geni-i2c";
3203 clock-names = "se";
3211 interconnect-names = "qup-core",
3212 "qup-config",
3213 "qup-memory";
3215 power-domains = <&rpmhpd RPMHPD_CX>;
3217 operating-points-v2 = <&qup_opp_table_120mhz>;
3221 dma-names = "tx",
3224 pinctrl-0 = <&qup_i2c4_data_clk>;
3225 pinctrl-names = "default";
3227 #address-cells = <1>;
3228 #size-cells = <0>;
3234 compatible = "qcom,geni-spi";
3240 clock-names = "se";
3248 interconnect-names = "qup-core",
3249 "qup-config",
3250 "qup-memory";
3252 power-domains = <&rpmhpd RPMHPD_CX>;
3254 operating-points-v2 = <&qup_opp_table_120mhz>;
3258 dma-names = "tx",
3261 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
3262 pinctrl-names = "default";
3264 #address-cells = <1>;
3265 #size-cells = <0>;
3271 compatible = "qcom,geni-i2c";
3277 clock-names = "se";
3285 interconnect-names = "qup-core",
3286 "qup-config",
3287 "qup-memory";
3289 power-domains = <&rpmhpd RPMHPD_CX>;
3291 operating-points-v2 = <&qup_opp_table_100mhz>;
3295 dma-names = "tx",
3298 pinctrl-0 = <&qup_i2c5_data_clk>;
3299 pinctrl-names = "default";
3301 #address-cells = <1>;
3302 #size-cells = <0>;
3308 compatible = "qcom,geni-spi";
3314 clock-names = "se";
3322 interconnect-names = "qup-core",
3323 "qup-config",
3324 "qup-memory";
3326 power-domains = <&rpmhpd RPMHPD_CX>;
3328 operating-points-v2 = <&qup_opp_table_100mhz>;
3332 dma-names = "tx",
3335 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
3336 pinctrl-names = "default";
3338 #address-cells = <1>;
3339 #size-cells = <0>;
3345 compatible = "qcom,geni-i2c";
3351 clock-names = "se";
3359 interconnect-names = "qup-core",
3360 "qup-config",
3361 "qup-memory";
3363 power-domains = <&rpmhpd RPMHPD_CX>;
3365 operating-points-v2 = <&qup_opp_table_120mhz>;
3369 dma-names = "tx",
3372 pinctrl-0 = <&qup_i2c6_data_clk>;
3373 pinctrl-names = "default";
3375 #address-cells = <1>;
3376 #size-cells = <0>;
3382 compatible = "qcom,geni-spi";
3388 clock-names = "se";
3396 interconnect-names = "qup-core",
3397 "qup-config",
3398 "qup-memory";
3400 power-domains = <&rpmhpd RPMHPD_CX>;
3402 operating-points-v2 = <&qup_opp_table_120mhz>;
3406 dma-names = "tx",
3409 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
3410 pinctrl-names = "default";
3412 #address-cells = <1>;
3413 #size-cells = <0>;
3419 compatible = "qcom,geni-i2c";
3425 clock-names = "se";
3433 interconnect-names = "qup-core",
3434 "qup-config",
3435 "qup-memory";
3437 power-domains = <&rpmhpd RPMHPD_CX>;
3439 operating-points-v2 = <&qup_opp_table_100mhz>;
3443 dma-names = "tx",
3446 pinctrl-0 = <&qup_i2c7_data_clk>;
3447 pinctrl-names = "default";
3449 #address-cells = <1>;
3450 #size-cells = <0>;
3456 compatible = "qcom,geni-spi";
3462 clock-names = "se";
3470 interconnect-names = "qup-core",
3471 "qup-config",
3472 "qup-memory";
3474 power-domains = <&rpmhpd RPMHPD_CX>;
3476 operating-points-v2 = <&qup_opp_table_100mhz>;
3480 dma-names = "tx",
3483 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
3484 pinctrl-names = "default";
3486 #address-cells = <1>;
3487 #size-cells = <0>;
3494 compatible = "qcom,sm8650-cnoc-main";
3497 qcom,bcm-voters = <&apps_bcm_voter>;
3499 #interconnect-cells = <2>;
3503 compatible = "qcom,sm8650-config-noc";
3506 qcom,bcm-voters = <&apps_bcm_voter>;
3508 #interconnect-cells = <2>;
3512 compatible = "qcom,sm8650-system-noc";
3515 qcom,bcm-voters = <&apps_bcm_voter>;
3517 #interconnect-cells = <2>;
3521 compatible = "qcom,sm8650-pcie-anoc";
3527 qcom,bcm-voters = <&apps_bcm_voter>;
3529 #interconnect-cells = <2>;
3533 compatible = "qcom,sm8650-aggre1-noc";
3539 qcom,bcm-voters = <&apps_bcm_voter>;
3541 #interconnect-cells = <2>;
3545 compatible = "qcom,sm8650-aggre2-noc";
3550 qcom,bcm-voters = <&apps_bcm_voter>;
3552 #interconnect-cells = <2>;
3556 compatible = "qcom,sm8650-mmss-noc";
3559 qcom,bcm-voters = <&apps_bcm_voter>;
3561 #interconnect-cells = <2>;
3565 compatible = "qcom,sm8650-trng", "qcom,trng";
3571 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550";
3577 reg-names = "parf", "dbi", "elbi", "atu", "config";
3588 interrupt-names = "msi0",
3606 clock-names = "aux",
3616 reset-names = "pci";
3622 interconnect-names = "pcie-mem",
3623 "cpu-pcie";
3625 power-domains = <&gcc PCIE_0_GDSC>;
3627 operating-points-v2 = <&pcie0_opp_table>;
3629 iommu-map = <0 &apps_smmu 0x1400 0x1>,
3632 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH 0>,
3636 interrupt-map-mask = <0 0 0 0x7>;
3637 #interrupt-cells = <1>;
3639 msi-map = <0x0 &gic_its 0x1400 0x1>,
3641 msi-map-mask = <0xff00>;
3643 linux,pci-domain = <0>;
3644 num-lanes = <2>;
3645 bus-range = <0 0xff>;
3648 phy-names = "pciephy";
3650 #address-cells = <3>;
3651 #size-cells = <2>;
3655 dma-coherent;
3659 pcie0_opp_table: opp-table {
3660 compatible = "operating-points-v2";
3663 opp-2500000 {
3664 opp-hz = /bits/ 64 <2500000>;
3665 required-opps = <&rpmhpd_opp_low_svs>;
3666 opp-peak-kBps = <250000 1>;
3670 opp-5000000 {
3671 opp-hz = /bits/ 64 <5000000>;
3672 required-opps = <&rpmhpd_opp_low_svs>;
3673 opp-peak-kBps = <500000 1>;
3677 opp-10000000 {
3678 opp-hz = /bits/ 64 <10000000>;
3679 required-opps = <&rpmhpd_opp_low_svs>;
3680 opp-peak-kBps = <1000000 1>;
3684 opp-8000000 {
3685 opp-hz = /bits/ 64 <8000000>;
3686 required-opps = <&rpmhpd_opp_nom>;
3687 opp-peak-kBps = <984500 1>;
3691 opp-16000000 {
3692 opp-hz = /bits/ 64 <16000000>;
3693 required-opps = <&rpmhpd_opp_nom>;
3694 opp-peak-kBps = <1969000 1>;
3701 bus-range = <0x01 0xff>;
3703 #address-cells = <3>;
3704 #size-cells = <2>;
3710 compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy";
3718 clock-names = "aux",
3724 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
3725 assigned-clock-rates = <100000000>;
3728 reset-names = "phy";
3730 power-domains = <&gcc PCIE_0_PHY_GDSC>;
3732 #clock-cells = <0>;
3733 clock-output-names = "pcie0_pipe_clk";
3735 #phy-cells = <0>;
3742 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550";
3748 reg-names = "parf",
3763 interrupt-names = "msi0",
3781 clock-names = "aux",
3790 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
3791 assigned-clock-rates = <19200000>;
3795 reset-names = "pci",
3802 interconnect-names = "pcie-mem",
3803 "cpu-pcie";
3805 power-domains = <&gcc PCIE_1_GDSC>;
3807 operating-points-v2 = <&pcie1_opp_table>;
3809 iommu-map = <0 &apps_smmu 0x1480 0x1>,
3812 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH 0>,
3816 interrupt-map-mask = <0 0 0 0x7>;
3817 #interrupt-cells = <1>;
3819 msi-map = <0x0 &gic_its 0x1480 0x1>,
3821 msi-map-mask = <0xff00>;
3823 linux,pci-domain = <1>;
3824 num-lanes = <2>;
3825 bus-range = <0 0xff>;
3828 phy-names = "pciephy";
3830 dma-coherent;
3832 #address-cells = <3>;
3833 #size-cells = <2>;
3839 pcie1_opp_table: opp-table {
3840 compatible = "operating-points-v2";
3843 opp-2500000 {
3844 opp-hz = /bits/ 64 <2500000>;
3845 required-opps = <&rpmhpd_opp_low_svs>;
3846 opp-peak-kBps = <250000 1>;
3850 opp-5000000 {
3851 opp-hz = /bits/ 64 <5000000>;
3852 required-opps = <&rpmhpd_opp_low_svs>;
3853 opp-peak-kBps = <500000 1>;
3857 opp-10000000 {
3858 opp-hz = /bits/ 64 <10000000>;
3859 required-opps = <&rpmhpd_opp_low_svs>;
3860 opp-peak-kBps = <1000000 1>;
3864 opp-8000000 {
3865 opp-hz = /bits/ 64 <8000000>;
3866 required-opps = <&rpmhpd_opp_nom>;
3867 opp-peak-kBps = <984500 1>;
3871 opp-16000000 {
3872 opp-hz = /bits/ 64 <16000000>;
3873 required-opps = <&rpmhpd_opp_nom>;
3874 opp-peak-kBps = <1969000 1>;
3878 opp-32000000 {
3879 opp-hz = /bits/ 64 <32000000>;
3880 required-opps = <&rpmhpd_opp_nom>;
3881 opp-peak-kBps = <3938000 1>;
3888 bus-range = <0x01 0xff>;
3890 #address-cells = <3>;
3891 #size-cells = <2>;
3897 compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy";
3905 clock-names = "aux",
3911 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
3912 assigned-clock-rates = <100000000>;
3916 reset-names = "phy",
3919 power-domains = <&gcc PCIE_1_PHY_GDSC>;
3921 #clock-cells = <1>;
3922 clock-output-names = "pcie1_pipe_clk";
3924 #phy-cells = <0>;
3929 cryptobam: dma-controller@1dc4000 {
3930 compatible = "qcom,bam-v1.7.0";
3935 #dma-cells = <1>;
3941 qcom,num-ees = <4>;
3942 num-channels = <20>;
3943 qcom,controlled-remotely;
3947 compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce";
3952 interconnect-names = "memory";
3955 dma-names = "rx", "tx";
3962 compatible = "qcom,sm8650-qmp-ufs-phy";
3968 clock-names = "ref",
3973 reset-names = "ufsphy";
3975 power-domains = <&gcc UFS_MEM_PHY_GDSC>;
3977 #clock-cells = <1>;
3978 #phy-cells = <0>;
3984 compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
3997 clock-names = "core_clk",
4007 reset-names = "rst";
4013 interconnect-names = "ufs-ddr",
4014 "cpu-ufs";
4016 power-domains = <&gcc UFS_PHY_GDSC>;
4017 required-opps = <&rpmhpd_opp_nom>;
4019 operating-points-v2 = <&ufs_opp_table>;
4023 lanes-per-direction = <2>;
4027 phy-names = "ufsphy";
4029 #reset-cells = <1>;
4033 ufs_opp_table: opp-table {
4034 compatible = "operating-points-v2";
4036 opp-100000000 {
4037 opp-hz = /bits/ 64 <100000000>,
4045 required-opps = <&rpmhpd_opp_low_svs>;
4048 opp-201500000 {
4049 opp-hz = /bits/ 64 <201500000>,
4057 required-opps = <&rpmhpd_opp_svs>;
4060 opp-403000000 {
4061 opp-hz = /bits/ 64 <403000000>,
4069 required-opps = <&rpmhpd_opp_nom>;
4075 compatible = "qcom,sm8650-inline-crypto-engine",
4076 "qcom,inline-crypto-engine";
4083 compatible = "qcom,tcsr-mutex";
4086 #hwlock-cells = <1>;
4089 tcsr: clock-controller@1fc0000 {
4090 compatible = "qcom,sm8650-tcsr", "syscon";
4095 #clock-cells = <1>;
4096 #reset-cells = <1>;
4100 compatible = "qcom,adreno-43051401", "qcom,adreno";
4104 reg-names = "kgsl_3d0_reg_memory",
4113 operating-points-v2 = <&gpu_opp_table>;
4116 #cooling-cells = <2>;
4120 interconnect-names = "gfx-mem";
4124 zap-shader {
4125 memory-region = <&gpu_micro_code_mem>;
4129 gpu_opp_table: opp-table {
4130 compatible = "operating-points-v2";
4132 opp-231000000 {
4133 opp-hz = /bits/ 64 <231000000>;
4134 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
4135 opp-peak-kBps = <2136718>;
4138 opp-310000000 {
4139 opp-hz = /bits/ 64 <310000000>;
4140 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
4141 opp-peak-kBps = <2136718>;
4144 opp-366000000 {
4145 opp-hz = /bits/ 64 <366000000>;
4146 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
4147 opp-peak-kBps = <6074218>;
4150 opp-422000000 {
4151 opp-hz = /bits/ 64 <422000000>;
4152 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4153 opp-peak-kBps = <8171875>;
4156 opp-500000000 {
4157 opp-hz = /bits/ 64 <500000000>;
4158 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
4159 opp-peak-kBps = <8171875>;
4162 opp-578000000 {
4163 opp-hz = /bits/ 64 <578000000>;
4164 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4165 opp-peak-kBps = <8171875>;
4168 opp-629000000 {
4169 opp-hz = /bits/ 64 <629000000>;
4170 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
4171 opp-peak-kBps = <10687500>;
4174 opp-680000000 {
4175 opp-hz = /bits/ 64 <680000000>;
4176 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4177 opp-peak-kBps = <12449218>;
4180 opp-720000000 {
4181 opp-hz = /bits/ 64 <720000000>;
4182 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
4183 opp-peak-kBps = <12449218>;
4186 opp-770000000 {
4187 opp-hz = /bits/ 64 <770000000>;
4188 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4189 opp-peak-kBps = <12449218>;
4192 opp-834000000 {
4193 opp-hz = /bits/ 64 <834000000>;
4194 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4195 opp-peak-kBps = <14398437>;
4201 compatible = "qcom,adreno-gmu-750.1", "qcom,adreno-gmu";
4205 reg-names = "gmu", "rscc", "gmu_pdc";
4209 interrupt-names = "hfi", "gmu";
4218 clock-names = "ahb",
4226 power-domains = <&gpucc GPU_CX_GDSC>,
4228 power-domain-names = "cx",
4235 operating-points-v2 = <&gmu_opp_table>;
4237 gmu_opp_table: opp-table {
4238 compatible = "operating-points-v2";
4240 opp-260000000 {
4241 opp-hz = /bits/ 64 <260000000>;
4242 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4245 opp-625000000 {
4246 opp-hz = /bits/ 64 <625000000>;
4247 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4252 gpucc: clock-controller@3d90000 {
4253 compatible = "qcom,sm8650-gpucc";
4260 #clock-cells = <1>;
4261 #reset-cells = <1>;
4262 #power-domain-cells = <1>;
4266 compatible = "qcom,sm8650-smmu-500", "qcom,adreno-smmu",
4267 "qcom,smmu-500", "arm,mmu-500";
4269 #iommu-cells = <2>;
4270 #global-interrupts = <1>;
4301 clock-names = "hlos",
4305 power-domains = <&gpucc GPU_CX_GDSC>;
4306 dma-coherent;
4310 compatible = "qcom,sm8650-ipa", "qcom,sm8550-ipa";
4317 reg-names = "ipa-reg",
4318 "ipa-shared",
4321 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING 0>,
4325 interrupt-names = "ipa",
4327 "ipa-clock-query",
4328 "ipa-setup-ready";
4331 clock-names = "core";
4337 interconnect-names = "memory",
4342 qcom,smem-states = <&ipa_smp2p_out 0>,
4344 qcom,smem-state-names = "ipa-clock-enabled-valid",
4345 "ipa-clock-enabled";
4351 compatible = "qcom,sm8650-mpss-pas";
4354 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING 0>,
4360 interrupt-names = "wdog",
4364 "stop-ack",
4365 "shutdown-ack";
4368 clock-names = "xo";
4373 power-domains = <&rpmhpd RPMHPD_CX>,
4375 power-domain-names = "cx",
4378 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>,
4384 qcom,smem-states = <&smp2p_modem_out 0>;
4385 qcom,smem-state-names = "stop";
4389 glink-edge {
4390 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
4397 qcom,remote-pid = <1>;
4404 compatible = "qcom,sm8650-adsp-pas";
4407 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
4412 interrupt-names = "wdog",
4416 "stop-ack";
4419 clock-names = "xo";
4424 power-domains = <&rpmhpd RPMHPD_LCX>,
4426 power-domain-names = "lcx",
4429 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
4433 qcom,smem-states = <&smp2p_adsp_out 0>;
4434 qcom,smem-state-names = "stop";
4438 remoteproc_adsp_glink: glink-edge {
4439 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
4446 qcom,remote-pid = <2>;
4453 qcom,glink-channels = "fastrpcglink-apps-dsp";
4457 qcom,non-secure-domain;
4459 #address-cells = <1>;
4460 #size-cells = <0>;
4462 compute-cb@3 {
4463 compatible = "qcom,fastrpc-compute-cb";
4468 dma-coherent;
4471 compute-cb@4 {
4472 compatible = "qcom,fastrpc-compute-cb";
4477 dma-coherent;
4480 compute-cb@5 {
4481 compatible = "qcom,fastrpc-compute-cb";
4486 dma-coherent;
4489 compute-cb@6 {
4490 compatible = "qcom,fastrpc-compute-cb";
4495 dma-coherent;
4498 compute-cb@7 {
4499 compatible = "qcom,fastrpc-compute-cb";
4505 dma-coherent;
4511 qcom,glink-channels = "adsp_apps";
4514 #address-cells = <1>;
4515 #size-cells = <0>;
4520 #sound-dai-cells = <0>;
4521 qcom,protection-domain = "avs/audio",
4525 compatible = "qcom,q6apm-lpass-dais";
4526 #sound-dai-cells = <1>;
4530 compatible = "qcom,q6apm-dais";
4539 qcom,protection-domain = "avs/audio",
4542 q6prmcc: clock-controller {
4543 compatible = "qcom,q6prm-lpass-clocks";
4544 #clock-cells = <2>;
4552 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
4558 clock-names = "mclk",
4563 #clock-cells = <0>;
4564 clock-output-names = "wsa2-mclk";
4565 #sound-dai-cells = <1>;
4569 compatible = "qcom,soundwire-v2.0.0";
4573 clock-names = "iface";
4576 pinctrl-0 = <&wsa2_swr_active>;
4577 pinctrl-names = "default";
4579 qcom,din-ports = <4>;
4580 qcom,dout-ports = <9>;
4582 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
4583 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
4584 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4585 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4586 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4587 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
4588 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
4589 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4590 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4592 #address-cells = <2>;
4593 #size-cells = <0>;
4594 #sound-dai-cells = <1>;
4599 compatible = "qcom,sm8650-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro";
4605 clock-names = "mclk",
4610 #clock-cells = <0>;
4611 clock-output-names = "mclk";
4612 #sound-dai-cells = <1>;
4616 compatible = "qcom,soundwire-v2.0.0";
4620 clock-names = "iface";
4623 pinctrl-0 = <&rx_swr_active>;
4624 pinctrl-names = "default";
4626 qcom,din-ports = <0>;
4627 qcom,dout-ports = <11>;
4629 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x03 0xff 0xff 0x31 0xff 0xff 0xff>;
4630 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x09 0x01 0xff 0xff 0x00 0xff 0xff 0xff>;
4631 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>;
4632 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0xff 0xff 0x00 0xff 0xff 0xff>;
4633 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0xff 0xff 0x0f 0xff 0xff 0xff>;
4634 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0x18 0xff 0xff 0xff>;
4635 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff 0xff 0x01 0xff 0xff 0xff>;
4636 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0x01 0x03 0xff 0xff 0x00 0xff 0xff 0xff>;
4637 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0xff 0xff 0xff>;
4639 #address-cells = <2>;
4640 #size-cells = <0>;
4641 #sound-dai-cells = <1>;
4646 compatible = "qcom,sm8650-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro";
4652 clock-names = "mclk",
4657 #clock-cells = <0>;
4658 clock-output-names = "mclk";
4659 #sound-dai-cells = <1>;
4663 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
4669 clock-names = "mclk",
4674 #clock-cells = <0>;
4675 clock-output-names = "mclk";
4676 #sound-dai-cells = <1>;
4680 compatible = "qcom,soundwire-v2.0.0";
4684 clock-names = "iface";
4687 pinctrl-0 = <&wsa_swr_active>;
4688 pinctrl-names = "default";
4690 qcom,din-ports = <4>;
4691 qcom,dout-ports = <9>;
4693 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
4694 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
4695 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4696 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4697 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4698 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
4699 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
4700 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4701 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4703 #address-cells = <2>;
4704 #size-cells = <0>;
4705 #sound-dai-cells = <1>;
4710 compatible = "qcom,soundwire-v2.0.0";
4714 interrupt-names = "core", "wakeup";
4716 clock-names = "iface";
4719 pinctrl-0 = <&tx_swr_active>;
4720 pinctrl-names = "default";
4722 qcom,din-ports = <4>;
4723 qcom,dout-ports = <0>;
4725 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
4726 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
4727 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
4728 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
4729 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
4730 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
4731 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
4732 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
4733 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
4735 #address-cells = <2>;
4736 #size-cells = <0>;
4737 #sound-dai-cells = <1>;
4742 compatible = "qcom,sm8650-lpass-va-macro", "qcom,sm8550-lpass-va-macro";
4747 clock-names = "mclk",
4751 #clock-cells = <0>;
4752 clock-output-names = "fsgen";
4753 #sound-dai-cells = <1>;
4757 compatible = "qcom,sm8650-lpass-lpi-pinctrl";
4762 clock-names = "core", "audio";
4764 gpio-controller;
4765 #gpio-cells = <2>;
4766 gpio-ranges = <&lpass_tlmm 0 0 23>;
4768 tx_swr_active: tx-swr-active-state {
4769 clk-pins {
4772 drive-strength = <2>;
4773 slew-rate = <1>;
4774 bias-disable;
4777 data-pins {
4780 drive-strength = <2>;
4781 slew-rate = <1>;
4782 bias-bus-hold;
4786 rx_swr_active: rx-swr-active-state {
4787 clk-pins {
4790 drive-strength = <2>;
4791 slew-rate = <1>;
4792 bias-disable;
4795 data-pins {
4798 drive-strength = <2>;
4799 slew-rate = <1>;
4800 bias-bus-hold;
4804 dmic01_default: dmic01-default-state {
4805 clk-pins {
4808 drive-strength = <8>;
4809 output-high;
4812 data-pins {
4815 drive-strength = <8>;
4816 input-enable;
4820 dmic23_default: dmic23-default-state {
4821 clk-pins {
4824 drive-strength = <8>;
4825 output-high;
4828 data-pins {
4831 drive-strength = <8>;
4832 input-enable;
4836 wsa_swr_active: wsa-swr-active-state {
4837 clk-pins {
4840 drive-strength = <2>;
4841 slew-rate = <1>;
4842 bias-disable;
4845 data-pins {
4848 drive-strength = <2>;
4849 slew-rate = <1>;
4850 bias-bus-hold;
4854 wsa2_swr_active: wsa2-swr-active-state {
4855 clk-pins {
4858 drive-strength = <2>;
4859 slew-rate = <1>;
4860 bias-disable;
4863 data-pins {
4866 drive-strength = <2>;
4867 slew-rate = <1>;
4868 bias-bus-hold;
4874 compatible = "qcom,sm8650-lpass-lpiaon-noc";
4877 #interconnect-cells = <2>;
4879 qcom,bcm-voters = <&apps_bcm_voter>;
4883 compatible = "qcom,sm8650-lpass-lpicx-noc";
4886 #interconnect-cells = <2>;
4888 qcom,bcm-voters = <&apps_bcm_voter>;
4892 compatible = "qcom,sm8650-lpass-ag-noc";
4895 #interconnect-cells = <2>;
4897 qcom,bcm-voters = <&apps_bcm_voter>;
4901 compatible = "qcom,sm8650-sdhci", "qcom,sdhci-msm-v5";
4906 interrupt-names = "hc_irq",
4912 clock-names = "iface",
4920 interconnect-names = "sdhc-ddr",
4921 "cpu-sdhc";
4923 power-domains = <&rpmhpd RPMHPD_CX>;
4924 operating-points-v2 = <&sdhc2_opp_table>;
4928 bus-width = <4>;
4930 /* Forbid SDR104/SDR50 - broken hw! */
4931 sdhci-caps-mask = <0x3 0>;
4933 qcom,dll-config = <0x0007642c>;
4934 qcom,ddr-config = <0x80040868>;
4936 dma-coherent;
4940 sdhc2_opp_table: opp-table {
4941 compatible = "operating-points-v2";
4943 opp-19200000 {
4944 opp-hz = /bits/ 64 <19200000>;
4945 required-opps = <&rpmhpd_opp_min_svs>;
4948 opp-50000000 {
4949 opp-hz = /bits/ 64 <50000000>;
4950 required-opps = <&rpmhpd_opp_low_svs>;
4953 opp-100000000 {
4954 opp-hz = /bits/ 64 <100000000>;
4955 required-opps = <&rpmhpd_opp_svs>;
4958 opp-202000000 {
4959 opp-hz = /bits/ 64 <202000000>;
4960 required-opps = <&rpmhpd_opp_svs_l1>;
4965 iris: video-codec@aa00000 {
4966 compatible = "qcom,sm8650-iris";
4971 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
4975 power-domain-names = "venus",
4980 operating-points-v2 = <&iris_opp_table>;
4985 clock-names = "iface",
4993 interconnect-names = "cpu-cfg",
4994 "video-mem";
4996 memory-region = <&video_mem>;
5001 reset-names = "bus",
5008 dma-coherent;
5017 iris_opp_table: opp-table {
5018 compatible = "operating-points-v2";
5020 opp-196000000 {
5021 opp-hz = /bits/ 64 <196000000>;
5022 required-opps = <&rpmhpd_opp_low_svs_d1>,
5026 opp-300000000 {
5027 opp-hz = /bits/ 64 <300000000>;
5028 required-opps = <&rpmhpd_opp_low_svs>,
5032 opp-380000000 {
5033 opp-hz = /bits/ 64 <380000000>;
5034 required-opps = <&rpmhpd_opp_svs>,
5038 opp-435000000 {
5039 opp-hz = /bits/ 64 <435000000>;
5040 required-opps = <&rpmhpd_opp_svs_l1>,
5044 opp-480000000 {
5045 opp-hz = /bits/ 64 <480000000>;
5046 required-opps = <&rpmhpd_opp_nom>,
5050 opp-533333334 {
5051 opp-hz = /bits/ 64 <533333334>;
5052 required-opps = <&rpmhpd_opp_turbo>,
5058 videocc: clock-controller@aaf0000 {
5059 compatible = "qcom,sm8650-videocc";
5063 power-domains = <&rpmhpd RPMHPD_MMCX>;
5064 #clock-cells = <1>;
5065 #reset-cells = <1>;
5066 #power-domain-cells = <1>;
5070 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
5073 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
5077 clock-names = "camnoc_axi",
5080 pinctrl-0 = <&cci0_0_default &cci0_1_default>;
5081 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
5082 pinctrl-names = "default", "sleep";
5084 #address-cells = <1>;
5085 #size-cells = <0>;
5087 cci0_i2c0: i2c-bus@0 {
5089 clock-frequency = <1000000>;
5090 #address-cells = <1>;
5091 #size-cells = <0>;
5094 cci0_i2c1: i2c-bus@1 {
5096 clock-frequency = <1000000>;
5097 #address-cells = <1>;
5098 #size-cells = <0>;
5103 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
5106 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
5110 clock-names = "camnoc_axi",
5113 pinctrl-0 = <&cci1_0_default &cci1_1_default>;
5114 pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>;
5115 pinctrl-names = "default", "sleep";
5117 #address-cells = <1>;
5118 #size-cells = <0>;
5120 cci1_i2c0: i2c-bus@0 {
5122 clock-frequency = <1000000>;
5123 #address-cells = <1>;
5124 #size-cells = <0>;
5127 cci1_i2c1: i2c-bus@1 {
5129 clock-frequency = <1000000>;
5130 #address-cells = <1>;
5131 #size-cells = <0>;
5136 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
5139 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
5143 clock-names = "camnoc_axi",
5146 pinctrl-0 = <&cci2_0_default &cci2_1_default>;
5147 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>;
5148 pinctrl-names = "default", "sleep";
5150 #address-cells = <1>;
5151 #size-cells = <0>;
5153 cci2_i2c0: i2c-bus@0 {
5155 clock-frequency = <1000000>;
5156 #address-cells = <1>;
5157 #size-cells = <0>;
5160 cci2_i2c1: i2c-bus@1 {
5162 clock-frequency = <1000000>;
5163 #address-cells = <1>;
5164 #size-cells = <0>;
5168 camcc: clock-controller@ade0000 {
5169 compatible = "qcom,sm8650-camcc";
5175 power-domains = <&rpmhpd RPMHPD_MMCX>;
5176 #clock-cells = <1>;
5177 #reset-cells = <1>;
5178 #power-domain-cells = <1>;
5181 mdss: display-subsystem@ae00000 {
5182 compatible = "qcom,sm8650-mdss";
5184 reg-names = "mdss";
5198 interconnect-names = "mdp0-mem",
5199 "cpu-cfg";
5201 power-domains = <&dispcc MDSS_GDSC>;
5205 interrupt-controller;
5206 #interrupt-cells = <1>;
5208 #address-cells = <2>;
5209 #size-cells = <2>;
5214 mdss_mdp: display-controller@ae01000 {
5215 compatible = "qcom,sm8650-dpu";
5218 reg-names = "mdp",
5221 interrupts-extended = <&mdss 0>;
5228 clock-names = "nrt_bus",
5234 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
5235 assigned-clock-rates = <19200000>;
5237 operating-points-v2 = <&mdp_opp_table>;
5239 power-domains = <&rpmhpd RPMHPD_MMCX>;
5242 #address-cells = <1>;
5243 #size-cells = <0>;
5249 remote-endpoint = <&mdss_dsi0_in>;
5257 remote-endpoint = <&mdss_dsi1_in>;
5265 remote-endpoint = <&mdss_dp0_in>;
5270 mdp_opp_table: opp-table {
5271 compatible = "operating-points-v2";
5273 opp-200000000 {
5274 opp-hz = /bits/ 64 <200000000>;
5275 required-opps = <&rpmhpd_opp_low_svs>;
5278 opp-325000000 {
5279 opp-hz = /bits/ 64 <325000000>;
5280 required-opps = <&rpmhpd_opp_svs>;
5283 opp-375000000 {
5284 opp-hz = /bits/ 64 <375000000>;
5285 required-opps = <&rpmhpd_opp_svs_l1>;
5288 opp-514000000 {
5289 opp-hz = /bits/ 64 <514000000>;
5290 required-opps = <&rpmhpd_opp_nom>;
5296 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
5298 reg-names = "dsi_ctrl";
5300 interrupts-extended = <&mdss 4>;
5308 clock-names = "byte",
5315 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
5317 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
5320 operating-points-v2 = <&mdss_dsi_opp_table>;
5322 power-domains = <&rpmhpd RPMHPD_MMCX>;
5325 phy-names = "dsi";
5327 #address-cells = <1>;
5328 #size-cells = <0>;
5333 #address-cells = <1>;
5334 #size-cells = <0>;
5340 remote-endpoint = <&dpu_intf1_out>;
5352 mdss_dsi_opp_table: opp-table {
5353 compatible = "operating-points-v2";
5355 opp-187500000 {
5356 opp-hz = /bits/ 64 <187500000>;
5357 required-opps = <&rpmhpd_opp_low_svs>;
5360 opp-300000000 {
5361 opp-hz = /bits/ 64 <300000000>;
5362 required-opps = <&rpmhpd_opp_svs>;
5365 opp-358000000 {
5366 opp-hz = /bits/ 64 <358000000>;
5367 required-opps = <&rpmhpd_opp_svs_l1>;
5373 compatible = "qcom,sm8650-dsi-phy-4nm";
5377 reg-names = "dsi_phy",
5383 clock-names = "iface",
5386 #clock-cells = <1>;
5387 #phy-cells = <0>;
5393 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
5395 reg-names = "dsi_ctrl";
5397 interrupts-extended = <&mdss 5>;
5405 clock-names = "byte",
5412 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
5414 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
5417 operating-points-v2 = <&mdss_dsi_opp_table>;
5419 power-domains = <&rpmhpd RPMHPD_MMCX>;
5422 phy-names = "dsi";
5424 #address-cells = <1>;
5425 #size-cells = <0>;
5430 #address-cells = <1>;
5431 #size-cells = <0>;
5437 remote-endpoint = <&dpu_intf2_out>;
5451 compatible = "qcom,sm8650-dsi-phy-4nm";
5455 reg-names = "dsi_phy",
5461 clock-names = "iface",
5464 #clock-cells = <1>;
5465 #phy-cells = <0>;
5470 mdss_dp0: displayport-controller@af54000 {
5471 compatible = "qcom,sm8650-dp";
5478 interrupts-extended = <&mdss 12>;
5485 clock-names = "core_iface",
5491 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
5493 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
5496 operating-points-v2 = <&dp_opp_table>;
5498 power-domains = <&rpmhpd RPMHPD_MMCX>;
5501 phy-names = "dp";
5503 #sound-dai-cells = <0>;
5507 dp_opp_table: opp-table {
5508 compatible = "operating-points-v2";
5510 opp-162000000 {
5511 opp-hz = /bits/ 64 <162000000>;
5512 required-opps = <&rpmhpd_opp_low_svs_d1>;
5515 opp-270000000 {
5516 opp-hz = /bits/ 64 <270000000>;
5517 required-opps = <&rpmhpd_opp_low_svs>;
5520 opp-540000000 {
5521 opp-hz = /bits/ 64 <540000000>;
5522 required-opps = <&rpmhpd_opp_svs_l1>;
5525 opp-810000000 {
5526 opp-hz = /bits/ 64 <810000000>;
5527 required-opps = <&rpmhpd_opp_nom>;
5532 #address-cells = <1>;
5533 #size-cells = <0>;
5539 remote-endpoint = <&dpu_intf0_out>;
5547 remote-endpoint = <&usb_dp_qmpphy_dp_in>;
5554 dispcc: clock-controller@af00000 {
5555 compatible = "qcom,sm8650-dispcc";
5575 power-domains = <&rpmhpd RPMHPD_MMCX>;
5576 required-opps = <&rpmhpd_opp_low_svs>;
5578 #clock-cells = <1>;
5579 #reset-cells = <1>;
5580 #power-domain-cells = <1>;
5584 compatible = "qcom,sm8650-snps-eusb2-phy",
5585 "qcom,sm8550-snps-eusb2-phy";
5589 clock-names = "ref";
5593 #phy-cells = <0>;
5599 compatible = "qcom,sm8650-qmp-usb3-dp-phy";
5606 clock-names = "aux",
5613 reset-names = "phy",
5616 power-domains = <&gcc USB3_PHY_GDSC>;
5618 #clock-cells = <1>;
5619 #phy-cells = <1>;
5621 orientation-switch;
5626 #address-cells = <1>;
5627 #size-cells = <0>;
5640 remote-endpoint = <&usb_1_dwc3_ss>;
5648 remote-endpoint = <&mdss_dp0_out>;
5655 compatible = "qcom,sm8650-dwc3", "qcom,dwc3";
5658 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>,
5663 interrupt-names = "pwr_event",
5675 clock-names = "cfg_noc",
5682 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
5684 assigned-clock-rates = <19200000>, <200000000>;
5692 interconnect-names = "usb-ddr",
5693 "apps-usb";
5695 power-domains = <&gcc USB30_PRIM_GDSC>;
5696 required-opps = <&rpmhpd_opp_nom>;
5698 #address-cells = <2>;
5699 #size-cells = <2>;
5714 phy-names = "usb2-phy",
5715 "usb3-phy";
5717 snps,hird-threshold = /bits/ 8 <0x0>;
5718 snps,usb2-gadget-lpm-disable;
5721 snps,dis-u1-entry-quirk;
5722 snps,dis-u2-entry-quirk;
5723 snps,is-utmi-l1-suspend;
5725 snps,usb2-lpm-disable;
5726 snps,has-lpm-erratum;
5727 tx-fifo-resize;
5729 dma-coherent;
5732 #address-cells = <1>;
5733 #size-cells = <0>;
5746 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
5753 pdc: interrupt-controller@b220000 {
5754 compatible = "qcom,sm8650-pdc", "qcom,pdc";
5757 interrupt-parent = <&intc>;
5759 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
5763 #interrupt-cells = <2>;
5764 interrupt-controller;
5767 tsens0: thermal-sensor@c228000 {
5768 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2";
5774 interrupt-names = "uplow",
5779 #thermal-sensor-cells = <1>;
5782 tsens1: thermal-sensor@c229000 {
5783 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2";
5789 interrupt-names = "uplow",
5794 #thermal-sensor-cells = <1>;
5797 tsens2: thermal-sensor@c22a000 {
5798 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2";
5804 interrupt-names = "uplow",
5809 #thermal-sensor-cells = <1>;
5812 aoss_qmp: power-management@c300000 {
5813 compatible = "qcom,sm8650-aoss-qmp", "qcom,aoss-qmp";
5816 interrupt-parent = <&ipcc>;
5817 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
5822 #clock-cells = <0>;
5826 compatible = "qcom,rpmh-stats";
5832 compatible = "qcom,spmi-pmic-arb";
5838 reg-names = "core",
5844 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5845 interrupt-names = "periph_irq";
5849 qcom,bus-id = <0>;
5851 interrupt-controller;
5852 #interrupt-cells = <4>;
5854 #address-cells = <2>;
5855 #size-cells = <0>;
5859 compatible = "qcom,sm8650-tlmm";
5864 gpio-controller;
5865 #gpio-cells = <2>;
5867 interrupt-controller;
5868 #interrupt-cells = <2>;
5870 gpio-ranges = <&tlmm 0 0 211>;
5872 wakeup-parent = <&pdc>;
5874 cci0_0_default: cci0-0-default-state {
5875 sda-pins {
5878 drive-strength = <2>;
5879 bias-pull-up = <2200>;
5882 scl-pins {
5885 drive-strength = <2>;
5886 bias-pull-up = <2200>;
5890 cci0_0_sleep: cci0-0-sleep-state {
5891 sda-pins {
5894 drive-strength = <2>;
5895 bias-pull-down;
5898 scl-pins {
5901 drive-strength = <2>;
5902 bias-pull-down;
5906 cci0_1_default: cci0-1-default-state {
5907 sda-pins {
5910 drive-strength = <2>;
5911 bias-pull-up = <2200>;
5914 scl-pins {
5917 drive-strength = <2>;
5918 bias-pull-up = <2200>;
5922 cci0_1_sleep: cci0-1-sleep-state {
5923 sda-pins {
5926 drive-strength = <2>;
5927 bias-pull-down;
5930 scl-pins {
5933 drive-strength = <2>;
5934 bias-pull-down;
5938 cci1_0_default: cci1-0-default-state {
5939 sda-pins {
5942 drive-strength = <2>;
5943 bias-pull-up = <2200>;
5946 scl-pins {
5949 drive-strength = <2>;
5950 bias-pull-up = <2200>;
5954 cci1_0_sleep: cci1-0-sleep-state {
5955 sda-pins {
5958 drive-strength = <2>;
5959 bias-pull-down;
5962 scl-pins {
5965 drive-strength = <2>;
5966 bias-pull-down;
5970 cci1_1_default: cci1-1-default-state {
5971 sda-pins {
5974 drive-strength = <2>;
5975 bias-pull-up = <2200>;
5978 scl-pins {
5981 drive-strength = <2>;
5982 bias-pull-up = <2200>;
5986 cci1_1_sleep: cci1-1-sleep-state {
5987 sda-pins {
5990 drive-strength = <2>;
5991 bias-pull-down;
5994 scl-pins {
5997 drive-strength = <2>;
5998 bias-pull-down;
6002 cci2_0_default: cci2-0-default-state {
6003 sda-pins {
6006 drive-strength = <2>;
6007 bias-pull-up = <2200>;
6010 scl-pins {
6013 drive-strength = <2>;
6014 bias-pull-up = <2200>;
6018 cci2_0_sleep: cci2-0-sleep-state {
6019 sda-pins {
6022 drive-strength = <2>;
6023 bias-pull-down;
6026 scl-pins {
6029 drive-strength = <2>;
6030 bias-pull-down;
6034 cci2_1_default: cci2-1-default-state {
6035 sda-pins {
6038 drive-strength = <2>;
6039 bias-pull-up = <2200>;
6042 scl-pins {
6045 drive-strength = <2>;
6046 bias-pull-up = <2200>;
6050 cci2_1_sleep: cci2-1-sleep-state {
6051 sda-pins {
6054 drive-strength = <2>;
6055 bias-pull-down;
6058 scl-pins {
6061 drive-strength = <2>;
6062 bias-pull-down;
6066 hub_i2c0_data_clk: hub-i2c0-data-clk-state {
6070 drive-strength = <2>;
6071 bias-pull-up;
6074 hub_i2c1_data_clk: hub-i2c1-data-clk-state {
6078 drive-strength = <2>;
6079 bias-pull-up;
6082 hub_i2c2_data_clk: hub-i2c2-data-clk-state {
6086 drive-strength = <2>;
6087 bias-pull-up;
6090 hub_i2c3_data_clk: hub-i2c3-data-clk-state {
6094 drive-strength = <2>;
6095 bias-pull-up;
6098 hub_i2c4_data_clk: hub-i2c4-data-clk-state {
6102 drive-strength = <2>;
6103 bias-pull-up;
6106 hub_i2c5_data_clk: hub-i2c5-data-clk-state {
6110 drive-strength = <2>;
6111 bias-pull-up;
6114 hub_i2c6_data_clk: hub-i2c6-data-clk-state {
6118 drive-strength = <2>;
6119 bias-pull-up;
6122 hub_i2c7_data_clk: hub-i2c7-data-clk-state {
6126 drive-strength = <2>;
6127 bias-pull-up;
6130 hub_i2c8_data_clk: hub-i2c8-data-clk-state {
6134 drive-strength = <2>;
6135 bias-pull-up;
6138 hub_i2c9_data_clk: hub-i2c9-data-clk-state {
6142 drive-strength = <2>;
6143 bias-pull-up;
6146 pcie0_default_state: pcie0-default-state {
6147 perst-pins {
6150 drive-strength = <2>;
6151 bias-pull-down;
6154 clkreq-pins {
6157 drive-strength = <2>;
6158 bias-pull-up;
6161 wake-pins {
6164 drive-strength = <2>;
6165 bias-pull-up;
6169 pcie1_default_state: pcie1-default-state {
6170 perst-pins {
6173 drive-strength = <2>;
6174 bias-pull-down;
6177 clkreq-pins {
6180 drive-strength = <2>;
6181 bias-pull-up;
6184 wake-pins {
6187 drive-strength = <2>;
6188 bias-pull-up;
6192 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
6196 drive-strength = <2>;
6197 bias-pull-up;
6200 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
6204 drive-strength = <2>;
6205 bias-pull-up;
6208 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
6212 drive-strength = <2>;
6213 bias-pull-up;
6216 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
6220 drive-strength = <2>;
6221 bias-pull-up;
6224 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
6228 drive-strength = <2>;
6229 bias-pull-up;
6232 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
6236 drive-strength = <2>;
6237 bias-pull-up;
6240 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
6244 drive-strength = <2>;
6245 bias-pull-up;
6248 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
6252 drive-strength = <2>;
6253 bias-pull-up;
6256 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
6260 drive-strength = <2>;
6261 bias-pull-up;
6264 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
6268 drive-strength = <2>;
6269 bias-pull-up;
6272 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
6276 drive-strength = <2>;
6277 bias-pull-up;
6280 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
6284 drive-strength = <2>;
6285 bias-pull-up;
6288 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
6292 drive-strength = <2>;
6293 bias-pull-up;
6296 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
6300 drive-strength = <2>;
6301 bias-pull-up;
6304 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
6308 drive-strength = <2>;
6309 bias-pull-up;
6312 qup_spi0_cs: qup-spi0-cs-state {
6315 drive-strength = <6>;
6316 bias-disable;
6319 qup_spi0_data_clk: qup-spi0-data-clk-state {
6323 drive-strength = <6>;
6324 bias-disable;
6327 qup_spi1_cs: qup-spi1-cs-state {
6330 drive-strength = <6>;
6331 bias-disable;
6334 qup_spi1_data_clk: qup-spi1-data-clk-state {
6338 drive-strength = <6>;
6339 bias-disable;
6342 qup_spi2_cs: qup-spi2-cs-state {
6345 drive-strength = <6>;
6346 bias-disable;
6349 qup_spi2_data_clk: qup-spi2-data-clk-state {
6353 drive-strength = <6>;
6354 bias-disable;
6357 qup_spi3_cs: qup-spi3-cs-state {
6360 drive-strength = <6>;
6361 bias-disable;
6364 qup_spi3_data_clk: qup-spi3-data-clk-state {
6368 drive-strength = <6>;
6369 bias-disable;
6372 qup_spi4_cs: qup-spi4-cs-state {
6375 drive-strength = <6>;
6376 bias-disable;
6379 qup_spi4_data_clk: qup-spi4-data-clk-state {
6383 drive-strength = <6>;
6384 bias-disable;
6387 qup_spi5_cs: qup-spi5-cs-state {
6390 drive-strength = <6>;
6391 bias-disable;
6394 qup_spi5_data_clk: qup-spi5-data-clk-state {
6398 drive-strength = <6>;
6399 bias-disable;
6402 qup_spi6_cs: qup-spi6-cs-state {
6405 drive-strength = <6>;
6406 bias-disable;
6409 qup_spi6_data_clk: qup-spi6-data-clk-state {
6413 drive-strength = <6>;
6414 bias-disable;
6417 qup_spi7_cs: qup-spi7-cs-state {
6420 drive-strength = <6>;
6421 bias-disable;
6424 qup_spi7_data_clk: qup-spi7-data-clk-state {
6428 drive-strength = <6>;
6429 bias-disable;
6432 qup_spi8_cs: qup-spi8-cs-state {
6435 drive-strength = <6>;
6436 bias-disable;
6439 qup_spi8_data_clk: qup-spi8-data-clk-state {
6443 drive-strength = <6>;
6444 bias-disable;
6447 qup_spi9_cs: qup-spi9-cs-state {
6450 drive-strength = <6>;
6451 bias-disable;
6454 qup_spi9_data_clk: qup-spi9-data-clk-state {
6458 drive-strength = <6>;
6459 bias-disable;
6462 qup_spi10_cs: qup-spi10-cs-state {
6465 drive-strength = <6>;
6466 bias-disable;
6469 qup_spi10_data_clk: qup-spi10-data-clk-state {
6473 drive-strength = <6>;
6474 bias-disable;
6477 qup_spi11_cs: qup-spi11-cs-state {
6480 drive-strength = <6>;
6481 bias-disable;
6484 qup_spi11_data_clk: qup-spi11-data-clk-state {
6488 drive-strength = <6>;
6489 bias-disable;
6492 qup_spi12_cs: qup-spi12-cs-state {
6495 drive-strength = <6>;
6496 bias-disable;
6499 qup_spi12_data_clk: qup-spi12-data-clk-state {
6503 drive-strength = <6>;
6504 bias-disable;
6507 qup_spi13_cs: qup-spi13-cs-state {
6510 drive-strength = <6>;
6511 bias-disable;
6514 qup_spi13_data_clk: qup-spi13-data-clk-state {
6518 drive-strength = <6>;
6519 bias-disable;
6522 qup_spi14_cs: qup-spi14-cs-state {
6525 drive-strength = <6>;
6526 bias-disable;
6529 qup_spi14_data_clk: qup-spi14-data-clk-state {
6533 drive-strength = <6>;
6534 bias-disable;
6537 qup_uart14_default: qup-uart14-default-state {
6541 drive-strength = <2>;
6542 bias-pull-up;
6545 qup_uart14_cts_rts: qup-uart14-cts-rts-state {
6549 drive-strength = <2>;
6550 bias-pull-down;
6553 qup_uart15_default: qup-uart15-default-state {
6557 drive-strength = <2>;
6558 bias-disable;
6561 sdc2_sleep: sdc2-sleep-state {
6562 clk-pins {
6564 drive-strength = <2>;
6565 bias-disable;
6568 cmd-pins {
6570 drive-strength = <2>;
6571 bias-pull-up;
6574 data-pins {
6576 drive-strength = <2>;
6577 bias-pull-up;
6581 sdc2_default: sdc2-default-state {
6582 clk-pins {
6584 drive-strength = <16>;
6585 bias-disable;
6588 cmd-pins {
6590 drive-strength = <10>;
6591 bias-pull-up;
6594 data-pins {
6596 drive-strength = <10>;
6597 bias-pull-up;
6603 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
6608 clock-names = "apb_pclk";
6610 in-ports {
6611 #address-cells = <1>;
6612 #size-cells = <0>;
6618 remote-endpoint = <&funnel_apss_out_funnel_in1>;
6623 out-ports {
6626 remote-endpoint = <&funnel_qdss_in_funnel_in1>;
6633 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
6638 clock-names = "apb_pclk";
6640 in-ports {
6641 #address-cells = <1>;
6642 #size-cells = <0>;
6648 remote-endpoint = <&funnel_in1_out_funnel_qdss>;
6653 out-ports {
6656 remote-endpoint = <&funnel_aoss_in_funnel_qdss>;
6663 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
6668 clock-names = "apb_pclk";
6670 in-ports {
6671 #address-cells = <1>;
6672 #size-cells = <0>;
6678 remote-endpoint = <&funnel_qdss_out_funnel_aoss>;
6683 out-ports {
6686 remote-endpoint = <&tmc_etf_in_funnel_aoss>;
6693 compatible = "arm,coresight-tmc", "arm,primecell";
6698 clock-names = "apb_pclk";
6700 in-ports {
6703 remote-endpoint = <&funnel_aoss_out_tmc_etf>;
6710 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
6715 clock-names = "apb_pclk";
6717 in-ports {
6720 remote-endpoint = <&funnel_ete_out_funnel_apss>;
6725 out-ports {
6728 remote-endpoint = <&funnel_in1_in_funnel_apss>;
6735 compatible = "qcom,sm8650-smmu-500", "qcom,smmu-500", "arm,mmu-500";
6836 #iommu-cells = <2>;
6837 #global-interrupts = <1>;
6839 dma-coherent;
6842 intc: interrupt-controller@17100000 {
6843 compatible = "arm,gic-v3";
6849 #interrupt-cells = <4>;
6850 interrupt-controller;
6852 #redistributor-regions = <1>;
6853 redistributor-stride = <0 0x40000>;
6855 #address-cells = <2>;
6856 #size-cells = <2>;
6859 ppi-partitions {
6860 ppi_cluster0: interrupt-partition-0 {
6864 ppi_cluster1: interrupt-partition-1 {
6868 ppi_cluster2: interrupt-partition-2 {
6873 gic_its: msi-controller@17140000 {
6874 compatible = "arm,gic-v3-its";
6877 msi-controller;
6878 #msi-cells = <1>;
6883 compatible = "arm,armv7-timer-mem";
6887 #address-cells = <1>;
6888 #size-cells = <1>;
6897 frame-number = <0>;
6905 frame-number = <1>;
6915 frame-number = <2>;
6925 frame-number = <3>;
6935 frame-number = <4>;
6945 frame-number = <5>;
6955 frame-number = <6>;
6962 compatible = "qcom,rpmh-rsc";
6966 reg-names = "drv-0",
6967 "drv-1",
6968 "drv-2";
6974 power-domains = <&cluster_pd>;
6976 qcom,tcs-offset = <0xd00>;
6977 qcom,drv-id = <2>;
6978 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
6983 apps_bcm_voter: bcm-voter {
6984 compatible = "qcom,bcm-voter";
6987 rpmhcc: clock-controller {
6988 compatible = "qcom,sm8650-rpmh-clk";
6991 clock-names = "xo";
6993 #clock-cells = <1>;
6996 rpmhpd: power-controller {
6997 compatible = "qcom,sm8650-rpmhpd";
6999 operating-points-v2 = <&rpmhpd_opp_table>;
7001 #power-domain-cells = <1>;
7003 rpmhpd_opp_table: opp-table {
7004 compatible = "operating-points-v2";
7006 rpmhpd_opp_ret: opp-16 {
7007 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
7010 rpmhpd_opp_min_svs: opp-48 {
7011 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
7014 rpmhpd_opp_low_svs_d2: opp-52 {
7015 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
7018 rpmhpd_opp_low_svs_d1: opp-56 {
7019 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
7022 rpmhpd_opp_low_svs_d0: opp-60 {
7023 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
7026 rpmhpd_opp_low_svs: opp-64 {
7027 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
7030 rpmhpd_opp_low_svs_l1: opp-80 {
7031 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
7034 rpmhpd_opp_svs: opp-128 {
7035 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
7038 rpmhpd_opp_svs_l0: opp-144 {
7039 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
7042 rpmhpd_opp_svs_l1: opp-192 {
7043 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
7046 rpmhpd_opp_nom: opp-256 {
7047 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
7050 rpmhpd_opp_nom_l1: opp-320 {
7051 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
7054 rpmhpd_opp_nom_l2: opp-336 {
7055 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
7058 rpmhpd_opp_turbo: opp-384 {
7059 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
7062 rpmhpd_opp_turbo_l1: opp-416 {
7063 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
7070 compatible = "qcom,sm8650-epss-l3", "qcom,epss-l3";
7074 clock-names = "xo", "alternate";
7076 #interconnect-cells = <1>;
7080 compatible = "qcom,sm8650-cpufreq-epss", "qcom,cpufreq-epss";
7085 reg-names = "freq-domain0",
7086 "freq-domain1",
7087 "freq-domain2",
7088 "freq-domain3";
7094 interrupt-names = "dcvsh-irq-0",
7095 "dcvsh-irq-1",
7096 "dcvsh-irq-2",
7097 "dcvsh-irq-3";
7100 clock-names = "xo", "alternate";
7102 #freq-domain-cells = <1>;
7103 #clock-cells = <1>;
7107 compatible = "qcom,sm8650-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
7115 operating-points-v2 = <&llcc_bwmon_opp_table>;
7117 llcc_bwmon_opp_table: opp-table {
7118 compatible = "operating-points-v2";
7120 opp-0 {
7121 opp-peak-kBps = <2086000>;
7124 opp-1 {
7125 opp-peak-kBps = <2929000>;
7128 opp-2 {
7129 opp-peak-kBps = <5931000>;
7132 opp-3 {
7133 opp-peak-kBps = <6515000>;
7136 opp-4 {
7137 opp-peak-kBps = <7980000>;
7140 opp-5 {
7141 opp-peak-kBps = <10437000>;
7144 opp-6 {
7145 opp-peak-kBps = <12157000>;
7148 opp-7 {
7149 opp-peak-kBps = <14060000>;
7152 opp-8 {
7153 opp-peak-kBps = <16113000>;
7159 compatible = "qcom,sm8650-cpu-bwmon", "qcom,sdm845-bwmon";
7167 operating-points-v2 = <&cpu_bwmon_opp_table>;
7169 cpu_bwmon_opp_table: opp-table {
7170 compatible = "operating-points-v2";
7172 opp-0 {
7173 opp-peak-kBps = <4577000>;
7176 opp-1 {
7177 opp-peak-kBps = <7110000>;
7180 opp-2 {
7181 opp-peak-kBps = <9155000>;
7184 opp-3 {
7185 opp-peak-kBps = <12298000>;
7188 opp-4 {
7189 opp-peak-kBps = <14236000>;
7192 opp-5 {
7193 opp-peak-kBps = <16265000>;
7199 compatible = "qcom,sm8650-gem-noc";
7202 qcom,bcm-voters = <&apps_bcm_voter>;
7204 #interconnect-cells = <2>;
7207 system-cache-controller@25000000 {
7208 compatible = "qcom,sm8650-llcc";
7215 reg-names = "llcc0_base",
7226 compatible = "qcom,sm8650-nsp-noc";
7229 qcom,bcm-voters = <&apps_bcm_voter>;
7231 #interconnect-cells = <2>;
7235 compatible = "qcom,sm8650-cdsp-pas";
7238 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>,
7243 interrupt-names = "wdog",
7247 "stop-ack";
7250 clock-names = "xo";
7255 power-domains = <&rpmhpd RPMHPD_CX>,
7258 power-domain-names = "cx",
7262 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>, <&global_sync_mem>;
7266 qcom,smem-states = <&smp2p_cdsp_out 0>;
7267 qcom,smem-state-names = "stop";
7271 glink-edge {
7272 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
7279 qcom,remote-pid = <5>;
7286 qcom,glink-channels = "fastrpcglink-apps-dsp";
7290 qcom,non-secure-domain;
7292 #address-cells = <1>;
7293 #size-cells = <0>;
7295 compute-cb@1 {
7296 compatible = "qcom,fastrpc-compute-cb";
7302 dma-coherent;
7305 compute-cb@2 {
7306 compatible = "qcom,fastrpc-compute-cb";
7312 dma-coherent;
7315 compute-cb@3 {
7316 compatible = "qcom,fastrpc-compute-cb";
7322 dma-coherent;
7325 compute-cb@4 {
7326 compatible = "qcom,fastrpc-compute-cb";
7332 dma-coherent;
7335 compute-cb@5 {
7336 compatible = "qcom,fastrpc-compute-cb";
7342 dma-coherent;
7345 compute-cb@6 {
7346 compatible = "qcom,fastrpc-compute-cb";
7352 dma-coherent;
7355 compute-cb@7 {
7356 compatible = "qcom,fastrpc-compute-cb";
7362 dma-coherent;
7365 compute-cb@8 {
7366 compatible = "qcom,fastrpc-compute-cb";
7372 dma-coherent;
7377 compute-cb@12 {
7378 compatible = "qcom,fastrpc-compute-cb";
7384 dma-coherent;
7387 compute-cb@13 {
7388 compatible = "qcom,fastrpc-compute-cb";
7394 dma-coherent;
7397 compute-cb@14 {
7398 compatible = "qcom,fastrpc-compute-cb";
7404 dma-coherent;
7411 thermal-zones {
7412 aoss0-thermal {
7413 thermal-sensors = <&tsens0 0>;
7416 aoss0-hot {
7422 aoss0-critical {
7430 cpuss0-thermal {
7431 thermal-sensors = <&tsens0 1>;
7434 cpuss0-hot {
7440 cpuss0-critical {
7448 cpuss1-thermal {
7449 thermal-sensors = <&tsens0 2>;
7452 cpuss1-hot {
7458 cpuss1-critical {
7466 cpuss2-thermal {
7467 thermal-sensors = <&tsens0 3>;
7470 cpuss2-hot {
7476 cpuss2-critical {
7484 cpuss3-thermal {
7485 thermal-sensors = <&tsens0 4>;
7488 cpuss3-hot {
7494 cpuss3-critical {
7502 cpu2-top-thermal {
7503 thermal-sensors = <&tsens0 5>;
7506 cpu2-critical {
7514 cpu2-bottom-thermal {
7515 thermal-sensors = <&tsens0 6>;
7518 cpu2-critical {
7526 cpu3-top-thermal {
7527 thermal-sensors = <&tsens0 7>;
7530 cpu3-critical {
7538 cpu3-bottom-thermal {
7539 thermal-sensors = <&tsens0 8>;
7542 cpu3-critical {
7550 cpu4-top-thermal {
7551 thermal-sensors = <&tsens0 9>;
7554 cpu4-critical {
7562 cpu4-bottom-thermal {
7563 thermal-sensors = <&tsens0 10>;
7566 cpu4-critical {
7574 cpu5-top-thermal {
7575 thermal-sensors = <&tsens0 11>;
7578 cpu5-critical {
7586 cpu5-bottom-thermal {
7587 thermal-sensors = <&tsens0 12>;
7590 cpu5-critical {
7598 cpu6-top-thermal {
7599 thermal-sensors = <&tsens0 13>;
7602 cpu6-critical {
7610 cpu6-bottom-thermal {
7611 thermal-sensors = <&tsens0 14>;
7614 cpu6-critical {
7622 aoss1-thermal {
7623 thermal-sensors = <&tsens1 0>;
7626 aoss1-hot {
7632 aoss1-critical {
7640 cpu7-top-thermal {
7641 thermal-sensors = <&tsens1 1>;
7644 cpu7-critical {
7652 cpu7-middle-thermal {
7653 thermal-sensors = <&tsens1 2>;
7656 cpu7-critical {
7664 cpu7-bottom-thermal {
7665 thermal-sensors = <&tsens1 3>;
7668 cpu7-critical {
7676 cpu0-thermal {
7677 thermal-sensors = <&tsens1 4>;
7680 cpu0-critical {
7688 cpu1-thermal {
7689 thermal-sensors = <&tsens1 5>;
7692 cpu1-critical {
7700 nsphvx0-thermal {
7701 thermal-sensors = <&tsens2 6>;
7704 nsphvx0-hot {
7710 nsphvx0-critical {
7718 nsphvx1-thermal {
7719 thermal-sensors = <&tsens2 7>;
7722 nsphvx1-hot {
7728 nsphvx1-critical {
7736 nsphmx0-thermal {
7737 thermal-sensors = <&tsens2 8>;
7740 nsphmx0-hot {
7746 nsphmx0-critical {
7754 nsphmx1-thermal {
7755 thermal-sensors = <&tsens2 9>;
7758 nsphmx1-hot {
7764 nsphmx1-critical {
7772 nsphmx2-thermal {
7773 thermal-sensors = <&tsens2 10>;
7776 nsphmx2-hot {
7782 nsphmx2-critical {
7790 nsphmx3-thermal {
7791 thermal-sensors = <&tsens2 11>;
7794 nsphmx3-hot {
7800 nsphmx3-critical {
7808 video-thermal {
7809 thermal-sensors = <&tsens1 12>;
7812 video-hot {
7818 video-critical {
7826 ddr-thermal {
7827 thermal-sensors = <&tsens1 13>;
7830 ddr-hot {
7836 ddr-critical {
7844 camera0-thermal {
7845 thermal-sensors = <&tsens1 14>;
7848 camera0-hot {
7854 camera0-critical {
7862 camera1-thermal {
7863 thermal-sensors = <&tsens1 15>;
7866 camera1-hot {
7872 camera1-critical {
7880 aoss2-thermal {
7881 thermal-sensors = <&tsens2 0>;
7884 aoss2-hot {
7890 aoss2-critical {
7898 gpuss0-thermal {
7899 polling-delay-passive = <10>;
7901 thermal-sensors = <&tsens2 1>;
7903 cooling-maps {
7906 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
7911 gpu0_alert0: trip-point0 {
7917 trip-point1 {
7923 trip-point2 {
7931 gpuss1-thermal {
7932 polling-delay-passive = <10>;
7934 thermal-sensors = <&tsens2 2>;
7936 cooling-maps {
7939 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
7944 gpu1_alert0: trip-point0 {
7950 trip-point1 {
7956 trip-point2 {
7964 gpuss2-thermal {
7965 polling-delay-passive = <10>;
7967 thermal-sensors = <&tsens2 3>;
7969 cooling-maps {
7972 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
7977 gpu2_alert0: trip-point0 {
7983 trip-point1 {
7989 trip-point2 {
7997 gpuss3-thermal {
7998 polling-delay-passive = <10>;
8000 thermal-sensors = <&tsens2 4>;
8002 cooling-maps {
8005 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
8010 gpu3_alert0: trip-point0 {
8016 trip-point1 {
8022 trip-point2 {
8030 gpuss4-thermal {
8031 polling-delay-passive = <10>;
8033 thermal-sensors = <&tsens2 5>;
8035 cooling-maps {
8038 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
8043 gpu4_alert0: trip-point0 {
8049 trip-point1 {
8055 trip-point2 {
8063 gpuss5-thermal {
8064 polling-delay-passive = <10>;
8066 thermal-sensors = <&tsens2 6>;
8068 cooling-maps {
8071 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
8076 gpu5_alert0: trip-point0 {
8082 trip-point1 {
8088 trip-point2 {
8096 gpuss6-thermal {
8097 polling-delay-passive = <10>;
8099 thermal-sensors = <&tsens2 7>;
8101 cooling-maps {
8104 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
8109 gpu6_alert0: trip-point0 {
8115 trip-point1 {
8121 trip-point2 {
8129 gpuss7-thermal {
8130 polling-delay-passive = <10>;
8132 thermal-sensors = <&tsens2 8>;
8134 cooling-maps {
8137 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
8142 gpu7_alert0: trip-point0 {
8148 trip-point1 {
8154 trip-point2 {
8162 modem0-thermal {
8163 thermal-sensors = <&tsens2 9>;
8166 modem0-hot {
8172 modem0-critical {
8180 modem1-thermal {
8181 thermal-sensors = <&tsens2 10>;
8184 modem1-hot {
8190 modem1-critical {
8198 modem2-thermal {
8199 thermal-sensors = <&tsens2 11>;
8202 modem2-hot {
8208 modem2-critical {
8216 modem3-thermal {
8217 thermal-sensors = <&tsens2 12>;
8220 modem3-hot {
8226 modem3-critical {
8236 compatible = "arm,armv8-timer";