Lines Matching +full:0 +full:xf1d
40 #clock-cells = <0>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
59 #clock-cells = <0>;
69 #size-cells = <0>;
71 cpu0: cpu@0 {
74 reg = <0 0>;
76 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
107 reg = <0 0x100>;
109 clocks = <&cpufreq_hw 0>;
119 qcom,freq-domain = <&cpufreq_hw 0>;
127 reg = <0 0x200>;
154 reg = <0 0x300>;
174 reg = <0 0x400>;
201 reg = <0 0x500>;
228 reg = <0 0x600>;
255 reg = <0 0x700>;
318 silver_cpu_sleep_0: cpu-sleep-0-0 {
321 arm,psci-suspend-param = <0x40000004>;
328 gold_cpu_sleep_0: cpu-sleep-1-0 {
331 arm,psci-suspend-param = <0x40000004>;
338 gold_plus_cpu_sleep_0: cpu-sleep-2-0 {
341 arm,psci-suspend-param = <0x40000004>;
350 cluster_sleep_0: cluster-sleep-0 {
352 arm,psci-suspend-param = <0x41000044>;
360 arm,psci-suspend-param = <0x4100c344>;
405 qcom,dload-mode = <&tcsr 0x19000>;
411 clk_virt: interconnect-0 {
426 reg = <0 0xa0000000 0 0>;
449 #power-domain-cells = <0>;
455 #power-domain-cells = <0>;
461 #power-domain-cells = <0>;
467 #power-domain-cells = <0>;
473 #power-domain-cells = <0>;
479 #power-domain-cells = <0>;
485 #power-domain-cells = <0>;
491 #power-domain-cells = <0>;
497 #power-domain-cells = <0>;
509 reg = <0 0x80000000 0 0xe00000>;
514 reg = <0 0x80e00000 0 0x400000>;
520 reg = <0 0x81a00000 0 0x260000>;
526 reg = <0 0x81c60000 0 0x20000>;
532 reg = <0 0x81c80000 0 0x75000>;
540 reg = <0 0x81d00000 0 0x200000>;
546 reg = <0 0x81f00000 0 0x20000>;
551 reg = <0 0x824a0000 0 0x100000>;
556 reg = <0 0x82600000 0 0x100000>;
561 reg = <0 0x82700000 0 0x100000>;
566 reg = <0 0x82800000 0 0x2000000>;
571 reg = <0 0x84800000 0 0x200000>;
576 reg = <0 0x86b00000 0 0x4900000>;
581 reg = <0 0x8b400000 0 0x800000>;
586 reg = <0 0x8bc00000 0 0xf400000>;
591 reg = <0 0x9b000000 0 0x80000>;
596 reg = <0 0x9b080000 0 0x10000>;
601 reg = <0 0x9b090000 0 0xa000>;
606 reg = <0 0x9b09a000 0 0x2000>;
611 reg = <0 0x9b0a0000 0 0x1e0000>;
617 reg = <0 0x9b280000 0 0x60000>;
623 reg = <0 0x9b2e0000 0 0x20000>;
628 reg = <0 0x9b300000 0 0x800000>;
633 reg = <0 0x9bb00000 0 0x800000>;
638 reg = <0 0x9c300000 0 0x700000>;
643 reg = <0 0x9ca00000 0 0x1400000>;
648 reg = <0 0x9de00000 0 0x80000>;
653 reg = <0 0x9de80000 0 0x80000>;
658 reg = <0 0x9df00000 0 0x4080000>;
664 reg = <0 0xd7c00000 0 0x400000>;
673 reg = <0 0xd8000000 0 0x800000>;
678 reg = <0 0xe6440000 0 0x2dd000>;
683 reg = <0 0xf3800000 0 0x4400000>;
688 reg = <0 0xf7c00000 0 0x4c00000>;
693 reg = <0 0xff800000 0 0x600000>;
709 qcom,local-pid = <0>;
735 qcom,local-pid = <0>;
761 qcom,local-pid = <0>;
787 soc: soc@0 {
792 dma-ranges = <0 0 0 0 0x10 0>;
793 ranges = <0 0 0 0 0x10 0>;
797 reg = <0 0x00100000 0 0x1f4200>;
805 <&ufs_mem_phy 0>,
817 reg = <0 0x00406000 0 0x1000>;
828 reg = <0 0x00800000 0 0x60000>;
844 dma-channel-mask = <0x3f>;
847 iommus = <&apps_smmu 0x436 0>;
856 reg = <0 0x008c0000 0 0x2000>;
863 iommus = <&apps_smmu 0x423 0>;
875 reg = <0 0x00880000 0 0x4000>;
892 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
893 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
897 pinctrl-0 = <&qup_i2c8_data_clk>;
901 #size-cells = <0>;
908 reg = <0 0x00880000 0 0x4000>;
925 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
926 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
930 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
934 #size-cells = <0>;
941 reg = <0 0x00884000 0 0x4000>;
958 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
963 pinctrl-0 = <&qup_i2c9_data_clk>;
967 #size-cells = <0>;
974 reg = <0 0x00884000 0 0x4000>;
991 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
996 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1000 #size-cells = <0>;
1007 reg = <0 0x00888000 0 0x4000>;
1024 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1029 pinctrl-0 = <&qup_i2c10_data_clk>;
1033 #size-cells = <0>;
1040 reg = <0 0x00888000 0 0x4000>;
1057 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1062 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1066 #size-cells = <0>;
1073 reg = <0 0x0088c000 0 0x4000>;
1090 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1095 pinctrl-0 = <&qup_i2c11_data_clk>;
1099 #size-cells = <0>;
1106 reg = <0 0x0088c000 0 0x4000>;
1123 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1128 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1132 #size-cells = <0>;
1139 reg = <0 0x00890000 0 0x4000>;
1156 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1161 pinctrl-0 = <&qup_i2c12_data_clk>;
1165 #size-cells = <0>;
1172 reg = <0 0x00890000 0 0x4000>;
1189 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1194 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1198 #size-cells = <0>;
1205 reg = <0 0x00894000 0 0x4000>;
1222 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1227 pinctrl-0 = <&qup_i2c13_data_clk>;
1231 #size-cells = <0>;
1238 reg = <0 0x00894000 0 0x4000>;
1255 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1260 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1264 #size-cells = <0>;
1271 reg = <0 0x00898000 0 0x4000>;
1285 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
1293 reg = <0 0x0089c000 0 0x4000>;
1307 pinctrl-0 = <&qup_uart15_default>;
1316 reg = <0 0x009c0000 0 0x2000>;
1329 reg = <0 0x00980000 0 0x4000>;
1345 pinctrl-0 = <&hub_i2c0_data_clk>;
1349 #size-cells = <0>;
1356 reg = <0 0x00984000 0 0x4000>;
1372 pinctrl-0 = <&hub_i2c1_data_clk>;
1376 #size-cells = <0>;
1383 reg = <0 0x00988000 0 0x4000>;
1399 pinctrl-0 = <&hub_i2c2_data_clk>;
1403 #size-cells = <0>;
1410 reg = <0 0x0098c000 0 0x4000>;
1426 pinctrl-0 = <&hub_i2c3_data_clk>;
1430 #size-cells = <0>;
1437 reg = <0 0x00990000 0 0x4000>;
1453 pinctrl-0 = <&hub_i2c4_data_clk>;
1457 #size-cells = <0>;
1464 reg = <0 0x00994000 0 0x4000>;
1480 pinctrl-0 = <&hub_i2c5_data_clk>;
1484 #size-cells = <0>;
1491 reg = <0 0x00998000 0 0x4000>;
1507 pinctrl-0 = <&hub_i2c6_data_clk>;
1511 #size-cells = <0>;
1518 reg = <0 0x0099c000 0 0x4000>;
1534 pinctrl-0 = <&hub_i2c7_data_clk>;
1538 #size-cells = <0>;
1545 reg = <0 0x009a0000 0 0x4000>;
1561 pinctrl-0 = <&hub_i2c8_data_clk>;
1565 #size-cells = <0>;
1572 reg = <0 0x009a4000 0 0x4000>;
1588 pinctrl-0 = <&hub_i2c9_data_clk>;
1592 #size-cells = <0>;
1600 reg = <0 0x00a00000 0 0x60000>;
1616 dma-channel-mask = <0xc>;
1619 iommus = <&apps_smmu 0xb6 0>;
1627 reg = <0 0x00ac0000 0 0x2000>;
1638 iommus = <&apps_smmu 0xa3 0>;
1650 reg = <0 0x00a80000 0 0x4000>;
1667 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1668 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1672 pinctrl-0 = <&qup_i2c0_data_clk>;
1676 #size-cells = <0>;
1683 reg = <0 0x00a80000 0 0x4000>;
1700 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1701 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1705 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1709 #size-cells = <0>;
1716 reg = <0 0x00a84000 0 0x4000>;
1733 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1738 pinctrl-0 = <&qup_i2c1_data_clk>;
1742 #size-cells = <0>;
1749 reg = <0 0x00a84000 0 0x4000>;
1766 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1771 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1775 #size-cells = <0>;
1782 reg = <0 0x00a88000 0 0x4000>;
1799 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1804 pinctrl-0 = <&qup_i2c2_data_clk>;
1808 #size-cells = <0>;
1815 reg = <0 0x00a88000 0 0x4000>;
1832 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1837 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1841 #size-cells = <0>;
1848 reg = <0 0x00a8c000 0 0x4000>;
1865 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1870 pinctrl-0 = <&qup_i2c3_data_clk>;
1874 #size-cells = <0>;
1881 reg = <0 0x00a8c000 0 0x4000>;
1898 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1903 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1907 #size-cells = <0>;
1914 reg = <0 0x00a90000 0 0x4000>;
1931 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1936 pinctrl-0 = <&qup_i2c4_data_clk>;
1940 #size-cells = <0>;
1947 reg = <0 0x00a90000 0 0x4000>;
1964 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1969 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1973 #size-cells = <0>;
1980 reg = <0 0x00a94000 0 0x4000>;
1997 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2002 pinctrl-0 = <&qup_i2c5_data_clk>;
2006 #size-cells = <0>;
2013 reg = <0 0x00a94000 0 0x4000>;
2030 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2035 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
2039 #size-cells = <0>;
2046 reg = <0 0x00a98000 0 0x4000>;
2063 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
2068 pinctrl-0 = <&qup_i2c6_data_clk>;
2072 #size-cells = <0>;
2079 reg = <0 0x00a98000 0 0x4000>;
2096 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
2101 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
2105 #size-cells = <0>;
2112 reg = <0 0x00a9c000 0 0x4000>;
2129 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
2134 pinctrl-0 = <&qup_i2c7_data_clk>;
2138 #size-cells = <0>;
2145 reg = <0 0x00a9c000 0 0x4000>;
2162 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
2167 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
2171 #size-cells = <0>;
2179 reg = <0 0x01500000 0 0x14080>;
2188 reg = <0 0x01600000 0 0x6200>;
2197 reg = <0 0x01680000 0 0x1d080>;
2206 reg = <0 0x016c0000 0 0x12200>;
2218 reg = <0 0x016e0000 0 0x16400>;
2230 reg = <0 0x01700000 0 0x1e400>;
2241 reg = <0 0x01780000 0 0x5b800>;
2250 reg = <0 0x010c3000 0 0x1000>;
2256 reg = <0 0x01c00000 0 0x3000>,
2257 <0 0x60000000 0 0xf1d>,
2258 <0 0x60000f20 0 0xa8>,
2259 <0 0x60001000 0 0x1000>,
2260 <0 0x60100000 0 0x100000>;
2311 iommu-map = <0 &apps_smmu 0x1400 0x1>,
2312 <0x100 &apps_smmu 0x1401 0x1>;
2314 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
2315 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
2316 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
2317 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
2318 interrupt-map-mask = <0 0 0 0x7>;
2321 msi-map = <0x0 &gic_its 0x1400 0x1>,
2322 <0x100 &gic_its 0x1401 0x1>;
2323 msi-map-mask = <0xff00>;
2325 linux,pci-domain = <0>;
2327 bus-range = <0 0xff>;
2334 ranges = <0x01000000 0 0x00000000 0 0x60200000 0 0x100000>,
2335 <0x02000000 0 0x60300000 0 0x60300000 0 0x3d00000>;
2341 pcieport0: pcie@0 {
2343 reg = <0x0 0x0 0x0 0x0 0x0>;
2344 bus-range = <0x01 0xff>;
2354 reg = <0 0x01c06000 0 0x2000>;
2375 #clock-cells = <0>;
2378 #phy-cells = <0>;
2386 reg = <0 0x01c08000 0 0x3000>,
2387 <0 0x40000000 0 0xf1d>,
2388 <0 0x40000f20 0 0xa8>,
2389 <0 0x40001000 0 0x1000>,
2390 <0 0x40100000 0 0x100000>;
2450 iommu-map = <0 &apps_smmu 0x1480 0x1>,
2451 <0x100 &apps_smmu 0x1481 0x1>;
2453 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2454 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,
2455 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
2456 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
2457 interrupt-map-mask = <0 0 0 0x7>;
2460 msi-map = <0x0 &gic_its 0x1480 0x1>,
2461 <0x100 &gic_its 0x1481 0x1>;
2462 msi-map-mask = <0xff00>;
2466 bus-range = <0 0xff>;
2475 ranges = <0x01000000 0 0x00000000 0 0x40200000 0 0x100000>,
2476 <0x02000000 0 0x40300000 0 0x40300000 0 0x1fd00000>;
2480 pcie@0 {
2482 reg = <0x0 0x0 0x0 0x0 0x0>;
2483 bus-range = <0x01 0xff>;
2493 reg = <0 0x01c0e000 0 0x2000>;
2519 #phy-cells = <0>;
2526 reg = <0 0x01dc4000 0 0x28000>;
2532 iommus = <&apps_smmu 0x480 0>,
2533 <&apps_smmu 0x481 0>;
2535 qcom,ee = <0>;
2541 reg = <0 0x01dfa000 0 0x6000>;
2550 iommus = <&apps_smmu 0x480 0>,
2551 <&apps_smmu 0x481 0>;
2556 reg = <0 0x01d80000 0 0x2000>;
2565 resets = <&ufs_mem_hc 0>;
2571 #phy-cells = <0>;
2578 reg = <0 0x01d84000 0 0x3000>;
2599 <0 0>,
2600 <0 0>,
2603 <0 0>,
2604 <0 0>,
2605 <0 0>;
2620 iommus = <&apps_smmu 0x60 0>;
2636 reg = <0 0x01d88000 0 0x18000>;
2643 reg = <0 0x01f40000 0 0x20000>;
2650 reg = <0 0x01fc0000 0 0xa0000>;
2660 reg = <0x0 0x03d00000 0x0 0x40000>,
2661 <0x0 0x03d9e000 0x0 0x2000>,
2662 <0x0 0x03d61000 0x0 0x800>;
2669 iommus = <&adreno_smmu 0 0x0>,
2670 <&adreno_smmu 1 0x0>;
2761 reg = <0x0 0x03d6a000 0x0 0x35000>,
2762 <0x0 0x03d50000 0x0 0x10000>,
2763 <0x0 0x0b280000 0x0 0x10000>;
2790 iommus = <&adreno_smmu 5 0x0>;
2813 reg = <0 0x03d90000 0 0xa000>;
2827 reg = <0x0 0x03da0000 0x0 0x40000>;
2871 iommus = <&apps_smmu 0x4a0 0x0>,
2872 <&apps_smmu 0x4a2 0x0>;
2873 reg = <0 0x3f40000 0 0x10000>,
2874 <0 0x3f50000 0 0x5000>,
2875 <0 0x3e04000 0 0xfc000>;
2882 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2892 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
2893 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2899 qcom,smem-states = <&ipa_smp2p_out 0>,
2909 reg = <0x0 0x04080000 0x0 0x10000>;
2912 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2941 qcom,smem-states = <&smp2p_modem_out 0>;
2962 reg = <0x0 0x06800000 0x0 0x10000>;
2965 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2990 qcom,smem-states = <&smp2p_adsp_out 0>;
3017 #size-cells = <0>;
3023 iommus = <&apps_smmu 0x1003 0x80>,
3024 <&apps_smmu 0x1043 0x20>;
3032 iommus = <&apps_smmu 0x1004 0x80>,
3033 <&apps_smmu 0x1044 0x20>;
3041 iommus = <&apps_smmu 0x1005 0x80>,
3042 <&apps_smmu 0x1045 0x20>;
3050 iommus = <&apps_smmu 0x1006 0x80>,
3051 <&apps_smmu 0x1046 0x20>;
3059 iommus = <&apps_smmu 0x1007 0x40>,
3060 <&apps_smmu 0x1067 0x0>,
3061 <&apps_smmu 0x1087 0x0>;
3072 #size-cells = <0>;
3077 #sound-dai-cells = <0>;
3088 iommus = <&apps_smmu 0x1001 0x80>,
3089 <&apps_smmu 0x1061 0x0>;
3110 reg = <0 0x06aa0000 0 0x1000>;
3120 #clock-cells = <0>;
3127 reg = <0 0x06ab0000 0 0x10000>;
3133 pinctrl-0 = <&wsa2_swr_active>;
3139 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
3140 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
3141 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3142 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3143 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3144 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
3145 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
3146 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3147 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3150 #size-cells = <0>;
3157 reg = <0 0x06ac0000 0 0x1000>;
3167 #clock-cells = <0>;
3174 reg = <0 0x06ad0000 0 0x10000>;
3180 pinctrl-0 = <&rx_swr_active>;
3183 qcom,din-ports = <0>;
3186 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x03 0xff 0xff 0x31 0xff 0xff 0xff>;
3187 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x09 0x01 0xff 0xff 0x00 0xff 0xff 0xff>;
3188 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>;
3189 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0xff 0xff 0x00 0xff 0xff 0xff>;
3190 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0xff 0xff 0x0f 0xff 0xff 0xff>;
3191 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0x18 0xff 0xff 0xff>;
3192 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff 0xff 0x01 0xff 0xff 0xff>;
3193 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0x01 0x03 0xff 0xff 0x00 0xff 0xff 0xff>;
3194 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0xff 0xff 0xff>;
3197 #size-cells = <0>;
3204 reg = <0 0x06ae0000 0 0x1000>;
3214 #clock-cells = <0>;
3221 reg = <0 0x06b00000 0 0x1000>;
3231 #clock-cells = <0>;
3238 reg = <0 0x06b10000 0 0x10000>;
3244 pinctrl-0 = <&wsa_swr_active>;
3250 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
3251 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
3252 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3253 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3254 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3255 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
3256 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
3257 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3258 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3261 #size-cells = <0>;
3268 reg = <0 0x06d30000 0 0x10000>;
3276 pinctrl-0 = <&tx_swr_active>;
3280 qcom,dout-ports = <0>;
3282 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
3283 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
3284 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
3285 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
3286 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
3287 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
3288 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
3289 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
3290 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
3293 #size-cells = <0>;
3300 reg = <0 0x06d44000 0 0x1000>;
3308 #clock-cells = <0>;
3315 reg = <0 0x06e80000 0 0x20000>;
3323 gpio-ranges = <&lpass_tlmm 0 0 23>;
3432 reg = <0 0x07400000 0 0x19080>;
3441 reg = <0 0x07430000 0 0x3a200>;
3450 reg = <0 0x07e40000 0 0xe080>;
3459 reg = <0 0x08804000 0 0x1000>;
3483 iommus = <&apps_smmu 0x540 0>;
3488 sdhci-caps-mask = <0x3 0>;
3490 qcom,dll-config = <0x0007642c>;
3491 qcom,ddr-config = <0x80040868>;
3524 reg = <0 0x0aaf0000 0 0x10000>;
3535 reg = <0 0x0ac15000 0 0x1000>;
3544 pinctrl-0 = <&cci0_0_default &cci0_1_default>;
3549 #size-cells = <0>;
3551 cci0_i2c0: i2c-bus@0 {
3552 reg = <0>;
3555 #size-cells = <0>;
3562 #size-cells = <0>;
3568 reg = <0 0x0ac16000 0 0x1000>;
3577 pinctrl-0 = <&cci1_0_default &cci1_1_default>;
3582 #size-cells = <0>;
3584 cci1_i2c0: i2c-bus@0 {
3585 reg = <0>;
3588 #size-cells = <0>;
3595 #size-cells = <0>;
3601 reg = <0 0x0ac17000 0 0x1000>;
3610 pinctrl-0 = <&cci2_0_default &cci2_1_default>;
3615 #size-cells = <0>;
3617 cci2_i2c0: i2c-bus@0 {
3618 reg = <0>;
3621 #size-cells = <0>;
3628 #size-cells = <0>;
3634 reg = <0 0x0ade0000 0 0x20000>;
3647 reg = <0 0x0ae00000 0 0x1000>;
3664 iommus = <&apps_smmu 0x1c00 0x2>;
3677 reg = <0 0x0ae01000 0 0x8f000>,
3678 <0 0x0aeb0000 0 0x2008>;
3682 interrupts-extended = <&mdss 0>;
3704 #size-cells = <0>;
3706 port@0 {
3707 reg = <0>;
3758 reg = <0 0x0ae94000 0 0x400>;
3778 assigned-clock-parents = <&mdss_dsi0_phy 0>,
3789 #size-cells = <0>;
3795 #size-cells = <0>;
3797 port@0 {
3798 reg = <0>;
3835 reg = <0 0x0ae95000 0 0x200>,
3836 <0 0x0ae95200 0 0x280>,
3837 <0 0x0ae95500 0 0x400>;
3848 #phy-cells = <0>;
3855 reg = <0 0x0ae96000 0 0x400>;
3875 assigned-clock-parents = <&mdss_dsi1_phy 0>,
3886 #size-cells = <0>;
3892 #size-cells = <0>;
3894 port@0 {
3895 reg = <0>;
3913 reg = <0 0x0ae97000 0 0x200>,
3914 <0 0x0ae97200 0 0x280>,
3915 <0 0x0ae97500 0 0x400>;
3926 #phy-cells = <0>;
3933 reg = <0 0xaf54000 0 0x104>,
3934 <0 0xaf54200 0 0xc0>,
3935 <0 0xaf55000 0 0x770>,
3936 <0 0xaf56000 0 0x9c>,
3937 <0 0xaf57000 0 0x9c>;
3964 #sound-dai-cells = <0>;
3994 #size-cells = <0>;
3996 port@0 {
3997 reg = <0>;
4017 reg = <0 0x0af00000 0 0x20000>;
4023 <&mdss_dsi0_phy 0>,
4025 <&mdss_dsi1_phy 0>,
4029 <0>, /* dp1 */
4030 <0>,
4031 <0>, /* dp2 */
4032 <0>,
4033 <0>, /* dp3 */
4034 <0>;
4047 reg = <0 0x088e3000 0 0x154>;
4054 #phy-cells = <0>;
4061 reg = <0 0x088e8000 0 0x3000>;
4088 #size-cells = <0>;
4090 port@0 {
4091 reg = <0>;
4117 reg = <0 0x0a6f8800 0 0x400>;
4160 reg = <0 0x0a600000 0 0xcd00>;
4164 iommus = <&apps_smmu 0x40 0>;
4171 snps,hird-threshold = /bits/ 8 <0x0>;
4187 #size-cells = <0>;
4189 port@0 {
4190 reg = <0>;
4209 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
4213 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
4223 reg = <0 0x0c228000 0 0x1000>, /* TM */
4224 <0 0x0c222000 0 0x1000>; /* SROT */
4238 reg = <0 0x0c229000 0 0x1000>, /* TM */
4239 <0 0x0c223000 0 0x1000>; /* SROT */
4253 reg = <0 0x0c22a000 0 0x1000>, /* TM */
4254 <0 0x0c224000 0 0x1000>; /* SROT */
4268 reg = <0 0x0c300000 0 0x400>;
4276 #clock-cells = <0>;
4281 reg = <0 0x0c3f0000 0 0x400>;
4286 reg = <0 0x0c400000 0 0x3000>,
4287 <0 0x0c500000 0 0x400000>,
4288 <0 0x0c440000 0 0x80000>,
4289 <0 0x0c4c0000 0 0x20000>,
4290 <0 0x0c42d000 0 0x4000>;
4300 qcom,ee = <0>;
4301 qcom,channel = <0>;
4302 qcom,bus-id = <0>;
4308 #size-cells = <0>;
4313 reg = <0 0x0f100000 0 0x300000>;
4323 gpio-ranges = <&tlmm 0 0 211>;
4327 cci0_0_default: cci0-0-default-state {
4343 cci0_0_sleep: cci0-0-sleep-state {
4391 cci1_0_default: cci1-0-default-state {
4407 cci1_0_sleep: cci1-0-sleep-state {
4455 cci2_0_default: cci2-0-default-state {
4471 cci2_0_sleep: cci2-0-sleep-state {
5058 reg = <0x0 0x10042000 0x0 0x1000>;
5065 #size-cells = <0>;
5088 reg = <0x0 0x10045000 0x0 0x1000>;
5095 #size-cells = <0>;
5118 reg = <0x0 0x10b04000 0x0 0x1000>;
5125 #size-cells = <0>;
5148 reg = <0x0 0x10b05000 0x0 0x1000>;
5165 reg = <0x0 0x13810000 0x0 0x1000>;
5189 reg = <0 0x15000000 0 0x100000>;
5297 reg = <0 0x17100000 0 0x10000>, /* GICD */
5298 <0 0x17180000 0 0x200000>; /* GICR * 8 */
5306 redistributor-stride = <0 0x40000>;
5314 reg = <0 0x17140000 0 0x20000>;
5323 reg = <0 0x17420000 0 0x1000>;
5325 ranges = <0 0 0 0x20000000>;
5330 reg = <0x17421000 0x1000>,
5331 <0x17422000 0x1000>;
5336 frame-number = <0>;
5340 reg = <0x17423000 0x1000>;
5350 reg = <0x17425000 0x1000>;
5360 reg = <0x17427000 0x1000>;
5370 reg = <0x17429000 0x1000>;
5380 reg = <0x1742b000 0x1000>;
5390 reg = <0x1742d000 0x1000>;
5402 reg = <0 0x17a00000 0 0x10000>,
5403 <0 0x17a10000 0 0x10000>,
5404 <0 0x17a20000 0 0x10000>,
5405 <0 0x17a30000 0 0x10000>;
5406 reg-names = "drv-0",
5416 qcom,tcs-offset = <0xd00>;
5419 <WAKE_TCS 2>, <CONTROL_TCS 0>;
5511 reg = <0 0x17d91000 0 0x1000>,
5512 <0 0x17d92000 0 0x1000>,
5513 <0 0x17d93000 0 0x1000>,
5514 <0 0x17d94000 0 0x1000>;
5524 interrupt-names = "dcvsh-irq-0",
5538 reg = <0 0x24091000 0 0x1000>;
5550 opp-0 {
5590 reg = <0 0x240b7400 0 0x600>;
5602 opp-0 {
5630 reg = <0 0x24100000 0 0xc5080>;
5639 reg = <0 0x25000000 0 0x200000>,
5640 <0 0x25400000 0 0x200000>,
5641 <0 0x25200000 0 0x200000>,
5642 <0 0x25600000 0 0x200000>,
5643 <0 0x25800000 0 0x200000>,
5644 <0 0x25a00000 0 0x200000>;
5657 reg = <0 0x320c0000 0 0xf080>;
5666 reg = <0x0 0x32300000 0x0 0x10000>;
5669 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
5696 qcom,smem-states = <&smp2p_cdsp_out 0>;
5723 #size-cells = <0>;
5729 iommus = <&apps_smmu 0x1961 0x0>,
5730 <&apps_smmu 0x0c01 0x20>,
5731 <&apps_smmu 0x19c1 0x0>;
5739 iommus = <&apps_smmu 0x1962 0x0>,
5740 <&apps_smmu 0x0c02 0x20>,
5741 <&apps_smmu 0x19c2 0x0>;
5749 iommus = <&apps_smmu 0x1963 0x0>,
5750 <&apps_smmu 0x0c03 0x20>,
5751 <&apps_smmu 0x19c3 0x0>;
5759 iommus = <&apps_smmu 0x1964 0x0>,
5760 <&apps_smmu 0x0c04 0x20>,
5761 <&apps_smmu 0x19c4 0x0>;
5769 iommus = <&apps_smmu 0x1965 0x0>,
5770 <&apps_smmu 0x0c05 0x20>,
5771 <&apps_smmu 0x19c5 0x0>;
5779 iommus = <&apps_smmu 0x1966 0x0>,
5780 <&apps_smmu 0x0c06 0x20>,
5781 <&apps_smmu 0x19c6 0x0>;
5789 iommus = <&apps_smmu 0x1967 0x0>,
5790 <&apps_smmu 0x0c07 0x20>,
5791 <&apps_smmu 0x19c7 0x0>;
5799 iommus = <&apps_smmu 0x1968 0x0>,
5800 <&apps_smmu 0x0c08 0x20>,
5801 <&apps_smmu 0x19c8 0x0>;
5811 iommus = <&apps_smmu 0x196c 0x0>,
5812 <&apps_smmu 0x0c0c 0x20>,
5813 <&apps_smmu 0x19cc 0x0>;
5821 iommus = <&apps_smmu 0x196d 0x0>,
5822 <&apps_smmu 0x0c0d 0x20>,
5823 <&apps_smmu 0x19cd 0x0>;
5831 iommus = <&apps_smmu 0x196e 0x0>,
5832 <&apps_smmu 0x0c0e 0x20>,
5833 <&apps_smmu 0x19ce 0x0>;
5843 thermal-sensors = <&tsens0 0>;
5854 hysteresis = <0>;
5872 hysteresis = <0>;
5890 hysteresis = <0>;
5908 hysteresis = <0>;
5926 hysteresis = <0>;
6173 thermal-sensors = <&tsens1 0>;
6184 hysteresis = <0>;
6324 hysteresis = <0>;
6344 hysteresis = <0>;
6364 hysteresis = <0>;
6384 hysteresis = <0>;
6404 hysteresis = <0>;
6424 hysteresis = <0>;
6444 hysteresis = <0>;
6464 hysteresis = <0>;
6482 hysteresis = <0>;
6500 hysteresis = <0>;
6507 thermal-sensors = <&tsens2 0>;
6518 hysteresis = <0>;
6800 hysteresis = <0>;
6818 hysteresis = <0>;
6836 hysteresis = <0>;
6854 hysteresis = <0>;