Lines Matching +full:0 +full:x0c400000
40 #clock-cells = <0>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
59 #clock-cells = <0>;
69 #size-cells = <0>;
71 CPU0: cpu@0 {
74 reg = <0 0>;
76 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
107 reg = <0 0x100>;
109 clocks = <&cpufreq_hw 0>;
119 qcom,freq-domain = <&cpufreq_hw 0>;
127 reg = <0 0x200>;
154 reg = <0 0x300>;
174 reg = <0 0x400>;
201 reg = <0 0x500>;
228 reg = <0 0x600>;
255 reg = <0 0x700>;
318 SILVER_CPU_SLEEP_0: cpu-sleep-0-0 {
321 arm,psci-suspend-param = <0x40000004>;
328 GOLD_CPU_SLEEP_0: cpu-sleep-1-0 {
331 arm,psci-suspend-param = <0x40000004>;
338 GOLD_PLUS_CPU_SLEEP_0: cpu-sleep-2-0 {
341 arm,psci-suspend-param = <0x40000004>;
350 CLUSTER_SLEEP_0: cluster-sleep-0 {
352 arm,psci-suspend-param = <0x41000044>;
360 arm,psci-suspend-param = <0x4100c344>;
371 qcom,dload-mode = <&tcsr 0x19000>;
377 clk_virt: interconnect-0 {
392 reg = <0 0xa0000000 0 0>;
415 #power-domain-cells = <0>;
421 #power-domain-cells = <0>;
427 #power-domain-cells = <0>;
433 #power-domain-cells = <0>;
439 #power-domain-cells = <0>;
445 #power-domain-cells = <0>;
451 #power-domain-cells = <0>;
457 #power-domain-cells = <0>;
463 #power-domain-cells = <0>;
475 reg = <0 0x80000000 0 0xe00000>;
480 reg = <0 0x80e00000 0 0x400000>;
486 reg = <0 0x81a00000 0 0x260000>;
492 reg = <0 0x81c60000 0 0x20000>;
498 reg = <0 0x81c80000 0 0x75000>;
506 reg = <0 0x81d00000 0 0x200000>;
512 reg = <0 0x81f00000 0 0x20000>;
517 reg = <0 0x824a0000 0 0x100000>;
522 reg = <0 0x82600000 0 0x100000>;
527 reg = <0 0x82700000 0 0x100000>;
532 reg = <0 0x82800000 0 0x2000000>;
537 reg = <0 0x84800000 0 0x200000>;
542 reg = <0 0x86b00000 0 0x4900000>;
547 reg = <0 0x8b400000 0 0x800000>;
552 reg = <0 0x8bc00000 0 0xf400000>;
557 reg = <0 0x9b000000 0 0x80000>;
562 reg = <0 0x9b080000 0 0x10000>;
567 reg = <0 0x9b090000 0 0xa000>;
572 reg = <0 0x9b09a000 0 0x2000>;
577 reg = <0 0x9b0a0000 0 0x1e0000>;
583 reg = <0 0x9b280000 0 0x60000>;
589 reg = <0 0x9b2e0000 0 0x20000>;
594 reg = <0 0x9b300000 0 0x800000>;
599 reg = <0 0x9bb00000 0 0x800000>;
604 reg = <0 0x9c300000 0 0x700000>;
609 reg = <0 0x9ca00000 0 0x1400000>;
614 reg = <0 0x9de00000 0 0x80000>;
619 reg = <0 0x9de80000 0 0x80000>;
624 reg = <0 0x9df00000 0 0x4080000>;
630 reg = <0 0xd7c00000 0 0x400000>;
639 reg = <0 0xd8000000 0 0x800000>;
644 reg = <0 0xe6440000 0 0x2dd000>;
649 reg = <0 0xf3800000 0 0x4400000>;
654 reg = <0 0xf7c00000 0 0x4c00000>;
659 reg = <0 0xff800000 0 0x600000>;
675 qcom,local-pid = <0>;
701 qcom,local-pid = <0>;
727 qcom,local-pid = <0>;
753 soc: soc@0 {
758 dma-ranges = <0 0 0 0 0x10 0>;
759 ranges = <0 0 0 0 0x10 0>;
763 reg = <0 0x00100000 0 0x1f4200>;
771 <&ufs_mem_phy 0>,
783 reg = <0 0x00406000 0 0x1000>;
794 reg = <0 0x00800000 0 0x60000>;
810 dma-channel-mask = <0x3f>;
813 iommus = <&apps_smmu 0x436 0>;
822 reg = <0 0x008c0000 0 0x2000>;
829 iommus = <&apps_smmu 0x423 0>;
841 reg = <0 0x00880000 0 0x4000>;
858 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
859 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
863 pinctrl-0 = <&qup_i2c8_data_clk>;
867 #size-cells = <0>;
874 reg = <0 0x00880000 0 0x4000>;
891 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
892 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
896 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
900 #size-cells = <0>;
907 reg = <0 0x00884000 0 0x4000>;
924 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
929 pinctrl-0 = <&qup_i2c9_data_clk>;
933 #size-cells = <0>;
940 reg = <0 0x00884000 0 0x4000>;
957 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
962 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
966 #size-cells = <0>;
973 reg = <0 0x00888000 0 0x4000>;
990 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
995 pinctrl-0 = <&qup_i2c10_data_clk>;
999 #size-cells = <0>;
1006 reg = <0 0x00888000 0 0x4000>;
1023 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1028 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1032 #size-cells = <0>;
1039 reg = <0 0x0088c000 0 0x4000>;
1056 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1061 pinctrl-0 = <&qup_i2c11_data_clk>;
1065 #size-cells = <0>;
1072 reg = <0 0x0088c000 0 0x4000>;
1089 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1094 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1098 #size-cells = <0>;
1105 reg = <0 0x00890000 0 0x4000>;
1122 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1127 pinctrl-0 = <&qup_i2c12_data_clk>;
1131 #size-cells = <0>;
1138 reg = <0 0x00890000 0 0x4000>;
1155 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1160 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1164 #size-cells = <0>;
1171 reg = <0 0x00894000 0 0x4000>;
1188 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1193 pinctrl-0 = <&qup_i2c13_data_clk>;
1197 #size-cells = <0>;
1204 reg = <0 0x00894000 0 0x4000>;
1221 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1226 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1230 #size-cells = <0>;
1237 reg = <0 0x00898000 0 0x4000>;
1251 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
1259 reg = <0 0x0089c000 0 0x4000>;
1273 pinctrl-0 = <&qup_uart15_default>;
1282 reg = <0 0x009c0000 0 0x2000>;
1295 reg = <0 0x00980000 0 0x4000>;
1311 pinctrl-0 = <&hub_i2c0_data_clk>;
1315 #size-cells = <0>;
1322 reg = <0 0x00984000 0 0x4000>;
1338 pinctrl-0 = <&hub_i2c1_data_clk>;
1342 #size-cells = <0>;
1349 reg = <0 0x00988000 0 0x4000>;
1365 pinctrl-0 = <&hub_i2c2_data_clk>;
1369 #size-cells = <0>;
1376 reg = <0 0x0098c000 0 0x4000>;
1392 pinctrl-0 = <&hub_i2c3_data_clk>;
1396 #size-cells = <0>;
1403 reg = <0 0x00990000 0 0x4000>;
1419 pinctrl-0 = <&hub_i2c4_data_clk>;
1423 #size-cells = <0>;
1430 reg = <0 0x00994000 0 0x4000>;
1446 pinctrl-0 = <&hub_i2c5_data_clk>;
1450 #size-cells = <0>;
1457 reg = <0 0x00998000 0 0x4000>;
1473 pinctrl-0 = <&hub_i2c6_data_clk>;
1477 #size-cells = <0>;
1484 reg = <0 0x0099c000 0 0x4000>;
1500 pinctrl-0 = <&hub_i2c7_data_clk>;
1504 #size-cells = <0>;
1511 reg = <0 0x009a0000 0 0x4000>;
1527 pinctrl-0 = <&hub_i2c8_data_clk>;
1531 #size-cells = <0>;
1538 reg = <0 0x009a4000 0 0x4000>;
1554 pinctrl-0 = <&hub_i2c9_data_clk>;
1558 #size-cells = <0>;
1566 reg = <0 0x00a00000 0 0x60000>;
1582 dma-channel-mask = <0xc>;
1585 iommus = <&apps_smmu 0xb6 0>;
1593 reg = <0 0x00ac0000 0 0x2000>;
1604 iommus = <&apps_smmu 0xa3 0>;
1616 reg = <0 0x00a80000 0 0x4000>;
1633 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1634 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1638 pinctrl-0 = <&qup_i2c0_data_clk>;
1642 #size-cells = <0>;
1649 reg = <0 0x00a80000 0 0x4000>;
1666 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1667 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1671 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1675 #size-cells = <0>;
1682 reg = <0 0x00a84000 0 0x4000>;
1699 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1704 pinctrl-0 = <&qup_i2c1_data_clk>;
1708 #size-cells = <0>;
1715 reg = <0 0x00a84000 0 0x4000>;
1732 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1737 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1741 #size-cells = <0>;
1748 reg = <0 0x00a88000 0 0x4000>;
1765 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1770 pinctrl-0 = <&qup_i2c2_data_clk>;
1774 #size-cells = <0>;
1781 reg = <0 0x00a88000 0 0x4000>;
1798 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1803 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1807 #size-cells = <0>;
1814 reg = <0 0x00a8c000 0 0x4000>;
1831 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1836 pinctrl-0 = <&qup_i2c3_data_clk>;
1840 #size-cells = <0>;
1847 reg = <0 0x00a8c000 0 0x4000>;
1864 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1869 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1873 #size-cells = <0>;
1880 reg = <0 0x00a90000 0 0x4000>;
1897 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1902 pinctrl-0 = <&qup_i2c4_data_clk>;
1906 #size-cells = <0>;
1913 reg = <0 0x00a90000 0 0x4000>;
1930 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1935 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1939 #size-cells = <0>;
1946 reg = <0 0x00a94000 0 0x4000>;
1963 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1968 pinctrl-0 = <&qup_i2c5_data_clk>;
1972 #size-cells = <0>;
1979 reg = <0 0x00a94000 0 0x4000>;
1996 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2001 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
2005 #size-cells = <0>;
2012 reg = <0 0x00a98000 0 0x4000>;
2029 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
2034 pinctrl-0 = <&qup_i2c6_data_clk>;
2038 #size-cells = <0>;
2045 reg = <0 0x00a98000 0 0x4000>;
2062 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
2067 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
2071 #size-cells = <0>;
2078 reg = <0 0x00a9c000 0 0x4000>;
2095 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
2100 pinctrl-0 = <&qup_i2c7_data_clk>;
2104 #size-cells = <0>;
2111 reg = <0 0x00a9c000 0 0x4000>;
2128 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
2133 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
2137 #size-cells = <0>;
2145 reg = <0 0x01500000 0 0x14080>;
2154 reg = <0 0x01600000 0 0x6200>;
2163 reg = <0 0x01680000 0 0x1d080>;
2172 reg = <0 0x016c0000 0 0x12200>;
2184 reg = <0 0x016e0000 0 0x16400>;
2196 reg = <0 0x01700000 0 0x1e400>;
2207 reg = <0 0x01780000 0 0x5b800>;
2216 reg = <0 0x010c3000 0 0x1000>;
2222 reg = <0 0x01c00000 0 0x3000>,
2223 <0 0x60000000 0 0xf1d>,
2224 <0 0x60000f20 0 0xa8>,
2225 <0 0x60001000 0 0x1000>,
2226 <0 0x60100000 0 0x100000>;
2275 iommu-map = <0 &apps_smmu 0x1400 0x1>,
2276 <0x100 &apps_smmu 0x1401 0x1>;
2278 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
2279 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
2280 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
2281 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
2282 interrupt-map-mask = <0 0 0 0x7>;
2285 msi-map = <0x0 &gic_its 0x1400 0x1>,
2286 <0x100 &gic_its 0x1401 0x1>;
2287 msi-map-mask = <0xff00>;
2289 linux,pci-domain = <0>;
2291 bus-range = <0 0xff>;
2298 ranges = <0x01000000 0 0x00000000 0 0x60200000 0 0x100000>,
2299 <0x02000000 0 0x60300000 0 0x60300000 0 0x3d00000>;
2305 pcieport0: pcie@0 {
2307 reg = <0x0 0x0 0x0 0x0 0x0>;
2308 bus-range = <0x01 0xff>;
2318 reg = <0 0x01c06000 0 0x2000>;
2339 #clock-cells = <0>;
2342 #phy-cells = <0>;
2350 reg = <0 0x01c08000 0 0x3000>,
2351 <0 0x40000000 0 0xf1d>,
2352 <0 0x40000f20 0 0xa8>,
2353 <0 0x40001000 0 0x1000>,
2354 <0 0x40100000 0 0x100000>;
2412 iommu-map = <0 &apps_smmu 0x1480 0x1>,
2413 <0x100 &apps_smmu 0x1481 0x1>;
2415 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2416 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,
2417 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
2418 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
2419 interrupt-map-mask = <0 0 0 0x7>;
2422 msi-map = <0x0 &gic_its 0x1480 0x1>,
2423 <0x100 &gic_its 0x1481 0x1>;
2424 msi-map-mask = <0xff00>;
2428 bus-range = <0 0xff>;
2437 ranges = <0x01000000 0 0x00000000 0 0x40200000 0 0x100000>,
2438 <0x02000000 0 0x40300000 0 0x40300000 0 0x1fd00000>;
2442 pcie@0 {
2444 reg = <0x0 0x0 0x0 0x0 0x0>;
2445 bus-range = <0x01 0xff>;
2455 reg = <0 0x01c0e000 0 0x2000>;
2481 #phy-cells = <0>;
2488 reg = <0 0x01dc4000 0 0x28000>;
2494 iommus = <&apps_smmu 0x480 0>,
2495 <&apps_smmu 0x481 0>;
2497 qcom,ee = <0>;
2503 reg = <0 0x01dfa000 0 0x6000>;
2512 iommus = <&apps_smmu 0x480 0>,
2513 <&apps_smmu 0x481 0>;
2518 reg = <0 0x01d80000 0 0x2000>;
2527 resets = <&ufs_mem_hc 0>;
2533 #phy-cells = <0>;
2540 reg = <0 0x01d84000 0 0x3000>;
2561 <0 0>,
2562 <0 0>,
2565 <0 0>,
2566 <0 0>,
2567 <0 0>;
2582 iommus = <&apps_smmu 0x60 0>;
2598 reg = <0 0x01d88000 0 0x8000>;
2605 reg = <0 0x01f40000 0 0x20000>;
2612 reg = <0 0x01fc0000 0 0xa0000>;
2622 reg = <0x0 0x03d00000 0x0 0x40000>,
2623 <0x0 0x03d9e000 0x0 0x2000>,
2624 <0x0 0x03d61000 0x0 0x800>;
2631 iommus = <&adreno_smmu 0 0x0>,
2632 <&adreno_smmu 1 0x0>;
2708 reg = <0x0 0x03d6a000 0x0 0x35000>,
2709 <0x0 0x03d50000 0x0 0x10000>,
2710 <0x0 0x0b280000 0x0 0x10000>;
2737 iommus = <&adreno_smmu 5 0x0>;
2760 reg = <0 0x03d90000 0 0xa000>;
2774 reg = <0x0 0x03da0000 0x0 0x40000>;
2818 iommus = <&apps_smmu 0x4a0 0x0>,
2819 <&apps_smmu 0x4a2 0x0>;
2820 reg = <0 0x3f40000 0 0x10000>,
2821 <0 0x3f50000 0 0x5000>,
2822 <0 0x3e04000 0 0xfc000>;
2829 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2839 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
2840 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2846 qcom,smem-states = <&ipa_smp2p_out 0>,
2856 reg = <0 0x04080000 0 0x4040>;
2859 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2888 qcom,smem-states = <&smp2p_modem_out 0>;
2909 reg = <0 0x06aa0000 0 0x1000>;
2919 #clock-cells = <0>;
2926 reg = <0 0x06ab0000 0 0x10000>;
2932 pinctrl-0 = <&wsa2_swr_active>;
2938 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
2939 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2940 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2941 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2942 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2943 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
2944 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
2945 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2946 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2949 #size-cells = <0>;
2956 reg = <0 0x06ac0000 0 0x1000>;
2966 #clock-cells = <0>;
2973 reg = <0 0x06ad0000 0 0x10000>;
2979 pinctrl-0 = <&rx_swr_active>;
2982 qcom,din-ports = <0>;
2985 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x03 0xff 0xff 0x31 0xff 0xff 0xff>;
2986 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x09 0x01 0xff 0xff 0x00 0xff 0xff 0xff>;
2987 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>;
2988 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0xff 0xff 0x00 0xff 0xff 0xff>;
2989 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0xff 0xff 0x0f 0xff 0xff 0xff>;
2990 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0x18 0xff 0xff 0xff>;
2991 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff 0xff 0x01 0xff 0xff 0xff>;
2992 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0x01 0x03 0xff 0xff 0x00 0xff 0xff 0xff>;
2993 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0xff 0xff 0xff>;
2996 #size-cells = <0>;
3003 reg = <0 0x06ae0000 0 0x1000>;
3013 #clock-cells = <0>;
3020 reg = <0 0x06b00000 0 0x1000>;
3030 #clock-cells = <0>;
3037 reg = <0 0x06b10000 0 0x10000>;
3043 pinctrl-0 = <&wsa_swr_active>;
3049 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
3050 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
3051 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3052 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3053 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3054 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
3055 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
3056 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
3057 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
3060 #size-cells = <0>;
3067 reg = <0 0x06d30000 0 0x10000>;
3075 pinctrl-0 = <&tx_swr_active>;
3079 qcom,dout-ports = <0>;
3081 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
3082 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
3083 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
3084 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
3085 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
3086 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
3087 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
3088 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
3089 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
3092 #size-cells = <0>;
3099 reg = <0 0x06d44000 0 0x1000>;
3107 #clock-cells = <0>;
3114 reg = <0 0x06e80000 0 0x20000>;
3122 gpio-ranges = <&lpass_tlmm 0 0 23>;
3231 reg = <0 0x07400000 0 0x19080>;
3240 reg = <0 0x07430000 0 0x3a200>;
3249 reg = <0 0x07e40000 0 0xe080>;
3258 reg = <0 0x08804000 0 0x1000>;
3282 iommus = <&apps_smmu 0x540 0>;
3287 sdhci-caps-mask = <0x3 0>;
3289 qcom,dll-config = <0x0007642c>;
3290 qcom,ddr-config = <0x80040868>;
3323 reg = <0 0x0aaf0000 0 0x10000>;
3334 reg = <0 0x0ac15000 0 0x1000>;
3343 pinctrl-0 = <&cci0_0_default &cci0_1_default>;
3348 #size-cells = <0>;
3350 cci0_i2c0: i2c-bus@0 {
3351 reg = <0>;
3354 #size-cells = <0>;
3361 #size-cells = <0>;
3367 reg = <0 0x0ac16000 0 0x1000>;
3376 pinctrl-0 = <&cci1_0_default &cci1_1_default>;
3381 #size-cells = <0>;
3383 cci1_i2c0: i2c-bus@0 {
3384 reg = <0>;
3387 #size-cells = <0>;
3394 #size-cells = <0>;
3400 reg = <0 0x0ac17000 0 0x1000>;
3409 pinctrl-0 = <&cci2_0_default &cci2_1_default>;
3414 #size-cells = <0>;
3416 cci2_i2c0: i2c-bus@0 {
3417 reg = <0>;
3420 #size-cells = <0>;
3427 #size-cells = <0>;
3433 reg = <0 0x0ade0000 0 0x20000>;
3446 reg = <0 0x0ae00000 0 0x1000>;
3466 iommus = <&apps_smmu 0x1c00 0x2>;
3479 reg = <0 0x0ae01000 0 0x8f000>,
3480 <0 0x0aeb0000 0 0x2008>;
3484 interrupts-extended = <&mdss 0>;
3506 #size-cells = <0>;
3508 port@0 {
3509 reg = <0>;
3560 reg = <0 0x0ae94000 0 0x400>;
3580 assigned-clock-parents = <&mdss_dsi0_phy 0>,
3591 #size-cells = <0>;
3597 #size-cells = <0>;
3599 port@0 {
3600 reg = <0>;
3637 reg = <0 0x0ae95000 0 0x200>,
3638 <0 0x0ae95200 0 0x280>,
3639 <0 0x0ae95500 0 0x400>;
3650 #phy-cells = <0>;
3657 reg = <0 0x0ae96000 0 0x400>;
3677 assigned-clock-parents = <&mdss_dsi1_phy 0>,
3688 #size-cells = <0>;
3694 #size-cells = <0>;
3696 port@0 {
3697 reg = <0>;
3715 reg = <0 0x0ae97000 0 0x200>,
3716 <0 0x0ae97200 0 0x280>,
3717 <0 0x0ae97500 0 0x400>;
3728 #phy-cells = <0>;
3735 reg = <0 0xaf54000 0 0x104>,
3736 <0 0xaf54200 0 0xc0>,
3737 <0 0xaf55000 0 0x770>,
3738 <0 0xaf56000 0 0x9c>,
3739 <0 0xaf57000 0 0x9c>;
3766 #sound-dai-cells = <0>;
3796 #size-cells = <0>;
3798 port@0 {
3799 reg = <0>;
3819 reg = <0 0x0af00000 0 0x20000>;
3825 <&mdss_dsi0_phy 0>,
3827 <&mdss_dsi1_phy 0>,
3831 <0>, /* dp1 */
3832 <0>,
3833 <0>, /* dp2 */
3834 <0>,
3835 <0>, /* dp3 */
3836 <0>;
3851 reg = <0 0x088e3000 0 0x154>;
3858 #phy-cells = <0>;
3865 reg = <0 0x088e8000 0 0x3000>;
3892 #size-cells = <0>;
3894 port@0 {
3895 reg = <0>;
3921 reg = <0 0x0a6f8800 0 0x400>;
3964 reg = <0 0x0a600000 0 0xcd00>;
3968 iommus = <&apps_smmu 0x40 0>;
3975 snps,hird-threshold = /bits/ 8 <0x0>;
3991 #size-cells = <0>;
3993 port@0 {
3994 reg = <0>;
4013 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
4017 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
4027 reg = <0 0x0c228000 0 0x1000>, /* TM */
4028 <0 0x0c222000 0 0x1000>; /* SROT */
4042 reg = <0 0x0c229000 0 0x1000>, /* TM */
4043 <0 0x0c223000 0 0x1000>; /* SROT */
4057 reg = <0 0x0c22a000 0 0x1000>, /* TM */
4058 <0 0x0c224000 0 0x1000>; /* SROT */
4072 reg = <0 0x0c300000 0 0x400>;
4080 #clock-cells = <0>;
4085 reg = <0 0x0c3f0000 0 0x400>;
4090 reg = <0 0x0c400000 0 0x3000>,
4091 <0 0x0c500000 0 0x400000>,
4092 <0 0x0c440000 0 0x80000>,
4093 <0 0x0c4c0000 0 0x20000>,
4094 <0 0x0c42d000 0 0x4000>;
4104 qcom,ee = <0>;
4105 qcom,channel = <0>;
4106 qcom,bus-id = <0>;
4112 #size-cells = <0>;
4117 reg = <0 0x0f100000 0 0x300000>;
4127 gpio-ranges = <&tlmm 0 0 211>;
4131 cci0_0_default: cci0-0-default-state {
4147 cci0_0_sleep: cci0-0-sleep-state {
4195 cci1_0_default: cci1-0-default-state {
4211 cci1_0_sleep: cci1-0-sleep-state {
4259 cci2_0_default: cci2-0-default-state {
4275 cci2_0_sleep: cci2-0-sleep-state {
4861 reg = <0 0x15000000 0 0x100000>;
4969 reg = <0 0x17100000 0 0x10000>, /* GICD */
4970 <0 0x17180000 0 0x200000>; /* GICR * 8 */
4978 redistributor-stride = <0 0x40000>;
4986 reg = <0 0x17140000 0 0x20000>;
4995 reg = <0 0x17420000 0 0x1000>;
4997 ranges = <0 0 0 0x20000000>;
5002 reg = <0x17421000 0x1000>,
5003 <0x17422000 0x1000>;
5008 frame-number = <0>;
5012 reg = <0x17423000 0x1000>;
5022 reg = <0x17425000 0x1000>;
5032 reg = <0x17427000 0x1000>;
5042 reg = <0x17429000 0x1000>;
5052 reg = <0x1742b000 0x1000>;
5062 reg = <0x1742d000 0x1000>;
5074 reg = <0 0x17a00000 0 0x10000>,
5075 <0 0x17a10000 0 0x10000>,
5076 <0 0x17a20000 0 0x10000>,
5077 <0 0x17a30000 0 0x10000>;
5078 reg-names = "drv-0",
5088 qcom,tcs-offset = <0xd00>;
5091 <WAKE_TCS 2>, <CONTROL_TCS 0>;
5183 reg = <0 0x17d91000 0 0x1000>,
5184 <0 0x17d92000 0 0x1000>,
5185 <0 0x17d93000 0 0x1000>,
5186 <0 0x17d94000 0 0x1000>;
5196 interrupt-names = "dcvsh-irq-0",
5210 reg = <0 0x24091000 0 0x1000>;
5222 opp-0 {
5262 reg = <0 0x240b7400 0 0x600>;
5274 opp-0 {
5302 reg = <0 0x24100000 0 0xc5080>;
5311 reg = <0 0x25000000 0 0x200000>,
5312 <0 0x25400000 0 0x200000>,
5313 <0 0x25200000 0 0x200000>,
5314 <0 0x25600000 0 0x200000>,
5315 <0 0x25800000 0 0x200000>,
5316 <0 0x25a00000 0 0x200000>;
5329 reg = <0 0x30000000 0 0x100>;
5332 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
5357 qcom,smem-states = <&smp2p_adsp_out 0>;
5384 #size-cells = <0>;
5390 iommus = <&apps_smmu 0x1003 0x80>,
5391 <&apps_smmu 0x1043 0x20>;
5399 iommus = <&apps_smmu 0x1004 0x80>,
5400 <&apps_smmu 0x1044 0x20>;
5408 iommus = <&apps_smmu 0x1005 0x80>,
5409 <&apps_smmu 0x1045 0x20>;
5417 iommus = <&apps_smmu 0x1006 0x80>,
5418 <&apps_smmu 0x1046 0x20>;
5426 iommus = <&apps_smmu 0x1007 0x40>,
5427 <&apps_smmu 0x1067 0x0>,
5428 <&apps_smmu 0x1087 0x0>;
5439 #size-cells = <0>;
5444 #sound-dai-cells = <0>;
5455 iommus = <&apps_smmu 0x1001 0x80>,
5456 <&apps_smmu 0x1061 0x0>;
5477 reg = <0 0x320c0000 0 0xf080>;
5486 reg = <0 0x32300000 0 0x1400000>;
5489 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
5516 qcom,smem-states = <&smp2p_cdsp_out 0>;
5543 #size-cells = <0>;
5549 iommus = <&apps_smmu 0x1961 0x0>,
5550 <&apps_smmu 0x0c01 0x20>,
5551 <&apps_smmu 0x19c1 0x0>;
5559 iommus = <&apps_smmu 0x1962 0x0>,
5560 <&apps_smmu 0x0c02 0x20>,
5561 <&apps_smmu 0x19c2 0x0>;
5569 iommus = <&apps_smmu 0x1963 0x0>,
5570 <&apps_smmu 0x0c03 0x20>,
5571 <&apps_smmu 0x19c3 0x0>;
5579 iommus = <&apps_smmu 0x1964 0x0>,
5580 <&apps_smmu 0x0c04 0x20>,
5581 <&apps_smmu 0x19c4 0x0>;
5589 iommus = <&apps_smmu 0x1965 0x0>,
5590 <&apps_smmu 0x0c05 0x20>,
5591 <&apps_smmu 0x19c5 0x0>;
5599 iommus = <&apps_smmu 0x1966 0x0>,
5600 <&apps_smmu 0x0c06 0x20>,
5601 <&apps_smmu 0x19c6 0x0>;
5609 iommus = <&apps_smmu 0x1967 0x0>,
5610 <&apps_smmu 0x0c07 0x20>,
5611 <&apps_smmu 0x19c7 0x0>;
5619 iommus = <&apps_smmu 0x1968 0x0>,
5620 <&apps_smmu 0x0c08 0x20>,
5621 <&apps_smmu 0x19c8 0x0>;
5631 iommus = <&apps_smmu 0x196c 0x0>,
5632 <&apps_smmu 0x0c0c 0x20>,
5633 <&apps_smmu 0x19cc 0x0>;
5641 iommus = <&apps_smmu 0x196d 0x0>,
5642 <&apps_smmu 0x0c0d 0x20>,
5643 <&apps_smmu 0x19cd 0x0>;
5651 iommus = <&apps_smmu 0x196e 0x0>,
5652 <&apps_smmu 0x0c0e 0x20>,
5653 <&apps_smmu 0x19ce 0x0>;
5663 thermal-sensors = <&tsens0 0>;
5674 hysteresis = <0>;
5692 hysteresis = <0>;
5710 hysteresis = <0>;
5728 hysteresis = <0>;
5746 hysteresis = <0>;
5993 thermal-sensors = <&tsens1 0>;
6004 hysteresis = <0>;
6144 hysteresis = <0>;
6164 hysteresis = <0>;
6184 hysteresis = <0>;
6204 hysteresis = <0>;
6224 hysteresis = <0>;
6244 hysteresis = <0>;
6264 hysteresis = <0>;
6284 hysteresis = <0>;
6302 hysteresis = <0>;
6320 hysteresis = <0>;
6327 thermal-sensors = <&tsens2 0>;
6338 hysteresis = <0>;
6620 hysteresis = <0>;
6638 hysteresis = <0>;
6656 hysteresis = <0>;
6674 hysteresis = <0>;