Lines Matching +full:0 +full:x0ae95000
42 #clock-cells = <0>;
47 #clock-cells = <0>;
52 #clock-cells = <0>;
61 #clock-cells = <0>;
71 #size-cells = <0>;
73 cpu0: cpu@0 {
76 reg = <0 0>;
78 clocks = <&cpufreq_hw 0>;
88 qcom,freq-domain = <&cpufreq_hw 0>;
118 reg = <0 0x100>;
120 clocks = <&cpufreq_hw 0>;
130 qcom,freq-domain = <&cpufreq_hw 0>;
147 reg = <0 0x200>;
183 reg = <0 0x300>;
219 reg = <0 0x400>;
255 reg = <0 0x500>;
291 reg = <0 0x600>;
327 reg = <0 0x700>;
399 silver_cpu_sleep_0: cpu-sleep-0-0 {
402 arm,psci-suspend-param = <0x40000004>;
409 gold_cpu_sleep_0: cpu-sleep-1-0 {
412 arm,psci-suspend-param = <0x40000004>;
419 gold_plus_cpu_sleep_0: cpu-sleep-2-0 {
422 arm,psci-suspend-param = <0x40000004>;
431 cluster_sleep_0: cluster-sleep-0 {
433 arm,psci-suspend-param = <0x41000044>;
441 arm,psci-suspend-param = <0x4100c344>;
449 ete-0 {
566 #size-cells = <0>;
568 port@0 {
569 reg = <0>;
645 qcom,dload-mode = <&tcsr 0x19000>;
651 clk_virt: interconnect-0 {
722 reg = <0 0xa0000000 0 0>;
1605 #power-domain-cells = <0>;
1611 #power-domain-cells = <0>;
1617 #power-domain-cells = <0>;
1623 #power-domain-cells = <0>;
1629 #power-domain-cells = <0>;
1635 #power-domain-cells = <0>;
1641 #power-domain-cells = <0>;
1647 #power-domain-cells = <0>;
1653 #power-domain-cells = <0>;
1665 reg = <0 0x80000000 0 0xe00000>;
1670 reg = <0 0x80e00000 0 0x400000>;
1676 reg = <0 0x81a00000 0 0x260000>;
1682 reg = <0 0x81c60000 0 0x20000>;
1688 reg = <0 0x81c80000 0 0x75000>;
1696 reg = <0 0x81d00000 0 0x200000>;
1702 reg = <0 0x81f00000 0 0x20000>;
1707 reg = <0 0x824a0000 0 0x100000>;
1712 reg = <0 0x82600000 0 0x100000>;
1717 reg = <0 0x82700000 0 0x100000>;
1722 reg = <0 0x82800000 0 0x2000000>;
1727 reg = <0 0x84800000 0 0x200000>;
1732 reg = <0 0x86b00000 0 0x4900000>;
1737 reg = <0 0x8b400000 0 0x800000>;
1742 reg = <0 0x8bc00000 0 0xf400000>;
1747 reg = <0 0x9b000000 0 0x80000>;
1752 reg = <0 0x9b080000 0 0x10000>;
1757 reg = <0 0x9b090000 0 0xa000>;
1762 reg = <0 0x9b09a000 0 0x2000>;
1767 reg = <0 0x9b0a0000 0 0x1e0000>;
1773 reg = <0 0x9b280000 0 0x60000>;
1779 reg = <0 0x9b2e0000 0 0x20000>;
1784 reg = <0 0x9b300000 0 0x800000>;
1789 reg = <0 0x9bb00000 0 0x800000>;
1794 reg = <0 0x9c300000 0 0x700000>;
1799 reg = <0 0x9ca00000 0 0x1400000>;
1804 reg = <0 0x9de00000 0 0x80000>;
1809 reg = <0 0x9de80000 0 0x80000>;
1814 reg = <0 0x9df00000 0 0x4080000>;
1820 reg = <0 0xd7c00000 0 0x400000>;
1829 reg = <0 0xd8000000 0 0x800000>;
1834 reg = <0 0xe6440000 0 0x2dd000>;
1839 reg = <0 0xf3800000 0 0x4400000>;
1844 reg = <0 0xf7c00000 0 0x4c00000>;
1849 reg = <0 0xff800000 0 0x600000>;
1865 qcom,local-pid = <0>;
1891 qcom,local-pid = <0>;
1917 qcom,local-pid = <0>;
1943 soc: soc@0 {
1948 dma-ranges = <0 0 0 0 0x10 0>;
1949 ranges = <0 0 0 0 0x10 0>;
1953 reg = <0 0x00100000 0 0x1f4200>;
1961 <&ufs_mem_phy 0>,
1973 reg = <0 0x00406000 0 0x1000>;
1975 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH 0>;
1984 reg = <0 0x00800000 0 0x60000>;
1986 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH 0>,
1987 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH 0>,
1988 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH 0>,
1989 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH 0>,
1990 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>,
1991 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH 0>,
1992 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>,
1993 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH 0>,
1994 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH 0>,
1995 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>,
1996 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH 0>,
1997 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH 0>;
2000 dma-channel-mask = <0x3f>;
2003 iommus = <&apps_smmu 0x436 0>;
2012 reg = <0 0x008c0000 0 0x2000>;
2019 iommus = <&apps_smmu 0x423 0>;
2031 reg = <0 0x00880000 0 0x4000>;
2033 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>;
2052 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
2053 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
2057 pinctrl-0 = <&qup_i2c8_data_clk>;
2061 #size-cells = <0>;
2068 reg = <0 0x00880000 0 0x4000>;
2070 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>;
2089 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
2090 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
2094 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
2098 #size-cells = <0>;
2105 reg = <0 0x00884000 0 0x4000>;
2107 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH 0>;
2126 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
2131 pinctrl-0 = <&qup_i2c9_data_clk>;
2135 #size-cells = <0>;
2142 reg = <0 0x00884000 0 0x4000>;
2144 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH 0>;
2163 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
2168 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
2172 #size-cells = <0>;
2179 reg = <0 0x00888000 0 0x4000>;
2181 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH 0>;
2200 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
2205 pinctrl-0 = <&qup_i2c10_data_clk>;
2209 #size-cells = <0>;
2216 reg = <0 0x00888000 0 0x4000>;
2218 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH 0>;
2237 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
2242 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
2246 #size-cells = <0>;
2253 reg = <0 0x0088c000 0 0x4000>;
2255 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>;
2274 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
2279 pinctrl-0 = <&qup_i2c11_data_clk>;
2283 #size-cells = <0>;
2290 reg = <0 0x0088c000 0 0x4000>;
2292 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>;
2311 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
2316 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
2320 #size-cells = <0>;
2327 reg = <0 0x00890000 0 0x4000>;
2329 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>;
2348 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
2353 pinctrl-0 = <&qup_i2c12_data_clk>;
2357 #size-cells = <0>;
2364 reg = <0 0x00890000 0 0x4000>;
2366 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>;
2385 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
2390 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
2394 #size-cells = <0>;
2401 reg = <0 0x00894000 0 0x4000>;
2403 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH 0>;
2422 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
2427 pinctrl-0 = <&qup_i2c13_data_clk>;
2431 #size-cells = <0>;
2438 reg = <0 0x00894000 0 0x4000>;
2440 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH 0>;
2459 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
2464 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
2468 #size-cells = <0>;
2475 reg = <0 0x00898000 0 0x4000>;
2477 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH 0>;
2493 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
2501 reg = <0 0x0089c000 0 0x4000>;
2503 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
2519 pinctrl-0 = <&qup_uart15_default>;
2528 reg = <0 0x009c0000 0 0x2000>;
2541 reg = <0 0x00980000 0 0x4000>;
2543 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH 0>;
2561 pinctrl-0 = <&hub_i2c0_data_clk>;
2565 #size-cells = <0>;
2572 reg = <0 0x00984000 0 0x4000>;
2574 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH 0>;
2592 pinctrl-0 = <&hub_i2c1_data_clk>;
2596 #size-cells = <0>;
2603 reg = <0 0x00988000 0 0x4000>;
2605 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH 0>;
2623 pinctrl-0 = <&hub_i2c2_data_clk>;
2627 #size-cells = <0>;
2634 reg = <0 0x0098c000 0 0x4000>;
2636 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH 0>;
2654 pinctrl-0 = <&hub_i2c3_data_clk>;
2658 #size-cells = <0>;
2665 reg = <0 0x00990000 0 0x4000>;
2667 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH 0>;
2685 pinctrl-0 = <&hub_i2c4_data_clk>;
2689 #size-cells = <0>;
2696 reg = <0 0x00994000 0 0x4000>;
2698 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH 0>;
2716 pinctrl-0 = <&hub_i2c5_data_clk>;
2720 #size-cells = <0>;
2727 reg = <0 0x00998000 0 0x4000>;
2729 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH 0>;
2747 pinctrl-0 = <&hub_i2c6_data_clk>;
2751 #size-cells = <0>;
2758 reg = <0 0x0099c000 0 0x4000>;
2760 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>;
2778 pinctrl-0 = <&hub_i2c7_data_clk>;
2782 #size-cells = <0>;
2789 reg = <0 0x009a0000 0 0x4000>;
2791 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH 0>;
2809 pinctrl-0 = <&hub_i2c8_data_clk>;
2813 #size-cells = <0>;
2820 reg = <0 0x009a4000 0 0x4000>;
2822 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH 0>;
2840 pinctrl-0 = <&hub_i2c9_data_clk>;
2844 #size-cells = <0>;
2852 reg = <0 0x00a00000 0 0x60000>;
2854 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>,
2855 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>,
2856 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>,
2857 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH 0>,
2858 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH 0>,
2859 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH 0>,
2860 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>,
2861 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>,
2862 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>,
2863 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH 0>,
2864 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>,
2865 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>;
2868 dma-channel-mask = <0xc>;
2871 iommus = <&apps_smmu 0xb6 0>;
2879 reg = <0 0x00ac0000 0 0x2000>;
2890 iommus = <&apps_smmu 0xa3 0>;
2902 reg = <0 0x00a80000 0 0x4000>;
2904 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>;
2923 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
2924 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
2928 pinctrl-0 = <&qup_i2c0_data_clk>;
2932 #size-cells = <0>;
2939 reg = <0 0x00a80000 0 0x4000>;
2941 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>;
2960 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
2961 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
2965 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
2969 #size-cells = <0>;
2976 reg = <0 0x00a84000 0 0x4000>;
2978 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>;
2997 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
3002 pinctrl-0 = <&qup_i2c1_data_clk>;
3006 #size-cells = <0>;
3013 reg = <0 0x00a84000 0 0x4000>;
3015 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>;
3034 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
3039 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
3043 #size-cells = <0>;
3050 reg = <0 0x00a88000 0 0x4000>;
3052 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>;
3071 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
3076 pinctrl-0 = <&qup_i2c2_data_clk>;
3080 #size-cells = <0>;
3087 reg = <0 0x00a88000 0 0x4000>;
3089 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>;
3108 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
3113 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
3117 #size-cells = <0>;
3124 reg = <0 0x00a8c000 0 0x4000>;
3126 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>;
3145 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
3150 pinctrl-0 = <&qup_i2c3_data_clk>;
3154 #size-cells = <0>;
3161 reg = <0 0x00a8c000 0 0x4000>;
3163 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>;
3182 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
3187 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
3191 #size-cells = <0>;
3198 reg = <0 0x00a90000 0 0x4000>;
3200 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 0>;
3219 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
3224 pinctrl-0 = <&qup_i2c4_data_clk>;
3228 #size-cells = <0>;
3235 reg = <0 0x00a90000 0 0x4000>;
3237 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 0>;
3256 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
3261 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
3265 #size-cells = <0>;
3272 reg = <0 0x00a94000 0 0x4000>;
3274 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 0>;
3293 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
3298 pinctrl-0 = <&qup_i2c5_data_clk>;
3302 #size-cells = <0>;
3309 reg = <0 0x00a94000 0 0x4000>;
3311 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 0>;
3330 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
3335 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
3339 #size-cells = <0>;
3346 reg = <0 0x00a98000 0 0x4000>;
3348 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>;
3367 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
3372 pinctrl-0 = <&qup_i2c6_data_clk>;
3376 #size-cells = <0>;
3383 reg = <0 0x00a98000 0 0x4000>;
3385 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>;
3404 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
3409 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
3413 #size-cells = <0>;
3420 reg = <0 0x00a9c000 0 0x4000>;
3422 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH 0>;
3441 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
3446 pinctrl-0 = <&qup_i2c7_data_clk>;
3450 #size-cells = <0>;
3457 reg = <0 0x00a9c000 0 0x4000>;
3459 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH 0>;
3478 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
3483 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
3487 #size-cells = <0>;
3495 reg = <0 0x01500000 0 0x14080>;
3504 reg = <0 0x01600000 0 0x6200>;
3513 reg = <0 0x01680000 0 0x1d080>;
3522 reg = <0 0x016c0000 0 0x12200>;
3534 reg = <0 0x016e0000 0 0x16400>;
3546 reg = <0 0x01700000 0 0x1e400>;
3557 reg = <0 0x01780000 0 0x5b800>;
3566 reg = <0 0x010c3000 0 0x1000>;
3572 reg = <0 0x01c00000 0 0x3000>,
3573 <0 0x60000000 0 0xf1d>,
3574 <0 0x60000f20 0 0xa8>,
3575 <0 0x60001000 0 0x1000>,
3576 <0 0x60100000 0 0x100000>;
3579 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>,
3580 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>,
3581 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>,
3582 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>,
3583 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>,
3584 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>,
3585 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>,
3586 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>,
3587 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH 0>;
3629 iommu-map = <0 &apps_smmu 0x1400 0x1>,
3630 <0x100 &apps_smmu 0x1401 0x1>;
3632 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH 0>,
3633 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH 0>,
3634 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH 0>,
3635 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH 0>;
3636 interrupt-map-mask = <0 0 0 0x7>;
3639 msi-map = <0x0 &gic_its 0x1400 0x1>,
3640 <0x100 &gic_its 0x1401 0x1>;
3641 msi-map-mask = <0xff00>;
3643 linux,pci-domain = <0>;
3645 bus-range = <0 0xff>;
3652 ranges = <0x01000000 0 0x00000000 0 0x60200000 0 0x100000>,
3653 <0x02000000 0 0x60300000 0 0x60300000 0 0x3d00000>;
3698 pcieport0: pcie@0 {
3700 reg = <0x0 0x0 0x0 0x0 0x0>;
3701 bus-range = <0x01 0xff>;
3711 reg = <0 0x01c06000 0 0x2000>;
3732 #clock-cells = <0>;
3735 #phy-cells = <0>;
3743 reg = <0 0x01c08000 0 0x3000>,
3744 <0 0x40000000 0 0xf1d>,
3745 <0 0x40000f20 0 0xa8>,
3746 <0 0x40001000 0 0x1000>,
3747 <0 0x40100000 0 0x100000>;
3754 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>,
3755 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 0>,
3756 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>,
3757 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 0>,
3758 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>,
3759 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 0>,
3760 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>,
3761 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH 0>,
3762 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>;
3809 iommu-map = <0 &apps_smmu 0x1480 0x1>,
3810 <0x100 &apps_smmu 0x1481 0x1>;
3812 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH 0>,
3813 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH 0>,
3814 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH 0>,
3815 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH 0>;
3816 interrupt-map-mask = <0 0 0 0x7>;
3819 msi-map = <0x0 &gic_its 0x1480 0x1>,
3820 <0x100 &gic_its 0x1481 0x1>;
3821 msi-map-mask = <0xff00>;
3825 bus-range = <0 0xff>;
3834 ranges = <0x01000000 0 0x00000000 0 0x40200000 0 0x100000>,
3835 <0x02000000 0 0x40300000 0 0x40300000 0 0x1fd00000>;
3885 pcie@0 {
3887 reg = <0x0 0x0 0x0 0x0 0x0>;
3888 bus-range = <0x01 0xff>;
3898 reg = <0 0x01c0e000 0 0x2000>;
3924 #phy-cells = <0>;
3931 reg = <0 0x01dc4000 0 0x28000>;
3933 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>;
3937 iommus = <&apps_smmu 0x480 0>,
3938 <&apps_smmu 0x481 0>;
3940 qcom,ee = <0>;
3948 reg = <0 0x01dfa000 0 0x6000>;
3957 iommus = <&apps_smmu 0x480 0>,
3958 <&apps_smmu 0x481 0>;
3963 reg = <0 0x01d80000 0 0x2000>;
3972 resets = <&ufs_mem_hc 0>;
3978 #phy-cells = <0>;
3985 reg = <0 0x01d84000 0 0x3000>;
3987 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
4021 iommus = <&apps_smmu 0x60 0>;
4038 /bits/ 64 <0>,
4039 /bits/ 64 <0>,
4041 /bits/ 64 <0>,
4042 /bits/ 64 <0>,
4043 /bits/ 64 <0>,
4044 /bits/ 64 <0>;
4050 /bits/ 64 <0>,
4051 /bits/ 64 <0>,
4053 /bits/ 64 <0>,
4054 /bits/ 64 <0>,
4055 /bits/ 64 <0>,
4056 /bits/ 64 <0>;
4062 /bits/ 64 <0>,
4063 /bits/ 64 <0>,
4065 /bits/ 64 <0>,
4066 /bits/ 64 <0>,
4067 /bits/ 64 <0>,
4068 /bits/ 64 <0>;
4077 reg = <0 0x01d88000 0 0x18000>;
4084 reg = <0 0x01f40000 0 0x20000>;
4091 reg = <0 0x01fc0000 0 0xa0000>;
4101 reg = <0x0 0x03d00000 0x0 0x40000>,
4102 <0x0 0x03d9e000 0x0 0x2000>,
4103 <0x0 0x03d61000 0x0 0x800>;
4108 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>;
4110 iommus = <&adreno_smmu 0 0x0>,
4111 <&adreno_smmu 1 0x0>;
4202 reg = <0x0 0x03d6a000 0x0 0x35000>,
4203 <0x0 0x03d50000 0x0 0x10000>,
4204 <0x0 0x0b280000 0x0 0x10000>;
4207 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>,
4208 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>;
4231 iommus = <&adreno_smmu 5 0x0>;
4254 reg = <0 0x03d90000 0 0xa000>;
4268 reg = <0x0 0x03da0000 0x0 0x40000>;
4271 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0>,
4272 <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH 0>,
4273 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH 0>,
4274 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH 0>,
4275 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH 0>,
4276 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH 0>,
4277 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH 0>,
4278 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH 0>,
4279 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH 0>,
4280 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH 0>,
4281 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH 0>,
4282 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH 0>,
4283 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 0>,
4284 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH 0>,
4285 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH 0>,
4286 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH 0>,
4287 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH 0>,
4288 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH 0>,
4289 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH 0>,
4290 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0>,
4291 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>,
4292 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH 0>,
4293 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH 0>,
4294 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH 0>,
4295 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>,
4296 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH 0>;
4312 iommus = <&apps_smmu 0x4a0 0x0>,
4313 <&apps_smmu 0x4a2 0x0>;
4314 reg = <0 0x3f40000 0 0x10000>,
4315 <0 0x3f50000 0 0x5000>,
4316 <0 0x3e04000 0 0xfc000>;
4321 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING 0>,
4322 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH 0>,
4323 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
4342 qcom,smem-states = <&ipa_smp2p_out 0>,
4352 reg = <0x0 0x04080000 0x0 0x10000>;
4354 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING 0>,
4355 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
4384 qcom,smem-states = <&smp2p_modem_out 0>;
4405 reg = <0x0 0x06800000 0x0 0x10000>;
4408 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
4433 qcom,smem-states = <&smp2p_adsp_out 0>;
4460 #size-cells = <0>;
4466 iommus = <&apps_smmu 0x1003 0x80>,
4467 <&apps_smmu 0x1043 0x20>;
4475 iommus = <&apps_smmu 0x1004 0x80>,
4476 <&apps_smmu 0x1044 0x20>;
4484 iommus = <&apps_smmu 0x1005 0x80>,
4485 <&apps_smmu 0x1045 0x20>;
4493 iommus = <&apps_smmu 0x1006 0x80>,
4494 <&apps_smmu 0x1046 0x20>;
4502 iommus = <&apps_smmu 0x1007 0x40>,
4503 <&apps_smmu 0x1067 0x0>,
4504 <&apps_smmu 0x1087 0x0>;
4515 #size-cells = <0>;
4520 #sound-dai-cells = <0>;
4531 iommus = <&apps_smmu 0x1001 0x80>,
4532 <&apps_smmu 0x1061 0x0>;
4553 reg = <0 0x06aa0000 0 0x1000>;
4563 #clock-cells = <0>;
4570 reg = <0 0x06ab0000 0 0x10000>;
4571 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>;
4576 pinctrl-0 = <&wsa2_swr_active>;
4582 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
4583 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
4584 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4585 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4586 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4587 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
4588 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
4589 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4590 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4593 #size-cells = <0>;
4600 reg = <0 0x06ac0000 0 0x1000>;
4610 #clock-cells = <0>;
4617 reg = <0 0x06ad0000 0 0x10000>;
4618 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>;
4623 pinctrl-0 = <&rx_swr_active>;
4626 qcom,din-ports = <0>;
4629 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x03 0xff 0xff 0x31 0xff 0xff 0xff>;
4630 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x09 0x01 0xff 0xff 0x00 0xff 0xff 0xff>;
4631 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>;
4632 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0xff 0xff 0x00 0xff 0xff 0xff>;
4633 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0xff 0xff 0x0f 0xff 0xff 0xff>;
4634 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0x18 0xff 0xff 0xff>;
4635 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff 0xff 0x01 0xff 0xff 0xff>;
4636 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0x01 0x03 0xff 0xff 0x00 0xff 0xff 0xff>;
4637 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0xff 0xff 0xff>;
4640 #size-cells = <0>;
4647 reg = <0 0x06ae0000 0 0x1000>;
4657 #clock-cells = <0>;
4664 reg = <0 0x06b00000 0 0x1000>;
4674 #clock-cells = <0>;
4681 reg = <0 0x06b10000 0 0x10000>;
4682 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
4687 pinctrl-0 = <&wsa_swr_active>;
4693 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
4694 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
4695 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4696 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4697 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4698 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
4699 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
4700 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4701 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4704 #size-cells = <0>;
4711 reg = <0 0x06d30000 0 0x10000>;
4712 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>,
4713 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH 0>;
4719 pinctrl-0 = <&tx_swr_active>;
4723 qcom,dout-ports = <0>;
4725 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
4726 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
4727 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
4728 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
4729 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
4730 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
4731 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
4732 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
4733 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
4736 #size-cells = <0>;
4743 reg = <0 0x06d44000 0 0x1000>;
4751 #clock-cells = <0>;
4758 reg = <0 0x06e80000 0 0x20000>;
4766 gpio-ranges = <&lpass_tlmm 0 0 23>;
4875 reg = <0 0x07400000 0 0x19080>;
4884 reg = <0 0x07430000 0 0x3a200>;
4893 reg = <0 0x07e40000 0 0xe080>;
4902 reg = <0 0x08804000 0 0x1000>;
4904 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>,
4905 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH 0>;
4926 iommus = <&apps_smmu 0x540 0>;
4931 sdhci-caps-mask = <0x3 0>;
4933 qcom,dll-config = <0x0007642c>;
4934 qcom,ddr-config = <0x80040868>;
4967 reg = <0 0x0aa00000 0 0xf0000>;
4969 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>;
5005 iommus = <&apps_smmu 0x1940 0>,
5006 <&apps_smmu 0x1947 0>;
5060 reg = <0 0x0aaf0000 0 0x10000>;
5071 reg = <0 0x0ac15000 0 0x1000>;
5072 interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING 0>;
5080 pinctrl-0 = <&cci0_0_default &cci0_1_default>;
5085 #size-cells = <0>;
5087 cci0_i2c0: i2c-bus@0 {
5088 reg = <0>;
5091 #size-cells = <0>;
5098 #size-cells = <0>;
5104 reg = <0 0x0ac16000 0 0x1000>;
5105 interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING 0>;
5113 pinctrl-0 = <&cci1_0_default &cci1_1_default>;
5118 #size-cells = <0>;
5120 cci1_i2c0: i2c-bus@0 {
5121 reg = <0>;
5124 #size-cells = <0>;
5131 #size-cells = <0>;
5137 reg = <0 0x0ac17000 0 0x1000>;
5138 interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING 0>;
5146 pinctrl-0 = <&cci2_0_default &cci2_1_default>;
5151 #size-cells = <0>;
5153 cci2_i2c0: i2c-bus@0 {
5154 reg = <0>;
5157 #size-cells = <0>;
5164 #size-cells = <0>;
5170 reg = <0 0x0ade0000 0 0x20000>;
5183 reg = <0 0x0ae00000 0 0x1000>;
5186 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH 0>;
5203 iommus = <&apps_smmu 0x1c00 0x2>;
5216 reg = <0 0x0ae01000 0 0x8f000>,
5217 <0 0x0aeb0000 0 0x3000>;
5221 interrupts-extended = <&mdss 0>;
5243 #size-cells = <0>;
5245 port@0 {
5246 reg = <0>;
5297 reg = <0 0x0ae94000 0 0x400>;
5328 #size-cells = <0>;
5334 #size-cells = <0>;
5336 port@0 {
5337 reg = <0>;
5374 reg = <0 0x0ae95000 0 0x200>,
5375 <0 0x0ae95200 0 0x280>,
5376 <0 0x0ae95500 0 0x400>;
5387 #phy-cells = <0>;
5394 reg = <0 0x0ae96000 0 0x400>;
5425 #size-cells = <0>;
5431 #size-cells = <0>;
5433 port@0 {
5434 reg = <0>;
5452 reg = <0 0x0ae97000 0 0x200>,
5453 <0 0x0ae97200 0 0x280>,
5454 <0 0x0ae97500 0 0x400>;
5465 #phy-cells = <0>;
5472 reg = <0 0xaf54000 0 0x104>,
5473 <0 0xaf54200 0 0xc0>,
5474 <0 0xaf55000 0 0x770>,
5475 <0 0xaf56000 0 0x9c>,
5476 <0 0xaf57000 0 0x9c>;
5503 #sound-dai-cells = <0>;
5533 #size-cells = <0>;
5535 port@0 {
5536 reg = <0>;
5556 reg = <0 0x0af00000 0 0x20000>;
5568 <0>, /* dp1 */
5569 <0>,
5570 <0>, /* dp2 */
5571 <0>,
5572 <0>, /* dp3 */
5573 <0>;
5586 reg = <0 0x088e3000 0 0x154>;
5593 #phy-cells = <0>;
5600 reg = <0 0x088e8000 0 0x3000>;
5627 #size-cells = <0>;
5629 port@0 {
5630 reg = <0>;
5656 reg = <0 0x0a6f8800 0 0x400>;
5658 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>,
5659 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>,
5706 reg = <0 0x0a600000 0 0xcd00>;
5708 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>;
5710 iommus = <&apps_smmu 0x40 0>;
5717 snps,hird-threshold = /bits/ 8 <0x0>;
5733 #size-cells = <0>;
5735 port@0 {
5736 reg = <0>;
5755 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
5759 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
5769 reg = <0 0x0c228000 0 0x1000>, /* TM */
5770 <0 0x0c222000 0 0x1000>; /* SROT */
5772 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>,
5773 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
5784 reg = <0 0x0c229000 0 0x1000>, /* TM */
5785 <0 0x0c223000 0 0x1000>; /* SROT */
5787 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>,
5788 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
5799 reg = <0 0x0c22a000 0 0x1000>, /* TM */
5800 <0 0x0c224000 0 0x1000>; /* SROT */
5802 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH 0>,
5803 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
5814 reg = <0 0x0c300000 0 0x400>;
5822 #clock-cells = <0>;
5827 reg = <0 0x0c3f0000 0 0x400>;
5833 reg = <0 0x0c400000 0 0x3000>,
5834 <0 0x0c500000 0 0x400000>,
5835 <0 0x0c440000 0 0x80000>,
5836 <0 0x0c4c0000 0 0x20000>,
5837 <0 0x0c42d000 0 0x4000>;
5847 qcom,ee = <0>;
5848 qcom,channel = <0>;
5849 qcom,bus-id = <0>;
5855 #size-cells = <0>;
5860 reg = <0 0x0f100000 0 0x300000>;
5862 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 0>;
5870 gpio-ranges = <&tlmm 0 0 211>;
5874 cci0_0_default: cci0-0-default-state {
5890 cci0_0_sleep: cci0-0-sleep-state {
5938 cci1_0_default: cci1-0-default-state {
5954 cci1_0_sleep: cci1-0-sleep-state {
6002 cci2_0_default: cci2-0-default-state {
6018 cci2_0_sleep: cci2-0-sleep-state {
6605 reg = <0x0 0x10042000 0x0 0x1000>;
6612 #size-cells = <0>;
6635 reg = <0x0 0x10045000 0x0 0x1000>;
6642 #size-cells = <0>;
6665 reg = <0x0 0x10b04000 0x0 0x1000>;
6672 #size-cells = <0>;
6695 reg = <0x0 0x10b05000 0x0 0x1000>;
6712 reg = <0x0 0x13810000 0x0 0x1000>;
6736 reg = <0 0x15000000 0 0x100000>;
6738 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>,
6739 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>,
6740 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>,
6741 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>,
6742 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>,
6743 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>,
6744 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>,
6745 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
6746 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
6747 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>,
6748 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>,
6749 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>,
6750 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
6751 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
6752 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>,
6753 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>,
6754 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>,
6755 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
6756 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
6757 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>,
6758 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>,
6759 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>,
6760 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>,
6761 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>,
6762 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>,
6763 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>,
6764 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>,
6765 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>,
6766 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>,
6767 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>,
6768 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>,
6769 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>,
6770 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>,
6771 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>,
6772 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>,
6773 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>,
6774 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 0>,
6775 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>,
6776 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>,
6777 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>,
6778 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>,
6779 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>,
6780 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>,
6781 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>,
6782 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>,
6783 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>,
6784 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>,
6785 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>,
6786 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>,
6787 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>,
6788 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>,
6789 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>,
6790 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>,
6791 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>,
6792 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>,
6793 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>,
6794 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>,
6795 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>,
6796 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>,
6797 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>,
6798 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>,
6799 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>,
6800 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>,
6801 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>,
6802 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>,
6803 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH 0>,
6804 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>,
6805 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>,
6806 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>,
6807 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>,
6808 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH 0>,
6809 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>,
6810 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH 0>,
6811 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH 0>,
6812 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH 0>,
6813 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH 0>,
6814 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH 0>,
6815 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH 0>,
6816 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>,
6817 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>,
6818 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>,
6819 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 0>,
6820 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 0>,
6821 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH 0>,
6822 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 0>,
6823 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH 0>,
6824 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 0>,
6825 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 0>,
6826 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>,
6827 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH 0>,
6828 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH 0>,
6829 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH 0>,
6830 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH 0>,
6831 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH 0>,
6832 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH 0>,
6833 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH 0>,
6834 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH 0>;
6844 reg = <0 0x17100000 0 0x10000>, /* GICD */
6845 <0 0x17180000 0 0x200000>; /* GICR * 8 */
6847 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW 0>;
6853 redistributor-stride = <0 0x40000>;
6860 ppi_cluster0: interrupt-partition-0 {
6875 reg = <0 0x17140000 0 0x20000>;
6884 reg = <0 0x17420000 0 0x1000>;
6886 ranges = <0 0 0 0x20000000>;
6891 reg = <0x17421000 0x1000>,
6892 <0x17422000 0x1000>;
6894 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>,
6895 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
6897 frame-number = <0>;
6901 reg = <0x17423000 0x1000>;
6903 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
6911 reg = <0x17425000 0x1000>;
6913 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
6921 reg = <0x17427000 0x1000>;
6923 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
6931 reg = <0x17429000 0x1000>;
6933 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
6941 reg = <0x1742b000 0x1000>;
6943 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>;
6951 reg = <0x1742d000 0x1000>;
6953 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
6963 reg = <0 0x17a00000 0 0x10000>,
6964 <0 0x17a10000 0 0x10000>,
6965 <0 0x17a20000 0 0x10000>;
6966 reg-names = "drv-0",
6970 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>,
6971 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>,
6972 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>;
6976 qcom,tcs-offset = <0xd00>;
6979 <WAKE_TCS 2>, <CONTROL_TCS 0>;
7071 reg = <0 0x17d90000 0 0x1000>;
7081 reg = <0 0x17d91000 0 0x1000>,
7082 <0 0x17d92000 0 0x1000>,
7083 <0 0x17d93000 0 0x1000>,
7084 <0 0x17d94000 0 0x1000>;
7090 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>,
7091 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>,
7092 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
7093 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH 0>;
7094 interrupt-names = "dcvsh-irq-0",
7108 reg = <0 0x24091000 0 0x1000>;
7110 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
7120 opp-0 {
7160 reg = <0 0x240b7400 0 0x600>;
7162 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH 0>;
7172 opp-0 {
7200 reg = <0 0x24100000 0 0xc5080>;
7209 reg = <0 0x25000000 0 0x200000>,
7210 <0 0x25400000 0 0x200000>,
7211 <0 0x25200000 0 0x200000>,
7212 <0 0x25600000 0 0x200000>,
7213 <0 0x25800000 0 0x200000>,
7214 <0 0x25a00000 0 0x200000>;
7222 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH 0>;
7227 reg = <0 0x320c0000 0 0xf080>;
7236 reg = <0x0 0x32300000 0x0 0x10000>;
7238 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>,
7239 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
7266 qcom,smem-states = <&smp2p_cdsp_out 0>;
7293 #size-cells = <0>;
7299 iommus = <&apps_smmu 0x1961 0x0>,
7300 <&apps_smmu 0x0c01 0x20>,
7301 <&apps_smmu 0x19c1 0x0>;
7309 iommus = <&apps_smmu 0x1962 0x0>,
7310 <&apps_smmu 0x0c02 0x20>,
7311 <&apps_smmu 0x19c2 0x0>;
7319 iommus = <&apps_smmu 0x1963 0x0>,
7320 <&apps_smmu 0x0c03 0x20>,
7321 <&apps_smmu 0x19c3 0x0>;
7329 iommus = <&apps_smmu 0x1964 0x0>,
7330 <&apps_smmu 0x0c04 0x20>,
7331 <&apps_smmu 0x19c4 0x0>;
7339 iommus = <&apps_smmu 0x1965 0x0>,
7340 <&apps_smmu 0x0c05 0x20>,
7341 <&apps_smmu 0x19c5 0x0>;
7349 iommus = <&apps_smmu 0x1966 0x0>,
7350 <&apps_smmu 0x0c06 0x20>,
7351 <&apps_smmu 0x19c6 0x0>;
7359 iommus = <&apps_smmu 0x1967 0x0>,
7360 <&apps_smmu 0x0c07 0x20>,
7361 <&apps_smmu 0x19c7 0x0>;
7369 iommus = <&apps_smmu 0x1968 0x0>,
7370 <&apps_smmu 0x0c08 0x20>,
7371 <&apps_smmu 0x19c8 0x0>;
7381 iommus = <&apps_smmu 0x196c 0x0>,
7382 <&apps_smmu 0x0c0c 0x20>,
7383 <&apps_smmu 0x19cc 0x0>;
7391 iommus = <&apps_smmu 0x196d 0x0>,
7392 <&apps_smmu 0x0c0d 0x20>,
7393 <&apps_smmu 0x19cd 0x0>;
7401 iommus = <&apps_smmu 0x196e 0x0>,
7402 <&apps_smmu 0x0c0e 0x20>,
7403 <&apps_smmu 0x19ce 0x0>;
7413 thermal-sensors = <&tsens0 0>;
7424 hysteresis = <0>;
7442 hysteresis = <0>;
7460 hysteresis = <0>;
7478 hysteresis = <0>;
7496 hysteresis = <0>;
7623 thermal-sensors = <&tsens1 0>;
7634 hysteresis = <0>;
7712 hysteresis = <0>;
7730 hysteresis = <0>;
7748 hysteresis = <0>;
7766 hysteresis = <0>;
7784 hysteresis = <0>;
7802 hysteresis = <0>;
7820 hysteresis = <0>;
7838 hysteresis = <0>;
7856 hysteresis = <0>;
7874 hysteresis = <0>;
7881 thermal-sensors = <&tsens2 0>;
7892 hysteresis = <0>;
7925 hysteresis = <0>;
7958 hysteresis = <0>;
7991 hysteresis = <0>;
8024 hysteresis = <0>;
8057 hysteresis = <0>;
8090 hysteresis = <0>;
8123 hysteresis = <0>;
8156 hysteresis = <0>;
8174 hysteresis = <0>;
8192 hysteresis = <0>;
8210 hysteresis = <0>;
8228 hysteresis = <0>;
8238 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
8239 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
8240 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
8241 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;