Lines Matching +full:ufs +full:- +full:ddr
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
7 #include <dt-bindings/clock/qcom,rpmh.h>
8 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
9 #include <dt-bindings/clock/qcom,sm8550-camcc.h>
10 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
11 #include <dt-bindings/clock/qcom,sm8550-gpucc.h>
12 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
13 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
14 #include <dt-bindings/dma/qcom-gpi.h>
15 #include <dt-bindings/firmware/qcom,scm.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interconnect/qcom,icc.h>
19 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
20 #include <dt-bindings/mailbox/qcom-ipcc.h>
21 #include <dt-bindings/power/qcom-rpmpd.h>
22 #include <dt-bindings/power/qcom,rpmhpd.h>
23 #include <dt-bindings/soc/qcom,gpr.h>
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
26 #include <dt-bindings/phy/phy-qcom-qmp.h>
27 #include <dt-bindings/thermal/thermal.h>
30 interrupt-parent = <&intc>;
32 #address-cells = <2>;
33 #size-cells = <2>;
38 xo_board: xo-board {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
43 sleep_clk: sleep-clk {
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
48 bi_tcxo_div2: bi-tcxo-div2-clk {
49 #clock-cells = <0>;
50 compatible = "fixed-factor-clock";
52 clock-mult = <1>;
53 clock-div = <2>;
56 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
57 #clock-cells = <0>;
58 compatible = "fixed-factor-clock";
60 clock-mult = <1>;
61 clock-div = <2>;
66 #address-cells = <2>;
67 #size-cells = <0>;
71 compatible = "arm,cortex-a510";
74 enable-method = "psci";
75 next-level-cache = <&l2_0>;
76 power-domains = <&cpu_pd0>;
77 power-domain-names = "psci";
78 qcom,freq-domain = <&cpufreq_hw 0>;
79 capacity-dmips-mhz = <1024>;
80 dynamic-power-coefficient = <100>;
81 #cooling-cells = <2>;
82 l2_0: l2-cache {
84 cache-level = <2>;
85 cache-unified;
86 next-level-cache = <&l3_0>;
87 l3_0: l3-cache {
89 cache-level = <3>;
90 cache-unified;
97 compatible = "arm,cortex-a510";
100 enable-method = "psci";
101 next-level-cache = <&l2_100>;
102 power-domains = <&cpu_pd1>;
103 power-domain-names = "psci";
104 qcom,freq-domain = <&cpufreq_hw 0>;
105 capacity-dmips-mhz = <1024>;
106 dynamic-power-coefficient = <100>;
107 #cooling-cells = <2>;
108 l2_100: l2-cache {
110 cache-level = <2>;
111 cache-unified;
112 next-level-cache = <&l3_0>;
118 compatible = "arm,cortex-a510";
121 enable-method = "psci";
122 next-level-cache = <&l2_200>;
123 power-domains = <&cpu_pd2>;
124 power-domain-names = "psci";
125 qcom,freq-domain = <&cpufreq_hw 0>;
126 capacity-dmips-mhz = <1024>;
127 dynamic-power-coefficient = <100>;
128 #cooling-cells = <2>;
129 l2_200: l2-cache {
131 cache-level = <2>;
132 cache-unified;
133 next-level-cache = <&l3_0>;
139 compatible = "arm,cortex-a715";
142 enable-method = "psci";
143 next-level-cache = <&l2_300>;
144 power-domains = <&cpu_pd3>;
145 power-domain-names = "psci";
146 qcom,freq-domain = <&cpufreq_hw 1>;
147 capacity-dmips-mhz = <1792>;
148 dynamic-power-coefficient = <270>;
149 #cooling-cells = <2>;
150 l2_300: l2-cache {
152 cache-level = <2>;
153 cache-unified;
154 next-level-cache = <&l3_0>;
160 compatible = "arm,cortex-a715";
163 enable-method = "psci";
164 next-level-cache = <&l2_400>;
165 power-domains = <&cpu_pd4>;
166 power-domain-names = "psci";
167 qcom,freq-domain = <&cpufreq_hw 1>;
168 capacity-dmips-mhz = <1792>;
169 dynamic-power-coefficient = <270>;
170 #cooling-cells = <2>;
171 l2_400: l2-cache {
173 cache-level = <2>;
174 cache-unified;
175 next-level-cache = <&l3_0>;
181 compatible = "arm,cortex-a710";
184 enable-method = "psci";
185 next-level-cache = <&l2_500>;
186 power-domains = <&cpu_pd5>;
187 power-domain-names = "psci";
188 qcom,freq-domain = <&cpufreq_hw 1>;
189 capacity-dmips-mhz = <1792>;
190 dynamic-power-coefficient = <270>;
191 #cooling-cells = <2>;
192 l2_500: l2-cache {
194 cache-level = <2>;
195 cache-unified;
196 next-level-cache = <&l3_0>;
202 compatible = "arm,cortex-a710";
205 enable-method = "psci";
206 next-level-cache = <&l2_600>;
207 power-domains = <&cpu_pd6>;
208 power-domain-names = "psci";
209 qcom,freq-domain = <&cpufreq_hw 1>;
210 capacity-dmips-mhz = <1792>;
211 dynamic-power-coefficient = <270>;
212 #cooling-cells = <2>;
213 l2_600: l2-cache {
215 cache-level = <2>;
216 cache-unified;
217 next-level-cache = <&l3_0>;
223 compatible = "arm,cortex-x3";
226 enable-method = "psci";
227 next-level-cache = <&l2_700>;
228 power-domains = <&cpu_pd7>;
229 power-domain-names = "psci";
230 qcom,freq-domain = <&cpufreq_hw 2>;
231 capacity-dmips-mhz = <1894>;
232 dynamic-power-coefficient = <588>;
233 #cooling-cells = <2>;
234 l2_700: l2-cache {
236 cache-level = <2>;
237 cache-unified;
238 next-level-cache = <&l3_0>;
242 cpu-map {
278 idle-states {
279 entry-method = "psci";
281 little_cpu_sleep_0: cpu-sleep-0-0 {
282 compatible = "arm,idle-state";
283 idle-state-name = "silver-rail-power-collapse";
284 arm,psci-suspend-param = <0x40000004>;
285 entry-latency-us = <550>;
286 exit-latency-us = <750>;
287 min-residency-us = <6700>;
288 local-timer-stop;
291 big_cpu_sleep_0: cpu-sleep-1-0 {
292 compatible = "arm,idle-state";
293 idle-state-name = "gold-rail-power-collapse";
294 arm,psci-suspend-param = <0x40000004>;
295 entry-latency-us = <600>;
296 exit-latency-us = <1300>;
297 min-residency-us = <8136>;
298 local-timer-stop;
301 prime_cpu_sleep_0: cpu-sleep-2-0 {
302 compatible = "arm,idle-state";
303 idle-state-name = "goldplus-rail-power-collapse";
304 arm,psci-suspend-param = <0x40000004>;
305 entry-latency-us = <500>;
306 exit-latency-us = <1350>;
307 min-residency-us = <7480>;
308 local-timer-stop;
312 domain-idle-states {
313 cluster_sleep_0: cluster-sleep-0 {
314 compatible = "domain-idle-state";
315 arm,psci-suspend-param = <0x41000044>;
316 entry-latency-us = <750>;
317 exit-latency-us = <2350>;
318 min-residency-us = <9144>;
321 cluster_sleep_1: cluster-sleep-1 {
322 compatible = "domain-idle-state";
323 arm,psci-suspend-param = <0x4100c344>;
324 entry-latency-us = <2800>;
325 exit-latency-us = <4400>;
326 min-residency-us = <10150>;
333 compatible = "qcom,scm-sm8550", "qcom,scm";
334 qcom,dload-mode = <&tcsr 0x19000>;
340 clk_virt: interconnect-0 {
341 compatible = "qcom,sm8550-clk-virt";
342 #interconnect-cells = <2>;
343 qcom,bcm-voters = <&apps_bcm_voter>;
346 mc_virt: interconnect-1 {
347 compatible = "qcom,sm8550-mc-virt";
348 #interconnect-cells = <2>;
349 qcom,bcm-voters = <&apps_bcm_voter>;
352 qup_opp_table_100mhz: opp-table-qup100mhz {
353 compatible = "operating-points-v2";
355 opp-75000000 {
356 opp-hz = /bits/ 64 <75000000>;
357 required-opps = <&rpmhpd_opp_low_svs>;
360 opp-100000000 {
361 opp-hz = /bits/ 64 <100000000>;
362 required-opps = <&rpmhpd_opp_svs>;
366 qup_opp_table_120mhz: opp-table-qup120mhz {
367 compatible = "operating-points-v2";
369 opp-75000000 {
370 opp-hz = /bits/ 64 <75000000>;
371 required-opps = <&rpmhpd_opp_low_svs>;
374 opp-120000000 {
375 opp-hz = /bits/ 64 <120000000>;
376 required-opps = <&rpmhpd_opp_svs>;
380 qup_opp_table_125mhz: opp-table-qup125mhz {
381 compatible = "operating-points-v2";
383 opp-75000000 {
384 opp-hz = /bits/ 64 <75000000>;
385 required-opps = <&rpmhpd_opp_low_svs>;
388 opp-125000000 {
389 opp-hz = /bits/ 64 <125000000>;
390 required-opps = <&rpmhpd_opp_svs>;
400 pmu-a510 {
401 compatible = "arm,cortex-a510-pmu";
405 pmu-a710 {
406 compatible = "arm,cortex-a710-pmu";
410 pmu-a715 {
411 compatible = "arm,cortex-a715-pmu";
415 pmu-x3 {
416 compatible = "arm,cortex-x3-pmu";
421 compatible = "arm,psci-1.0";
424 cpu_pd0: power-domain-cpu0 {
425 #power-domain-cells = <0>;
426 power-domains = <&cluster_pd>;
427 domain-idle-states = <&little_cpu_sleep_0>;
430 cpu_pd1: power-domain-cpu1 {
431 #power-domain-cells = <0>;
432 power-domains = <&cluster_pd>;
433 domain-idle-states = <&little_cpu_sleep_0>;
436 cpu_pd2: power-domain-cpu2 {
437 #power-domain-cells = <0>;
438 power-domains = <&cluster_pd>;
439 domain-idle-states = <&little_cpu_sleep_0>;
442 cpu_pd3: power-domain-cpu3 {
443 #power-domain-cells = <0>;
444 power-domains = <&cluster_pd>;
445 domain-idle-states = <&big_cpu_sleep_0>;
448 cpu_pd4: power-domain-cpu4 {
449 #power-domain-cells = <0>;
450 power-domains = <&cluster_pd>;
451 domain-idle-states = <&big_cpu_sleep_0>;
454 cpu_pd5: power-domain-cpu5 {
455 #power-domain-cells = <0>;
456 power-domains = <&cluster_pd>;
457 domain-idle-states = <&big_cpu_sleep_0>;
460 cpu_pd6: power-domain-cpu6 {
461 #power-domain-cells = <0>;
462 power-domains = <&cluster_pd>;
463 domain-idle-states = <&big_cpu_sleep_0>;
466 cpu_pd7: power-domain-cpu7 {
467 #power-domain-cells = <0>;
468 power-domains = <&cluster_pd>;
469 domain-idle-states = <&prime_cpu_sleep_0>;
472 cluster_pd: power-domain-cluster {
473 #power-domain-cells = <0>;
474 domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>;
478 reserved_memory: reserved-memory {
479 #address-cells = <2>;
480 #size-cells = <2>;
483 hyp_mem: hyp-region@80000000 {
485 no-map;
488 cpusys_vm_mem: cpusys-vm-region@80a00000 {
490 no-map;
493 hyp_tags_mem: hyp-tags-region@80e00000 {
495 no-map;
498 xbl_sc_mem: xbl-sc-region@d8100000 {
500 no-map;
503 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 {
505 no-map;
509 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 {
511 no-map;
514 aop_cmd_db_mem: aop-cmd-db-region@81c60000 {
515 compatible = "qcom,cmd-db";
517 no-map;
521 aop_config_merged_mem: aop-config-merged-region@81c80000 {
523 no-map;
531 no-map;
534 adsp_mhi_mem: adsp-mhi-region@81f00000 {
536 no-map;
539 global_sync_mem: global-sync-region@82600000 {
541 no-map;
544 tz_stat_mem: tz-stat-region@82700000 {
546 no-map;
549 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 {
551 no-map;
554 mpss_mem: mpss-region@8a800000 {
556 no-map;
559 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 {
561 no-map;
564 ipa_fw_mem: ipa-fw-region@9b080000 {
566 no-map;
569 ipa_gsi_mem: ipa-gsi-region@9b090000 {
571 no-map;
574 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 {
576 no-map;
579 spss_region_mem: spss-region@9b100000 {
581 no-map;
585 spu_tz_shared_mem: spu-tz-shared-region@9b280000 {
587 no-map;
591 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 {
593 no-map;
596 camera_mem: camera-region@9b300000 {
598 no-map;
601 video_mem: video-region@9bb00000 {
603 no-map;
606 cvp_mem: cvp-region@9c200000 {
608 no-map;
611 cdsp_mem: cdsp-region@9c900000 {
613 no-map;
616 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 {
618 no-map;
621 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 {
623 no-map;
626 adspslpi_mem: adspslpi-region@9ea00000 {
628 no-map;
635 rmtfs_mem: rmtfs-region@d4a80000 {
636 compatible = "qcom,rmtfs-mem";
638 no-map;
640 qcom,client-id = <1>;
644 mpss_dsm_mem: mpss-dsm-region@d4d00000 {
646 no-map;
649 tz_reserved_mem: tz-reserved-region@d8000000 {
651 no-map;
654 cpucp_fw_mem: cpucp-fw-region@d8140000 {
656 no-map;
659 qtee_mem: qtee-region@d8300000 {
661 no-map;
664 ta_mem: ta-region@d8800000 {
666 no-map;
669 tz_tags_mem: tz-tags-region@e1200000 {
671 no-map;
674 hwfence_shbuf: hwfence-shbuf-region@e6440000 {
676 no-map;
679 trust_ui_vm_mem: trust-ui-vm-region@f3600000 {
681 no-map;
684 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 {
686 no-map;
689 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 {
691 no-map;
694 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 {
696 no-map;
699 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 {
701 no-map;
704 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 {
706 no-map;
709 oem_vm_mem: oem-vm-region@f8400000 {
711 no-map;
714 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 {
716 no-map;
719 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 {
721 no-map;
724 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 {
726 no-map;
729 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 {
731 no-map;
735 smp2p-adsp {
738 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
744 qcom,local-pid = <0>;
745 qcom,remote-pid = <2>;
747 smp2p_adsp_out: master-kernel {
748 qcom,entry-name = "master-kernel";
749 #qcom,smem-state-cells = <1>;
752 smp2p_adsp_in: slave-kernel {
753 qcom,entry-name = "slave-kernel";
754 interrupt-controller;
755 #interrupt-cells = <2>;
759 smp2p-cdsp {
762 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
768 qcom,local-pid = <0>;
769 qcom,remote-pid = <5>;
771 smp2p_cdsp_out: master-kernel {
772 qcom,entry-name = "master-kernel";
773 #qcom,smem-state-cells = <1>;
776 smp2p_cdsp_in: slave-kernel {
777 qcom,entry-name = "slave-kernel";
778 interrupt-controller;
779 #interrupt-cells = <2>;
783 smp2p-modem {
786 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
792 qcom,local-pid = <0>;
793 qcom,remote-pid = <1>;
795 smp2p_modem_out: master-kernel {
796 qcom,entry-name = "master-kernel";
797 #qcom,smem-state-cells = <1>;
800 smp2p_modem_in: slave-kernel {
801 qcom,entry-name = "slave-kernel";
802 interrupt-controller;
803 #interrupt-cells = <2>;
806 ipa_smp2p_out: ipa-ap-to-modem {
807 qcom,entry-name = "ipa";
808 #qcom,smem-state-cells = <1>;
811 ipa_smp2p_in: ipa-modem-to-ap {
812 qcom,entry-name = "ipa";
813 interrupt-controller;
814 #interrupt-cells = <2>;
819 compatible = "simple-bus";
821 dma-ranges = <0 0 0 0 0x10 0>;
823 #address-cells = <2>;
824 #size-cells = <2>;
826 gcc: clock-controller@100000 {
827 compatible = "qcom,sm8550-gcc";
829 #clock-cells = <1>;
830 #reset-cells = <1>;
831 #power-domain-cells = <1>;
843 compatible = "qcom,sm8550-ipcc", "qcom,ipcc";
846 interrupt-controller;
847 #interrupt-cells = <3>;
848 #mbox-cells = <2>;
851 gpi_dma2: dma-controller@800000 {
852 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
853 #dma-cells = <3>;
867 dma-channels = <12>;
868 dma-channel-mask = <0x3e>;
870 dma-coherent;
875 compatible = "qcom,geni-se-qup";
878 clock-names = "m-ahb", "s-ahb";
882 dma-coherent;
883 #address-cells = <2>;
884 #size-cells = <2>;
888 compatible = "qcom,geni-i2c";
890 clock-names = "se";
892 pinctrl-names = "default";
893 pinctrl-0 = <&qup_i2c8_data_clk>;
895 #address-cells = <1>;
896 #size-cells = <0>;
903 interconnect-names = "qup-core", "qup-config", "qup-memory";
906 dma-names = "tx", "rx";
907 power-domains = <&rpmhpd RPMHPD_CX>;
908 operating-points-v2 = <&qup_opp_table_120mhz>;
913 compatible = "qcom,geni-spi";
915 clock-names = "se";
918 pinctrl-names = "default";
919 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
926 interconnect-names = "qup-core", "qup-config", "qup-memory";
929 dma-names = "tx", "rx";
930 power-domains = <&rpmhpd RPMHPD_CX>;
931 operating-points-v2 = <&qup_opp_table_120mhz>;
932 #address-cells = <1>;
933 #size-cells = <0>;
938 compatible = "qcom,geni-i2c";
940 clock-names = "se";
942 pinctrl-names = "default";
943 pinctrl-0 = <&qup_i2c9_data_clk>;
945 #address-cells = <1>;
946 #size-cells = <0>;
953 interconnect-names = "qup-core", "qup-config", "qup-memory";
956 dma-names = "tx", "rx";
957 power-domains = <&rpmhpd RPMHPD_CX>;
958 operating-points-v2 = <&qup_opp_table_120mhz>;
963 compatible = "qcom,geni-spi";
965 clock-names = "se";
968 pinctrl-names = "default";
969 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
976 interconnect-names = "qup-core", "qup-config", "qup-memory";
979 dma-names = "tx", "rx";
980 power-domains = <&rpmhpd RPMHPD_CX>;
981 operating-points-v2 = <&qup_opp_table_120mhz>;
982 #address-cells = <1>;
983 #size-cells = <0>;
988 compatible = "qcom,geni-i2c";
990 clock-names = "se";
992 pinctrl-names = "default";
993 pinctrl-0 = <&qup_i2c10_data_clk>;
995 #address-cells = <1>;
996 #size-cells = <0>;
1003 interconnect-names = "qup-core", "qup-config", "qup-memory";
1006 dma-names = "tx", "rx";
1007 power-domains = <&rpmhpd RPMHPD_CX>;
1008 operating-points-v2 = <&qup_opp_table_120mhz>;
1013 compatible = "qcom,geni-spi";
1015 clock-names = "se";
1018 pinctrl-names = "default";
1019 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1026 interconnect-names = "qup-core", "qup-config", "qup-memory";
1029 dma-names = "tx", "rx";
1030 power-domains = <&rpmhpd RPMHPD_CX>;
1031 operating-points-v2 = <&qup_opp_table_120mhz>;
1032 #address-cells = <1>;
1033 #size-cells = <0>;
1038 compatible = "qcom,geni-i2c";
1040 clock-names = "se";
1042 pinctrl-names = "default";
1043 pinctrl-0 = <&qup_i2c11_data_clk>;
1045 #address-cells = <1>;
1046 #size-cells = <0>;
1053 interconnect-names = "qup-core", "qup-config", "qup-memory";
1056 dma-names = "tx", "rx";
1057 power-domains = <&rpmhpd RPMHPD_CX>;
1058 operating-points-v2 = <&qup_opp_table_120mhz>;
1063 compatible = "qcom,geni-spi";
1065 clock-names = "se";
1068 pinctrl-names = "default";
1069 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1076 interconnect-names = "qup-core", "qup-config", "qup-memory";
1079 dma-names = "tx", "rx";
1080 power-domains = <&rpmhpd RPMHPD_CX>;
1081 operating-points-v2 = <&qup_opp_table_120mhz>;
1082 #address-cells = <1>;
1083 #size-cells = <0>;
1088 compatible = "qcom,geni-i2c";
1090 clock-names = "se";
1092 pinctrl-names = "default";
1093 pinctrl-0 = <&qup_i2c12_data_clk>;
1095 #address-cells = <1>;
1096 #size-cells = <0>;
1103 interconnect-names = "qup-core", "qup-config", "qup-memory";
1106 dma-names = "tx", "rx";
1107 power-domains = <&rpmhpd RPMHPD_CX>;
1108 operating-points-v2 = <&qup_opp_table_120mhz>;
1113 compatible = "qcom,geni-spi";
1115 clock-names = "se";
1118 pinctrl-names = "default";
1119 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1126 interconnect-names = "qup-core", "qup-config", "qup-memory";
1129 dma-names = "tx", "rx";
1130 power-domains = <&rpmhpd RPMHPD_CX>;
1131 operating-points-v2 = <&qup_opp_table_120mhz>;
1132 #address-cells = <1>;
1133 #size-cells = <0>;
1138 compatible = "qcom,geni-i2c";
1140 clock-names = "se";
1142 pinctrl-names = "default";
1143 pinctrl-0 = <&qup_i2c13_data_clk>;
1145 #address-cells = <1>;
1146 #size-cells = <0>;
1153 interconnect-names = "qup-core", "qup-config", "qup-memory";
1156 dma-names = "tx", "rx";
1157 power-domains = <&rpmhpd RPMHPD_CX>;
1158 operating-points-v2 = <&qup_opp_table_120mhz>;
1163 compatible = "qcom,geni-spi";
1165 clock-names = "se";
1168 pinctrl-names = "default";
1169 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1176 interconnect-names = "qup-core", "qup-config", "qup-memory";
1179 dma-names = "tx", "rx";
1180 power-domains = <&rpmhpd RPMHPD_CX>;
1181 operating-points-v2 = <&qup_opp_table_120mhz>;
1182 #address-cells = <1>;
1183 #size-cells = <0>;
1188 compatible = "qcom,geni-uart";
1190 clock-names = "se";
1192 pinctrl-names = "default";
1193 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
1199 interconnect-names = "qup-core", "qup-config";
1200 power-domains = <&rpmhpd RPMHPD_CX>;
1201 operating-points-v2 = <&qup_opp_table_125mhz>;
1206 compatible = "qcom,geni-i2c";
1208 clock-names = "se";
1210 pinctrl-names = "default";
1211 pinctrl-0 = <&qup_i2c15_data_clk>;
1213 #address-cells = <1>;
1214 #size-cells = <0>;
1221 interconnect-names = "qup-core", "qup-config", "qup-memory";
1224 dma-names = "tx", "rx";
1225 power-domains = <&rpmhpd RPMHPD_CX>;
1226 operating-points-v2 = <&qup_opp_table_100mhz>;
1231 compatible = "qcom,geni-spi";
1233 clock-names = "se";
1236 pinctrl-names = "default";
1237 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1244 interconnect-names = "qup-core", "qup-config", "qup-memory";
1247 dma-names = "tx", "rx";
1248 power-domains = <&rpmhpd RPMHPD_CX>;
1249 operating-points-v2 = <&qup_opp_table_100mhz>;
1250 #address-cells = <1>;
1251 #size-cells = <0>;
1257 compatible = "qcom,geni-se-i2c-master-hub";
1259 clock-names = "s-ahb";
1261 #address-cells = <2>;
1262 #size-cells = <2>;
1267 compatible = "qcom,geni-i2c-master-hub";
1269 clock-names = "se", "core";
1272 pinctrl-names = "default";
1273 pinctrl-0 = <&hub_i2c0_data_clk>;
1275 #address-cells = <1>;
1276 #size-cells = <0>;
1281 interconnect-names = "qup-core", "qup-config";
1282 power-domains = <&rpmhpd RPMHPD_CX>;
1283 required-opps = <&rpmhpd_opp_low_svs>;
1288 compatible = "qcom,geni-i2c-master-hub";
1290 clock-names = "se", "core";
1293 pinctrl-names = "default";
1294 pinctrl-0 = <&hub_i2c1_data_clk>;
1296 #address-cells = <1>;
1297 #size-cells = <0>;
1302 interconnect-names = "qup-core", "qup-config";
1303 power-domains = <&rpmhpd RPMHPD_CX>;
1304 required-opps = <&rpmhpd_opp_low_svs>;
1309 compatible = "qcom,geni-i2c-master-hub";
1311 clock-names = "se", "core";
1314 pinctrl-names = "default";
1315 pinctrl-0 = <&hub_i2c2_data_clk>;
1317 #address-cells = <1>;
1318 #size-cells = <0>;
1323 interconnect-names = "qup-core", "qup-config";
1324 power-domains = <&rpmhpd RPMHPD_CX>;
1325 required-opps = <&rpmhpd_opp_low_svs>;
1330 compatible = "qcom,geni-i2c-master-hub";
1332 clock-names = "se", "core";
1335 pinctrl-names = "default";
1336 pinctrl-0 = <&hub_i2c3_data_clk>;
1338 #address-cells = <1>;
1339 #size-cells = <0>;
1344 interconnect-names = "qup-core", "qup-config";
1345 power-domains = <&rpmhpd RPMHPD_CX>;
1346 required-opps = <&rpmhpd_opp_low_svs>;
1351 compatible = "qcom,geni-i2c-master-hub";
1353 clock-names = "se", "core";
1356 pinctrl-names = "default";
1357 pinctrl-0 = <&hub_i2c4_data_clk>;
1359 #address-cells = <1>;
1360 #size-cells = <0>;
1365 interconnect-names = "qup-core", "qup-config";
1366 power-domains = <&rpmhpd RPMHPD_CX>;
1367 required-opps = <&rpmhpd_opp_low_svs>;
1372 compatible = "qcom,geni-i2c-master-hub";
1374 clock-names = "se", "core";
1377 pinctrl-names = "default";
1378 pinctrl-0 = <&hub_i2c5_data_clk>;
1380 #address-cells = <1>;
1381 #size-cells = <0>;
1386 interconnect-names = "qup-core", "qup-config";
1387 power-domains = <&rpmhpd RPMHPD_CX>;
1388 required-opps = <&rpmhpd_opp_low_svs>;
1393 compatible = "qcom,geni-i2c-master-hub";
1395 clock-names = "se", "core";
1398 pinctrl-names = "default";
1399 pinctrl-0 = <&hub_i2c6_data_clk>;
1401 #address-cells = <1>;
1402 #size-cells = <0>;
1407 interconnect-names = "qup-core", "qup-config";
1408 power-domains = <&rpmhpd RPMHPD_CX>;
1409 required-opps = <&rpmhpd_opp_low_svs>;
1414 compatible = "qcom,geni-i2c-master-hub";
1416 clock-names = "se", "core";
1419 pinctrl-names = "default";
1420 pinctrl-0 = <&hub_i2c7_data_clk>;
1422 #address-cells = <1>;
1423 #size-cells = <0>;
1428 interconnect-names = "qup-core", "qup-config";
1429 power-domains = <&rpmhpd RPMHPD_CX>;
1430 required-opps = <&rpmhpd_opp_low_svs>;
1435 compatible = "qcom,geni-i2c-master-hub";
1437 clock-names = "se", "core";
1440 pinctrl-names = "default";
1441 pinctrl-0 = <&hub_i2c8_data_clk>;
1443 #address-cells = <1>;
1444 #size-cells = <0>;
1449 interconnect-names = "qup-core", "qup-config";
1450 power-domains = <&rpmhpd RPMHPD_CX>;
1451 required-opps = <&rpmhpd_opp_low_svs>;
1456 compatible = "qcom,geni-i2c-master-hub";
1458 clock-names = "se", "core";
1461 pinctrl-names = "default";
1462 pinctrl-0 = <&hub_i2c9_data_clk>;
1464 #address-cells = <1>;
1465 #size-cells = <0>;
1470 interconnect-names = "qup-core", "qup-config";
1471 power-domains = <&rpmhpd RPMHPD_CX>;
1472 required-opps = <&rpmhpd_opp_low_svs>;
1477 gpi_dma1: dma-controller@a00000 {
1478 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
1479 #dma-cells = <3>;
1493 dma-channels = <12>;
1494 dma-channel-mask = <0x1e>;
1496 dma-coherent;
1501 compatible = "qcom,geni-se-qup";
1504 clock-names = "m-ahb", "s-ahb";
1510 interconnect-names = "qup-core";
1511 dma-coherent;
1512 #address-cells = <2>;
1513 #size-cells = <2>;
1517 compatible = "qcom,geni-i2c";
1519 clock-names = "se";
1521 pinctrl-names = "default";
1522 pinctrl-0 = <&qup_i2c0_data_clk>;
1524 #address-cells = <1>;
1525 #size-cells = <0>;
1532 interconnect-names = "qup-core", "qup-config", "qup-memory";
1535 dma-names = "tx", "rx";
1536 power-domains = <&rpmhpd RPMHPD_CX>;
1537 operating-points-v2 = <&qup_opp_table_120mhz>;
1542 compatible = "qcom,geni-spi";
1544 clock-names = "se";
1547 pinctrl-names = "default";
1548 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1555 interconnect-names = "qup-core", "qup-config", "qup-memory";
1558 dma-names = "tx", "rx";
1559 power-domains = <&rpmhpd RPMHPD_CX>;
1560 operating-points-v2 = <&qup_opp_table_120mhz>;
1561 #address-cells = <1>;
1562 #size-cells = <0>;
1567 compatible = "qcom,geni-i2c";
1569 clock-names = "se";
1571 pinctrl-names = "default";
1572 pinctrl-0 = <&qup_i2c1_data_clk>;
1574 #address-cells = <1>;
1575 #size-cells = <0>;
1582 interconnect-names = "qup-core", "qup-config", "qup-memory";
1585 dma-names = "tx", "rx";
1586 power-domains = <&rpmhpd RPMHPD_CX>;
1587 operating-points-v2 = <&qup_opp_table_120mhz>;
1592 compatible = "qcom,geni-spi";
1594 clock-names = "se";
1597 pinctrl-names = "default";
1598 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1605 interconnect-names = "qup-core", "qup-config", "qup-memory";
1608 dma-names = "tx", "rx";
1609 power-domains = <&rpmhpd RPMHPD_CX>;
1610 operating-points-v2 = <&qup_opp_table_120mhz>;
1611 #address-cells = <1>;
1612 #size-cells = <0>;
1617 compatible = "qcom,geni-i2c";
1619 clock-names = "se";
1621 pinctrl-names = "default";
1622 pinctrl-0 = <&qup_i2c2_data_clk>;
1624 #address-cells = <1>;
1625 #size-cells = <0>;
1632 interconnect-names = "qup-core", "qup-config", "qup-memory";
1635 dma-names = "tx", "rx";
1636 power-domains = <&rpmhpd RPMHPD_CX>;
1637 operating-points-v2 = <&qup_opp_table_100mhz>;
1642 compatible = "qcom,geni-spi";
1644 clock-names = "se";
1647 pinctrl-names = "default";
1648 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1655 interconnect-names = "qup-core", "qup-config", "qup-memory";
1658 dma-names = "tx", "rx";
1659 power-domains = <&rpmhpd RPMHPD_CX>;
1660 operating-points-v2 = <&qup_opp_table_100mhz>;
1661 #address-cells = <1>;
1662 #size-cells = <0>;
1667 compatible = "qcom,geni-i2c";
1669 clock-names = "se";
1671 pinctrl-names = "default";
1672 pinctrl-0 = <&qup_i2c3_data_clk>;
1674 #address-cells = <1>;
1675 #size-cells = <0>;
1682 interconnect-names = "qup-core", "qup-config", "qup-memory";
1685 dma-names = "tx", "rx";
1686 power-domains = <&rpmhpd RPMHPD_CX>;
1687 operating-points-v2 = <&qup_opp_table_100mhz>;
1692 compatible = "qcom,geni-spi";
1694 clock-names = "se";
1697 pinctrl-names = "default";
1698 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1705 interconnect-names = "qup-core", "qup-config", "qup-memory";
1708 dma-names = "tx", "rx";
1709 power-domains = <&rpmhpd RPMHPD_CX>;
1710 operating-points-v2 = <&qup_opp_table_100mhz>;
1711 #address-cells = <1>;
1712 #size-cells = <0>;
1717 compatible = "qcom,geni-i2c";
1719 clock-names = "se";
1721 pinctrl-names = "default";
1722 pinctrl-0 = <&qup_i2c4_data_clk>;
1724 #address-cells = <1>;
1725 #size-cells = <0>;
1732 interconnect-names = "qup-core", "qup-config", "qup-memory";
1735 dma-names = "tx", "rx";
1736 power-domains = <&rpmhpd RPMHPD_CX>;
1737 operating-points-v2 = <&qup_opp_table_100mhz>;
1742 compatible = "qcom,geni-spi";
1744 clock-names = "se";
1747 pinctrl-names = "default";
1748 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1755 interconnect-names = "qup-core", "qup-config", "qup-memory";
1758 dma-names = "tx", "rx";
1759 power-domains = <&rpmhpd RPMHPD_CX>;
1760 operating-points-v2 = <&qup_opp_table_100mhz>;
1761 #address-cells = <1>;
1762 #size-cells = <0>;
1767 compatible = "qcom,geni-i2c";
1769 clock-names = "se";
1771 pinctrl-names = "default";
1772 pinctrl-0 = <&qup_i2c5_data_clk>;
1780 interconnect-names = "qup-core", "qup-config", "qup-memory";
1783 dma-names = "tx", "rx";
1784 power-domains = <&rpmhpd RPMHPD_CX>;
1785 operating-points-v2 = <&qup_opp_table_100mhz>;
1786 #address-cells = <1>;
1787 #size-cells = <0>;
1792 compatible = "qcom,geni-spi";
1794 clock-names = "se";
1797 pinctrl-names = "default";
1798 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1805 interconnect-names = "qup-core", "qup-config", "qup-memory";
1808 dma-names = "tx", "rx";
1809 power-domains = <&rpmhpd RPMHPD_CX>;
1810 operating-points-v2 = <&qup_opp_table_100mhz>;
1811 #address-cells = <1>;
1812 #size-cells = <0>;
1817 compatible = "qcom,geni-i2c";
1819 clock-names = "se";
1821 pinctrl-names = "default";
1822 pinctrl-0 = <&qup_i2c6_data_clk>;
1830 interconnect-names = "qup-core", "qup-config", "qup-memory";
1833 dma-names = "tx", "rx";
1834 power-domains = <&rpmhpd RPMHPD_CX>;
1835 operating-points-v2 = <&qup_opp_table_100mhz>;
1836 #address-cells = <1>;
1837 #size-cells = <0>;
1842 compatible = "qcom,geni-spi";
1844 clock-names = "se";
1847 pinctrl-names = "default";
1848 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1855 interconnect-names = "qup-core", "qup-config", "qup-memory";
1858 dma-names = "tx", "rx";
1859 power-domains = <&rpmhpd RPMHPD_CX>;
1860 operating-points-v2 = <&qup_opp_table_100mhz>;
1861 #address-cells = <1>;
1862 #size-cells = <0>;
1867 compatible = "qcom,geni-debug-uart";
1869 clock-names = "se";
1871 pinctrl-names = "default";
1872 pinctrl-0 = <&qup_uart7_default>;
1874 interconnect-names = "qup-core", "qup-config";
1879 power-domains = <&rpmhpd RPMHPD_CX>;
1880 operating-points-v2 = <&qup_opp_table_100mhz>;
1886 compatible = "qcom,sm8550-cnoc-main";
1888 #interconnect-cells = <2>;
1889 qcom,bcm-voters = <&apps_bcm_voter>;
1893 compatible = "qcom,sm8550-config-noc";
1895 #interconnect-cells = <2>;
1896 qcom,bcm-voters = <&apps_bcm_voter>;
1900 compatible = "qcom,sm8550-system-noc";
1902 #interconnect-cells = <2>;
1903 qcom,bcm-voters = <&apps_bcm_voter>;
1907 compatible = "qcom,sm8550-pcie-anoc";
1909 #interconnect-cells = <2>;
1912 qcom,bcm-voters = <&apps_bcm_voter>;
1916 compatible = "qcom,sm8550-aggre1-noc";
1918 #interconnect-cells = <2>;
1921 qcom,bcm-voters = <&apps_bcm_voter>;
1925 compatible = "qcom,sm8550-aggre2-noc";
1927 #interconnect-cells = <2>;
1929 qcom,bcm-voters = <&apps_bcm_voter>;
1933 compatible = "qcom,sm8550-mmss-noc";
1935 #interconnect-cells = <2>;
1936 qcom,bcm-voters = <&apps_bcm_voter>;
1940 compatible = "qcom,sm8550-trng", "qcom,trng";
1946 compatible = "qcom,pcie-sm8550";
1952 reg-names = "parf", "dbi", "elbi", "atu", "config";
1953 #address-cells = <3>;
1954 #size-cells = <2>;
1957 bus-range = <0x00 0xff>;
1959 dma-coherent;
1961 linux,pci-domain = <0>;
1962 num-lanes = <2>;
1973 interrupt-names = "msi0",
1982 #interrupt-cells = <1>;
1983 interrupt-map-mask = <0 0 0 0x7>;
1984 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1996 clock-names = "aux",
2008 interconnect-names = "pcie-mem", "cpu-pcie";
2010 msi-map = <0x0 &gic_its 0x1400 0x1>,
2012 iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
2016 reset-names = "pci";
2018 power-domains = <&gcc PCIE_0_GDSC>;
2021 phy-names = "pciephy";
2023 operating-points-v2 = <&pcie0_opp_table>;
2027 pcie0_opp_table: opp-table {
2028 compatible = "operating-points-v2";
2031 opp-2500000 {
2032 opp-hz = /bits/ 64 <2500000>;
2033 required-opps = <&rpmhpd_opp_low_svs>;
2034 opp-peak-kBps = <250000 1>;
2038 opp-5000000 {
2039 opp-hz = /bits/ 64 <5000000>;
2040 required-opps = <&rpmhpd_opp_low_svs>;
2041 opp-peak-kBps = <500000 1>;
2045 opp-10000000 {
2046 opp-hz = /bits/ 64 <10000000>;
2047 required-opps = <&rpmhpd_opp_low_svs>;
2048 opp-peak-kBps = <1000000 1>;
2052 opp-8000000 {
2053 opp-hz = /bits/ 64 <8000000>;
2054 required-opps = <&rpmhpd_opp_nom>;
2055 opp-peak-kBps = <984500 1>;
2059 opp-16000000 {
2060 opp-hz = /bits/ 64 <16000000>;
2061 required-opps = <&rpmhpd_opp_nom>;
2062 opp-peak-kBps = <1969000 1>;
2069 bus-range = <0x01 0xff>;
2071 #address-cells = <3>;
2072 #size-cells = <2>;
2078 compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy";
2086 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2090 reset-names = "phy";
2092 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
2093 assigned-clock-rates = <100000000>;
2095 power-domains = <&gcc PCIE_0_PHY_GDSC>;
2097 #clock-cells = <0>;
2098 clock-output-names = "pcie0_pipe_clk";
2100 #phy-cells = <0>;
2107 compatible = "qcom,pcie-sm8550";
2113 reg-names = "parf", "dbi", "elbi", "atu", "config";
2114 #address-cells = <3>;
2115 #size-cells = <2>;
2118 bus-range = <0x00 0xff>;
2120 dma-coherent;
2122 linux,pci-domain = <1>;
2123 num-lanes = <2>;
2134 interrupt-names = "msi0",
2143 #interrupt-cells = <1>;
2144 interrupt-map-mask = <0 0 0 0x7>;
2145 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2158 clock-names = "aux",
2167 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2168 assigned-clock-rates = <19200000>;
2174 interconnect-names = "pcie-mem", "cpu-pcie";
2176 msi-map = <0x0 &gic_its 0x1480 0x1>,
2178 iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
2183 reset-names = "pci", "link_down";
2185 power-domains = <&gcc PCIE_1_GDSC>;
2188 phy-names = "pciephy";
2190 operating-points-v2 = <&pcie1_opp_table>;
2194 pcie1_opp_table: opp-table {
2195 compatible = "operating-points-v2";
2198 opp-2500000 {
2199 opp-hz = /bits/ 64 <2500000>;
2200 required-opps = <&rpmhpd_opp_low_svs>;
2201 opp-peak-kBps = <250000 1>;
2205 opp-5000000 {
2206 opp-hz = /bits/ 64 <5000000>;
2207 required-opps = <&rpmhpd_opp_low_svs>;
2208 opp-peak-kBps = <500000 1>;
2212 opp-10000000 {
2213 opp-hz = /bits/ 64 <10000000>;
2214 required-opps = <&rpmhpd_opp_low_svs>;
2215 opp-peak-kBps = <1000000 1>;
2219 opp-8000000 {
2220 opp-hz = /bits/ 64 <8000000>;
2221 required-opps = <&rpmhpd_opp_nom>;
2222 opp-peak-kBps = <984500 1>;
2226 opp-16000000 {
2227 opp-hz = /bits/ 64 <16000000>;
2228 required-opps = <&rpmhpd_opp_nom>;
2229 opp-peak-kBps = <1969000 1>;
2233 opp-32000000 {
2234 opp-hz = /bits/ 64 <32000000>;
2235 required-opps = <&rpmhpd_opp_nom>;
2236 opp-peak-kBps = <3938000 1>;
2243 bus-range = <0x01 0xff>;
2245 #address-cells = <3>;
2246 #size-cells = <2>;
2252 compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy";
2260 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2265 reset-names = "phy", "phy_nocsr";
2267 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2268 assigned-clock-rates = <100000000>;
2270 power-domains = <&gcc PCIE_1_PHY_GDSC>;
2272 #clock-cells = <1>;
2273 clock-output-names = "pcie1_pipe_clk";
2275 #phy-cells = <0>;
2280 cryptobam: dma-controller@1dc4000 {
2281 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2284 #dma-cells = <1>;
2286 qcom,num-ees = <4>;
2287 num-channels = <20>;
2288 qcom,controlled-remotely;
2294 compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce";
2297 dma-names = "rx", "tx";
2302 interconnect-names = "memory";
2306 compatible = "qcom,sm8550-qmp-ufs-phy";
2311 clock-names = "ref",
2315 power-domains = <&gcc UFS_MEM_PHY_GDSC>;
2318 reset-names = "ufsphy";
2320 #clock-cells = <1>;
2321 #phy-cells = <0>;
2327 compatible = "qcom,sm8550-ufshc", "qcom,ufshc",
2328 "jedec,ufs-2.0";
2332 phy-names = "ufsphy";
2333 lanes-per-direction = <2>;
2334 #reset-cells = <1>;
2336 reset-names = "rst";
2338 power-domains = <&gcc UFS_PHY_GDSC>;
2339 required-opps = <&rpmhpd_opp_nom>;
2342 dma-coherent;
2344 operating-points-v2 = <&ufs_opp_table>;
2350 interconnect-names = "ufs-ddr", "cpu-ufs";
2351 clock-names = "core_clk",
2371 ufs_opp_table: opp-table {
2372 compatible = "operating-points-v2";
2374 opp-75000000 {
2375 opp-hz = /bits/ 64 <75000000>,
2383 required-opps = <&rpmhpd_opp_low_svs>;
2386 opp-150000000 {
2387 opp-hz = /bits/ 64 <150000000>,
2395 required-opps = <&rpmhpd_opp_svs>;
2398 opp-300000000 {
2399 opp-hz = /bits/ 64 <300000000>,
2407 required-opps = <&rpmhpd_opp_nom>;
2413 compatible = "qcom,sm8550-inline-crypto-engine",
2414 "qcom,inline-crypto-engine";
2421 compatible = "qcom,tcsr-mutex";
2423 #hwlock-cells = <1>;
2426 tcsr: clock-controller@1fc0000 {
2427 compatible = "qcom,sm8550-tcsr", "syscon";
2430 #clock-cells = <1>;
2431 #reset-cells = <1>;
2435 compatible = "qcom,adreno-43050a01", "qcom,adreno";
2439 reg-names = "kgsl_3d0_reg_memory",
2448 operating-points-v2 = <&gpu_opp_table>;
2451 #cooling-cells = <2>;
2455 interconnect-names = "gfx-mem";
2459 zap-shader {
2460 memory-region = <&gpu_micro_code_mem>;
2464 gpu_opp_table: opp-table {
2465 compatible = "operating-points-v2";
2467 opp-680000000 {
2468 opp-hz = /bits/ 64 <680000000>;
2469 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2470 opp-peak-kBps = <16500000>;
2473 opp-615000000 {
2474 opp-hz = /bits/ 64 <615000000>;
2475 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2476 opp-peak-kBps = <12449218>;
2479 opp-550000000 {
2480 opp-hz = /bits/ 64 <550000000>;
2481 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2482 opp-peak-kBps = <10687500>;
2485 opp-475000000 {
2486 opp-hz = /bits/ 64 <475000000>;
2487 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
2488 opp-peak-kBps = <6074218>;
2491 opp-401000000 {
2492 opp-hz = /bits/ 64 <401000000>;
2493 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2494 opp-peak-kBps = <6074218>;
2497 opp-348000000 {
2498 opp-hz = /bits/ 64 <348000000>;
2499 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
2500 opp-peak-kBps = <6074218>;
2503 opp-295000000 {
2504 opp-hz = /bits/ 64 <295000000>;
2505 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2506 opp-peak-kBps = <6074218>;
2509 opp-220000000 {
2510 opp-hz = /bits/ 64 <220000000>;
2511 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
2512 opp-peak-kBps = <2136718>;
2518 compatible = "qcom,adreno-gmu-740.1", "qcom,adreno-gmu";
2522 reg-names = "gmu", "rscc", "gmu_pdc";
2526 interrupt-names = "hfi", "gmu";
2535 clock-names = "ahb",
2543 power-domains = <&gpucc GPU_CC_CX_GDSC>,
2545 power-domain-names = "cx",
2552 operating-points-v2 = <&gmu_opp_table>;
2554 gmu_opp_table: opp-table {
2555 compatible = "operating-points-v2";
2557 opp-500000000 {
2558 opp-hz = /bits/ 64 <500000000>;
2559 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2562 opp-200000000 {
2563 opp-hz = /bits/ 64 <200000000>;
2564 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2569 gpucc: clock-controller@3d90000 {
2570 compatible = "qcom,sm8550-gpucc";
2575 #clock-cells = <1>;
2576 #reset-cells = <1>;
2577 #power-domain-cells = <1>;
2581 compatible = "qcom,sm8550-smmu-500", "qcom,adreno-smmu",
2582 "qcom,smmu-500", "arm,mmu-500";
2584 #iommu-cells = <2>;
2585 #global-interrupts = <1>;
2616 clock-names = "hlos",
2620 power-domains = <&gpucc GPU_CC_CX_GDSC>;
2621 dma-coherent;
2625 compatible = "qcom,sm8550-ipa";
2632 reg-names = "ipa-reg",
2633 "ipa-shared",
2636 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
2640 interrupt-names = "ipa",
2642 "ipa-clock-query",
2643 "ipa-setup-ready";
2646 clock-names = "core";
2652 interconnect-names = "memory",
2657 qcom,smem-states = <&ipa_smp2p_out 0>,
2659 qcom,smem-state-names = "ipa-clock-enabled-valid",
2660 "ipa-clock-enabled";
2666 compatible = "qcom,sm8550-mpss-pas";
2669 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2675 interrupt-names = "wdog", "fatal", "ready", "handover",
2676 "stop-ack", "shutdown-ack";
2679 clock-names = "xo";
2681 power-domains = <&rpmhpd RPMHPD_CX>,
2683 power-domain-names = "cx", "mss";
2688 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>;
2692 qcom,smem-states = <&smp2p_modem_out 0>;
2693 qcom,smem-state-names = "stop";
2697 glink-edge {
2698 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2704 qcom,remote-pid = <1>;
2709 compatible = "qcom,sm8550-adsp-pas";
2712 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2717 interrupt-names = "wdog", "fatal", "ready",
2718 "handover", "stop-ack";
2721 clock-names = "xo";
2723 power-domains = <&rpmhpd RPMHPD_LCX>,
2725 power-domain-names = "lcx", "lmx";
2730 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
2734 qcom,smem-states = <&smp2p_adsp_out 0>;
2735 qcom,smem-state-names = "stop";
2739 remoteproc_adsp_glink: glink-edge {
2740 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2747 qcom,remote-pid = <2>;
2751 qcom,glink-channels = "fastrpcglink-apps-dsp";
2753 qcom,non-secure-domain;
2754 #address-cells = <1>;
2755 #size-cells = <0>;
2757 compute-cb@3 {
2758 compatible = "qcom,fastrpc-compute-cb";
2762 dma-coherent;
2765 compute-cb@4 {
2766 compatible = "qcom,fastrpc-compute-cb";
2770 dma-coherent;
2773 compute-cb@5 {
2774 compatible = "qcom,fastrpc-compute-cb";
2778 dma-coherent;
2781 compute-cb@6 {
2782 compatible = "qcom,fastrpc-compute-cb";
2786 dma-coherent;
2789 compute-cb@7 {
2790 compatible = "qcom,fastrpc-compute-cb";
2794 dma-coherent;
2800 qcom,glink-channels = "adsp_apps";
2803 #address-cells = <1>;
2804 #size-cells = <0>;
2809 #sound-dai-cells = <0>;
2810 qcom,protection-domain = "avs/audio",
2814 compatible = "qcom,q6apm-dais";
2820 compatible = "qcom,q6apm-lpass-dais";
2821 #sound-dai-cells = <1>;
2828 qcom,protection-domain = "avs/audio",
2831 q6prmcc: clock-controller {
2832 compatible = "qcom,q6prm-lpass-clocks";
2833 #clock-cells = <2>;
2841 compatible = "qcom,sm8550-lpass-wsa-macro";
2847 clock-names = "mclk", "macro", "dcodec", "fsgen";
2849 #clock-cells = <0>;
2850 clock-output-names = "wsa2-mclk";
2851 #sound-dai-cells = <1>;
2855 compatible = "qcom,soundwire-v2.0.0";
2859 clock-names = "iface";
2862 pinctrl-0 = <&wsa2_swr_active>;
2863 pinctrl-names = "default";
2865 qcom,din-ports = <4>;
2866 qcom,dout-ports = <9>;
2868 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
2869 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2870 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2871 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2872 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2873 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
2874 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
2875 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2876 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2878 #address-cells = <2>;
2879 #size-cells = <0>;
2880 #sound-dai-cells = <1>;
2885 compatible = "qcom,sm8550-lpass-rx-macro";
2891 clock-names = "mclk", "macro", "dcodec", "fsgen";
2893 #clock-cells = <0>;
2894 clock-output-names = "mclk";
2895 #sound-dai-cells = <1>;
2899 compatible = "qcom,soundwire-v2.0.0";
2903 clock-names = "iface";
2906 pinctrl-0 = <&rx_swr_active>;
2907 pinctrl-names = "default";
2909 qcom,din-ports = <1>;
2910 qcom,dout-ports = <11>;
2912 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff 0xff 0xff>;
2913 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2914 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2915 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>;
2916 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>;
2917 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff 0xff 0xff>;
2918 …qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff 0xff 0xff…
2919 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0x…
2920 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2922 #address-cells = <2>;
2923 #size-cells = <0>;
2924 #sound-dai-cells = <1>;
2929 compatible = "qcom,sm8550-lpass-tx-macro";
2935 clock-names = "mclk", "macro", "dcodec", "fsgen";
2937 #clock-cells = <0>;
2938 clock-output-names = "mclk";
2939 #sound-dai-cells = <1>;
2943 compatible = "qcom,sm8550-lpass-wsa-macro";
2949 clock-names = "mclk", "macro", "dcodec", "fsgen";
2951 #clock-cells = <0>;
2952 clock-output-names = "mclk";
2953 #sound-dai-cells = <1>;
2957 compatible = "qcom,soundwire-v2.0.0";
2961 clock-names = "iface";
2964 pinctrl-0 = <&wsa_swr_active>;
2965 pinctrl-names = "default";
2967 qcom,din-ports = <4>;
2968 qcom,dout-ports = <9>;
2970 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
2971 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2972 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2973 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2974 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2975 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
2976 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
2977 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2978 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2980 #address-cells = <2>;
2981 #size-cells = <0>;
2982 #sound-dai-cells = <1>;
2987 compatible = "qcom,soundwire-v2.0.0";
2991 interrupt-names = "core", "wakeup";
2993 clock-names = "iface";
2996 pinctrl-0 = <&tx_swr_active>;
2997 pinctrl-names = "default";
2999 qcom,din-ports = <4>;
3000 qcom,dout-ports = <0>;
3001 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
3002 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
3003 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
3004 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
3005 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
3006 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
3007 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
3008 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
3009 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
3011 #address-cells = <2>;
3012 #size-cells = <0>;
3013 #sound-dai-cells = <1>;
3018 compatible = "qcom,sm8550-lpass-va-macro";
3023 clock-names = "mclk", "macro", "dcodec";
3025 #clock-cells = <0>;
3026 clock-output-names = "fsgen";
3027 #sound-dai-cells = <1>;
3031 compatible = "qcom,sm8550-lpass-lpi-pinctrl";
3034 gpio-controller;
3035 #gpio-cells = <2>;
3036 gpio-ranges = <&lpass_tlmm 0 0 23>;
3040 clock-names = "core", "audio";
3042 tx_swr_active: tx-swr-active-state {
3043 clk-pins {
3046 drive-strength = <2>;
3047 slew-rate = <1>;
3048 bias-disable;
3051 data-pins {
3054 drive-strength = <2>;
3055 slew-rate = <1>;
3056 bias-bus-hold;
3060 rx_swr_active: rx-swr-active-state {
3061 clk-pins {
3064 drive-strength = <2>;
3065 slew-rate = <1>;
3066 bias-disable;
3069 data-pins {
3072 drive-strength = <2>;
3073 slew-rate = <1>;
3074 bias-bus-hold;
3078 dmic01_default: dmic01-default-state {
3079 clk-pins {
3082 drive-strength = <8>;
3083 output-high;
3086 data-pins {
3089 drive-strength = <8>;
3090 input-enable;
3094 dmic23_default: dmic23-default-state {
3095 clk-pins {
3098 drive-strength = <8>;
3099 output-high;
3102 data-pins {
3105 drive-strength = <8>;
3106 input-enable;
3110 wsa_swr_active: wsa-swr-active-state {
3111 clk-pins {
3114 drive-strength = <2>;
3115 slew-rate = <1>;
3116 bias-disable;
3119 data-pins {
3122 drive-strength = <2>;
3123 slew-rate = <1>;
3124 bias-bus-hold;
3128 wsa2_swr_active: wsa2-swr-active-state {
3129 clk-pins {
3132 drive-strength = <2>;
3133 slew-rate = <1>;
3134 bias-disable;
3137 data-pins {
3140 drive-strength = <2>;
3141 slew-rate = <1>;
3142 bias-bus-hold;
3148 compatible = "qcom,sm8550-lpass-lpiaon-noc";
3150 #interconnect-cells = <2>;
3151 qcom,bcm-voters = <&apps_bcm_voter>;
3155 compatible = "qcom,sm8550-lpass-lpicx-noc";
3157 #interconnect-cells = <2>;
3158 qcom,bcm-voters = <&apps_bcm_voter>;
3162 compatible = "qcom,sm8550-lpass-ag-noc";
3164 #interconnect-cells = <2>;
3165 qcom,bcm-voters = <&apps_bcm_voter>;
3169 compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5";
3174 interrupt-names = "hc_irq", "pwr_irq";
3179 clock-names = "iface", "core", "xo";
3181 qcom,dll-config = <0x0007642c>;
3182 qcom,ddr-config = <0x80040868>;
3183 power-domains = <&rpmhpd RPMHPD_CX>;
3184 operating-points-v2 = <&sdhc2_opp_table>;
3190 interconnect-names = "sdhc-ddr", "cpu-sdhc";
3191 bus-width = <4>;
3192 dma-coherent;
3194 /* Forbid SDR104/SDR50 - broken hw! */
3195 sdhci-caps-mask = <0x3 0>;
3199 sdhc2_opp_table: opp-table {
3200 compatible = "operating-points-v2";
3202 opp-19200000 {
3203 opp-hz = /bits/ 64 <19200000>;
3204 required-opps = <&rpmhpd_opp_min_svs>;
3207 opp-50000000 {
3208 opp-hz = /bits/ 64 <50000000>;
3209 required-opps = <&rpmhpd_opp_low_svs>;
3212 opp-100000000 {
3213 opp-hz = /bits/ 64 <100000000>;
3214 required-opps = <&rpmhpd_opp_svs>;
3217 opp-202000000 {
3218 opp-hz = /bits/ 64 <202000000>;
3219 required-opps = <&rpmhpd_opp_svs_l1>;
3224 iris: video-codec@aa00000 {
3225 compatible = "qcom,sm8550-iris";
3230 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
3234 power-domain-names = "venus",
3238 operating-points-v2 = <&iris_opp_table>;
3243 clock-names = "iface",
3251 interconnect-names = "cpu-cfg",
3252 "video-mem";
3254 memory-region = <&video_mem>;
3257 reset-names = "bus";
3261 dma-coherent;
3270 iris_opp_table: opp-table {
3271 compatible = "operating-points-v2";
3273 opp-240000000 {
3274 opp-hz = /bits/ 64 <240000000>;
3275 required-opps = <&rpmhpd_opp_svs>,
3279 opp-338000000 {
3280 opp-hz = /bits/ 64 <338000000>;
3281 required-opps = <&rpmhpd_opp_svs>,
3285 opp-366000000 {
3286 opp-hz = /bits/ 64 <366000000>;
3287 required-opps = <&rpmhpd_opp_svs_l1>,
3291 opp-444000000 {
3292 opp-hz = /bits/ 64 <444000000>;
3293 required-opps = <&rpmhpd_opp_nom>,
3297 opp-533333334 {
3298 opp-hz = /bits/ 64 <533333334>;
3299 required-opps = <&rpmhpd_opp_turbo>,
3305 videocc: clock-controller@aaf0000 {
3306 compatible = "qcom,sm8550-videocc";
3310 power-domains = <&rpmhpd RPMHPD_MMCX>;
3311 required-opps = <&rpmhpd_opp_low_svs>;
3312 #clock-cells = <1>;
3313 #reset-cells = <1>;
3314 #power-domain-cells = <1>;
3318 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci";
3321 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
3325 clock-names = "camnoc_axi",
3328 pinctrl-0 = <&cci0_0_default &cci0_1_default>;
3329 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
3330 pinctrl-names = "default", "sleep";
3332 #address-cells = <1>;
3333 #size-cells = <0>;
3335 cci0_i2c0: i2c-bus@0 {
3337 clock-frequency = <1000000>;
3338 #address-cells = <1>;
3339 #size-cells = <0>;
3342 cci0_i2c1: i2c-bus@1 {
3344 clock-frequency = <1000000>;
3345 #address-cells = <1>;
3346 #size-cells = <0>;
3351 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci";
3354 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
3358 clock-names = "camnoc_axi",
3361 pinctrl-0 = <&cci1_0_default>;
3362 pinctrl-1 = <&cci1_0_sleep>;
3363 pinctrl-names = "default", "sleep";
3365 #address-cells = <1>;
3366 #size-cells = <0>;
3368 cci1_i2c0: i2c-bus@0 {
3370 clock-frequency = <1000000>;
3371 #address-cells = <1>;
3372 #size-cells = <0>;
3377 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci";
3380 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
3384 clock-names = "camnoc_axi",
3387 pinctrl-0 = <&cci2_0_default &cci2_1_default>;
3388 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>;
3389 pinctrl-names = "default", "sleep";
3391 #address-cells = <1>;
3392 #size-cells = <0>;
3394 cci2_i2c0: i2c-bus@0 {
3396 clock-frequency = <1000000>;
3397 #address-cells = <1>;
3398 #size-cells = <0>;
3401 cci2_i2c1: i2c-bus@1 {
3403 clock-frequency = <1000000>;
3404 #address-cells = <1>;
3405 #size-cells = <0>;
3409 camcc: clock-controller@ade0000 {
3410 compatible = "qcom,sm8550-camcc";
3416 power-domains = <&rpmhpd SM8550_MMCX>;
3417 required-opps = <&rpmhpd_opp_low_svs>;
3418 #clock-cells = <1>;
3419 #reset-cells = <1>;
3420 #power-domain-cells = <1>;
3423 mdss: display-subsystem@ae00000 {
3424 compatible = "qcom,sm8550-mdss";
3426 reg-names = "mdss";
3429 interrupt-controller;
3430 #interrupt-cells = <1>;
3439 power-domains = <&dispcc MDSS_GDSC>;
3445 interconnect-names = "mdp0-mem", "cpu-cfg";
3449 #address-cells = <2>;
3450 #size-cells = <2>;
3455 mdss_mdp: display-controller@ae01000 {
3456 compatible = "qcom,sm8550-dpu";
3459 reg-names = "mdp", "vbif";
3461 interrupt-parent = <&mdss>;
3470 clock-names = "bus",
3477 power-domains = <&rpmhpd RPMHPD_MMCX>;
3479 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3480 assigned-clock-rates = <19200000>;
3482 operating-points-v2 = <&mdp_opp_table>;
3485 #address-cells = <1>;
3486 #size-cells = <0>;
3491 remote-endpoint = <&mdss_dsi0_in>;
3498 remote-endpoint = <&mdss_dsi1_in>;
3505 remote-endpoint = <&mdss_dp0_in>;
3510 mdp_opp_table: opp-table {
3511 compatible = "operating-points-v2";
3513 opp-200000000 {
3514 opp-hz = /bits/ 64 <200000000>;
3515 required-opps = <&rpmhpd_opp_low_svs>;
3518 opp-325000000 {
3519 opp-hz = /bits/ 64 <325000000>;
3520 required-opps = <&rpmhpd_opp_svs>;
3523 opp-375000000 {
3524 opp-hz = /bits/ 64 <375000000>;
3525 required-opps = <&rpmhpd_opp_svs_l1>;
3528 opp-514000000 {
3529 opp-hz = /bits/ 64 <514000000>;
3530 required-opps = <&rpmhpd_opp_nom>;
3535 mdss_dp0: displayport-controller@ae90000 {
3536 compatible = "qcom,sm8550-dp", "qcom,sm8350-dp";
3542 interrupt-parent = <&mdss>;
3549 clock-names = "core_iface",
3555 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
3557 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3561 phy-names = "dp";
3563 #sound-dai-cells = <0>;
3565 operating-points-v2 = <&dp_opp_table>;
3566 power-domains = <&rpmhpd RPMHPD_MMCX>;
3571 #address-cells = <1>;
3572 #size-cells = <0>;
3577 remote-endpoint = <&dpu_intf0_out>;
3584 remote-endpoint = <&usb_dp_qmpphy_dp_in>;
3589 dp_opp_table: opp-table {
3590 compatible = "operating-points-v2";
3592 opp-162000000 {
3593 opp-hz = /bits/ 64 <162000000>;
3594 required-opps = <&rpmhpd_opp_low_svs_d1>;
3597 opp-270000000 {
3598 opp-hz = /bits/ 64 <270000000>;
3599 required-opps = <&rpmhpd_opp_low_svs>;
3602 opp-540000000 {
3603 opp-hz = /bits/ 64 <540000000>;
3604 required-opps = <&rpmhpd_opp_svs_l1>;
3607 opp-810000000 {
3608 opp-hz = /bits/ 64 <810000000>;
3609 required-opps = <&rpmhpd_opp_nom>;
3615 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3617 reg-names = "dsi_ctrl";
3619 interrupt-parent = <&mdss>;
3628 clock-names = "byte",
3635 power-domains = <&rpmhpd RPMHPD_MMCX>;
3637 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
3639 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
3642 operating-points-v2 = <&mdss_dsi_opp_table>;
3645 phy-names = "dsi";
3647 #address-cells = <1>;
3648 #size-cells = <0>;
3653 #address-cells = <1>;
3654 #size-cells = <0>;
3659 remote-endpoint = <&dpu_intf1_out>;
3670 mdss_dsi_opp_table: opp-table {
3671 compatible = "operating-points-v2";
3673 opp-187500000 {
3674 opp-hz = /bits/ 64 <187500000>;
3675 required-opps = <&rpmhpd_opp_low_svs>;
3678 opp-300000000 {
3679 opp-hz = /bits/ 64 <300000000>;
3680 required-opps = <&rpmhpd_opp_svs>;
3683 opp-358000000 {
3684 opp-hz = /bits/ 64 <358000000>;
3685 required-opps = <&rpmhpd_opp_svs_l1>;
3691 compatible = "qcom,sm8550-dsi-phy-4nm";
3695 reg-names = "dsi_phy",
3701 clock-names = "iface", "ref";
3703 #clock-cells = <1>;
3704 #phy-cells = <0>;
3710 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3712 reg-names = "dsi_ctrl";
3714 interrupt-parent = <&mdss>;
3723 clock-names = "byte",
3730 power-domains = <&rpmhpd RPMHPD_MMCX>;
3732 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
3734 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
3737 operating-points-v2 = <&mdss_dsi_opp_table>;
3740 phy-names = "dsi";
3742 #address-cells = <1>;
3743 #size-cells = <0>;
3748 #address-cells = <1>;
3749 #size-cells = <0>;
3754 remote-endpoint = <&dpu_intf2_out>;
3767 compatible = "qcom,sm8550-dsi-phy-4nm";
3771 reg-names = "dsi_phy",
3777 clock-names = "iface", "ref";
3779 #clock-cells = <1>;
3780 #phy-cells = <0>;
3786 dispcc: clock-controller@af00000 {
3787 compatible = "qcom,sm8550-dispcc";
3805 power-domains = <&rpmhpd RPMHPD_MMCX>;
3806 required-opps = <&rpmhpd_opp_low_svs>;
3807 #clock-cells = <1>;
3808 #reset-cells = <1>;
3809 #power-domain-cells = <1>;
3813 compatible = "qcom,sm8550-snps-eusb2-phy";
3815 #phy-cells = <0>;
3818 clock-names = "ref";
3826 compatible = "qcom,sm8550-qmp-usb3-dp-phy";
3833 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3835 power-domains = <&gcc USB3_PHY_GDSC>;
3839 reset-names = "phy", "common";
3841 #clock-cells = <1>;
3842 #phy-cells = <1>;
3844 orientation-switch;
3849 #address-cells = <1>;
3850 #size-cells = <0>;
3863 remote-endpoint = <&usb_1_dwc3_ss>;
3871 remote-endpoint = <&mdss_dp0_out>;
3878 compatible = "qcom,sm8550-dwc3", "qcom,dwc3";
3880 #address-cells = <2>;
3881 #size-cells = <2>;
3890 clock-names = "cfg_noc",
3897 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3899 assigned-clock-rates = <19200000>, <200000000>;
3901 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3906 interrupt-names = "pwr_event",
3912 power-domains = <&gcc USB30_PRIM_GDSC>;
3913 required-opps = <&rpmhpd_opp_nom>;
3921 interconnect-names = "usb-ddr", "apps-usb";
3932 phy-names = "usb2-phy", "usb3-phy";
3933 snps,hird-threshold = /bits/ 8 <0x0>;
3934 snps,usb2-gadget-lpm-disable;
3937 snps,dis-u1-entry-quirk;
3938 snps,dis-u2-entry-quirk;
3939 snps,is-utmi-l1-suspend;
3941 snps,usb2-lpm-disable;
3942 snps,has-lpm-erratum;
3943 tx-fifo-resize;
3944 dma-coherent;
3945 usb-role-switch;
3948 #address-cells = <1>;
3949 #size-cells = <0>;
3962 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
3969 pdc: interrupt-controller@b220000 {
3970 compatible = "qcom,sm8550-pdc", "qcom,pdc";
3972 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
3975 #interrupt-cells = <2>;
3976 interrupt-parent = <&intc>;
3977 interrupt-controller;
3980 tsens0: thermal-sensor@c271000 {
3981 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
3987 interrupt-names = "uplow", "critical";
3988 #thermal-sensor-cells = <1>;
3991 tsens1: thermal-sensor@c272000 {
3992 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
3998 interrupt-names = "uplow", "critical";
3999 #thermal-sensor-cells = <1>;
4002 tsens2: thermal-sensor@c273000 {
4003 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
4009 interrupt-names = "uplow", "critical";
4010 #thermal-sensor-cells = <1>;
4013 aoss_qmp: power-management@c300000 {
4014 compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp";
4016 interrupt-parent = <&ipcc>;
4017 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
4021 #clock-cells = <0>;
4025 compatible = "qcom,rpmh-stats";
4030 compatible = "qcom,spmi-pmic-arb";
4036 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4037 interrupt-names = "periph_irq";
4038 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4041 qcom,bus-id = <0>;
4042 #address-cells = <2>;
4043 #size-cells = <0>;
4044 interrupt-controller;
4045 #interrupt-cells = <4>;
4049 compatible = "qcom,sm8550-tlmm";
4052 gpio-controller;
4053 #gpio-cells = <2>;
4054 interrupt-controller;
4055 #interrupt-cells = <2>;
4056 gpio-ranges = <&tlmm 0 0 211>;
4057 wakeup-parent = <&pdc>;
4059 cci0_0_default: cci0-0-default-state {
4060 sda-pins {
4063 drive-strength = <2>;
4064 bias-pull-up = <2200>;
4067 scl-pins {
4070 drive-strength = <2>;
4071 bias-pull-up = <2200>;
4075 cci0_0_sleep: cci0-0-sleep-state {
4076 sda-pins {
4079 drive-strength = <2>;
4080 bias-pull-down;
4083 scl-pins {
4086 drive-strength = <2>;
4087 bias-pull-down;
4091 cci0_1_default: cci0-1-default-state {
4092 sda-pins {
4095 drive-strength = <2>;
4096 bias-pull-up = <2200>;
4099 scl-pins {
4102 drive-strength = <2>;
4103 bias-pull-up = <2200>;
4107 cci0_1_sleep: cci0-1-sleep-state {
4108 sda-pins {
4111 drive-strength = <2>;
4112 bias-pull-down;
4115 scl-pins {
4118 drive-strength = <2>;
4119 bias-pull-down;
4123 cci1_0_default: cci1-0-default-state {
4124 sda-pins {
4127 drive-strength = <2>;
4128 bias-pull-up = <2200>;
4131 scl-pins {
4134 drive-strength = <2>;
4135 bias-pull-up = <2200>;
4139 cci1_0_sleep: cci1-0-sleep-state {
4140 sda-pins {
4143 drive-strength = <2>;
4144 bias-pull-down;
4147 scl-pins {
4150 drive-strength = <2>;
4151 bias-pull-down;
4155 cci2_0_default: cci2-0-default-state {
4156 sda-pins {
4159 drive-strength = <2>;
4160 bias-pull-up = <2200>;
4163 scl-pins {
4166 drive-strength = <2>;
4167 bias-pull-up = <2200>;
4171 cci2_0_sleep: cci2-0-sleep-state {
4172 sda-pins {
4175 drive-strength = <2>;
4176 bias-pull-down;
4179 scl-pins {
4182 drive-strength = <2>;
4183 bias-pull-down;
4187 cci2_1_default: cci2-1-default-state {
4188 sda-pins {
4191 drive-strength = <2>;
4192 bias-pull-up = <2200>;
4195 scl-pins {
4198 drive-strength = <2>;
4199 bias-pull-up = <2200>;
4203 cci2_1_sleep: cci2-1-sleep-state {
4204 sda-pins {
4207 drive-strength = <2>;
4208 bias-pull-down;
4211 scl-pins {
4214 drive-strength = <2>;
4215 bias-pull-down;
4219 hub_i2c0_data_clk: hub-i2c0-data-clk-state {
4223 drive-strength = <2>;
4224 bias-pull-up;
4227 hub_i2c1_data_clk: hub-i2c1-data-clk-state {
4231 drive-strength = <2>;
4232 bias-pull-up;
4235 hub_i2c2_data_clk: hub-i2c2-data-clk-state {
4239 drive-strength = <2>;
4240 bias-pull-up;
4243 hub_i2c3_data_clk: hub-i2c3-data-clk-state {
4247 drive-strength = <2>;
4248 bias-pull-up;
4251 hub_i2c4_data_clk: hub-i2c4-data-clk-state {
4255 drive-strength = <2>;
4256 bias-pull-up;
4259 hub_i2c5_data_clk: hub-i2c5-data-clk-state {
4263 drive-strength = <2>;
4264 bias-pull-up;
4267 hub_i2c6_data_clk: hub-i2c6-data-clk-state {
4271 drive-strength = <2>;
4272 bias-pull-up;
4275 hub_i2c7_data_clk: hub-i2c7-data-clk-state {
4279 drive-strength = <2>;
4280 bias-pull-up;
4283 hub_i2c8_data_clk: hub-i2c8-data-clk-state {
4287 drive-strength = <2>;
4288 bias-pull-up;
4291 hub_i2c9_data_clk: hub-i2c9-data-clk-state {
4295 drive-strength = <2>;
4296 bias-pull-up;
4299 pcie0_default_state: pcie0-default-state {
4300 perst-pins {
4303 drive-strength = <2>;
4304 bias-pull-down;
4307 clkreq-pins {
4310 drive-strength = <2>;
4311 bias-pull-up;
4314 wake-pins {
4317 drive-strength = <2>;
4318 bias-pull-up;
4322 pcie1_default_state: pcie1-default-state {
4323 perst-pins {
4326 drive-strength = <2>;
4327 bias-pull-down;
4330 clkreq-pins {
4333 drive-strength = <2>;
4334 bias-pull-up;
4337 wake-pins {
4340 drive-strength = <2>;
4341 bias-pull-up;
4345 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
4349 drive-strength = <2>;
4350 bias-pull-up = <2200>;
4353 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
4357 drive-strength = <2>;
4358 bias-pull-up = <2200>;
4361 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
4365 drive-strength = <2>;
4366 bias-pull-up = <2200>;
4369 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
4373 drive-strength = <2>;
4374 bias-pull-up = <2200>;
4377 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
4381 drive-strength = <2>;
4382 bias-pull-up = <2200>;
4385 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
4389 drive-strength = <2>;
4390 bias-pull-up = <2200>;
4393 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
4397 drive-strength = <2>;
4398 bias-pull-up = <2200>;
4401 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
4402 scl-pins {
4405 drive-strength = <2>;
4406 bias-pull-up = <2200>;
4409 sda-pins {
4412 drive-strength = <2>;
4413 bias-pull-up = <2200>;
4417 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
4421 drive-strength = <2>;
4422 bias-pull-up = <2200>;
4425 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
4429 drive-strength = <2>;
4430 bias-pull-up = <2200>;
4433 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
4437 drive-strength = <2>;
4438 bias-pull-up = <2200>;
4441 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
4445 drive-strength = <2>;
4446 bias-pull-up = <2200>;
4449 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
4453 drive-strength = <2>;
4454 bias-pull-up = <2200>;
4457 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
4461 drive-strength = <2>;
4462 bias-pull-up = <2200>;
4465 qup_spi0_cs: qup-spi0-cs-state {
4468 drive-strength = <6>;
4469 bias-disable;
4472 qup_spi0_data_clk: qup-spi0-data-clk-state {
4476 drive-strength = <6>;
4477 bias-disable;
4480 qup_spi1_cs: qup-spi1-cs-state {
4483 drive-strength = <6>;
4484 bias-disable;
4487 qup_spi1_data_clk: qup-spi1-data-clk-state {
4491 drive-strength = <6>;
4492 bias-disable;
4495 qup_spi2_cs: qup-spi2-cs-state {
4498 drive-strength = <6>;
4499 bias-disable;
4502 qup_spi2_data_clk: qup-spi2-data-clk-state {
4506 drive-strength = <6>;
4507 bias-disable;
4510 qup_spi3_cs: qup-spi3-cs-state {
4513 drive-strength = <6>;
4514 bias-disable;
4517 qup_spi3_data_clk: qup-spi3-data-clk-state {
4521 drive-strength = <6>;
4522 bias-disable;
4525 qup_spi4_cs: qup-spi4-cs-state {
4528 drive-strength = <6>;
4529 bias-disable;
4532 qup_spi4_data_clk: qup-spi4-data-clk-state {
4536 drive-strength = <6>;
4537 bias-disable;
4540 qup_spi5_cs: qup-spi5-cs-state {
4543 drive-strength = <6>;
4544 bias-disable;
4547 qup_spi5_data_clk: qup-spi5-data-clk-state {
4551 drive-strength = <6>;
4552 bias-disable;
4555 qup_spi6_cs: qup-spi6-cs-state {
4558 drive-strength = <6>;
4559 bias-disable;
4562 qup_spi6_data_clk: qup-spi6-data-clk-state {
4566 drive-strength = <6>;
4567 bias-disable;
4570 qup_spi8_cs: qup-spi8-cs-state {
4573 drive-strength = <6>;
4574 bias-disable;
4577 qup_spi8_data_clk: qup-spi8-data-clk-state {
4581 drive-strength = <6>;
4582 bias-disable;
4585 qup_spi9_cs: qup-spi9-cs-state {
4588 drive-strength = <6>;
4589 bias-disable;
4592 qup_spi9_data_clk: qup-spi9-data-clk-state {
4596 drive-strength = <6>;
4597 bias-disable;
4600 qup_spi10_cs: qup-spi10-cs-state {
4603 drive-strength = <6>;
4604 bias-disable;
4607 qup_spi10_data_clk: qup-spi10-data-clk-state {
4611 drive-strength = <6>;
4612 bias-disable;
4615 qup_spi11_cs: qup-spi11-cs-state {
4618 drive-strength = <6>;
4619 bias-disable;
4622 qup_spi11_data_clk: qup-spi11-data-clk-state {
4626 drive-strength = <6>;
4627 bias-disable;
4630 qup_spi12_cs: qup-spi12-cs-state {
4633 drive-strength = <6>;
4634 bias-disable;
4637 qup_spi12_data_clk: qup-spi12-data-clk-state {
4641 drive-strength = <6>;
4642 bias-disable;
4645 qup_spi13_cs: qup-spi13-cs-state {
4648 drive-strength = <6>;
4649 bias-disable;
4652 qup_spi13_data_clk: qup-spi13-data-clk-state {
4656 drive-strength = <6>;
4657 bias-disable;
4660 qup_spi15_cs: qup-spi15-cs-state {
4663 drive-strength = <6>;
4664 bias-disable;
4667 qup_spi15_data_clk: qup-spi15-data-clk-state {
4671 drive-strength = <6>;
4672 bias-disable;
4675 qup_uart7_default: qup-uart7-default-state {
4679 drive-strength = <2>;
4680 bias-disable;
4683 qup_uart14_default: qup-uart14-default-state {
4687 drive-strength = <2>;
4688 bias-pull-up;
4691 qup_uart14_cts_rts: qup-uart14-cts-rts-state {
4695 drive-strength = <2>;
4696 bias-pull-down;
4699 sdc2_sleep: sdc2-sleep-state {
4700 clk-pins {
4702 bias-disable;
4703 drive-strength = <2>;
4706 cmd-pins {
4708 bias-pull-up;
4709 drive-strength = <2>;
4712 data-pins {
4714 bias-pull-up;
4715 drive-strength = <2>;
4719 sdc2_default: sdc2-default-state {
4720 clk-pins {
4722 bias-disable;
4723 drive-strength = <16>;
4726 cmd-pins {
4728 bias-pull-up;
4729 drive-strength = <10>;
4732 data-pins {
4734 bias-pull-up;
4735 drive-strength = <10>;
4741 compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500";
4743 #iommu-cells = <2>;
4744 #global-interrupts = <1>;
4842 dma-coherent;
4845 intc: interrupt-controller@17100000 {
4846 compatible = "arm,gic-v3";
4850 #interrupt-cells = <3>;
4851 interrupt-controller;
4852 #redistributor-regions = <1>;
4853 redistributor-stride = <0 0x40000>;
4855 #address-cells = <2>;
4856 #size-cells = <2>;
4858 gic_its: msi-controller@17140000 {
4859 compatible = "arm,gic-v3-its";
4861 msi-controller;
4862 #msi-cells = <1>;
4867 compatible = "arm,armv7-timer-mem";
4870 #address-cells = <1>;
4871 #size-cells = <1>;
4876 frame-number = <0>;
4883 frame-number = <1>;
4890 frame-number = <2>;
4897 frame-number = <3>;
4904 frame-number = <4>;
4911 frame-number = <5>;
4918 frame-number = <6>;
4926 compatible = "qcom,rpmh-rsc";
4931 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4935 qcom,tcs-offset = <0xd00>;
4936 qcom,drv-id = <2>;
4937 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
4939 power-domains = <&cluster_pd>;
4941 apps_bcm_voter: bcm-voter {
4942 compatible = "qcom,bcm-voter";
4945 rpmhcc: clock-controller {
4946 compatible = "qcom,sm8550-rpmh-clk";
4947 #clock-cells = <1>;
4948 clock-names = "xo";
4952 rpmhpd: power-controller {
4953 compatible = "qcom,sm8550-rpmhpd";
4954 #power-domain-cells = <1>;
4955 operating-points-v2 = <&rpmhpd_opp_table>;
4957 rpmhpd_opp_table: opp-table {
4958 compatible = "operating-points-v2";
4960 rpmhpd_opp_ret: opp-16 {
4961 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4964 rpmhpd_opp_min_svs: opp-48 {
4965 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4968 rpmhpd_opp_low_svs_d2: opp-52 {
4969 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
4972 rpmhpd_opp_low_svs_d1: opp-56 {
4973 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
4976 rpmhpd_opp_low_svs_d0: opp-60 {
4977 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
4980 rpmhpd_opp_low_svs: opp-64 {
4981 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4984 rpmhpd_opp_low_svs_l1: opp-80 {
4985 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
4988 rpmhpd_opp_svs: opp-128 {
4989 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4992 rpmhpd_opp_svs_l0: opp-144 {
4993 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
4996 rpmhpd_opp_svs_l1: opp-192 {
4997 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5000 rpmhpd_opp_nom: opp-256 {
5001 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5004 rpmhpd_opp_nom_l1: opp-320 {
5005 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5008 rpmhpd_opp_nom_l2: opp-336 {
5009 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5012 rpmhpd_opp_turbo: opp-384 {
5013 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5016 rpmhpd_opp_turbo_l1: opp-416 {
5017 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5024 compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss";
5028 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
5030 clock-names = "xo", "alternate";
5034 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
5035 #freq-domain-cells = <1>;
5036 #clock-cells = <1>;
5040 compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
5046 operating-points-v2 = <&llcc_bwmon_opp_table>;
5048 llcc_bwmon_opp_table: opp-table {
5049 compatible = "operating-points-v2";
5051 opp-0 {
5052 opp-peak-kBps = <2086000>;
5055 opp-1 {
5056 opp-peak-kBps = <2929000>;
5059 opp-2 {
5060 opp-peak-kBps = <5931000>;
5063 opp-3 {
5064 opp-peak-kBps = <6515000>;
5067 opp-4 {
5068 opp-peak-kBps = <7980000>;
5071 opp-5 {
5072 opp-peak-kBps = <10437000>;
5075 opp-6 {
5076 opp-peak-kBps = <12157000>;
5079 opp-7 {
5080 opp-peak-kBps = <14060000>;
5083 opp-8 {
5084 opp-peak-kBps = <16113000>;
5090 compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon";
5096 operating-points-v2 = <&cpu_bwmon_opp_table>;
5098 cpu_bwmon_opp_table: opp-table {
5099 compatible = "operating-points-v2";
5101 opp-0 {
5102 opp-peak-kBps = <4577000>;
5105 opp-1 {
5106 opp-peak-kBps = <7110000>;
5109 opp-2 {
5110 opp-peak-kBps = <9155000>;
5113 opp-3 {
5114 opp-peak-kBps = <12298000>;
5117 opp-4 {
5118 opp-peak-kBps = <14236000>;
5121 opp-5 {
5122 opp-peak-kBps = <16265000>;
5128 compatible = "qcom,sm8550-gem-noc";
5130 #interconnect-cells = <2>;
5131 qcom,bcm-voters = <&apps_bcm_voter>;
5134 system-cache-controller@25000000 {
5135 compatible = "qcom,sm8550-llcc";
5142 reg-names = "llcc0_base",
5152 compatible = "qcom,sm8550-nsp-noc";
5154 #interconnect-cells = <2>;
5155 qcom,bcm-voters = <&apps_bcm_voter>;
5159 compatible = "qcom,sm8550-cdsp-pas";
5162 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
5167 interrupt-names = "wdog", "fatal", "ready",
5168 "handover", "stop-ack";
5171 clock-names = "xo";
5173 power-domains = <&rpmhpd RPMHPD_CX>,
5176 power-domain-names = "cx", "mxc", "nsp";
5181 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>;
5185 qcom,smem-states = <&smp2p_cdsp_out 0>;
5186 qcom,smem-state-names = "stop";
5190 glink-edge {
5191 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
5198 qcom,remote-pid = <5>;
5202 qcom,glink-channels = "fastrpcglink-apps-dsp";
5204 qcom,non-secure-domain;
5205 #address-cells = <1>;
5206 #size-cells = <0>;
5208 compute-cb@1 {
5209 compatible = "qcom,fastrpc-compute-cb";
5214 dma-coherent;
5217 compute-cb@2 {
5218 compatible = "qcom,fastrpc-compute-cb";
5223 dma-coherent;
5226 compute-cb@3 {
5227 compatible = "qcom,fastrpc-compute-cb";
5232 dma-coherent;
5235 compute-cb@4 {
5236 compatible = "qcom,fastrpc-compute-cb";
5241 dma-coherent;
5244 compute-cb@5 {
5245 compatible = "qcom,fastrpc-compute-cb";
5250 dma-coherent;
5253 compute-cb@6 {
5254 compatible = "qcom,fastrpc-compute-cb";
5259 dma-coherent;
5262 compute-cb@7 {
5263 compatible = "qcom,fastrpc-compute-cb";
5268 dma-coherent;
5271 compute-cb@8 {
5272 compatible = "qcom,fastrpc-compute-cb";
5277 dma-coherent;
5286 thermal-zones {
5287 aoss0-thermal {
5288 thermal-sensors = <&tsens0 0>;
5291 thermal-engine-config {
5297 reset-mon-config {
5305 cpuss0-thermal {
5306 thermal-sensors = <&tsens0 1>;
5309 thermal-engine-config {
5315 reset-mon-config {
5323 cpuss1-thermal {
5324 thermal-sensors = <&tsens0 2>;
5327 thermal-engine-config {
5333 reset-mon-config {
5341 cpuss2-thermal {
5342 thermal-sensors = <&tsens0 3>;
5345 thermal-engine-config {
5351 reset-mon-config {
5359 cpuss3-thermal {
5360 thermal-sensors = <&tsens0 4>;
5363 thermal-engine-config {
5369 reset-mon-config {
5377 cpu3-top-thermal {
5378 thermal-sensors = <&tsens0 5>;
5381 cpu3_top_alert0: trip-point0 {
5387 cpu3_top_alert1: trip-point1 {
5393 cpu3_top_crit: cpu-critical {
5401 cpu3-bottom-thermal {
5402 thermal-sensors = <&tsens0 6>;
5405 cpu3_bottom_alert0: trip-point0 {
5411 cpu3_bottom_alert1: trip-point1 {
5417 cpu3_bottom_crit: cpu-critical {
5425 cpu4-top-thermal {
5426 thermal-sensors = <&tsens0 7>;
5429 cpu4_top_alert0: trip-point0 {
5435 cpu4_top_alert1: trip-point1 {
5441 cpu4_top_crit: cpu-critical {
5449 cpu4-bottom-thermal {
5450 thermal-sensors = <&tsens0 8>;
5453 cpu4_bottom_alert0: trip-point0 {
5459 cpu4_bottom_alert1: trip-point1 {
5465 cpu4_bottom_crit: cpu-critical {
5473 cpu5-top-thermal {
5474 thermal-sensors = <&tsens0 9>;
5477 cpu5_top_alert0: trip-point0 {
5483 cpu5_top_alert1: trip-point1 {
5489 cpu5_top_crit: cpu-critical {
5497 cpu5-bottom-thermal {
5498 thermal-sensors = <&tsens0 10>;
5501 cpu5_bottom_alert0: trip-point0 {
5507 cpu5_bottom_alert1: trip-point1 {
5513 cpu5_bottom_crit: cpu-critical {
5521 cpu6-top-thermal {
5522 thermal-sensors = <&tsens0 11>;
5525 cpu6_top_alert0: trip-point0 {
5531 cpu6_top_alert1: trip-point1 {
5537 cpu6_top_crit: cpu-critical {
5545 cpu6-bottom-thermal {
5546 thermal-sensors = <&tsens0 12>;
5549 cpu6_bottom_alert0: trip-point0 {
5555 cpu6_bottom_alert1: trip-point1 {
5561 cpu6_bottom_crit: cpu-critical {
5569 cpu7-top-thermal {
5570 thermal-sensors = <&tsens0 13>;
5573 cpu7_top_alert0: trip-point0 {
5579 cpu7_top_alert1: trip-point1 {
5585 cpu7_top_crit: cpu-critical {
5593 cpu7-middle-thermal {
5594 thermal-sensors = <&tsens0 14>;
5597 cpu7_middle_alert0: trip-point0 {
5603 cpu7_middle_alert1: trip-point1 {
5609 cpu7_middle_crit: cpu-critical {
5617 cpu7-bottom-thermal {
5618 thermal-sensors = <&tsens0 15>;
5621 cpu7_bottom_alert0: trip-point0 {
5627 cpu7_bottom_alert1: trip-point1 {
5633 cpu7_bottom_crit: cpu-critical {
5641 aoss1-thermal {
5642 thermal-sensors = <&tsens1 0>;
5645 thermal-engine-config {
5651 reset-mon-config {
5659 cpu0-thermal {
5660 thermal-sensors = <&tsens1 1>;
5663 cpu0_alert0: trip-point0 {
5669 cpu0_alert1: trip-point1 {
5675 cpu0_crit: cpu-critical {
5683 cpu1-thermal {
5684 thermal-sensors = <&tsens1 2>;
5687 cpu1_alert0: trip-point0 {
5693 cpu1_alert1: trip-point1 {
5699 cpu1_crit: cpu-critical {
5707 cpu2-thermal {
5708 thermal-sensors = <&tsens1 3>;
5711 cpu2_alert0: trip-point0 {
5717 cpu2_alert1: trip-point1 {
5723 cpu2_crit: cpu-critical {
5731 cdsp0-thermal {
5732 polling-delay-passive = <10>;
5734 thermal-sensors = <&tsens2 4>;
5737 thermal-engine-config {
5743 thermal-hal-config {
5749 reset-mon-config {
5755 cdsp0_junction_config: junction-config {
5763 cdsp1-thermal {
5764 polling-delay-passive = <10>;
5766 thermal-sensors = <&tsens2 5>;
5769 thermal-engine-config {
5775 thermal-hal-config {
5781 reset-mon-config {
5787 cdsp1_junction_config: junction-config {
5795 cdsp2-thermal {
5796 polling-delay-passive = <10>;
5798 thermal-sensors = <&tsens2 6>;
5801 thermal-engine-config {
5807 thermal-hal-config {
5813 reset-mon-config {
5819 cdsp2_junction_config: junction-config {
5827 cdsp3-thermal {
5828 polling-delay-passive = <10>;
5830 thermal-sensors = <&tsens2 7>;
5833 thermal-engine-config {
5839 thermal-hal-config {
5845 reset-mon-config {
5851 cdsp3_junction_config: junction-config {
5859 video-thermal {
5860 thermal-sensors = <&tsens1 8>;
5863 thermal-engine-config {
5869 reset-mon-config {
5877 mem-thermal {
5878 polling-delay-passive = <10>;
5880 thermal-sensors = <&tsens1 9>;
5883 thermal-engine-config {
5889 ddr_config0: ddr0-config {
5895 reset-mon-config {
5903 modem0-thermal {
5904 thermal-sensors = <&tsens1 10>;
5907 thermal-engine-config {
5913 mdmss0_config0: mdmss0-config0 {
5919 mdmss0_config1: mdmss0-config1 {
5925 reset-mon-config {
5933 modem1-thermal {
5934 thermal-sensors = <&tsens1 11>;
5937 thermal-engine-config {
5943 mdmss1_config0: mdmss1-config0 {
5949 mdmss1_config1: mdmss1-config1 {
5955 reset-mon-config {
5963 modem2-thermal {
5964 thermal-sensors = <&tsens1 12>;
5967 thermal-engine-config {
5973 mdmss2_config0: mdmss2-config0 {
5979 mdmss2_config1: mdmss2-config1 {
5985 reset-mon-config {
5993 modem3-thermal {
5994 thermal-sensors = <&tsens1 13>;
5997 thermal-engine-config {
6003 mdmss3_config0: mdmss3-config0 {
6009 mdmss3_config1: mdmss3-config1 {
6015 reset-mon-config {
6023 camera0-thermal {
6024 thermal-sensors = <&tsens1 14>;
6027 thermal-engine-config {
6033 reset-mon-config {
6041 camera1-thermal {
6042 thermal-sensors = <&tsens1 15>;
6045 thermal-engine-config {
6051 reset-mon-config {
6059 aoss2-thermal {
6060 thermal-sensors = <&tsens2 0>;
6063 thermal-engine-config {
6069 reset-mon-config {
6077 gpuss-0-thermal {
6078 polling-delay-passive = <10>;
6080 thermal-sensors = <&tsens2 1>;
6082 cooling-maps {
6085 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6090 gpu0_alert0: trip-point0 {
6096 trip-point1 {
6102 trip-point2 {
6110 gpuss-1-thermal {
6111 polling-delay-passive = <10>;
6113 thermal-sensors = <&tsens2 2>;
6115 cooling-maps {
6118 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6123 gpu1_alert0: trip-point0 {
6129 trip-point1 {
6135 trip-point2 {
6143 gpuss-2-thermal {
6144 polling-delay-passive = <10>;
6146 thermal-sensors = <&tsens2 3>;
6148 cooling-maps {
6151 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6156 gpu2_alert0: trip-point0 {
6162 trip-point1 {
6168 trip-point2 {
6176 gpuss-3-thermal {
6177 polling-delay-passive = <10>;
6179 thermal-sensors = <&tsens2 4>;
6181 cooling-maps {
6184 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6189 gpu3_alert0: trip-point0 {
6195 trip-point1 {
6201 trip-point2 {
6209 gpuss-4-thermal {
6210 polling-delay-passive = <10>;
6212 thermal-sensors = <&tsens2 5>;
6214 cooling-maps {
6217 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6222 gpu4_alert0: trip-point0 {
6228 trip-point1 {
6234 trip-point2 {
6242 gpuss-5-thermal {
6243 polling-delay-passive = <10>;
6245 thermal-sensors = <&tsens2 6>;
6247 cooling-maps {
6250 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6255 gpu5_alert0: trip-point0 {
6261 trip-point1 {
6267 trip-point2 {
6275 gpuss-6-thermal {
6276 polling-delay-passive = <10>;
6278 thermal-sensors = <&tsens2 7>;
6280 cooling-maps {
6283 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6288 gpu6_alert0: trip-point0 {
6294 trip-point1 {
6300 trip-point2 {
6308 gpuss-7-thermal {
6309 polling-delay-passive = <10>;
6311 thermal-sensors = <&tsens2 8>;
6313 cooling-maps {
6316 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6321 gpu7_alert0: trip-point0 {
6327 trip-point1 {
6333 trip-point2 {
6343 compatible = "arm,armv8-timer";