Lines Matching +full:tcsr +full:- +full:mutex
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
8 #include <dt-bindings/clock/qcom,sm8550-camcc.h>
9 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
10 #include <dt-bindings/clock/qcom,sm8550-gpucc.h>
11 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
12 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/interconnect/qcom,icc.h>
18 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
19 #include <dt-bindings/mailbox/qcom-ipcc.h>
20 #include <dt-bindings/power/qcom-rpmpd.h>
21 #include <dt-bindings/power/qcom,rpmhpd.h>
22 #include <dt-bindings/soc/qcom,gpr.h>
23 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
24 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
25 #include <dt-bindings/phy/phy-qcom-qmp.h>
26 #include <dt-bindings/thermal/thermal.h>
29 interrupt-parent = <&intc>;
31 #address-cells = <2>;
32 #size-cells = <2>;
37 xo_board: xo-board {
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
42 sleep_clk: sleep-clk {
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
47 bi_tcxo_div2: bi-tcxo-div2-clk {
48 #clock-cells = <0>;
49 compatible = "fixed-factor-clock";
51 clock-mult = <1>;
52 clock-div = <2>;
55 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
56 #clock-cells = <0>;
57 compatible = "fixed-factor-clock";
59 clock-mult = <1>;
60 clock-div = <2>;
65 #address-cells = <2>;
66 #size-cells = <0>;
70 compatible = "arm,cortex-a510";
73 enable-method = "psci";
74 next-level-cache = <&l2_0>;
75 power-domains = <&cpu_pd0>;
76 power-domain-names = "psci";
77 qcom,freq-domain = <&cpufreq_hw 0>;
78 capacity-dmips-mhz = <1024>;
79 dynamic-power-coefficient = <100>;
80 #cooling-cells = <2>;
81 l2_0: l2-cache {
83 cache-level = <2>;
84 cache-unified;
85 next-level-cache = <&l3_0>;
86 l3_0: l3-cache {
88 cache-level = <3>;
89 cache-unified;
96 compatible = "arm,cortex-a510";
99 enable-method = "psci";
100 next-level-cache = <&l2_100>;
101 power-domains = <&cpu_pd1>;
102 power-domain-names = "psci";
103 qcom,freq-domain = <&cpufreq_hw 0>;
104 capacity-dmips-mhz = <1024>;
105 dynamic-power-coefficient = <100>;
106 #cooling-cells = <2>;
107 l2_100: l2-cache {
109 cache-level = <2>;
110 cache-unified;
111 next-level-cache = <&l3_0>;
117 compatible = "arm,cortex-a510";
120 enable-method = "psci";
121 next-level-cache = <&l2_200>;
122 power-domains = <&cpu_pd2>;
123 power-domain-names = "psci";
124 qcom,freq-domain = <&cpufreq_hw 0>;
125 capacity-dmips-mhz = <1024>;
126 dynamic-power-coefficient = <100>;
127 #cooling-cells = <2>;
128 l2_200: l2-cache {
130 cache-level = <2>;
131 cache-unified;
132 next-level-cache = <&l3_0>;
138 compatible = "arm,cortex-a715";
141 enable-method = "psci";
142 next-level-cache = <&l2_300>;
143 power-domains = <&cpu_pd3>;
144 power-domain-names = "psci";
145 qcom,freq-domain = <&cpufreq_hw 1>;
146 capacity-dmips-mhz = <1792>;
147 dynamic-power-coefficient = <270>;
148 #cooling-cells = <2>;
149 l2_300: l2-cache {
151 cache-level = <2>;
152 cache-unified;
153 next-level-cache = <&l3_0>;
159 compatible = "arm,cortex-a715";
162 enable-method = "psci";
163 next-level-cache = <&l2_400>;
164 power-domains = <&cpu_pd4>;
165 power-domain-names = "psci";
166 qcom,freq-domain = <&cpufreq_hw 1>;
167 capacity-dmips-mhz = <1792>;
168 dynamic-power-coefficient = <270>;
169 #cooling-cells = <2>;
170 l2_400: l2-cache {
172 cache-level = <2>;
173 cache-unified;
174 next-level-cache = <&l3_0>;
180 compatible = "arm,cortex-a710";
183 enable-method = "psci";
184 next-level-cache = <&l2_500>;
185 power-domains = <&cpu_pd5>;
186 power-domain-names = "psci";
187 qcom,freq-domain = <&cpufreq_hw 1>;
188 capacity-dmips-mhz = <1792>;
189 dynamic-power-coefficient = <270>;
190 #cooling-cells = <2>;
191 l2_500: l2-cache {
193 cache-level = <2>;
194 cache-unified;
195 next-level-cache = <&l3_0>;
201 compatible = "arm,cortex-a710";
204 enable-method = "psci";
205 next-level-cache = <&l2_600>;
206 power-domains = <&cpu_pd6>;
207 power-domain-names = "psci";
208 qcom,freq-domain = <&cpufreq_hw 1>;
209 capacity-dmips-mhz = <1792>;
210 dynamic-power-coefficient = <270>;
211 #cooling-cells = <2>;
212 l2_600: l2-cache {
214 cache-level = <2>;
215 cache-unified;
216 next-level-cache = <&l3_0>;
222 compatible = "arm,cortex-x3";
225 enable-method = "psci";
226 next-level-cache = <&l2_700>;
227 power-domains = <&cpu_pd7>;
228 power-domain-names = "psci";
229 qcom,freq-domain = <&cpufreq_hw 2>;
230 capacity-dmips-mhz = <1894>;
231 dynamic-power-coefficient = <588>;
232 #cooling-cells = <2>;
233 l2_700: l2-cache {
235 cache-level = <2>;
236 cache-unified;
237 next-level-cache = <&l3_0>;
241 cpu-map {
277 idle-states {
278 entry-method = "psci";
280 little_cpu_sleep_0: cpu-sleep-0-0 {
281 compatible = "arm,idle-state";
282 idle-state-name = "silver-rail-power-collapse";
283 arm,psci-suspend-param = <0x40000004>;
284 entry-latency-us = <550>;
285 exit-latency-us = <750>;
286 min-residency-us = <6700>;
287 local-timer-stop;
290 big_cpu_sleep_0: cpu-sleep-1-0 {
291 compatible = "arm,idle-state";
292 idle-state-name = "gold-rail-power-collapse";
293 arm,psci-suspend-param = <0x40000004>;
294 entry-latency-us = <600>;
295 exit-latency-us = <1300>;
296 min-residency-us = <8136>;
297 local-timer-stop;
300 prime_cpu_sleep_0: cpu-sleep-2-0 {
301 compatible = "arm,idle-state";
302 idle-state-name = "goldplus-rail-power-collapse";
303 arm,psci-suspend-param = <0x40000004>;
304 entry-latency-us = <500>;
305 exit-latency-us = <1350>;
306 min-residency-us = <7480>;
307 local-timer-stop;
311 domain-idle-states {
312 cluster_sleep_0: cluster-sleep-0 {
313 compatible = "domain-idle-state";
314 arm,psci-suspend-param = <0x41000044>;
315 entry-latency-us = <750>;
316 exit-latency-us = <2350>;
317 min-residency-us = <9144>;
320 cluster_sleep_1: cluster-sleep-1 {
321 compatible = "domain-idle-state";
322 arm,psci-suspend-param = <0x4100c344>;
323 entry-latency-us = <2800>;
324 exit-latency-us = <4400>;
325 min-residency-us = <10150>;
332 compatible = "qcom,scm-sm8550", "qcom,scm";
333 qcom,dload-mode = <&tcsr 0x19000>;
338 clk_virt: interconnect-0 {
339 compatible = "qcom,sm8550-clk-virt";
340 #interconnect-cells = <2>;
341 qcom,bcm-voters = <&apps_bcm_voter>;
344 mc_virt: interconnect-1 {
345 compatible = "qcom,sm8550-mc-virt";
346 #interconnect-cells = <2>;
347 qcom,bcm-voters = <&apps_bcm_voter>;
356 pmu-a510 {
357 compatible = "arm,cortex-a510-pmu";
361 pmu-a710 {
362 compatible = "arm,cortex-a710-pmu";
366 pmu-a715 {
367 compatible = "arm,cortex-a715-pmu";
371 pmu-x3 {
372 compatible = "arm,cortex-x3-pmu";
377 compatible = "arm,psci-1.0";
380 cpu_pd0: power-domain-cpu0 {
381 #power-domain-cells = <0>;
382 power-domains = <&cluster_pd>;
383 domain-idle-states = <&little_cpu_sleep_0>;
386 cpu_pd1: power-domain-cpu1 {
387 #power-domain-cells = <0>;
388 power-domains = <&cluster_pd>;
389 domain-idle-states = <&little_cpu_sleep_0>;
392 cpu_pd2: power-domain-cpu2 {
393 #power-domain-cells = <0>;
394 power-domains = <&cluster_pd>;
395 domain-idle-states = <&little_cpu_sleep_0>;
398 cpu_pd3: power-domain-cpu3 {
399 #power-domain-cells = <0>;
400 power-domains = <&cluster_pd>;
401 domain-idle-states = <&big_cpu_sleep_0>;
404 cpu_pd4: power-domain-cpu4 {
405 #power-domain-cells = <0>;
406 power-domains = <&cluster_pd>;
407 domain-idle-states = <&big_cpu_sleep_0>;
410 cpu_pd5: power-domain-cpu5 {
411 #power-domain-cells = <0>;
412 power-domains = <&cluster_pd>;
413 domain-idle-states = <&big_cpu_sleep_0>;
416 cpu_pd6: power-domain-cpu6 {
417 #power-domain-cells = <0>;
418 power-domains = <&cluster_pd>;
419 domain-idle-states = <&big_cpu_sleep_0>;
422 cpu_pd7: power-domain-cpu7 {
423 #power-domain-cells = <0>;
424 power-domains = <&cluster_pd>;
425 domain-idle-states = <&prime_cpu_sleep_0>;
428 cluster_pd: power-domain-cluster {
429 #power-domain-cells = <0>;
430 domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>;
434 reserved_memory: reserved-memory {
435 #address-cells = <2>;
436 #size-cells = <2>;
439 hyp_mem: hyp-region@80000000 {
441 no-map;
444 cpusys_vm_mem: cpusys-vm-region@80a00000 {
446 no-map;
449 hyp_tags_mem: hyp-tags-region@80e00000 {
451 no-map;
454 xbl_sc_mem: xbl-sc-region@d8100000 {
456 no-map;
459 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 {
461 no-map;
465 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 {
467 no-map;
470 aop_cmd_db_mem: aop-cmd-db-region@81c60000 {
471 compatible = "qcom,cmd-db";
473 no-map;
477 aop_config_merged_mem: aop-config-merged-region@81c80000 {
479 no-map;
487 no-map;
490 adsp_mhi_mem: adsp-mhi-region@81f00000 {
492 no-map;
495 global_sync_mem: global-sync-region@82600000 {
497 no-map;
500 tz_stat_mem: tz-stat-region@82700000 {
502 no-map;
505 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 {
507 no-map;
510 mpss_mem: mpss-region@8a800000 {
512 no-map;
515 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 {
517 no-map;
520 ipa_fw_mem: ipa-fw-region@9b080000 {
522 no-map;
525 ipa_gsi_mem: ipa-gsi-region@9b090000 {
527 no-map;
530 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 {
532 no-map;
535 spss_region_mem: spss-region@9b100000 {
537 no-map;
541 spu_tz_shared_mem: spu-tz-shared-region@9b280000 {
543 no-map;
547 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 {
549 no-map;
552 camera_mem: camera-region@9b300000 {
554 no-map;
557 video_mem: video-region@9bb00000 {
559 no-map;
562 cvp_mem: cvp-region@9c200000 {
564 no-map;
567 cdsp_mem: cdsp-region@9c900000 {
569 no-map;
572 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 {
574 no-map;
577 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 {
579 no-map;
582 adspslpi_mem: adspslpi-region@9ea00000 {
584 no-map;
591 rmtfs_mem: rmtfs-region@d4a80000 {
592 compatible = "qcom,rmtfs-mem";
594 no-map;
596 qcom,client-id = <1>;
600 mpss_dsm_mem: mpss-dsm-region@d4d00000 {
602 no-map;
605 tz_reserved_mem: tz-reserved-region@d8000000 {
607 no-map;
610 cpucp_fw_mem: cpucp-fw-region@d8140000 {
612 no-map;
615 qtee_mem: qtee-region@d8300000 {
617 no-map;
620 ta_mem: ta-region@d8800000 {
622 no-map;
625 tz_tags_mem: tz-tags-region@e1200000 {
627 no-map;
630 hwfence_shbuf: hwfence-shbuf-region@e6440000 {
632 no-map;
635 trust_ui_vm_mem: trust-ui-vm-region@f3600000 {
637 no-map;
640 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 {
642 no-map;
645 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 {
647 no-map;
650 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 {
652 no-map;
655 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 {
657 no-map;
660 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 {
662 no-map;
665 oem_vm_mem: oem-vm-region@f8400000 {
667 no-map;
670 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 {
672 no-map;
675 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 {
677 no-map;
680 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 {
682 no-map;
685 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 {
687 no-map;
691 smp2p-adsp {
694 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
700 qcom,local-pid = <0>;
701 qcom,remote-pid = <2>;
703 smp2p_adsp_out: master-kernel {
704 qcom,entry-name = "master-kernel";
705 #qcom,smem-state-cells = <1>;
708 smp2p_adsp_in: slave-kernel {
709 qcom,entry-name = "slave-kernel";
710 interrupt-controller;
711 #interrupt-cells = <2>;
715 smp2p-cdsp {
718 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
724 qcom,local-pid = <0>;
725 qcom,remote-pid = <5>;
727 smp2p_cdsp_out: master-kernel {
728 qcom,entry-name = "master-kernel";
729 #qcom,smem-state-cells = <1>;
732 smp2p_cdsp_in: slave-kernel {
733 qcom,entry-name = "slave-kernel";
734 interrupt-controller;
735 #interrupt-cells = <2>;
739 smp2p-modem {
742 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
748 qcom,local-pid = <0>;
749 qcom,remote-pid = <1>;
751 smp2p_modem_out: master-kernel {
752 qcom,entry-name = "master-kernel";
753 #qcom,smem-state-cells = <1>;
756 smp2p_modem_in: slave-kernel {
757 qcom,entry-name = "slave-kernel";
758 interrupt-controller;
759 #interrupt-cells = <2>;
762 ipa_smp2p_out: ipa-ap-to-modem {
763 qcom,entry-name = "ipa";
764 #qcom,smem-state-cells = <1>;
767 ipa_smp2p_in: ipa-modem-to-ap {
768 qcom,entry-name = "ipa";
769 interrupt-controller;
770 #interrupt-cells = <2>;
775 compatible = "simple-bus";
777 dma-ranges = <0 0 0 0 0x10 0>;
779 #address-cells = <2>;
780 #size-cells = <2>;
782 gcc: clock-controller@100000 {
783 compatible = "qcom,sm8550-gcc";
785 #clock-cells = <1>;
786 #reset-cells = <1>;
787 #power-domain-cells = <1>;
799 compatible = "qcom,sm8550-ipcc", "qcom,ipcc";
802 interrupt-controller;
803 #interrupt-cells = <3>;
804 #mbox-cells = <2>;
807 gpi_dma2: dma-controller@800000 {
808 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
809 #dma-cells = <3>;
823 dma-channels = <12>;
824 dma-channel-mask = <0x3e>;
826 dma-coherent;
831 compatible = "qcom,geni-se-qup";
834 clock-names = "m-ahb", "s-ahb";
838 dma-coherent;
839 #address-cells = <2>;
840 #size-cells = <2>;
844 compatible = "qcom,geni-i2c";
846 clock-names = "se";
848 pinctrl-names = "default";
849 pinctrl-0 = <&qup_i2c8_data_clk>;
851 #address-cells = <1>;
852 #size-cells = <0>;
856 interconnect-names = "qup-core", "qup-config", "qup-memory";
859 dma-names = "tx", "rx";
864 compatible = "qcom,geni-spi";
866 clock-names = "se";
869 pinctrl-names = "default";
870 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
874 interconnect-names = "qup-core", "qup-config", "qup-memory";
877 dma-names = "tx", "rx";
878 #address-cells = <1>;
879 #size-cells = <0>;
884 compatible = "qcom,geni-i2c";
886 clock-names = "se";
888 pinctrl-names = "default";
889 pinctrl-0 = <&qup_i2c9_data_clk>;
891 #address-cells = <1>;
892 #size-cells = <0>;
896 interconnect-names = "qup-core", "qup-config", "qup-memory";
899 dma-names = "tx", "rx";
904 compatible = "qcom,geni-spi";
906 clock-names = "se";
909 pinctrl-names = "default";
910 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
914 interconnect-names = "qup-core", "qup-config", "qup-memory";
917 dma-names = "tx", "rx";
918 #address-cells = <1>;
919 #size-cells = <0>;
924 compatible = "qcom,geni-i2c";
926 clock-names = "se";
928 pinctrl-names = "default";
929 pinctrl-0 = <&qup_i2c10_data_clk>;
931 #address-cells = <1>;
932 #size-cells = <0>;
936 interconnect-names = "qup-core", "qup-config", "qup-memory";
939 dma-names = "tx", "rx";
944 compatible = "qcom,geni-spi";
946 clock-names = "se";
949 pinctrl-names = "default";
950 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
954 interconnect-names = "qup-core", "qup-config", "qup-memory";
957 dma-names = "tx", "rx";
958 #address-cells = <1>;
959 #size-cells = <0>;
964 compatible = "qcom,geni-i2c";
966 clock-names = "se";
968 pinctrl-names = "default";
969 pinctrl-0 = <&qup_i2c11_data_clk>;
971 #address-cells = <1>;
972 #size-cells = <0>;
976 interconnect-names = "qup-core", "qup-config", "qup-memory";
979 dma-names = "tx", "rx";
984 compatible = "qcom,geni-spi";
986 clock-names = "se";
989 pinctrl-names = "default";
990 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
994 interconnect-names = "qup-core", "qup-config", "qup-memory";
997 dma-names = "tx", "rx";
998 #address-cells = <1>;
999 #size-cells = <0>;
1004 compatible = "qcom,geni-i2c";
1006 clock-names = "se";
1008 pinctrl-names = "default";
1009 pinctrl-0 = <&qup_i2c12_data_clk>;
1011 #address-cells = <1>;
1012 #size-cells = <0>;
1016 interconnect-names = "qup-core", "qup-config", "qup-memory";
1019 dma-names = "tx", "rx";
1024 compatible = "qcom,geni-spi";
1026 clock-names = "se";
1029 pinctrl-names = "default";
1030 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1034 interconnect-names = "qup-core", "qup-config", "qup-memory";
1037 dma-names = "tx", "rx";
1038 #address-cells = <1>;
1039 #size-cells = <0>;
1044 compatible = "qcom,geni-i2c";
1046 clock-names = "se";
1048 pinctrl-names = "default";
1049 pinctrl-0 = <&qup_i2c13_data_clk>;
1051 #address-cells = <1>;
1052 #size-cells = <0>;
1056 interconnect-names = "qup-core", "qup-config", "qup-memory";
1059 dma-names = "tx", "rx";
1064 compatible = "qcom,geni-spi";
1066 clock-names = "se";
1069 pinctrl-names = "default";
1070 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1074 interconnect-names = "qup-core", "qup-config", "qup-memory";
1077 dma-names = "tx", "rx";
1078 #address-cells = <1>;
1079 #size-cells = <0>;
1084 compatible = "qcom,geni-uart";
1086 clock-names = "se";
1088 pinctrl-names = "default";
1089 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
1093 interconnect-names = "qup-core", "qup-config";
1098 compatible = "qcom,geni-i2c";
1100 clock-names = "se";
1102 pinctrl-names = "default";
1103 pinctrl-0 = <&qup_i2c15_data_clk>;
1105 #address-cells = <1>;
1106 #size-cells = <0>;
1110 interconnect-names = "qup-core", "qup-config", "qup-memory";
1113 dma-names = "tx", "rx";
1118 compatible = "qcom,geni-spi";
1120 clock-names = "se";
1123 pinctrl-names = "default";
1124 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1128 interconnect-names = "qup-core", "qup-config", "qup-memory";
1131 dma-names = "tx", "rx";
1132 #address-cells = <1>;
1133 #size-cells = <0>;
1139 compatible = "qcom,geni-se-i2c-master-hub";
1141 clock-names = "s-ahb";
1143 #address-cells = <2>;
1144 #size-cells = <2>;
1149 compatible = "qcom,geni-i2c-master-hub";
1151 clock-names = "se", "core";
1154 pinctrl-names = "default";
1155 pinctrl-0 = <&hub_i2c0_data_clk>;
1157 #address-cells = <1>;
1158 #size-cells = <0>;
1161 interconnect-names = "qup-core", "qup-config";
1166 compatible = "qcom,geni-i2c-master-hub";
1168 clock-names = "se", "core";
1171 pinctrl-names = "default";
1172 pinctrl-0 = <&hub_i2c1_data_clk>;
1174 #address-cells = <1>;
1175 #size-cells = <0>;
1178 interconnect-names = "qup-core", "qup-config";
1183 compatible = "qcom,geni-i2c-master-hub";
1185 clock-names = "se", "core";
1188 pinctrl-names = "default";
1189 pinctrl-0 = <&hub_i2c2_data_clk>;
1191 #address-cells = <1>;
1192 #size-cells = <0>;
1195 interconnect-names = "qup-core", "qup-config";
1200 compatible = "qcom,geni-i2c-master-hub";
1202 clock-names = "se", "core";
1205 pinctrl-names = "default";
1206 pinctrl-0 = <&hub_i2c3_data_clk>;
1208 #address-cells = <1>;
1209 #size-cells = <0>;
1212 interconnect-names = "qup-core", "qup-config";
1217 compatible = "qcom,geni-i2c-master-hub";
1219 clock-names = "se", "core";
1222 pinctrl-names = "default";
1223 pinctrl-0 = <&hub_i2c4_data_clk>;
1225 #address-cells = <1>;
1226 #size-cells = <0>;
1229 interconnect-names = "qup-core", "qup-config";
1234 compatible = "qcom,geni-i2c-master-hub";
1236 clock-names = "se", "core";
1239 pinctrl-names = "default";
1240 pinctrl-0 = <&hub_i2c5_data_clk>;
1242 #address-cells = <1>;
1243 #size-cells = <0>;
1246 interconnect-names = "qup-core", "qup-config";
1251 compatible = "qcom,geni-i2c-master-hub";
1253 clock-names = "se", "core";
1256 pinctrl-names = "default";
1257 pinctrl-0 = <&hub_i2c6_data_clk>;
1259 #address-cells = <1>;
1260 #size-cells = <0>;
1263 interconnect-names = "qup-core", "qup-config";
1268 compatible = "qcom,geni-i2c-master-hub";
1270 clock-names = "se", "core";
1273 pinctrl-names = "default";
1274 pinctrl-0 = <&hub_i2c7_data_clk>;
1276 #address-cells = <1>;
1277 #size-cells = <0>;
1280 interconnect-names = "qup-core", "qup-config";
1285 compatible = "qcom,geni-i2c-master-hub";
1287 clock-names = "se", "core";
1290 pinctrl-names = "default";
1291 pinctrl-0 = <&hub_i2c8_data_clk>;
1293 #address-cells = <1>;
1294 #size-cells = <0>;
1297 interconnect-names = "qup-core", "qup-config";
1302 compatible = "qcom,geni-i2c-master-hub";
1304 clock-names = "se", "core";
1307 pinctrl-names = "default";
1308 pinctrl-0 = <&hub_i2c9_data_clk>;
1310 #address-cells = <1>;
1311 #size-cells = <0>;
1314 interconnect-names = "qup-core", "qup-config";
1319 gpi_dma1: dma-controller@a00000 {
1320 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
1321 #dma-cells = <3>;
1335 dma-channels = <12>;
1336 dma-channel-mask = <0x1e>;
1338 dma-coherent;
1343 compatible = "qcom,geni-se-qup";
1346 clock-names = "m-ahb", "s-ahb";
1351 interconnect-names = "qup-core";
1352 dma-coherent;
1353 #address-cells = <2>;
1354 #size-cells = <2>;
1358 compatible = "qcom,geni-i2c";
1360 clock-names = "se";
1362 pinctrl-names = "default";
1363 pinctrl-0 = <&qup_i2c0_data_clk>;
1365 #address-cells = <1>;
1366 #size-cells = <0>;
1370 interconnect-names = "qup-core", "qup-config", "qup-memory";
1373 dma-names = "tx", "rx";
1378 compatible = "qcom,geni-spi";
1380 clock-names = "se";
1383 pinctrl-names = "default";
1384 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1388 interconnect-names = "qup-core", "qup-config", "qup-memory";
1391 dma-names = "tx", "rx";
1392 #address-cells = <1>;
1393 #size-cells = <0>;
1398 compatible = "qcom,geni-i2c";
1400 clock-names = "se";
1402 pinctrl-names = "default";
1403 pinctrl-0 = <&qup_i2c1_data_clk>;
1405 #address-cells = <1>;
1406 #size-cells = <0>;
1410 interconnect-names = "qup-core", "qup-config", "qup-memory";
1413 dma-names = "tx", "rx";
1418 compatible = "qcom,geni-spi";
1420 clock-names = "se";
1423 pinctrl-names = "default";
1424 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1428 interconnect-names = "qup-core", "qup-config", "qup-memory";
1431 dma-names = "tx", "rx";
1432 #address-cells = <1>;
1433 #size-cells = <0>;
1438 compatible = "qcom,geni-i2c";
1440 clock-names = "se";
1442 pinctrl-names = "default";
1443 pinctrl-0 = <&qup_i2c2_data_clk>;
1445 #address-cells = <1>;
1446 #size-cells = <0>;
1450 interconnect-names = "qup-core", "qup-config", "qup-memory";
1453 dma-names = "tx", "rx";
1458 compatible = "qcom,geni-spi";
1460 clock-names = "se";
1463 pinctrl-names = "default";
1464 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1468 interconnect-names = "qup-core", "qup-config", "qup-memory";
1471 dma-names = "tx", "rx";
1472 #address-cells = <1>;
1473 #size-cells = <0>;
1478 compatible = "qcom,geni-i2c";
1480 clock-names = "se";
1482 pinctrl-names = "default";
1483 pinctrl-0 = <&qup_i2c3_data_clk>;
1485 #address-cells = <1>;
1486 #size-cells = <0>;
1490 interconnect-names = "qup-core", "qup-config", "qup-memory";
1493 dma-names = "tx", "rx";
1498 compatible = "qcom,geni-spi";
1500 clock-names = "se";
1503 pinctrl-names = "default";
1504 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1508 interconnect-names = "qup-core", "qup-config", "qup-memory";
1511 dma-names = "tx", "rx";
1512 #address-cells = <1>;
1513 #size-cells = <0>;
1518 compatible = "qcom,geni-i2c";
1520 clock-names = "se";
1522 pinctrl-names = "default";
1523 pinctrl-0 = <&qup_i2c4_data_clk>;
1525 #address-cells = <1>;
1526 #size-cells = <0>;
1530 interconnect-names = "qup-core", "qup-config", "qup-memory";
1533 dma-names = "tx", "rx";
1538 compatible = "qcom,geni-spi";
1540 clock-names = "se";
1543 pinctrl-names = "default";
1544 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1548 interconnect-names = "qup-core", "qup-config", "qup-memory";
1551 dma-names = "tx", "rx";
1552 #address-cells = <1>;
1553 #size-cells = <0>;
1558 compatible = "qcom,geni-i2c";
1560 clock-names = "se";
1562 pinctrl-names = "default";
1563 pinctrl-0 = <&qup_i2c5_data_clk>;
1568 interconnect-names = "qup-core", "qup-config", "qup-memory";
1571 dma-names = "tx", "rx";
1572 #address-cells = <1>;
1573 #size-cells = <0>;
1578 compatible = "qcom,geni-spi";
1580 clock-names = "se";
1583 pinctrl-names = "default";
1584 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1588 interconnect-names = "qup-core", "qup-config", "qup-memory";
1591 dma-names = "tx", "rx";
1592 #address-cells = <1>;
1593 #size-cells = <0>;
1598 compatible = "qcom,geni-i2c";
1600 clock-names = "se";
1602 pinctrl-names = "default";
1603 pinctrl-0 = <&qup_i2c6_data_clk>;
1608 interconnect-names = "qup-core", "qup-config", "qup-memory";
1611 dma-names = "tx", "rx";
1612 #address-cells = <1>;
1613 #size-cells = <0>;
1618 compatible = "qcom,geni-spi";
1620 clock-names = "se";
1623 pinctrl-names = "default";
1624 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1628 interconnect-names = "qup-core", "qup-config", "qup-memory";
1631 dma-names = "tx", "rx";
1632 #address-cells = <1>;
1633 #size-cells = <0>;
1638 compatible = "qcom,geni-debug-uart";
1640 clock-names = "se";
1642 pinctrl-names = "default";
1643 pinctrl-0 = <&qup_uart7_default>;
1645 interconnect-names = "qup-core", "qup-config";
1653 compatible = "qcom,sm8550-cnoc-main";
1655 #interconnect-cells = <2>;
1656 qcom,bcm-voters = <&apps_bcm_voter>;
1660 compatible = "qcom,sm8550-config-noc";
1662 #interconnect-cells = <2>;
1663 qcom,bcm-voters = <&apps_bcm_voter>;
1667 compatible = "qcom,sm8550-system-noc";
1669 #interconnect-cells = <2>;
1670 qcom,bcm-voters = <&apps_bcm_voter>;
1674 compatible = "qcom,sm8550-pcie-anoc";
1676 #interconnect-cells = <2>;
1679 qcom,bcm-voters = <&apps_bcm_voter>;
1683 compatible = "qcom,sm8550-aggre1-noc";
1685 #interconnect-cells = <2>;
1688 qcom,bcm-voters = <&apps_bcm_voter>;
1692 compatible = "qcom,sm8550-aggre2-noc";
1694 #interconnect-cells = <2>;
1696 qcom,bcm-voters = <&apps_bcm_voter>;
1700 compatible = "qcom,sm8550-mmss-noc";
1702 #interconnect-cells = <2>;
1703 qcom,bcm-voters = <&apps_bcm_voter>;
1707 compatible = "qcom,sm8550-trng", "qcom,trng";
1713 compatible = "qcom,pcie-sm8550";
1719 reg-names = "parf", "dbi", "elbi", "atu", "config";
1720 #address-cells = <3>;
1721 #size-cells = <2>;
1724 bus-range = <0x00 0xff>;
1726 dma-coherent;
1728 linux,pci-domain = <0>;
1729 num-lanes = <2>;
1740 interrupt-names = "msi0",
1749 #interrupt-cells = <1>;
1750 interrupt-map-mask = <0 0 0 0x7>;
1751 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1763 clock-names = "aux",
1773 interconnect-names = "pcie-mem", "cpu-pcie";
1775 msi-map = <0x0 &gic_its 0x1400 0x1>,
1777 iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
1781 reset-names = "pci";
1783 power-domains = <&gcc PCIE_0_GDSC>;
1786 phy-names = "pciephy";
1793 bus-range = <0x01 0xff>;
1795 #address-cells = <3>;
1796 #size-cells = <2>;
1802 compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy";
1807 <&tcsr TCSR_PCIE_0_CLKREF_EN>,
1810 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1814 reset-names = "phy";
1816 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1817 assigned-clock-rates = <100000000>;
1819 power-domains = <&gcc PCIE_0_PHY_GDSC>;
1821 #clock-cells = <0>;
1822 clock-output-names = "pcie0_pipe_clk";
1824 #phy-cells = <0>;
1831 compatible = "qcom,pcie-sm8550";
1837 reg-names = "parf", "dbi", "elbi", "atu", "config";
1838 #address-cells = <3>;
1839 #size-cells = <2>;
1842 bus-range = <0x00 0xff>;
1844 dma-coherent;
1846 linux,pci-domain = <1>;
1847 num-lanes = <2>;
1858 interrupt-names = "msi0",
1867 #interrupt-cells = <1>;
1868 interrupt-map-mask = <0 0 0 0x7>;
1869 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1882 clock-names = "aux",
1891 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1892 assigned-clock-rates = <19200000>;
1896 interconnect-names = "pcie-mem", "cpu-pcie";
1898 msi-map = <0x0 &gic_its 0x1480 0x1>,
1900 iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
1905 reset-names = "pci", "link_down";
1907 power-domains = <&gcc PCIE_1_GDSC>;
1910 phy-names = "pciephy";
1917 bus-range = <0x01 0xff>;
1919 #address-cells = <3>;
1920 #size-cells = <2>;
1926 compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy";
1931 <&tcsr TCSR_PCIE_1_CLKREF_EN>,
1934 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1939 reset-names = "phy", "phy_nocsr";
1941 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
1942 assigned-clock-rates = <100000000>;
1944 power-domains = <&gcc PCIE_1_PHY_GDSC>;
1946 #clock-cells = <1>;
1947 clock-output-names = "pcie1_pipe_clk";
1949 #phy-cells = <0>;
1954 cryptobam: dma-controller@1dc4000 {
1955 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
1958 #dma-cells = <1>;
1960 qcom,controlled-remotely;
1966 compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce";
1969 dma-names = "rx", "tx";
1973 interconnect-names = "memory";
1977 compatible = "qcom,sm8550-qmp-ufs-phy";
1981 <&tcsr TCSR_UFS_CLKREF_EN>;
1982 clock-names = "ref",
1986 power-domains = <&gcc UFS_MEM_PHY_GDSC>;
1989 reset-names = "ufsphy";
1991 #clock-cells = <1>;
1992 #phy-cells = <0>;
1998 compatible = "qcom,sm8550-ufshc", "qcom,ufshc",
1999 "jedec,ufs-2.0";
2003 phy-names = "ufsphy";
2004 lanes-per-direction = <2>;
2005 #reset-cells = <1>;
2007 reset-names = "rst";
2009 power-domains = <&gcc UFS_PHY_GDSC>;
2010 required-opps = <&rpmhpd_opp_nom>;
2013 dma-coherent;
2015 operating-points-v2 = <&ufs_opp_table>;
2019 interconnect-names = "ufs-ddr", "cpu-ufs";
2020 clock-names = "core_clk",
2032 <&tcsr TCSR_UFS_PAD_CLKREF_EN>,
2040 ufs_opp_table: opp-table {
2041 compatible = "operating-points-v2";
2043 opp-75000000 {
2044 opp-hz = /bits/ 64 <75000000>,
2052 required-opps = <&rpmhpd_opp_low_svs>;
2055 opp-150000000 {
2056 opp-hz = /bits/ 64 <150000000>,
2064 required-opps = <&rpmhpd_opp_svs>;
2067 opp-300000000 {
2068 opp-hz = /bits/ 64 <300000000>,
2076 required-opps = <&rpmhpd_opp_nom>;
2082 compatible = "qcom,sm8550-inline-crypto-engine",
2083 "qcom,inline-crypto-engine";
2090 compatible = "qcom,tcsr-mutex";
2092 #hwlock-cells = <1>;
2095 tcsr: clock-controller@1fc0000 {
2096 compatible = "qcom,sm8550-tcsr", "syscon";
2099 #clock-cells = <1>;
2100 #reset-cells = <1>;
2104 compatible = "qcom,adreno-43050a01", "qcom,adreno";
2108 reg-names = "kgsl_3d0_reg_memory",
2117 operating-points-v2 = <&gpu_opp_table>;
2120 #cooling-cells = <2>;
2124 interconnect-names = "gfx-mem";
2128 zap-shader {
2129 memory-region = <&gpu_micro_code_mem>;
2133 gpu_opp_table: opp-table {
2134 compatible = "operating-points-v2";
2136 opp-680000000 {
2137 opp-hz = /bits/ 64 <680000000>;
2138 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2139 opp-peak-kBps = <16500000>;
2142 opp-615000000 {
2143 opp-hz = /bits/ 64 <615000000>;
2144 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2145 opp-peak-kBps = <12449218>;
2148 opp-550000000 {
2149 opp-hz = /bits/ 64 <550000000>;
2150 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2151 opp-peak-kBps = <10687500>;
2154 opp-475000000 {
2155 opp-hz = /bits/ 64 <475000000>;
2156 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
2157 opp-peak-kBps = <6074218>;
2160 opp-401000000 {
2161 opp-hz = /bits/ 64 <401000000>;
2162 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2163 opp-peak-kBps = <6074218>;
2166 opp-348000000 {
2167 opp-hz = /bits/ 64 <348000000>;
2168 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
2169 opp-peak-kBps = <6074218>;
2172 opp-295000000 {
2173 opp-hz = /bits/ 64 <295000000>;
2174 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2175 opp-peak-kBps = <6074218>;
2178 opp-220000000 {
2179 opp-hz = /bits/ 64 <220000000>;
2180 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
2181 opp-peak-kBps = <2136718>;
2187 compatible = "qcom,adreno-gmu-740.1", "qcom,adreno-gmu";
2191 reg-names = "gmu", "rscc", "gmu_pdc";
2195 interrupt-names = "hfi", "gmu";
2204 clock-names = "ahb",
2212 power-domains = <&gpucc GPU_CC_CX_GDSC>,
2214 power-domain-names = "cx",
2221 operating-points-v2 = <&gmu_opp_table>;
2223 gmu_opp_table: opp-table {
2224 compatible = "operating-points-v2";
2226 opp-500000000 {
2227 opp-hz = /bits/ 64 <500000000>;
2228 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2231 opp-200000000 {
2232 opp-hz = /bits/ 64 <200000000>;
2233 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2238 gpucc: clock-controller@3d90000 {
2239 compatible = "qcom,sm8550-gpucc";
2244 #clock-cells = <1>;
2245 #reset-cells = <1>;
2246 #power-domain-cells = <1>;
2250 compatible = "qcom,sm8550-smmu-500", "qcom,adreno-smmu",
2251 "qcom,smmu-500", "arm,mmu-500";
2253 #iommu-cells = <2>;
2254 #global-interrupts = <1>;
2285 clock-names = "hlos",
2289 power-domains = <&gpucc GPU_CC_CX_GDSC>;
2290 dma-coherent;
2294 compatible = "qcom,sm8550-ipa";
2301 reg-names = "ipa-reg",
2302 "ipa-shared",
2305 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
2309 interrupt-names = "ipa",
2311 "ipa-clock-query",
2312 "ipa-setup-ready";
2315 clock-names = "core";
2319 interconnect-names = "memory",
2324 qcom,smem-states = <&ipa_smp2p_out 0>,
2326 qcom,smem-state-names = "ipa-clock-enabled-valid",
2327 "ipa-clock-enabled";
2333 compatible = "qcom,sm8550-mpss-pas";
2336 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2342 interrupt-names = "wdog", "fatal", "ready", "handover",
2343 "stop-ack", "shutdown-ack";
2346 clock-names = "xo";
2348 power-domains = <&rpmhpd RPMHPD_CX>,
2350 power-domain-names = "cx", "mss";
2354 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>;
2358 qcom,smem-states = <&smp2p_modem_out 0>;
2359 qcom,smem-state-names = "stop";
2363 glink-edge {
2364 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2370 qcom,remote-pid = <1>;
2375 compatible = "qcom,sm8550-adsp-pas";
2378 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2383 interrupt-names = "wdog", "fatal", "ready",
2384 "handover", "stop-ack";
2387 clock-names = "xo";
2389 power-domains = <&rpmhpd RPMHPD_LCX>,
2391 power-domain-names = "lcx", "lmx";
2395 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
2399 qcom,smem-states = <&smp2p_adsp_out 0>;
2400 qcom,smem-state-names = "stop";
2404 remoteproc_adsp_glink: glink-edge {
2405 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2412 qcom,remote-pid = <2>;
2416 qcom,glink-channels = "fastrpcglink-apps-dsp";
2418 qcom,non-secure-domain;
2419 #address-cells = <1>;
2420 #size-cells = <0>;
2422 compute-cb@3 {
2423 compatible = "qcom,fastrpc-compute-cb";
2427 dma-coherent;
2430 compute-cb@4 {
2431 compatible = "qcom,fastrpc-compute-cb";
2435 dma-coherent;
2438 compute-cb@5 {
2439 compatible = "qcom,fastrpc-compute-cb";
2443 dma-coherent;
2446 compute-cb@6 {
2447 compatible = "qcom,fastrpc-compute-cb";
2451 dma-coherent;
2454 compute-cb@7 {
2455 compatible = "qcom,fastrpc-compute-cb";
2459 dma-coherent;
2465 qcom,glink-channels = "adsp_apps";
2468 #address-cells = <1>;
2469 #size-cells = <0>;
2474 #sound-dai-cells = <0>;
2475 qcom,protection-domain = "avs/audio",
2479 compatible = "qcom,q6apm-dais";
2485 compatible = "qcom,q6apm-lpass-dais";
2486 #sound-dai-cells = <1>;
2493 qcom,protection-domain = "avs/audio",
2496 q6prmcc: clock-controller {
2497 compatible = "qcom,q6prm-lpass-clocks";
2498 #clock-cells = <2>;
2506 compatible = "qcom,sm8550-lpass-wsa-macro";
2512 clock-names = "mclk", "macro", "dcodec", "fsgen";
2514 #clock-cells = <0>;
2515 clock-output-names = "wsa2-mclk";
2516 #sound-dai-cells = <1>;
2520 compatible = "qcom,soundwire-v2.0.0";
2524 clock-names = "iface";
2527 pinctrl-0 = <&wsa2_swr_active>;
2528 pinctrl-names = "default";
2530 qcom,din-ports = <4>;
2531 qcom,dout-ports = <9>;
2533 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
2534 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2535 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2536 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2537 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2538 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
2539 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
2540 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2541 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2543 #address-cells = <2>;
2544 #size-cells = <0>;
2545 #sound-dai-cells = <1>;
2550 compatible = "qcom,sm8550-lpass-rx-macro";
2556 clock-names = "mclk", "macro", "dcodec", "fsgen";
2558 #clock-cells = <0>;
2559 clock-output-names = "mclk";
2560 #sound-dai-cells = <1>;
2564 compatible = "qcom,soundwire-v2.0.0";
2568 clock-names = "iface";
2571 pinctrl-0 = <&rx_swr_active>;
2572 pinctrl-names = "default";
2574 qcom,din-ports = <1>;
2575 qcom,dout-ports = <11>;
2577 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff 0xff 0xff>;
2578 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2579 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2580 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>;
2581 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>;
2582 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff 0xff 0xff>;
2583 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2584 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2585 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2587 #address-cells = <2>;
2588 #size-cells = <0>;
2589 #sound-dai-cells = <1>;
2594 compatible = "qcom,sm8550-lpass-tx-macro";
2600 clock-names = "mclk", "macro", "dcodec", "fsgen";
2602 #clock-cells = <0>;
2603 clock-output-names = "mclk";
2604 #sound-dai-cells = <1>;
2608 compatible = "qcom,sm8550-lpass-wsa-macro";
2614 clock-names = "mclk", "macro", "dcodec", "fsgen";
2616 #clock-cells = <0>;
2617 clock-output-names = "mclk";
2618 #sound-dai-cells = <1>;
2622 compatible = "qcom,soundwire-v2.0.0";
2626 clock-names = "iface";
2629 pinctrl-0 = <&wsa_swr_active>;
2630 pinctrl-names = "default";
2632 qcom,din-ports = <4>;
2633 qcom,dout-ports = <9>;
2635 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
2636 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2637 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2638 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2639 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2640 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
2641 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
2642 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2643 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2645 #address-cells = <2>;
2646 #size-cells = <0>;
2647 #sound-dai-cells = <1>;
2652 compatible = "qcom,soundwire-v2.0.0";
2656 interrupt-names = "core", "wakeup";
2658 clock-names = "iface";
2661 pinctrl-0 = <&tx_swr_active>;
2662 pinctrl-names = "default";
2664 qcom,din-ports = <4>;
2665 qcom,dout-ports = <0>;
2666 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2667 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2668 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2669 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2670 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2671 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2672 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2673 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2674 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2676 #address-cells = <2>;
2677 #size-cells = <0>;
2678 #sound-dai-cells = <1>;
2683 compatible = "qcom,sm8550-lpass-va-macro";
2688 clock-names = "mclk", "macro", "dcodec";
2690 #clock-cells = <0>;
2691 clock-output-names = "fsgen";
2692 #sound-dai-cells = <1>;
2696 compatible = "qcom,sm8550-lpass-lpi-pinctrl";
2699 gpio-controller;
2700 #gpio-cells = <2>;
2701 gpio-ranges = <&lpass_tlmm 0 0 23>;
2705 clock-names = "core", "audio";
2707 tx_swr_active: tx-swr-active-state {
2708 clk-pins {
2711 drive-strength = <2>;
2712 slew-rate = <1>;
2713 bias-disable;
2716 data-pins {
2719 drive-strength = <2>;
2720 slew-rate = <1>;
2721 bias-bus-hold;
2725 rx_swr_active: rx-swr-active-state {
2726 clk-pins {
2729 drive-strength = <2>;
2730 slew-rate = <1>;
2731 bias-disable;
2734 data-pins {
2737 drive-strength = <2>;
2738 slew-rate = <1>;
2739 bias-bus-hold;
2743 dmic01_default: dmic01-default-state {
2744 clk-pins {
2747 drive-strength = <8>;
2748 output-high;
2751 data-pins {
2754 drive-strength = <8>;
2755 input-enable;
2759 dmic23_default: dmic23-default-state {
2760 clk-pins {
2763 drive-strength = <8>;
2764 output-high;
2767 data-pins {
2770 drive-strength = <8>;
2771 input-enable;
2775 wsa_swr_active: wsa-swr-active-state {
2776 clk-pins {
2779 drive-strength = <2>;
2780 slew-rate = <1>;
2781 bias-disable;
2784 data-pins {
2787 drive-strength = <2>;
2788 slew-rate = <1>;
2789 bias-bus-hold;
2793 wsa2_swr_active: wsa2-swr-active-state {
2794 clk-pins {
2797 drive-strength = <2>;
2798 slew-rate = <1>;
2799 bias-disable;
2802 data-pins {
2805 drive-strength = <2>;
2806 slew-rate = <1>;
2807 bias-bus-hold;
2813 compatible = "qcom,sm8550-lpass-lpiaon-noc";
2815 #interconnect-cells = <2>;
2816 qcom,bcm-voters = <&apps_bcm_voter>;
2820 compatible = "qcom,sm8550-lpass-lpicx-noc";
2822 #interconnect-cells = <2>;
2823 qcom,bcm-voters = <&apps_bcm_voter>;
2827 compatible = "qcom,sm8550-lpass-ag-noc";
2829 #interconnect-cells = <2>;
2830 qcom,bcm-voters = <&apps_bcm_voter>;
2834 compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5";
2839 interrupt-names = "hc_irq", "pwr_irq";
2844 clock-names = "iface", "core", "xo";
2846 qcom,dll-config = <0x0007642c>;
2847 qcom,ddr-config = <0x80040868>;
2848 power-domains = <&rpmhpd RPMHPD_CX>;
2849 operating-points-v2 = <&sdhc2_opp_table>;
2853 interconnect-names = "sdhc-ddr", "cpu-sdhc";
2854 bus-width = <4>;
2855 dma-coherent;
2857 /* Forbid SDR104/SDR50 - broken hw! */
2858 sdhci-caps-mask = <0x3 0>;
2862 sdhc2_opp_table: opp-table {
2863 compatible = "operating-points-v2";
2865 opp-19200000 {
2866 opp-hz = /bits/ 64 <19200000>;
2867 required-opps = <&rpmhpd_opp_min_svs>;
2870 opp-50000000 {
2871 opp-hz = /bits/ 64 <50000000>;
2872 required-opps = <&rpmhpd_opp_low_svs>;
2875 opp-100000000 {
2876 opp-hz = /bits/ 64 <100000000>;
2877 required-opps = <&rpmhpd_opp_svs>;
2880 opp-202000000 {
2881 opp-hz = /bits/ 64 <202000000>;
2882 required-opps = <&rpmhpd_opp_svs_l1>;
2887 videocc: clock-controller@aaf0000 {
2888 compatible = "qcom,sm8550-videocc";
2892 power-domains = <&rpmhpd RPMHPD_MMCX>;
2893 required-opps = <&rpmhpd_opp_low_svs>;
2894 #clock-cells = <1>;
2895 #reset-cells = <1>;
2896 #power-domain-cells = <1>;
2900 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci";
2903 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
2907 clock-names = "camnoc_axi",
2910 pinctrl-0 = <&cci0_0_default &cci0_1_default>;
2911 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
2912 pinctrl-names = "default", "sleep";
2914 #address-cells = <1>;
2915 #size-cells = <0>;
2917 cci0_i2c0: i2c-bus@0 {
2919 clock-frequency = <1000000>;
2920 #address-cells = <1>;
2921 #size-cells = <0>;
2924 cci0_i2c1: i2c-bus@1 {
2926 clock-frequency = <1000000>;
2927 #address-cells = <1>;
2928 #size-cells = <0>;
2933 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci";
2936 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
2940 clock-names = "camnoc_axi",
2943 pinctrl-0 = <&cci1_0_default>;
2944 pinctrl-1 = <&cci1_0_sleep>;
2945 pinctrl-names = "default", "sleep";
2947 #address-cells = <1>;
2948 #size-cells = <0>;
2950 cci1_i2c0: i2c-bus@0 {
2952 clock-frequency = <1000000>;
2953 #address-cells = <1>;
2954 #size-cells = <0>;
2959 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci";
2962 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
2966 clock-names = "camnoc_axi",
2969 pinctrl-0 = <&cci2_0_default &cci2_1_default>;
2970 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>;
2971 pinctrl-names = "default", "sleep";
2973 #address-cells = <1>;
2974 #size-cells = <0>;
2976 cci2_i2c0: i2c-bus@0 {
2978 clock-frequency = <1000000>;
2979 #address-cells = <1>;
2980 #size-cells = <0>;
2983 cci2_i2c1: i2c-bus@1 {
2985 clock-frequency = <1000000>;
2986 #address-cells = <1>;
2987 #size-cells = <0>;
2991 camcc: clock-controller@ade0000 {
2992 compatible = "qcom,sm8550-camcc";
2998 power-domains = <&rpmhpd SM8550_MMCX>;
2999 required-opps = <&rpmhpd_opp_low_svs>;
3000 #clock-cells = <1>;
3001 #reset-cells = <1>;
3002 #power-domain-cells = <1>;
3005 mdss: display-subsystem@ae00000 {
3006 compatible = "qcom,sm8550-mdss";
3008 reg-names = "mdss";
3011 interrupt-controller;
3012 #interrupt-cells = <1>;
3021 power-domains = <&dispcc MDSS_GDSC>;
3024 interconnect-names = "mdp0-mem";
3028 #address-cells = <2>;
3029 #size-cells = <2>;
3034 mdss_mdp: display-controller@ae01000 {
3035 compatible = "qcom,sm8550-dpu";
3038 reg-names = "mdp", "vbif";
3040 interrupt-parent = <&mdss>;
3049 clock-names = "bus",
3056 power-domains = <&rpmhpd RPMHPD_MMCX>;
3058 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3059 assigned-clock-rates = <19200000>;
3061 operating-points-v2 = <&mdp_opp_table>;
3064 #address-cells = <1>;
3065 #size-cells = <0>;
3070 remote-endpoint = <&mdss_dsi0_in>;
3077 remote-endpoint = <&mdss_dsi1_in>;
3084 remote-endpoint = <&mdss_dp0_in>;
3089 mdp_opp_table: opp-table {
3090 compatible = "operating-points-v2";
3092 opp-200000000 {
3093 opp-hz = /bits/ 64 <200000000>;
3094 required-opps = <&rpmhpd_opp_low_svs>;
3097 opp-325000000 {
3098 opp-hz = /bits/ 64 <325000000>;
3099 required-opps = <&rpmhpd_opp_svs>;
3102 opp-375000000 {
3103 opp-hz = /bits/ 64 <375000000>;
3104 required-opps = <&rpmhpd_opp_svs_l1>;
3107 opp-514000000 {
3108 opp-hz = /bits/ 64 <514000000>;
3109 required-opps = <&rpmhpd_opp_nom>;
3114 mdss_dp0: displayport-controller@ae90000 {
3115 compatible = "qcom,sm8550-dp", "qcom,sm8350-dp";
3121 interrupt-parent = <&mdss>;
3128 clock-names = "core_iface",
3134 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
3136 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3140 phy-names = "dp";
3142 #sound-dai-cells = <0>;
3144 operating-points-v2 = <&dp_opp_table>;
3145 power-domains = <&rpmhpd RPMHPD_MMCX>;
3150 #address-cells = <1>;
3151 #size-cells = <0>;
3156 remote-endpoint = <&dpu_intf0_out>;
3163 remote-endpoint = <&usb_dp_qmpphy_dp_in>;
3168 dp_opp_table: opp-table {
3169 compatible = "operating-points-v2";
3171 opp-162000000 {
3172 opp-hz = /bits/ 64 <162000000>;
3173 required-opps = <&rpmhpd_opp_low_svs_d1>;
3176 opp-270000000 {
3177 opp-hz = /bits/ 64 <270000000>;
3178 required-opps = <&rpmhpd_opp_low_svs>;
3181 opp-540000000 {
3182 opp-hz = /bits/ 64 <540000000>;
3183 required-opps = <&rpmhpd_opp_svs_l1>;
3186 opp-810000000 {
3187 opp-hz = /bits/ 64 <810000000>;
3188 required-opps = <&rpmhpd_opp_nom>;
3194 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3196 reg-names = "dsi_ctrl";
3198 interrupt-parent = <&mdss>;
3207 clock-names = "byte",
3214 power-domains = <&rpmhpd RPMHPD_MMCX>;
3216 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
3218 assigned-clock-parents = <&mdss_dsi0_phy 0>,
3221 operating-points-v2 = <&mdss_dsi_opp_table>;
3224 phy-names = "dsi";
3226 #address-cells = <1>;
3227 #size-cells = <0>;
3232 #address-cells = <1>;
3233 #size-cells = <0>;
3238 remote-endpoint = <&dpu_intf1_out>;
3249 mdss_dsi_opp_table: opp-table {
3250 compatible = "operating-points-v2";
3252 opp-187500000 {
3253 opp-hz = /bits/ 64 <187500000>;
3254 required-opps = <&rpmhpd_opp_low_svs>;
3257 opp-300000000 {
3258 opp-hz = /bits/ 64 <300000000>;
3259 required-opps = <&rpmhpd_opp_svs>;
3262 opp-358000000 {
3263 opp-hz = /bits/ 64 <358000000>;
3264 required-opps = <&rpmhpd_opp_svs_l1>;
3270 compatible = "qcom,sm8550-dsi-phy-4nm";
3274 reg-names = "dsi_phy",
3280 clock-names = "iface", "ref";
3282 #clock-cells = <1>;
3283 #phy-cells = <0>;
3289 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3291 reg-names = "dsi_ctrl";
3293 interrupt-parent = <&mdss>;
3302 clock-names = "byte",
3309 power-domains = <&rpmhpd RPMHPD_MMCX>;
3311 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
3313 assigned-clock-parents = <&mdss_dsi1_phy 0>,
3316 operating-points-v2 = <&mdss_dsi_opp_table>;
3319 phy-names = "dsi";
3321 #address-cells = <1>;
3322 #size-cells = <0>;
3327 #address-cells = <1>;
3328 #size-cells = <0>;
3333 remote-endpoint = <&dpu_intf2_out>;
3346 compatible = "qcom,sm8550-dsi-phy-4nm";
3350 reg-names = "dsi_phy",
3356 clock-names = "iface", "ref";
3358 #clock-cells = <1>;
3359 #phy-cells = <0>;
3365 dispcc: clock-controller@af00000 {
3366 compatible = "qcom,sm8550-dispcc";
3384 power-domains = <&rpmhpd RPMHPD_MMCX>;
3385 required-opps = <&rpmhpd_opp_low_svs>;
3386 #clock-cells = <1>;
3387 #reset-cells = <1>;
3388 #power-domain-cells = <1>;
3392 compatible = "qcom,sm8550-snps-eusb2-phy";
3394 #phy-cells = <0>;
3396 clocks = <&tcsr TCSR_USB2_CLKREF_EN>;
3397 clock-names = "ref";
3405 compatible = "qcom,sm8550-qmp-usb3-dp-phy";
3412 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3414 power-domains = <&gcc USB3_PHY_GDSC>;
3418 reset-names = "phy", "common";
3420 #clock-cells = <1>;
3421 #phy-cells = <1>;
3423 orientation-switch;
3428 #address-cells = <1>;
3429 #size-cells = <0>;
3442 remote-endpoint = <&usb_1_dwc3_ss>;
3450 remote-endpoint = <&mdss_dp0_out>;
3457 compatible = "qcom,sm8550-dwc3", "qcom,dwc3";
3459 #address-cells = <2>;
3460 #size-cells = <2>;
3468 <&tcsr TCSR_USB3_CLKREF_EN>;
3469 clock-names = "cfg_noc",
3476 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3478 assigned-clock-rates = <19200000>, <200000000>;
3480 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3485 interrupt-names = "pwr_event",
3491 power-domains = <&gcc USB30_PRIM_GDSC>;
3492 required-opps = <&rpmhpd_opp_nom>;
3498 interconnect-names = "usb-ddr", "apps-usb";
3509 phy-names = "usb2-phy", "usb3-phy";
3510 snps,hird-threshold = /bits/ 8 <0x0>;
3511 snps,usb2-gadget-lpm-disable;
3514 snps,dis-u1-entry-quirk;
3515 snps,dis-u2-entry-quirk;
3516 snps,is-utmi-l1-suspend;
3518 snps,usb2-lpm-disable;
3519 snps,has-lpm-erratum;
3520 tx-fifo-resize;
3521 dma-coherent;
3522 usb-role-switch;
3525 #address-cells = <1>;
3526 #size-cells = <0>;
3539 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
3546 pdc: interrupt-controller@b220000 {
3547 compatible = "qcom,sm8550-pdc", "qcom,pdc";
3549 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
3552 #interrupt-cells = <2>;
3553 interrupt-parent = <&intc>;
3554 interrupt-controller;
3557 tsens0: thermal-sensor@c271000 {
3558 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
3564 interrupt-names = "uplow", "critical";
3565 #thermal-sensor-cells = <1>;
3568 tsens1: thermal-sensor@c272000 {
3569 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
3575 interrupt-names = "uplow", "critical";
3576 #thermal-sensor-cells = <1>;
3579 tsens2: thermal-sensor@c273000 {
3580 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
3586 interrupt-names = "uplow", "critical";
3587 #thermal-sensor-cells = <1>;
3590 aoss_qmp: power-management@c300000 {
3591 compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp";
3593 interrupt-parent = <&ipcc>;
3594 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3598 #clock-cells = <0>;
3602 compatible = "qcom,rpmh-stats";
3607 compatible = "qcom,spmi-pmic-arb";
3613 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3614 interrupt-names = "periph_irq";
3615 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3618 qcom,bus-id = <0>;
3619 #address-cells = <2>;
3620 #size-cells = <0>;
3621 interrupt-controller;
3622 #interrupt-cells = <4>;
3626 compatible = "qcom,sm8550-tlmm";
3629 gpio-controller;
3630 #gpio-cells = <2>;
3631 interrupt-controller;
3632 #interrupt-cells = <2>;
3633 gpio-ranges = <&tlmm 0 0 211>;
3634 wakeup-parent = <&pdc>;
3636 cci0_0_default: cci0-0-default-state {
3637 sda-pins {
3640 drive-strength = <2>;
3641 bias-pull-up = <2200>;
3644 scl-pins {
3647 drive-strength = <2>;
3648 bias-pull-up = <2200>;
3652 cci0_0_sleep: cci0-0-sleep-state {
3653 sda-pins {
3656 drive-strength = <2>;
3657 bias-pull-down;
3660 scl-pins {
3663 drive-strength = <2>;
3664 bias-pull-down;
3668 cci0_1_default: cci0-1-default-state {
3669 sda-pins {
3672 drive-strength = <2>;
3673 bias-pull-up = <2200>;
3676 scl-pins {
3679 drive-strength = <2>;
3680 bias-pull-up = <2200>;
3684 cci0_1_sleep: cci0-1-sleep-state {
3685 sda-pins {
3688 drive-strength = <2>;
3689 bias-pull-down;
3692 scl-pins {
3695 drive-strength = <2>;
3696 bias-pull-down;
3700 cci1_0_default: cci1-0-default-state {
3701 sda-pins {
3704 drive-strength = <2>;
3705 bias-pull-up = <2200>;
3708 scl-pins {
3711 drive-strength = <2>;
3712 bias-pull-up = <2200>;
3716 cci1_0_sleep: cci1-0-sleep-state {
3717 sda-pins {
3720 drive-strength = <2>;
3721 bias-pull-down;
3724 scl-pins {
3727 drive-strength = <2>;
3728 bias-pull-down;
3732 cci2_0_default: cci2-0-default-state {
3733 sda-pins {
3736 drive-strength = <2>;
3737 bias-pull-up = <2200>;
3740 scl-pins {
3743 drive-strength = <2>;
3744 bias-pull-up = <2200>;
3748 cci2_0_sleep: cci2-0-sleep-state {
3749 sda-pins {
3752 drive-strength = <2>;
3753 bias-pull-down;
3756 scl-pins {
3759 drive-strength = <2>;
3760 bias-pull-down;
3764 cci2_1_default: cci2-1-default-state {
3765 sda-pins {
3768 drive-strength = <2>;
3769 bias-pull-up = <2200>;
3772 scl-pins {
3775 drive-strength = <2>;
3776 bias-pull-up = <2200>;
3780 cci2_1_sleep: cci2-1-sleep-state {
3781 sda-pins {
3784 drive-strength = <2>;
3785 bias-pull-down;
3788 scl-pins {
3791 drive-strength = <2>;
3792 bias-pull-down;
3796 hub_i2c0_data_clk: hub-i2c0-data-clk-state {
3800 drive-strength = <2>;
3801 bias-pull-up;
3804 hub_i2c1_data_clk: hub-i2c1-data-clk-state {
3808 drive-strength = <2>;
3809 bias-pull-up;
3812 hub_i2c2_data_clk: hub-i2c2-data-clk-state {
3816 drive-strength = <2>;
3817 bias-pull-up;
3820 hub_i2c3_data_clk: hub-i2c3-data-clk-state {
3824 drive-strength = <2>;
3825 bias-pull-up;
3828 hub_i2c4_data_clk: hub-i2c4-data-clk-state {
3832 drive-strength = <2>;
3833 bias-pull-up;
3836 hub_i2c5_data_clk: hub-i2c5-data-clk-state {
3840 drive-strength = <2>;
3841 bias-pull-up;
3844 hub_i2c6_data_clk: hub-i2c6-data-clk-state {
3848 drive-strength = <2>;
3849 bias-pull-up;
3852 hub_i2c7_data_clk: hub-i2c7-data-clk-state {
3856 drive-strength = <2>;
3857 bias-pull-up;
3860 hub_i2c8_data_clk: hub-i2c8-data-clk-state {
3864 drive-strength = <2>;
3865 bias-pull-up;
3868 hub_i2c9_data_clk: hub-i2c9-data-clk-state {
3872 drive-strength = <2>;
3873 bias-pull-up;
3876 pcie0_default_state: pcie0-default-state {
3877 perst-pins {
3880 drive-strength = <2>;
3881 bias-pull-down;
3884 clkreq-pins {
3887 drive-strength = <2>;
3888 bias-pull-up;
3891 wake-pins {
3894 drive-strength = <2>;
3895 bias-pull-up;
3899 pcie1_default_state: pcie1-default-state {
3900 perst-pins {
3903 drive-strength = <2>;
3904 bias-pull-down;
3907 clkreq-pins {
3910 drive-strength = <2>;
3911 bias-pull-up;
3914 wake-pins {
3917 drive-strength = <2>;
3918 bias-pull-up;
3922 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3926 drive-strength = <2>;
3927 bias-pull-up = <2200>;
3930 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3934 drive-strength = <2>;
3935 bias-pull-up = <2200>;
3938 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3942 drive-strength = <2>;
3943 bias-pull-up = <2200>;
3946 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3950 drive-strength = <2>;
3951 bias-pull-up = <2200>;
3954 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3958 drive-strength = <2>;
3959 bias-pull-up = <2200>;
3962 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3966 drive-strength = <2>;
3967 bias-pull-up = <2200>;
3970 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3974 drive-strength = <2>;
3975 bias-pull-up = <2200>;
3978 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3979 scl-pins {
3982 drive-strength = <2>;
3983 bias-pull-up = <2200>;
3986 sda-pins {
3989 drive-strength = <2>;
3990 bias-pull-up = <2200>;
3994 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3998 drive-strength = <2>;
3999 bias-pull-up = <2200>;
4002 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
4006 drive-strength = <2>;
4007 bias-pull-up = <2200>;
4010 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
4014 drive-strength = <2>;
4015 bias-pull-up = <2200>;
4018 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
4022 drive-strength = <2>;
4023 bias-pull-up = <2200>;
4026 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
4030 drive-strength = <2>;
4031 bias-pull-up = <2200>;
4034 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
4038 drive-strength = <2>;
4039 bias-pull-up = <2200>;
4042 qup_spi0_cs: qup-spi0-cs-state {
4045 drive-strength = <6>;
4046 bias-disable;
4049 qup_spi0_data_clk: qup-spi0-data-clk-state {
4053 drive-strength = <6>;
4054 bias-disable;
4057 qup_spi1_cs: qup-spi1-cs-state {
4060 drive-strength = <6>;
4061 bias-disable;
4064 qup_spi1_data_clk: qup-spi1-data-clk-state {
4068 drive-strength = <6>;
4069 bias-disable;
4072 qup_spi2_cs: qup-spi2-cs-state {
4075 drive-strength = <6>;
4076 bias-disable;
4079 qup_spi2_data_clk: qup-spi2-data-clk-state {
4083 drive-strength = <6>;
4084 bias-disable;
4087 qup_spi3_cs: qup-spi3-cs-state {
4090 drive-strength = <6>;
4091 bias-disable;
4094 qup_spi3_data_clk: qup-spi3-data-clk-state {
4098 drive-strength = <6>;
4099 bias-disable;
4102 qup_spi4_cs: qup-spi4-cs-state {
4105 drive-strength = <6>;
4106 bias-disable;
4109 qup_spi4_data_clk: qup-spi4-data-clk-state {
4113 drive-strength = <6>;
4114 bias-disable;
4117 qup_spi5_cs: qup-spi5-cs-state {
4120 drive-strength = <6>;
4121 bias-disable;
4124 qup_spi5_data_clk: qup-spi5-data-clk-state {
4128 drive-strength = <6>;
4129 bias-disable;
4132 qup_spi6_cs: qup-spi6-cs-state {
4135 drive-strength = <6>;
4136 bias-disable;
4139 qup_spi6_data_clk: qup-spi6-data-clk-state {
4143 drive-strength = <6>;
4144 bias-disable;
4147 qup_spi8_cs: qup-spi8-cs-state {
4150 drive-strength = <6>;
4151 bias-disable;
4154 qup_spi8_data_clk: qup-spi8-data-clk-state {
4158 drive-strength = <6>;
4159 bias-disable;
4162 qup_spi9_cs: qup-spi9-cs-state {
4165 drive-strength = <6>;
4166 bias-disable;
4169 qup_spi9_data_clk: qup-spi9-data-clk-state {
4173 drive-strength = <6>;
4174 bias-disable;
4177 qup_spi10_cs: qup-spi10-cs-state {
4180 drive-strength = <6>;
4181 bias-disable;
4184 qup_spi10_data_clk: qup-spi10-data-clk-state {
4188 drive-strength = <6>;
4189 bias-disable;
4192 qup_spi11_cs: qup-spi11-cs-state {
4195 drive-strength = <6>;
4196 bias-disable;
4199 qup_spi11_data_clk: qup-spi11-data-clk-state {
4203 drive-strength = <6>;
4204 bias-disable;
4207 qup_spi12_cs: qup-spi12-cs-state {
4210 drive-strength = <6>;
4211 bias-disable;
4214 qup_spi12_data_clk: qup-spi12-data-clk-state {
4218 drive-strength = <6>;
4219 bias-disable;
4222 qup_spi13_cs: qup-spi13-cs-state {
4225 drive-strength = <6>;
4226 bias-disable;
4229 qup_spi13_data_clk: qup-spi13-data-clk-state {
4233 drive-strength = <6>;
4234 bias-disable;
4237 qup_spi15_cs: qup-spi15-cs-state {
4240 drive-strength = <6>;
4241 bias-disable;
4244 qup_spi15_data_clk: qup-spi15-data-clk-state {
4248 drive-strength = <6>;
4249 bias-disable;
4252 qup_uart7_default: qup-uart7-default-state {
4256 drive-strength = <2>;
4257 bias-disable;
4260 qup_uart14_default: qup-uart14-default-state {
4264 drive-strength = <2>;
4265 bias-pull-up;
4268 qup_uart14_cts_rts: qup-uart14-cts-rts-state {
4272 drive-strength = <2>;
4273 bias-pull-down;
4276 sdc2_sleep: sdc2-sleep-state {
4277 clk-pins {
4279 bias-disable;
4280 drive-strength = <2>;
4283 cmd-pins {
4285 bias-pull-up;
4286 drive-strength = <2>;
4289 data-pins {
4291 bias-pull-up;
4292 drive-strength = <2>;
4296 sdc2_default: sdc2-default-state {
4297 clk-pins {
4299 bias-disable;
4300 drive-strength = <16>;
4303 cmd-pins {
4305 bias-pull-up;
4306 drive-strength = <10>;
4309 data-pins {
4311 bias-pull-up;
4312 drive-strength = <10>;
4318 compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500";
4320 #iommu-cells = <2>;
4321 #global-interrupts = <1>;
4419 dma-coherent;
4422 intc: interrupt-controller@17100000 {
4423 compatible = "arm,gic-v3";
4427 #interrupt-cells = <3>;
4428 interrupt-controller;
4429 #redistributor-regions = <1>;
4430 redistributor-stride = <0 0x40000>;
4432 #address-cells = <2>;
4433 #size-cells = <2>;
4435 gic_its: msi-controller@17140000 {
4436 compatible = "arm,gic-v3-its";
4438 msi-controller;
4439 #msi-cells = <1>;
4444 compatible = "arm,armv7-timer-mem";
4447 #address-cells = <1>;
4448 #size-cells = <1>;
4453 frame-number = <0>;
4460 frame-number = <1>;
4467 frame-number = <2>;
4474 frame-number = <3>;
4481 frame-number = <4>;
4488 frame-number = <5>;
4495 frame-number = <6>;
4503 compatible = "qcom,rpmh-rsc";
4508 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4512 qcom,tcs-offset = <0xd00>;
4513 qcom,drv-id = <2>;
4514 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
4516 power-domains = <&cluster_pd>;
4518 apps_bcm_voter: bcm-voter {
4519 compatible = "qcom,bcm-voter";
4522 rpmhcc: clock-controller {
4523 compatible = "qcom,sm8550-rpmh-clk";
4524 #clock-cells = <1>;
4525 clock-names = "xo";
4529 rpmhpd: power-controller {
4530 compatible = "qcom,sm8550-rpmhpd";
4531 #power-domain-cells = <1>;
4532 operating-points-v2 = <&rpmhpd_opp_table>;
4534 rpmhpd_opp_table: opp-table {
4535 compatible = "operating-points-v2";
4537 rpmhpd_opp_ret: opp-16 {
4538 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4541 rpmhpd_opp_min_svs: opp-48 {
4542 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4545 rpmhpd_opp_low_svs_d2: opp-52 {
4546 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
4549 rpmhpd_opp_low_svs_d1: opp-56 {
4550 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
4553 rpmhpd_opp_low_svs_d0: opp-60 {
4554 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
4557 rpmhpd_opp_low_svs: opp-64 {
4558 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4561 rpmhpd_opp_low_svs_l1: opp-80 {
4562 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
4565 rpmhpd_opp_svs: opp-128 {
4566 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4569 rpmhpd_opp_svs_l0: opp-144 {
4570 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
4573 rpmhpd_opp_svs_l1: opp-192 {
4574 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4577 rpmhpd_opp_nom: opp-256 {
4578 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4581 rpmhpd_opp_nom_l1: opp-320 {
4582 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4585 rpmhpd_opp_nom_l2: opp-336 {
4586 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4589 rpmhpd_opp_turbo: opp-384 {
4590 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4593 rpmhpd_opp_turbo_l1: opp-416 {
4594 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4601 compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss";
4605 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
4607 clock-names = "xo", "alternate";
4611 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4612 #freq-domain-cells = <1>;
4613 #clock-cells = <1>;
4617 compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
4622 operating-points-v2 = <&llcc_bwmon_opp_table>;
4624 llcc_bwmon_opp_table: opp-table {
4625 compatible = "operating-points-v2";
4627 opp-0 {
4628 opp-peak-kBps = <2086000>;
4631 opp-1 {
4632 opp-peak-kBps = <2929000>;
4635 opp-2 {
4636 opp-peak-kBps = <5931000>;
4639 opp-3 {
4640 opp-peak-kBps = <6515000>;
4643 opp-4 {
4644 opp-peak-kBps = <7980000>;
4647 opp-5 {
4648 opp-peak-kBps = <10437000>;
4651 opp-6 {
4652 opp-peak-kBps = <12157000>;
4655 opp-7 {
4656 opp-peak-kBps = <14060000>;
4659 opp-8 {
4660 opp-peak-kBps = <16113000>;
4666 compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon";
4671 operating-points-v2 = <&cpu_bwmon_opp_table>;
4673 cpu_bwmon_opp_table: opp-table {
4674 compatible = "operating-points-v2";
4676 opp-0 {
4677 opp-peak-kBps = <4577000>;
4680 opp-1 {
4681 opp-peak-kBps = <7110000>;
4684 opp-2 {
4685 opp-peak-kBps = <9155000>;
4688 opp-3 {
4689 opp-peak-kBps = <12298000>;
4692 opp-4 {
4693 opp-peak-kBps = <14236000>;
4696 opp-5 {
4697 opp-peak-kBps = <16265000>;
4703 compatible = "qcom,sm8550-gem-noc";
4705 #interconnect-cells = <2>;
4706 qcom,bcm-voters = <&apps_bcm_voter>;
4709 system-cache-controller@25000000 {
4710 compatible = "qcom,sm8550-llcc";
4717 reg-names = "llcc0_base",
4727 compatible = "qcom,sm8550-nsp-noc";
4729 #interconnect-cells = <2>;
4730 qcom,bcm-voters = <&apps_bcm_voter>;
4734 compatible = "qcom,sm8550-cdsp-pas";
4737 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
4742 interrupt-names = "wdog", "fatal", "ready",
4743 "handover", "stop-ack";
4746 clock-names = "xo";
4748 power-domains = <&rpmhpd RPMHPD_CX>,
4751 power-domain-names = "cx", "mxc", "nsp";
4755 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>;
4759 qcom,smem-states = <&smp2p_cdsp_out 0>;
4760 qcom,smem-state-names = "stop";
4764 glink-edge {
4765 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
4772 qcom,remote-pid = <5>;
4776 qcom,glink-channels = "fastrpcglink-apps-dsp";
4778 qcom,non-secure-domain;
4779 #address-cells = <1>;
4780 #size-cells = <0>;
4782 compute-cb@1 {
4783 compatible = "qcom,fastrpc-compute-cb";
4788 dma-coherent;
4791 compute-cb@2 {
4792 compatible = "qcom,fastrpc-compute-cb";
4797 dma-coherent;
4800 compute-cb@3 {
4801 compatible = "qcom,fastrpc-compute-cb";
4806 dma-coherent;
4809 compute-cb@4 {
4810 compatible = "qcom,fastrpc-compute-cb";
4815 dma-coherent;
4818 compute-cb@5 {
4819 compatible = "qcom,fastrpc-compute-cb";
4824 dma-coherent;
4827 compute-cb@6 {
4828 compatible = "qcom,fastrpc-compute-cb";
4833 dma-coherent;
4836 compute-cb@7 {
4837 compatible = "qcom,fastrpc-compute-cb";
4842 dma-coherent;
4845 compute-cb@8 {
4846 compatible = "qcom,fastrpc-compute-cb";
4851 dma-coherent;
4860 thermal-zones {
4861 aoss0-thermal {
4862 thermal-sensors = <&tsens0 0>;
4865 thermal-engine-config {
4871 reset-mon-config {
4879 cpuss0-thermal {
4880 thermal-sensors = <&tsens0 1>;
4883 thermal-engine-config {
4889 reset-mon-config {
4897 cpuss1-thermal {
4898 thermal-sensors = <&tsens0 2>;
4901 thermal-engine-config {
4907 reset-mon-config {
4915 cpuss2-thermal {
4916 thermal-sensors = <&tsens0 3>;
4919 thermal-engine-config {
4925 reset-mon-config {
4933 cpuss3-thermal {
4934 thermal-sensors = <&tsens0 4>;
4937 thermal-engine-config {
4943 reset-mon-config {
4951 cpu3-top-thermal {
4952 thermal-sensors = <&tsens0 5>;
4955 cpu3_top_alert0: trip-point0 {
4961 cpu3_top_alert1: trip-point1 {
4967 cpu3_top_crit: cpu-critical {
4975 cpu3-bottom-thermal {
4976 thermal-sensors = <&tsens0 6>;
4979 cpu3_bottom_alert0: trip-point0 {
4985 cpu3_bottom_alert1: trip-point1 {
4991 cpu3_bottom_crit: cpu-critical {
4999 cpu4-top-thermal {
5000 thermal-sensors = <&tsens0 7>;
5003 cpu4_top_alert0: trip-point0 {
5009 cpu4_top_alert1: trip-point1 {
5015 cpu4_top_crit: cpu-critical {
5023 cpu4-bottom-thermal {
5024 thermal-sensors = <&tsens0 8>;
5027 cpu4_bottom_alert0: trip-point0 {
5033 cpu4_bottom_alert1: trip-point1 {
5039 cpu4_bottom_crit: cpu-critical {
5047 cpu5-top-thermal {
5048 thermal-sensors = <&tsens0 9>;
5051 cpu5_top_alert0: trip-point0 {
5057 cpu5_top_alert1: trip-point1 {
5063 cpu5_top_crit: cpu-critical {
5071 cpu5-bottom-thermal {
5072 thermal-sensors = <&tsens0 10>;
5075 cpu5_bottom_alert0: trip-point0 {
5081 cpu5_bottom_alert1: trip-point1 {
5087 cpu5_bottom_crit: cpu-critical {
5095 cpu6-top-thermal {
5096 thermal-sensors = <&tsens0 11>;
5099 cpu6_top_alert0: trip-point0 {
5105 cpu6_top_alert1: trip-point1 {
5111 cpu6_top_crit: cpu-critical {
5119 cpu6-bottom-thermal {
5120 thermal-sensors = <&tsens0 12>;
5123 cpu6_bottom_alert0: trip-point0 {
5129 cpu6_bottom_alert1: trip-point1 {
5135 cpu6_bottom_crit: cpu-critical {
5143 cpu7-top-thermal {
5144 thermal-sensors = <&tsens0 13>;
5147 cpu7_top_alert0: trip-point0 {
5153 cpu7_top_alert1: trip-point1 {
5159 cpu7_top_crit: cpu-critical {
5167 cpu7-middle-thermal {
5168 thermal-sensors = <&tsens0 14>;
5171 cpu7_middle_alert0: trip-point0 {
5177 cpu7_middle_alert1: trip-point1 {
5183 cpu7_middle_crit: cpu-critical {
5191 cpu7-bottom-thermal {
5192 thermal-sensors = <&tsens0 15>;
5195 cpu7_bottom_alert0: trip-point0 {
5201 cpu7_bottom_alert1: trip-point1 {
5207 cpu7_bottom_crit: cpu-critical {
5215 aoss1-thermal {
5216 thermal-sensors = <&tsens1 0>;
5219 thermal-engine-config {
5225 reset-mon-config {
5233 cpu0-thermal {
5234 thermal-sensors = <&tsens1 1>;
5237 cpu0_alert0: trip-point0 {
5243 cpu0_alert1: trip-point1 {
5249 cpu0_crit: cpu-critical {
5257 cpu1-thermal {
5258 thermal-sensors = <&tsens1 2>;
5261 cpu1_alert0: trip-point0 {
5267 cpu1_alert1: trip-point1 {
5273 cpu1_crit: cpu-critical {
5281 cpu2-thermal {
5282 thermal-sensors = <&tsens1 3>;
5285 cpu2_alert0: trip-point0 {
5291 cpu2_alert1: trip-point1 {
5297 cpu2_crit: cpu-critical {
5305 cdsp0-thermal {
5306 polling-delay-passive = <10>;
5308 thermal-sensors = <&tsens2 4>;
5311 thermal-engine-config {
5317 thermal-hal-config {
5323 reset-mon-config {
5329 cdsp0_junction_config: junction-config {
5337 cdsp1-thermal {
5338 polling-delay-passive = <10>;
5340 thermal-sensors = <&tsens2 5>;
5343 thermal-engine-config {
5349 thermal-hal-config {
5355 reset-mon-config {
5361 cdsp1_junction_config: junction-config {
5369 cdsp2-thermal {
5370 polling-delay-passive = <10>;
5372 thermal-sensors = <&tsens2 6>;
5375 thermal-engine-config {
5381 thermal-hal-config {
5387 reset-mon-config {
5393 cdsp2_junction_config: junction-config {
5401 cdsp3-thermal {
5402 polling-delay-passive = <10>;
5404 thermal-sensors = <&tsens2 7>;
5407 thermal-engine-config {
5413 thermal-hal-config {
5419 reset-mon-config {
5425 cdsp3_junction_config: junction-config {
5433 video-thermal {
5434 thermal-sensors = <&tsens1 8>;
5437 thermal-engine-config {
5443 reset-mon-config {
5451 mem-thermal {
5452 polling-delay-passive = <10>;
5454 thermal-sensors = <&tsens1 9>;
5457 thermal-engine-config {
5463 ddr_config0: ddr0-config {
5469 reset-mon-config {
5477 modem0-thermal {
5478 thermal-sensors = <&tsens1 10>;
5481 thermal-engine-config {
5487 mdmss0_config0: mdmss0-config0 {
5493 mdmss0_config1: mdmss0-config1 {
5499 reset-mon-config {
5507 modem1-thermal {
5508 thermal-sensors = <&tsens1 11>;
5511 thermal-engine-config {
5517 mdmss1_config0: mdmss1-config0 {
5523 mdmss1_config1: mdmss1-config1 {
5529 reset-mon-config {
5537 modem2-thermal {
5538 thermal-sensors = <&tsens1 12>;
5541 thermal-engine-config {
5547 mdmss2_config0: mdmss2-config0 {
5553 mdmss2_config1: mdmss2-config1 {
5559 reset-mon-config {
5567 modem3-thermal {
5568 thermal-sensors = <&tsens1 13>;
5571 thermal-engine-config {
5577 mdmss3_config0: mdmss3-config0 {
5583 mdmss3_config1: mdmss3-config1 {
5589 reset-mon-config {
5597 camera0-thermal {
5598 thermal-sensors = <&tsens1 14>;
5601 thermal-engine-config {
5607 reset-mon-config {
5615 camera1-thermal {
5616 thermal-sensors = <&tsens1 15>;
5619 thermal-engine-config {
5625 reset-mon-config {
5633 aoss2-thermal {
5634 thermal-sensors = <&tsens2 0>;
5637 thermal-engine-config {
5643 reset-mon-config {
5651 gpuss-0-thermal {
5652 polling-delay-passive = <10>;
5654 thermal-sensors = <&tsens2 1>;
5656 cooling-maps {
5659 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5664 gpu0_alert0: trip-point0 {
5670 trip-point1 {
5676 trip-point2 {
5684 gpuss-1-thermal {
5685 polling-delay-passive = <10>;
5687 thermal-sensors = <&tsens2 2>;
5689 cooling-maps {
5692 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5697 gpu1_alert0: trip-point0 {
5703 trip-point1 {
5709 trip-point2 {
5717 gpuss-2-thermal {
5718 polling-delay-passive = <10>;
5720 thermal-sensors = <&tsens2 3>;
5722 cooling-maps {
5725 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5730 gpu2_alert0: trip-point0 {
5736 trip-point1 {
5742 trip-point2 {
5750 gpuss-3-thermal {
5751 polling-delay-passive = <10>;
5753 thermal-sensors = <&tsens2 4>;
5755 cooling-maps {
5758 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5763 gpu3_alert0: trip-point0 {
5769 trip-point1 {
5775 trip-point2 {
5783 gpuss-4-thermal {
5784 polling-delay-passive = <10>;
5786 thermal-sensors = <&tsens2 5>;
5788 cooling-maps {
5791 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5796 gpu4_alert0: trip-point0 {
5802 trip-point1 {
5808 trip-point2 {
5816 gpuss-5-thermal {
5817 polling-delay-passive = <10>;
5819 thermal-sensors = <&tsens2 6>;
5821 cooling-maps {
5824 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5829 gpu5_alert0: trip-point0 {
5835 trip-point1 {
5841 trip-point2 {
5849 gpuss-6-thermal {
5850 polling-delay-passive = <10>;
5852 thermal-sensors = <&tsens2 7>;
5854 cooling-maps {
5857 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5862 gpu6_alert0: trip-point0 {
5868 trip-point1 {
5874 trip-point2 {
5882 gpuss-7-thermal {
5883 polling-delay-passive = <10>;
5885 thermal-sensors = <&tsens2 8>;
5887 cooling-maps {
5890 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5895 gpu7_alert0: trip-point0 {
5901 trip-point1 {
5907 trip-point2 {
5917 compatible = "arm,armv8-timer";