Lines Matching +full:smem +full:- +full:part
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
8 #include <dt-bindings/clock/qcom,sm8550-camcc.h>
9 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
10 #include <dt-bindings/clock/qcom,sm8550-gpucc.h>
11 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
12 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
18 #include <dt-bindings/mailbox/qcom-ipcc.h>
19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/power/qcom,rpmhpd.h>
21 #include <dt-bindings/soc/qcom,gpr.h>
22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
23 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
24 #include <dt-bindings/phy/phy-qcom-qmp.h>
25 #include <dt-bindings/thermal/thermal.h>
28 interrupt-parent = <&intc>;
30 #address-cells = <2>;
31 #size-cells = <2>;
36 xo_board: xo-board {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
41 sleep_clk: sleep-clk {
42 compatible = "fixed-clock";
43 #clock-cells = <0>;
46 bi_tcxo_div2: bi-tcxo-div2-clk {
47 #clock-cells = <0>;
48 compatible = "fixed-factor-clock";
50 clock-mult = <1>;
51 clock-div = <2>;
54 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
55 #clock-cells = <0>;
56 compatible = "fixed-factor-clock";
58 clock-mult = <1>;
59 clock-div = <2>;
64 #address-cells = <2>;
65 #size-cells = <0>;
69 compatible = "arm,cortex-a510";
72 enable-method = "psci";
73 next-level-cache = <&l2_0>;
74 power-domains = <&cpu_pd0>;
75 power-domain-names = "psci";
76 qcom,freq-domain = <&cpufreq_hw 0>;
77 capacity-dmips-mhz = <1024>;
78 dynamic-power-coefficient = <100>;
79 #cooling-cells = <2>;
80 l2_0: l2-cache {
82 cache-level = <2>;
83 cache-unified;
84 next-level-cache = <&l3_0>;
85 l3_0: l3-cache {
87 cache-level = <3>;
88 cache-unified;
95 compatible = "arm,cortex-a510";
98 enable-method = "psci";
99 next-level-cache = <&l2_100>;
100 power-domains = <&cpu_pd1>;
101 power-domain-names = "psci";
102 qcom,freq-domain = <&cpufreq_hw 0>;
103 capacity-dmips-mhz = <1024>;
104 dynamic-power-coefficient = <100>;
105 #cooling-cells = <2>;
106 l2_100: l2-cache {
108 cache-level = <2>;
109 cache-unified;
110 next-level-cache = <&l3_0>;
116 compatible = "arm,cortex-a510";
119 enable-method = "psci";
120 next-level-cache = <&l2_200>;
121 power-domains = <&cpu_pd2>;
122 power-domain-names = "psci";
123 qcom,freq-domain = <&cpufreq_hw 0>;
124 capacity-dmips-mhz = <1024>;
125 dynamic-power-coefficient = <100>;
126 #cooling-cells = <2>;
127 l2_200: l2-cache {
129 cache-level = <2>;
130 cache-unified;
131 next-level-cache = <&l3_0>;
137 compatible = "arm,cortex-a715";
140 enable-method = "psci";
141 next-level-cache = <&l2_300>;
142 power-domains = <&cpu_pd3>;
143 power-domain-names = "psci";
144 qcom,freq-domain = <&cpufreq_hw 1>;
145 capacity-dmips-mhz = <1792>;
146 dynamic-power-coefficient = <270>;
147 #cooling-cells = <2>;
148 l2_300: l2-cache {
150 cache-level = <2>;
151 cache-unified;
152 next-level-cache = <&l3_0>;
158 compatible = "arm,cortex-a715";
161 enable-method = "psci";
162 next-level-cache = <&l2_400>;
163 power-domains = <&cpu_pd4>;
164 power-domain-names = "psci";
165 qcom,freq-domain = <&cpufreq_hw 1>;
166 capacity-dmips-mhz = <1792>;
167 dynamic-power-coefficient = <270>;
168 #cooling-cells = <2>;
169 l2_400: l2-cache {
171 cache-level = <2>;
172 cache-unified;
173 next-level-cache = <&l3_0>;
179 compatible = "arm,cortex-a710";
182 enable-method = "psci";
183 next-level-cache = <&l2_500>;
184 power-domains = <&cpu_pd5>;
185 power-domain-names = "psci";
186 qcom,freq-domain = <&cpufreq_hw 1>;
187 capacity-dmips-mhz = <1792>;
188 dynamic-power-coefficient = <270>;
189 #cooling-cells = <2>;
190 l2_500: l2-cache {
192 cache-level = <2>;
193 cache-unified;
194 next-level-cache = <&l3_0>;
200 compatible = "arm,cortex-a710";
203 enable-method = "psci";
204 next-level-cache = <&l2_600>;
205 power-domains = <&cpu_pd6>;
206 power-domain-names = "psci";
207 qcom,freq-domain = <&cpufreq_hw 1>;
208 capacity-dmips-mhz = <1792>;
209 dynamic-power-coefficient = <270>;
210 #cooling-cells = <2>;
211 l2_600: l2-cache {
213 cache-level = <2>;
214 cache-unified;
215 next-level-cache = <&l3_0>;
221 compatible = "arm,cortex-x3";
224 enable-method = "psci";
225 next-level-cache = <&l2_700>;
226 power-domains = <&cpu_pd7>;
227 power-domain-names = "psci";
228 qcom,freq-domain = <&cpufreq_hw 2>;
229 capacity-dmips-mhz = <1894>;
230 dynamic-power-coefficient = <588>;
231 #cooling-cells = <2>;
232 l2_700: l2-cache {
234 cache-level = <2>;
235 cache-unified;
236 next-level-cache = <&l3_0>;
240 cpu-map {
276 idle-states {
277 entry-method = "psci";
279 little_cpu_sleep_0: cpu-sleep-0-0 {
280 compatible = "arm,idle-state";
281 idle-state-name = "silver-rail-power-collapse";
282 arm,psci-suspend-param = <0x40000004>;
283 entry-latency-us = <550>;
284 exit-latency-us = <750>;
285 min-residency-us = <6700>;
286 local-timer-stop;
289 big_cpu_sleep_0: cpu-sleep-1-0 {
290 compatible = "arm,idle-state";
291 idle-state-name = "gold-rail-power-collapse";
292 arm,psci-suspend-param = <0x40000004>;
293 entry-latency-us = <600>;
294 exit-latency-us = <1300>;
295 min-residency-us = <8136>;
296 local-timer-stop;
299 prime_cpu_sleep_0: cpu-sleep-2-0 {
300 compatible = "arm,idle-state";
301 idle-state-name = "goldplus-rail-power-collapse";
302 arm,psci-suspend-param = <0x40000004>;
303 entry-latency-us = <500>;
304 exit-latency-us = <1350>;
305 min-residency-us = <7480>;
306 local-timer-stop;
310 domain-idle-states {
311 cluster_sleep_0: cluster-sleep-0 {
312 compatible = "domain-idle-state";
313 arm,psci-suspend-param = <0x41000044>;
314 entry-latency-us = <750>;
315 exit-latency-us = <2350>;
316 min-residency-us = <9144>;
319 cluster_sleep_1: cluster-sleep-1 {
320 compatible = "domain-idle-state";
321 arm,psci-suspend-param = <0x4100c344>;
322 entry-latency-us = <2800>;
323 exit-latency-us = <4400>;
324 min-residency-us = <10150>;
331 compatible = "qcom,scm-sm8550", "qcom,scm";
332 qcom,dload-mode = <&tcsr 0x19000>;
337 clk_virt: interconnect-0 {
338 compatible = "qcom,sm8550-clk-virt";
339 #interconnect-cells = <2>;
340 qcom,bcm-voters = <&apps_bcm_voter>;
343 mc_virt: interconnect-1 {
344 compatible = "qcom,sm8550-mc-virt";
345 #interconnect-cells = <2>;
346 qcom,bcm-voters = <&apps_bcm_voter>;
355 pmu-a510 {
356 compatible = "arm,cortex-a510-pmu";
360 pmu-a710 {
361 compatible = "arm,cortex-a710-pmu";
365 pmu-a715 {
366 compatible = "arm,cortex-a715-pmu";
370 pmu-x3 {
371 compatible = "arm,cortex-x3-pmu";
376 compatible = "arm,psci-1.0";
379 cpu_pd0: power-domain-cpu0 {
380 #power-domain-cells = <0>;
381 power-domains = <&cluster_pd>;
382 domain-idle-states = <&little_cpu_sleep_0>;
385 cpu_pd1: power-domain-cpu1 {
386 #power-domain-cells = <0>;
387 power-domains = <&cluster_pd>;
388 domain-idle-states = <&little_cpu_sleep_0>;
391 cpu_pd2: power-domain-cpu2 {
392 #power-domain-cells = <0>;
393 power-domains = <&cluster_pd>;
394 domain-idle-states = <&little_cpu_sleep_0>;
397 cpu_pd3: power-domain-cpu3 {
398 #power-domain-cells = <0>;
399 power-domains = <&cluster_pd>;
400 domain-idle-states = <&big_cpu_sleep_0>;
403 cpu_pd4: power-domain-cpu4 {
404 #power-domain-cells = <0>;
405 power-domains = <&cluster_pd>;
406 domain-idle-states = <&big_cpu_sleep_0>;
409 cpu_pd5: power-domain-cpu5 {
410 #power-domain-cells = <0>;
411 power-domains = <&cluster_pd>;
412 domain-idle-states = <&big_cpu_sleep_0>;
415 cpu_pd6: power-domain-cpu6 {
416 #power-domain-cells = <0>;
417 power-domains = <&cluster_pd>;
418 domain-idle-states = <&big_cpu_sleep_0>;
421 cpu_pd7: power-domain-cpu7 {
422 #power-domain-cells = <0>;
423 power-domains = <&cluster_pd>;
424 domain-idle-states = <&prime_cpu_sleep_0>;
427 cluster_pd: power-domain-cluster {
428 #power-domain-cells = <0>;
429 domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>;
433 reserved_memory: reserved-memory {
434 #address-cells = <2>;
435 #size-cells = <2>;
438 hyp_mem: hyp-region@80000000 {
440 no-map;
443 cpusys_vm_mem: cpusys-vm-region@80a00000 {
445 no-map;
448 hyp_tags_mem: hyp-tags-region@80e00000 {
450 no-map;
453 xbl_sc_mem: xbl-sc-region@d8100000 {
455 no-map;
458 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 {
460 no-map;
464 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 {
466 no-map;
469 aop_cmd_db_mem: aop-cmd-db-region@81c60000 {
470 compatible = "qcom,cmd-db";
472 no-map;
476 aop_config_merged_mem: aop-config-merged-region@81c80000 {
478 no-map;
482 smem: smem@81d00000 { label
483 compatible = "qcom,smem";
486 no-map;
489 adsp_mhi_mem: adsp-mhi-region@81f00000 {
491 no-map;
494 global_sync_mem: global-sync-region@82600000 {
496 no-map;
499 tz_stat_mem: tz-stat-region@82700000 {
501 no-map;
504 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 {
506 no-map;
509 mpss_mem: mpss-region@8a800000 {
511 no-map;
514 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 {
516 no-map;
519 ipa_fw_mem: ipa-fw-region@9b080000 {
521 no-map;
524 ipa_gsi_mem: ipa-gsi-region@9b090000 {
526 no-map;
529 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 {
531 no-map;
534 spss_region_mem: spss-region@9b100000 {
536 no-map;
539 /* First part of the "SPU secure shared memory" region */
540 spu_tz_shared_mem: spu-tz-shared-region@9b280000 {
542 no-map;
545 /* Second part of the "SPU secure shared memory" region */
546 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 {
548 no-map;
551 camera_mem: camera-region@9b300000 {
553 no-map;
556 video_mem: video-region@9bb00000 {
558 no-map;
561 cvp_mem: cvp-region@9c200000 {
563 no-map;
566 cdsp_mem: cdsp-region@9c900000 {
568 no-map;
571 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 {
573 no-map;
576 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 {
578 no-map;
581 adspslpi_mem: adspslpi-region@9ea00000 {
583 no-map;
590 rmtfs_mem: rmtfs-region@d4a80000 {
591 compatible = "qcom,rmtfs-mem";
593 no-map;
595 qcom,client-id = <1>;
599 mpss_dsm_mem: mpss-dsm-region@d4d00000 {
601 no-map;
604 tz_reserved_mem: tz-reserved-region@d8000000 {
606 no-map;
609 cpucp_fw_mem: cpucp-fw-region@d8140000 {
611 no-map;
614 qtee_mem: qtee-region@d8300000 {
616 no-map;
619 ta_mem: ta-region@d8800000 {
621 no-map;
624 tz_tags_mem: tz-tags-region@e1200000 {
626 no-map;
629 hwfence_shbuf: hwfence-shbuf-region@e6440000 {
631 no-map;
634 trust_ui_vm_mem: trust-ui-vm-region@f3600000 {
636 no-map;
639 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 {
641 no-map;
644 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 {
646 no-map;
649 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 {
651 no-map;
654 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 {
656 no-map;
659 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 {
661 no-map;
664 oem_vm_mem: oem-vm-region@f8400000 {
666 no-map;
669 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 {
671 no-map;
674 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 {
676 no-map;
679 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 {
681 no-map;
684 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 {
686 no-map;
690 smp2p-adsp {
692 qcom,smem = <443>, <429>;
693 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
699 qcom,local-pid = <0>;
700 qcom,remote-pid = <2>;
702 smp2p_adsp_out: master-kernel {
703 qcom,entry-name = "master-kernel";
704 #qcom,smem-state-cells = <1>;
707 smp2p_adsp_in: slave-kernel {
708 qcom,entry-name = "slave-kernel";
709 interrupt-controller;
710 #interrupt-cells = <2>;
714 smp2p-cdsp {
716 qcom,smem = <94>, <432>;
717 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
723 qcom,local-pid = <0>;
724 qcom,remote-pid = <5>;
726 smp2p_cdsp_out: master-kernel {
727 qcom,entry-name = "master-kernel";
728 #qcom,smem-state-cells = <1>;
731 smp2p_cdsp_in: slave-kernel {
732 qcom,entry-name = "slave-kernel";
733 interrupt-controller;
734 #interrupt-cells = <2>;
738 smp2p-modem {
740 qcom,smem = <435>, <428>;
741 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
747 qcom,local-pid = <0>;
748 qcom,remote-pid = <1>;
750 smp2p_modem_out: master-kernel {
751 qcom,entry-name = "master-kernel";
752 #qcom,smem-state-cells = <1>;
755 smp2p_modem_in: slave-kernel {
756 qcom,entry-name = "slave-kernel";
757 interrupt-controller;
758 #interrupt-cells = <2>;
761 ipa_smp2p_out: ipa-ap-to-modem {
762 qcom,entry-name = "ipa";
763 #qcom,smem-state-cells = <1>;
766 ipa_smp2p_in: ipa-modem-to-ap {
767 qcom,entry-name = "ipa";
768 interrupt-controller;
769 #interrupt-cells = <2>;
774 compatible = "simple-bus";
776 dma-ranges = <0 0 0 0 0x10 0>;
778 #address-cells = <2>;
779 #size-cells = <2>;
781 gcc: clock-controller@100000 {
782 compatible = "qcom,sm8550-gcc";
784 #clock-cells = <1>;
785 #reset-cells = <1>;
786 #power-domain-cells = <1>;
798 compatible = "qcom,sm8550-ipcc", "qcom,ipcc";
801 interrupt-controller;
802 #interrupt-cells = <3>;
803 #mbox-cells = <2>;
806 gpi_dma2: dma-controller@800000 {
807 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
808 #dma-cells = <3>;
822 dma-channels = <12>;
823 dma-channel-mask = <0x3e>;
825 dma-coherent;
830 compatible = "qcom,geni-se-qup";
833 clock-names = "m-ahb", "s-ahb";
837 dma-coherent;
838 #address-cells = <2>;
839 #size-cells = <2>;
843 compatible = "qcom,geni-i2c";
845 clock-names = "se";
847 pinctrl-names = "default";
848 pinctrl-0 = <&qup_i2c8_data_clk>;
850 #address-cells = <1>;
851 #size-cells = <0>;
855 interconnect-names = "qup-core", "qup-config", "qup-memory";
858 dma-names = "tx", "rx";
863 compatible = "qcom,geni-spi";
865 clock-names = "se";
868 pinctrl-names = "default";
869 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
873 interconnect-names = "qup-core", "qup-config", "qup-memory";
876 dma-names = "tx", "rx";
877 #address-cells = <1>;
878 #size-cells = <0>;
883 compatible = "qcom,geni-i2c";
885 clock-names = "se";
887 pinctrl-names = "default";
888 pinctrl-0 = <&qup_i2c9_data_clk>;
890 #address-cells = <1>;
891 #size-cells = <0>;
895 interconnect-names = "qup-core", "qup-config", "qup-memory";
898 dma-names = "tx", "rx";
903 compatible = "qcom,geni-spi";
905 clock-names = "se";
908 pinctrl-names = "default";
909 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
913 interconnect-names = "qup-core", "qup-config", "qup-memory";
916 dma-names = "tx", "rx";
917 #address-cells = <1>;
918 #size-cells = <0>;
923 compatible = "qcom,geni-i2c";
925 clock-names = "se";
927 pinctrl-names = "default";
928 pinctrl-0 = <&qup_i2c10_data_clk>;
930 #address-cells = <1>;
931 #size-cells = <0>;
935 interconnect-names = "qup-core", "qup-config", "qup-memory";
938 dma-names = "tx", "rx";
943 compatible = "qcom,geni-spi";
945 clock-names = "se";
948 pinctrl-names = "default";
949 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
953 interconnect-names = "qup-core", "qup-config", "qup-memory";
956 dma-names = "tx", "rx";
957 #address-cells = <1>;
958 #size-cells = <0>;
963 compatible = "qcom,geni-i2c";
965 clock-names = "se";
967 pinctrl-names = "default";
968 pinctrl-0 = <&qup_i2c11_data_clk>;
970 #address-cells = <1>;
971 #size-cells = <0>;
975 interconnect-names = "qup-core", "qup-config", "qup-memory";
978 dma-names = "tx", "rx";
983 compatible = "qcom,geni-spi";
985 clock-names = "se";
988 pinctrl-names = "default";
989 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
993 interconnect-names = "qup-core", "qup-config", "qup-memory";
996 dma-names = "tx", "rx";
997 #address-cells = <1>;
998 #size-cells = <0>;
1003 compatible = "qcom,geni-i2c";
1005 clock-names = "se";
1007 pinctrl-names = "default";
1008 pinctrl-0 = <&qup_i2c12_data_clk>;
1010 #address-cells = <1>;
1011 #size-cells = <0>;
1015 interconnect-names = "qup-core", "qup-config", "qup-memory";
1018 dma-names = "tx", "rx";
1023 compatible = "qcom,geni-spi";
1025 clock-names = "se";
1028 pinctrl-names = "default";
1029 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1033 interconnect-names = "qup-core", "qup-config", "qup-memory";
1036 dma-names = "tx", "rx";
1037 #address-cells = <1>;
1038 #size-cells = <0>;
1043 compatible = "qcom,geni-i2c";
1045 clock-names = "se";
1047 pinctrl-names = "default";
1048 pinctrl-0 = <&qup_i2c13_data_clk>;
1050 #address-cells = <1>;
1051 #size-cells = <0>;
1055 interconnect-names = "qup-core", "qup-config", "qup-memory";
1058 dma-names = "tx", "rx";
1063 compatible = "qcom,geni-spi";
1065 clock-names = "se";
1068 pinctrl-names = "default";
1069 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1073 interconnect-names = "qup-core", "qup-config", "qup-memory";
1076 dma-names = "tx", "rx";
1077 #address-cells = <1>;
1078 #size-cells = <0>;
1083 compatible = "qcom,geni-uart";
1085 clock-names = "se";
1087 pinctrl-names = "default";
1088 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
1092 interconnect-names = "qup-core", "qup-config";
1097 compatible = "qcom,geni-i2c";
1099 clock-names = "se";
1101 pinctrl-names = "default";
1102 pinctrl-0 = <&qup_i2c15_data_clk>;
1104 #address-cells = <1>;
1105 #size-cells = <0>;
1109 interconnect-names = "qup-core", "qup-config", "qup-memory";
1112 dma-names = "tx", "rx";
1117 compatible = "qcom,geni-spi";
1119 clock-names = "se";
1122 pinctrl-names = "default";
1123 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1127 interconnect-names = "qup-core", "qup-config", "qup-memory";
1130 dma-names = "tx", "rx";
1131 #address-cells = <1>;
1132 #size-cells = <0>;
1138 compatible = "qcom,geni-se-i2c-master-hub";
1140 clock-names = "s-ahb";
1142 #address-cells = <2>;
1143 #size-cells = <2>;
1148 compatible = "qcom,geni-i2c-master-hub";
1150 clock-names = "se", "core";
1153 pinctrl-names = "default";
1154 pinctrl-0 = <&hub_i2c0_data_clk>;
1156 #address-cells = <1>;
1157 #size-cells = <0>;
1160 interconnect-names = "qup-core", "qup-config";
1165 compatible = "qcom,geni-i2c-master-hub";
1167 clock-names = "se", "core";
1170 pinctrl-names = "default";
1171 pinctrl-0 = <&hub_i2c1_data_clk>;
1173 #address-cells = <1>;
1174 #size-cells = <0>;
1177 interconnect-names = "qup-core", "qup-config";
1182 compatible = "qcom,geni-i2c-master-hub";
1184 clock-names = "se", "core";
1187 pinctrl-names = "default";
1188 pinctrl-0 = <&hub_i2c2_data_clk>;
1190 #address-cells = <1>;
1191 #size-cells = <0>;
1194 interconnect-names = "qup-core", "qup-config";
1199 compatible = "qcom,geni-i2c-master-hub";
1201 clock-names = "se", "core";
1204 pinctrl-names = "default";
1205 pinctrl-0 = <&hub_i2c3_data_clk>;
1207 #address-cells = <1>;
1208 #size-cells = <0>;
1211 interconnect-names = "qup-core", "qup-config";
1216 compatible = "qcom,geni-i2c-master-hub";
1218 clock-names = "se", "core";
1221 pinctrl-names = "default";
1222 pinctrl-0 = <&hub_i2c4_data_clk>;
1224 #address-cells = <1>;
1225 #size-cells = <0>;
1228 interconnect-names = "qup-core", "qup-config";
1233 compatible = "qcom,geni-i2c-master-hub";
1235 clock-names = "se", "core";
1238 pinctrl-names = "default";
1239 pinctrl-0 = <&hub_i2c5_data_clk>;
1241 #address-cells = <1>;
1242 #size-cells = <0>;
1245 interconnect-names = "qup-core", "qup-config";
1250 compatible = "qcom,geni-i2c-master-hub";
1252 clock-names = "se", "core";
1255 pinctrl-names = "default";
1256 pinctrl-0 = <&hub_i2c6_data_clk>;
1258 #address-cells = <1>;
1259 #size-cells = <0>;
1262 interconnect-names = "qup-core", "qup-config";
1267 compatible = "qcom,geni-i2c-master-hub";
1269 clock-names = "se", "core";
1272 pinctrl-names = "default";
1273 pinctrl-0 = <&hub_i2c7_data_clk>;
1275 #address-cells = <1>;
1276 #size-cells = <0>;
1279 interconnect-names = "qup-core", "qup-config";
1284 compatible = "qcom,geni-i2c-master-hub";
1286 clock-names = "se", "core";
1289 pinctrl-names = "default";
1290 pinctrl-0 = <&hub_i2c8_data_clk>;
1292 #address-cells = <1>;
1293 #size-cells = <0>;
1296 interconnect-names = "qup-core", "qup-config";
1301 compatible = "qcom,geni-i2c-master-hub";
1303 clock-names = "se", "core";
1306 pinctrl-names = "default";
1307 pinctrl-0 = <&hub_i2c9_data_clk>;
1309 #address-cells = <1>;
1310 #size-cells = <0>;
1313 interconnect-names = "qup-core", "qup-config";
1318 gpi_dma1: dma-controller@a00000 {
1319 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
1320 #dma-cells = <3>;
1334 dma-channels = <12>;
1335 dma-channel-mask = <0x1e>;
1337 dma-coherent;
1342 compatible = "qcom,geni-se-qup";
1345 clock-names = "m-ahb", "s-ahb";
1350 interconnect-names = "qup-core";
1351 dma-coherent;
1352 #address-cells = <2>;
1353 #size-cells = <2>;
1357 compatible = "qcom,geni-i2c";
1359 clock-names = "se";
1361 pinctrl-names = "default";
1362 pinctrl-0 = <&qup_i2c0_data_clk>;
1364 #address-cells = <1>;
1365 #size-cells = <0>;
1369 interconnect-names = "qup-core", "qup-config", "qup-memory";
1372 dma-names = "tx", "rx";
1377 compatible = "qcom,geni-spi";
1379 clock-names = "se";
1382 pinctrl-names = "default";
1383 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1387 interconnect-names = "qup-core", "qup-config", "qup-memory";
1390 dma-names = "tx", "rx";
1391 #address-cells = <1>;
1392 #size-cells = <0>;
1397 compatible = "qcom,geni-i2c";
1399 clock-names = "se";
1401 pinctrl-names = "default";
1402 pinctrl-0 = <&qup_i2c1_data_clk>;
1404 #address-cells = <1>;
1405 #size-cells = <0>;
1409 interconnect-names = "qup-core", "qup-config", "qup-memory";
1412 dma-names = "tx", "rx";
1417 compatible = "qcom,geni-spi";
1419 clock-names = "se";
1422 pinctrl-names = "default";
1423 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1427 interconnect-names = "qup-core", "qup-config", "qup-memory";
1430 dma-names = "tx", "rx";
1431 #address-cells = <1>;
1432 #size-cells = <0>;
1437 compatible = "qcom,geni-i2c";
1439 clock-names = "se";
1441 pinctrl-names = "default";
1442 pinctrl-0 = <&qup_i2c2_data_clk>;
1444 #address-cells = <1>;
1445 #size-cells = <0>;
1449 interconnect-names = "qup-core", "qup-config", "qup-memory";
1452 dma-names = "tx", "rx";
1457 compatible = "qcom,geni-spi";
1459 clock-names = "se";
1462 pinctrl-names = "default";
1463 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1467 interconnect-names = "qup-core", "qup-config", "qup-memory";
1470 dma-names = "tx", "rx";
1471 #address-cells = <1>;
1472 #size-cells = <0>;
1477 compatible = "qcom,geni-i2c";
1479 clock-names = "se";
1481 pinctrl-names = "default";
1482 pinctrl-0 = <&qup_i2c3_data_clk>;
1484 #address-cells = <1>;
1485 #size-cells = <0>;
1489 interconnect-names = "qup-core", "qup-config", "qup-memory";
1492 dma-names = "tx", "rx";
1497 compatible = "qcom,geni-spi";
1499 clock-names = "se";
1502 pinctrl-names = "default";
1503 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1507 interconnect-names = "qup-core", "qup-config", "qup-memory";
1510 dma-names = "tx", "rx";
1511 #address-cells = <1>;
1512 #size-cells = <0>;
1517 compatible = "qcom,geni-i2c";
1519 clock-names = "se";
1521 pinctrl-names = "default";
1522 pinctrl-0 = <&qup_i2c4_data_clk>;
1524 #address-cells = <1>;
1525 #size-cells = <0>;
1529 interconnect-names = "qup-core", "qup-config", "qup-memory";
1532 dma-names = "tx", "rx";
1537 compatible = "qcom,geni-spi";
1539 clock-names = "se";
1542 pinctrl-names = "default";
1543 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1547 interconnect-names = "qup-core", "qup-config", "qup-memory";
1550 dma-names = "tx", "rx";
1551 #address-cells = <1>;
1552 #size-cells = <0>;
1557 compatible = "qcom,geni-i2c";
1559 clock-names = "se";
1561 pinctrl-names = "default";
1562 pinctrl-0 = <&qup_i2c5_data_clk>;
1567 interconnect-names = "qup-core", "qup-config", "qup-memory";
1570 dma-names = "tx", "rx";
1571 #address-cells = <1>;
1572 #size-cells = <0>;
1577 compatible = "qcom,geni-spi";
1579 clock-names = "se";
1582 pinctrl-names = "default";
1583 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1587 interconnect-names = "qup-core", "qup-config", "qup-memory";
1590 dma-names = "tx", "rx";
1591 #address-cells = <1>;
1592 #size-cells = <0>;
1597 compatible = "qcom,geni-i2c";
1599 clock-names = "se";
1601 pinctrl-names = "default";
1602 pinctrl-0 = <&qup_i2c6_data_clk>;
1607 interconnect-names = "qup-core", "qup-config", "qup-memory";
1610 dma-names = "tx", "rx";
1611 #address-cells = <1>;
1612 #size-cells = <0>;
1617 compatible = "qcom,geni-spi";
1619 clock-names = "se";
1622 pinctrl-names = "default";
1623 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1627 interconnect-names = "qup-core", "qup-config", "qup-memory";
1630 dma-names = "tx", "rx";
1631 #address-cells = <1>;
1632 #size-cells = <0>;
1637 compatible = "qcom,geni-debug-uart";
1639 clock-names = "se";
1641 pinctrl-names = "default";
1642 pinctrl-0 = <&qup_uart7_default>;
1644 interconnect-names = "qup-core", "qup-config";
1652 compatible = "qcom,sm8550-cnoc-main";
1654 #interconnect-cells = <2>;
1655 qcom,bcm-voters = <&apps_bcm_voter>;
1659 compatible = "qcom,sm8550-config-noc";
1661 #interconnect-cells = <2>;
1662 qcom,bcm-voters = <&apps_bcm_voter>;
1666 compatible = "qcom,sm8550-system-noc";
1668 #interconnect-cells = <2>;
1669 qcom,bcm-voters = <&apps_bcm_voter>;
1673 compatible = "qcom,sm8550-pcie-anoc";
1675 #interconnect-cells = <2>;
1678 qcom,bcm-voters = <&apps_bcm_voter>;
1682 compatible = "qcom,sm8550-aggre1-noc";
1684 #interconnect-cells = <2>;
1687 qcom,bcm-voters = <&apps_bcm_voter>;
1691 compatible = "qcom,sm8550-aggre2-noc";
1693 #interconnect-cells = <2>;
1695 qcom,bcm-voters = <&apps_bcm_voter>;
1699 compatible = "qcom,sm8550-mmss-noc";
1701 #interconnect-cells = <2>;
1702 qcom,bcm-voters = <&apps_bcm_voter>;
1706 compatible = "qcom,sm8550-trng", "qcom,trng";
1712 compatible = "qcom,pcie-sm8550";
1718 reg-names = "parf", "dbi", "elbi", "atu", "config";
1719 #address-cells = <3>;
1720 #size-cells = <2>;
1723 bus-range = <0x00 0xff>;
1725 dma-coherent;
1727 linux,pci-domain = <0>;
1728 num-lanes = <2>;
1738 interrupt-names = "msi0",
1746 #interrupt-cells = <1>;
1747 interrupt-map-mask = <0 0 0 0x7>;
1748 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1760 clock-names = "aux",
1770 interconnect-names = "pcie-mem", "cpu-pcie";
1772 msi-map = <0x0 &gic_its 0x1400 0x1>,
1774 iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
1778 reset-names = "pci";
1780 power-domains = <&gcc PCIE_0_GDSC>;
1783 phy-names = "pciephy";
1790 bus-range = <0x01 0xff>;
1792 #address-cells = <3>;
1793 #size-cells = <2>;
1799 compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy";
1807 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1811 reset-names = "phy";
1813 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1814 assigned-clock-rates = <100000000>;
1816 power-domains = <&gcc PCIE_0_PHY_GDSC>;
1818 #clock-cells = <0>;
1819 clock-output-names = "pcie0_pipe_clk";
1821 #phy-cells = <0>;
1828 compatible = "qcom,pcie-sm8550";
1834 reg-names = "parf", "dbi", "elbi", "atu", "config";
1835 #address-cells = <3>;
1836 #size-cells = <2>;
1839 bus-range = <0x00 0xff>;
1841 dma-coherent;
1843 linux,pci-domain = <1>;
1844 num-lanes = <2>;
1854 interrupt-names = "msi0",
1862 #interrupt-cells = <1>;
1863 interrupt-map-mask = <0 0 0 0x7>;
1864 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1877 clock-names = "aux",
1886 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1887 assigned-clock-rates = <19200000>;
1891 interconnect-names = "pcie-mem", "cpu-pcie";
1893 msi-map = <0x0 &gic_its 0x1480 0x1>,
1895 iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
1900 reset-names = "pci", "link_down";
1902 power-domains = <&gcc PCIE_1_GDSC>;
1905 phy-names = "pciephy";
1912 bus-range = <0x01 0xff>;
1914 #address-cells = <3>;
1915 #size-cells = <2>;
1921 compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy";
1929 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1934 reset-names = "phy", "phy_nocsr";
1936 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
1937 assigned-clock-rates = <100000000>;
1939 power-domains = <&gcc PCIE_1_PHY_GDSC>;
1941 #clock-cells = <1>;
1942 clock-output-names = "pcie1_pipe_clk";
1944 #phy-cells = <0>;
1949 cryptobam: dma-controller@1dc4000 {
1950 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
1953 #dma-cells = <1>;
1955 qcom,controlled-remotely;
1961 compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce";
1964 dma-names = "rx", "tx";
1968 interconnect-names = "memory";
1972 compatible = "qcom,sm8550-qmp-ufs-phy";
1977 clock-names = "ref",
1981 power-domains = <&gcc UFS_MEM_PHY_GDSC>;
1984 reset-names = "ufsphy";
1986 #clock-cells = <1>;
1987 #phy-cells = <0>;
1993 compatible = "qcom,sm8550-ufshc", "qcom,ufshc",
1994 "jedec,ufs-2.0";
1998 phy-names = "ufsphy";
1999 lanes-per-direction = <2>;
2000 #reset-cells = <1>;
2002 reset-names = "rst";
2004 power-domains = <&gcc UFS_PHY_GDSC>;
2005 required-opps = <&rpmhpd_opp_nom>;
2008 dma-coherent;
2010 operating-points-v2 = <&ufs_opp_table>;
2014 interconnect-names = "ufs-ddr", "cpu-ufs";
2015 clock-names = "core_clk",
2035 ufs_opp_table: opp-table {
2036 compatible = "operating-points-v2";
2038 opp-75000000 {
2039 opp-hz = /bits/ 64 <75000000>,
2047 required-opps = <&rpmhpd_opp_low_svs>;
2050 opp-150000000 {
2051 opp-hz = /bits/ 64 <150000000>,
2059 required-opps = <&rpmhpd_opp_svs>;
2062 opp-300000000 {
2063 opp-hz = /bits/ 64 <300000000>,
2071 required-opps = <&rpmhpd_opp_nom>;
2077 compatible = "qcom,sm8550-inline-crypto-engine",
2078 "qcom,inline-crypto-engine";
2085 compatible = "qcom,tcsr-mutex";
2087 #hwlock-cells = <1>;
2090 tcsr: clock-controller@1fc0000 {
2091 compatible = "qcom,sm8550-tcsr", "syscon";
2094 #clock-cells = <1>;
2095 #reset-cells = <1>;
2099 compatible = "qcom,adreno-43050a01", "qcom,adreno";
2103 reg-names = "kgsl_3d0_reg_memory",
2112 operating-points-v2 = <&gpu_opp_table>;
2115 #cooling-cells = <2>;
2119 zap-shader {
2120 memory-region = <&gpu_micro_code_mem>;
2124 gpu_opp_table: opp-table {
2125 compatible = "operating-points-v2";
2127 opp-680000000 {
2128 opp-hz = /bits/ 64 <680000000>;
2129 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2132 opp-615000000 {
2133 opp-hz = /bits/ 64 <615000000>;
2134 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2137 opp-550000000 {
2138 opp-hz = /bits/ 64 <550000000>;
2139 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2142 opp-475000000 {
2143 opp-hz = /bits/ 64 <475000000>;
2144 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
2147 opp-401000000 {
2148 opp-hz = /bits/ 64 <401000000>;
2149 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2152 opp-348000000 {
2153 opp-hz = /bits/ 64 <348000000>;
2154 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
2157 opp-295000000 {
2158 opp-hz = /bits/ 64 <295000000>;
2159 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2162 opp-220000000 {
2163 opp-hz = /bits/ 64 <220000000>;
2164 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
2170 compatible = "qcom,adreno-gmu-740.1", "qcom,adreno-gmu";
2174 reg-names = "gmu", "rscc", "gmu_pdc";
2178 interrupt-names = "hfi", "gmu";
2187 clock-names = "ahb",
2195 power-domains = <&gpucc GPU_CC_CX_GDSC>,
2197 power-domain-names = "cx",
2204 operating-points-v2 = <&gmu_opp_table>;
2206 gmu_opp_table: opp-table {
2207 compatible = "operating-points-v2";
2209 opp-500000000 {
2210 opp-hz = /bits/ 64 <500000000>;
2211 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2214 opp-200000000 {
2215 opp-hz = /bits/ 64 <200000000>;
2216 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2221 gpucc: clock-controller@3d90000 {
2222 compatible = "qcom,sm8550-gpucc";
2227 #clock-cells = <1>;
2228 #reset-cells = <1>;
2229 #power-domain-cells = <1>;
2233 compatible = "qcom,sm8550-smmu-500", "qcom,adreno-smmu",
2234 "qcom,smmu-500", "arm,mmu-500";
2236 #iommu-cells = <2>;
2237 #global-interrupts = <1>;
2268 clock-names = "hlos",
2272 power-domains = <&gpucc GPU_CC_CX_GDSC>;
2273 dma-coherent;
2277 compatible = "qcom,sm8550-ipa";
2284 reg-names = "ipa-reg",
2285 "ipa-shared",
2288 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
2292 interrupt-names = "ipa",
2294 "ipa-clock-query",
2295 "ipa-setup-ready";
2298 clock-names = "core";
2302 interconnect-names = "memory",
2307 qcom,smem-states = <&ipa_smp2p_out 0>,
2309 qcom,smem-state-names = "ipa-clock-enabled-valid",
2310 "ipa-clock-enabled";
2316 compatible = "qcom,sm8550-mpss-pas";
2319 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2325 interrupt-names = "wdog", "fatal", "ready", "handover",
2326 "stop-ack", "shutdown-ack";
2329 clock-names = "xo";
2331 power-domains = <&rpmhpd RPMHPD_CX>,
2333 power-domain-names = "cx", "mss";
2337 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>;
2341 qcom,smem-states = <&smp2p_modem_out 0>;
2342 qcom,smem-state-names = "stop";
2346 glink-edge {
2347 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2353 qcom,remote-pid = <1>;
2358 compatible = "qcom,sm8550-lpass-wsa-macro";
2364 clock-names = "mclk", "macro", "dcodec", "fsgen";
2366 #clock-cells = <0>;
2367 clock-output-names = "wsa2-mclk";
2368 #sound-dai-cells = <1>;
2372 compatible = "qcom,soundwire-v2.0.0";
2376 clock-names = "iface";
2379 pinctrl-0 = <&wsa2_swr_active>;
2380 pinctrl-names = "default";
2382 qcom,din-ports = <4>;
2383 qcom,dout-ports = <9>;
2385 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
2386 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2387 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2388 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2389 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2390 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
2391 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
2392 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2393 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2395 #address-cells = <2>;
2396 #size-cells = <0>;
2397 #sound-dai-cells = <1>;
2402 compatible = "qcom,sm8550-lpass-rx-macro";
2408 clock-names = "mclk", "macro", "dcodec", "fsgen";
2410 #clock-cells = <0>;
2411 clock-output-names = "mclk";
2412 #sound-dai-cells = <1>;
2416 compatible = "qcom,soundwire-v2.0.0";
2420 clock-names = "iface";
2423 pinctrl-0 = <&rx_swr_active>;
2424 pinctrl-names = "default";
2426 qcom,din-ports = <1>;
2427 qcom,dout-ports = <11>;
2429 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff 0xff 0xff>;
2430 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2431 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2432 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>;
2433 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>;
2434 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff 0xff 0xff>;
2435 …qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff 0xff 0xff…
2436 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0x…
2437 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2439 #address-cells = <2>;
2440 #size-cells = <0>;
2441 #sound-dai-cells = <1>;
2446 compatible = "qcom,sm8550-lpass-tx-macro";
2452 clock-names = "mclk", "macro", "dcodec", "fsgen";
2454 #clock-cells = <0>;
2455 clock-output-names = "mclk";
2456 #sound-dai-cells = <1>;
2460 compatible = "qcom,sm8550-lpass-wsa-macro";
2466 clock-names = "mclk", "macro", "dcodec", "fsgen";
2468 #clock-cells = <0>;
2469 clock-output-names = "mclk";
2470 #sound-dai-cells = <1>;
2474 compatible = "qcom,soundwire-v2.0.0";
2478 clock-names = "iface";
2481 pinctrl-0 = <&wsa_swr_active>;
2482 pinctrl-names = "default";
2484 qcom,din-ports = <4>;
2485 qcom,dout-ports = <9>;
2487 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
2488 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2489 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2490 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2491 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2492 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
2493 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
2494 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2495 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2497 #address-cells = <2>;
2498 #size-cells = <0>;
2499 #sound-dai-cells = <1>;
2504 compatible = "qcom,soundwire-v2.0.0";
2508 interrupt-names = "core", "wakeup";
2510 clock-names = "iface";
2513 pinctrl-0 = <&tx_swr_active>;
2514 pinctrl-names = "default";
2516 qcom,din-ports = <4>;
2517 qcom,dout-ports = <0>;
2518 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2519 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2520 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2521 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2522 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2523 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2524 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2525 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2526 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2528 #address-cells = <2>;
2529 #size-cells = <0>;
2530 #sound-dai-cells = <1>;
2535 compatible = "qcom,sm8550-lpass-va-macro";
2540 clock-names = "mclk", "macro", "dcodec";
2542 #clock-cells = <0>;
2543 clock-output-names = "fsgen";
2544 #sound-dai-cells = <1>;
2548 compatible = "qcom,sm8550-lpass-lpi-pinctrl";
2551 gpio-controller;
2552 #gpio-cells = <2>;
2553 gpio-ranges = <&lpass_tlmm 0 0 23>;
2557 clock-names = "core", "audio";
2559 tx_swr_active: tx-swr-active-state {
2560 clk-pins {
2563 drive-strength = <2>;
2564 slew-rate = <1>;
2565 bias-disable;
2568 data-pins {
2571 drive-strength = <2>;
2572 slew-rate = <1>;
2573 bias-bus-hold;
2577 rx_swr_active: rx-swr-active-state {
2578 clk-pins {
2581 drive-strength = <2>;
2582 slew-rate = <1>;
2583 bias-disable;
2586 data-pins {
2589 drive-strength = <2>;
2590 slew-rate = <1>;
2591 bias-bus-hold;
2595 dmic01_default: dmic01-default-state {
2596 clk-pins {
2599 drive-strength = <8>;
2600 output-high;
2603 data-pins {
2606 drive-strength = <8>;
2607 input-enable;
2611 dmic23_default: dmic23-default-state {
2612 clk-pins {
2615 drive-strength = <8>;
2616 output-high;
2619 data-pins {
2622 drive-strength = <8>;
2623 input-enable;
2627 wsa_swr_active: wsa-swr-active-state {
2628 clk-pins {
2631 drive-strength = <2>;
2632 slew-rate = <1>;
2633 bias-disable;
2636 data-pins {
2639 drive-strength = <2>;
2640 slew-rate = <1>;
2641 bias-bus-hold;
2645 wsa2_swr_active: wsa2-swr-active-state {
2646 clk-pins {
2649 drive-strength = <2>;
2650 slew-rate = <1>;
2651 bias-disable;
2654 data-pins {
2657 drive-strength = <2>;
2658 slew-rate = <1>;
2659 bias-bus-hold;
2665 compatible = "qcom,sm8550-lpass-lpiaon-noc";
2667 #interconnect-cells = <2>;
2668 qcom,bcm-voters = <&apps_bcm_voter>;
2672 compatible = "qcom,sm8550-lpass-lpicx-noc";
2674 #interconnect-cells = <2>;
2675 qcom,bcm-voters = <&apps_bcm_voter>;
2679 compatible = "qcom,sm8550-lpass-ag-noc";
2681 #interconnect-cells = <2>;
2682 qcom,bcm-voters = <&apps_bcm_voter>;
2686 compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5";
2691 interrupt-names = "hc_irq", "pwr_irq";
2696 clock-names = "iface", "core", "xo";
2698 qcom,dll-config = <0x0007642c>;
2699 qcom,ddr-config = <0x80040868>;
2700 power-domains = <&rpmhpd RPMHPD_CX>;
2701 operating-points-v2 = <&sdhc2_opp_table>;
2705 interconnect-names = "sdhc-ddr", "cpu-sdhc";
2706 bus-width = <4>;
2707 dma-coherent;
2709 /* Forbid SDR104/SDR50 - broken hw! */
2710 sdhci-caps-mask = <0x3 0>;
2714 sdhc2_opp_table: opp-table {
2715 compatible = "operating-points-v2";
2717 opp-19200000 {
2718 opp-hz = /bits/ 64 <19200000>;
2719 required-opps = <&rpmhpd_opp_min_svs>;
2722 opp-50000000 {
2723 opp-hz = /bits/ 64 <50000000>;
2724 required-opps = <&rpmhpd_opp_low_svs>;
2727 opp-100000000 {
2728 opp-hz = /bits/ 64 <100000000>;
2729 required-opps = <&rpmhpd_opp_svs>;
2732 opp-202000000 {
2733 opp-hz = /bits/ 64 <202000000>;
2734 required-opps = <&rpmhpd_opp_svs_l1>;
2739 videocc: clock-controller@aaf0000 {
2740 compatible = "qcom,sm8550-videocc";
2744 power-domains = <&rpmhpd RPMHPD_MMCX>;
2745 required-opps = <&rpmhpd_opp_low_svs>;
2746 #clock-cells = <1>;
2747 #reset-cells = <1>;
2748 #power-domain-cells = <1>;
2752 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci";
2755 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
2759 clock-names = "camnoc_axi",
2762 pinctrl-0 = <&cci0_0_default &cci0_1_default>;
2763 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
2764 pinctrl-names = "default", "sleep";
2766 #address-cells = <1>;
2767 #size-cells = <0>;
2769 cci0_i2c0: i2c-bus@0 {
2771 clock-frequency = <1000000>;
2772 #address-cells = <1>;
2773 #size-cells = <0>;
2776 cci0_i2c1: i2c-bus@1 {
2778 clock-frequency = <1000000>;
2779 #address-cells = <1>;
2780 #size-cells = <0>;
2785 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci";
2788 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
2792 clock-names = "camnoc_axi",
2795 pinctrl-0 = <&cci1_0_default>;
2796 pinctrl-1 = <&cci1_0_sleep>;
2797 pinctrl-names = "default", "sleep";
2799 #address-cells = <1>;
2800 #size-cells = <0>;
2802 cci1_i2c0: i2c-bus@0 {
2804 clock-frequency = <1000000>;
2805 #address-cells = <1>;
2806 #size-cells = <0>;
2811 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci";
2814 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
2818 clock-names = "camnoc_axi",
2821 pinctrl-0 = <&cci2_0_default &cci2_1_default>;
2822 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>;
2823 pinctrl-names = "default", "sleep";
2825 #address-cells = <1>;
2826 #size-cells = <0>;
2828 cci2_i2c0: i2c-bus@0 {
2830 clock-frequency = <1000000>;
2831 #address-cells = <1>;
2832 #size-cells = <0>;
2835 cci2_i2c1: i2c-bus@1 {
2837 clock-frequency = <1000000>;
2838 #address-cells = <1>;
2839 #size-cells = <0>;
2843 camcc: clock-controller@ade0000 {
2844 compatible = "qcom,sm8550-camcc";
2850 power-domains = <&rpmhpd SM8550_MMCX>;
2851 required-opps = <&rpmhpd_opp_low_svs>;
2852 #clock-cells = <1>;
2853 #reset-cells = <1>;
2854 #power-domain-cells = <1>;
2857 mdss: display-subsystem@ae00000 {
2858 compatible = "qcom,sm8550-mdss";
2860 reg-names = "mdss";
2863 interrupt-controller;
2864 #interrupt-cells = <1>;
2873 power-domains = <&dispcc MDSS_GDSC>;
2877 interconnect-names = "mdp0-mem", "mdp1-mem";
2881 #address-cells = <2>;
2882 #size-cells = <2>;
2887 mdss_mdp: display-controller@ae01000 {
2888 compatible = "qcom,sm8550-dpu";
2891 reg-names = "mdp", "vbif";
2893 interrupt-parent = <&mdss>;
2902 clock-names = "bus",
2909 power-domains = <&rpmhpd RPMHPD_MMCX>;
2911 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2912 assigned-clock-rates = <19200000>;
2914 operating-points-v2 = <&mdp_opp_table>;
2917 #address-cells = <1>;
2918 #size-cells = <0>;
2923 remote-endpoint = <&mdss_dsi0_in>;
2930 remote-endpoint = <&mdss_dsi1_in>;
2937 remote-endpoint = <&mdss_dp0_in>;
2942 mdp_opp_table: opp-table {
2943 compatible = "operating-points-v2";
2945 opp-200000000 {
2946 opp-hz = /bits/ 64 <200000000>;
2947 required-opps = <&rpmhpd_opp_low_svs>;
2950 opp-325000000 {
2951 opp-hz = /bits/ 64 <325000000>;
2952 required-opps = <&rpmhpd_opp_svs>;
2955 opp-375000000 {
2956 opp-hz = /bits/ 64 <375000000>;
2957 required-opps = <&rpmhpd_opp_svs_l1>;
2960 opp-514000000 {
2961 opp-hz = /bits/ 64 <514000000>;
2962 required-opps = <&rpmhpd_opp_nom>;
2967 mdss_dp0: displayport-controller@ae90000 {
2968 compatible = "qcom,sm8550-dp", "qcom,sm8350-dp";
2974 interrupt-parent = <&mdss>;
2981 clock-names = "core_iface",
2987 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
2989 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2993 phy-names = "dp";
2995 #sound-dai-cells = <0>;
2997 operating-points-v2 = <&dp_opp_table>;
2998 power-domains = <&rpmhpd RPMHPD_MMCX>;
3003 #address-cells = <1>;
3004 #size-cells = <0>;
3009 remote-endpoint = <&dpu_intf0_out>;
3016 remote-endpoint = <&usb_dp_qmpphy_dp_in>;
3021 dp_opp_table: opp-table {
3022 compatible = "operating-points-v2";
3024 opp-162000000 {
3025 opp-hz = /bits/ 64 <162000000>;
3026 required-opps = <&rpmhpd_opp_low_svs_d1>;
3029 opp-270000000 {
3030 opp-hz = /bits/ 64 <270000000>;
3031 required-opps = <&rpmhpd_opp_low_svs>;
3034 opp-540000000 {
3035 opp-hz = /bits/ 64 <540000000>;
3036 required-opps = <&rpmhpd_opp_svs_l1>;
3039 opp-810000000 {
3040 opp-hz = /bits/ 64 <810000000>;
3041 required-opps = <&rpmhpd_opp_nom>;
3047 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3049 reg-names = "dsi_ctrl";
3051 interrupt-parent = <&mdss>;
3060 clock-names = "byte",
3067 power-domains = <&rpmhpd RPMHPD_MMCX>;
3069 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
3071 assigned-clock-parents = <&mdss_dsi0_phy 0>,
3074 operating-points-v2 = <&mdss_dsi_opp_table>;
3077 phy-names = "dsi";
3079 #address-cells = <1>;
3080 #size-cells = <0>;
3085 #address-cells = <1>;
3086 #size-cells = <0>;
3091 remote-endpoint = <&dpu_intf1_out>;
3102 mdss_dsi_opp_table: opp-table {
3103 compatible = "operating-points-v2";
3105 opp-187500000 {
3106 opp-hz = /bits/ 64 <187500000>;
3107 required-opps = <&rpmhpd_opp_low_svs>;
3110 opp-300000000 {
3111 opp-hz = /bits/ 64 <300000000>;
3112 required-opps = <&rpmhpd_opp_svs>;
3115 opp-358000000 {
3116 opp-hz = /bits/ 64 <358000000>;
3117 required-opps = <&rpmhpd_opp_svs_l1>;
3123 compatible = "qcom,sm8550-dsi-phy-4nm";
3127 reg-names = "dsi_phy",
3133 clock-names = "iface", "ref";
3135 #clock-cells = <1>;
3136 #phy-cells = <0>;
3142 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3144 reg-names = "dsi_ctrl";
3146 interrupt-parent = <&mdss>;
3155 clock-names = "byte",
3162 power-domains = <&rpmhpd RPMHPD_MMCX>;
3164 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
3166 assigned-clock-parents = <&mdss_dsi1_phy 0>,
3169 operating-points-v2 = <&mdss_dsi_opp_table>;
3172 phy-names = "dsi";
3174 #address-cells = <1>;
3175 #size-cells = <0>;
3180 #address-cells = <1>;
3181 #size-cells = <0>;
3186 remote-endpoint = <&dpu_intf2_out>;
3199 compatible = "qcom,sm8550-dsi-phy-4nm";
3203 reg-names = "dsi_phy",
3209 clock-names = "iface", "ref";
3211 #clock-cells = <1>;
3212 #phy-cells = <0>;
3218 dispcc: clock-controller@af00000 {
3219 compatible = "qcom,sm8550-dispcc";
3237 power-domains = <&rpmhpd RPMHPD_MMCX>;
3238 required-opps = <&rpmhpd_opp_low_svs>;
3239 #clock-cells = <1>;
3240 #reset-cells = <1>;
3241 #power-domain-cells = <1>;
3245 compatible = "qcom,sm8550-snps-eusb2-phy";
3247 #phy-cells = <0>;
3250 clock-names = "ref";
3258 compatible = "qcom,sm8550-qmp-usb3-dp-phy";
3265 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3267 power-domains = <&gcc USB3_PHY_GDSC>;
3271 reset-names = "phy", "common";
3273 #clock-cells = <1>;
3274 #phy-cells = <1>;
3276 orientation-switch;
3281 #address-cells = <1>;
3282 #size-cells = <0>;
3295 remote-endpoint = <&usb_1_dwc3_ss>;
3303 remote-endpoint = <&mdss_dp0_out>;
3310 compatible = "qcom,sm8550-dwc3", "qcom,dwc3";
3312 #address-cells = <2>;
3313 #size-cells = <2>;
3322 clock-names = "cfg_noc",
3329 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3331 assigned-clock-rates = <19200000>, <200000000>;
3333 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3338 interrupt-names = "pwr_event",
3344 power-domains = <&gcc USB30_PRIM_GDSC>;
3345 required-opps = <&rpmhpd_opp_nom>;
3351 interconnect-names = "usb-ddr", "apps-usb";
3362 phy-names = "usb2-phy", "usb3-phy";
3363 snps,hird-threshold = /bits/ 8 <0x0>;
3364 snps,usb2-gadget-lpm-disable;
3367 snps,dis-u1-entry-quirk;
3368 snps,dis-u2-entry-quirk;
3369 snps,is-utmi-l1-suspend;
3371 snps,usb2-lpm-disable;
3372 snps,has-lpm-erratum;
3373 tx-fifo-resize;
3374 dma-coherent;
3375 usb-role-switch;
3378 #address-cells = <1>;
3379 #size-cells = <0>;
3392 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
3399 pdc: interrupt-controller@b220000 {
3400 compatible = "qcom,sm8550-pdc", "qcom,pdc";
3402 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
3405 #interrupt-cells = <2>;
3406 interrupt-parent = <&intc>;
3407 interrupt-controller;
3410 tsens0: thermal-sensor@c271000 {
3411 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
3417 interrupt-names = "uplow", "critical";
3418 #thermal-sensor-cells = <1>;
3421 tsens1: thermal-sensor@c272000 {
3422 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
3428 interrupt-names = "uplow", "critical";
3429 #thermal-sensor-cells = <1>;
3432 tsens2: thermal-sensor@c273000 {
3433 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
3439 interrupt-names = "uplow", "critical";
3440 #thermal-sensor-cells = <1>;
3443 aoss_qmp: power-management@c300000 {
3444 compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp";
3446 interrupt-parent = <&ipcc>;
3447 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3451 #clock-cells = <0>;
3455 compatible = "qcom,rpmh-stats";
3460 compatible = "qcom,spmi-pmic-arb";
3466 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3467 interrupt-names = "periph_irq";
3468 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3471 qcom,bus-id = <0>;
3472 #address-cells = <2>;
3473 #size-cells = <0>;
3474 interrupt-controller;
3475 #interrupt-cells = <4>;
3479 compatible = "qcom,sm8550-tlmm";
3482 gpio-controller;
3483 #gpio-cells = <2>;
3484 interrupt-controller;
3485 #interrupt-cells = <2>;
3486 gpio-ranges = <&tlmm 0 0 211>;
3487 wakeup-parent = <&pdc>;
3489 cci0_0_default: cci0-0-default-state {
3490 sda-pins {
3493 drive-strength = <2>;
3494 bias-pull-up = <2200>;
3497 scl-pins {
3500 drive-strength = <2>;
3501 bias-pull-up = <2200>;
3505 cci0_0_sleep: cci0-0-sleep-state {
3506 sda-pins {
3509 drive-strength = <2>;
3510 bias-pull-down;
3513 scl-pins {
3516 drive-strength = <2>;
3517 bias-pull-down;
3521 cci0_1_default: cci0-1-default-state {
3522 sda-pins {
3525 drive-strength = <2>;
3526 bias-pull-up = <2200>;
3529 scl-pins {
3532 drive-strength = <2>;
3533 bias-pull-up = <2200>;
3537 cci0_1_sleep: cci0-1-sleep-state {
3538 sda-pins {
3541 drive-strength = <2>;
3542 bias-pull-down;
3545 scl-pins {
3548 drive-strength = <2>;
3549 bias-pull-down;
3553 cci1_0_default: cci1-0-default-state {
3554 sda-pins {
3557 drive-strength = <2>;
3558 bias-pull-up = <2200>;
3561 scl-pins {
3564 drive-strength = <2>;
3565 bias-pull-up = <2200>;
3569 cci1_0_sleep: cci1-0-sleep-state {
3570 sda-pins {
3573 drive-strength = <2>;
3574 bias-pull-down;
3577 scl-pins {
3580 drive-strength = <2>;
3581 bias-pull-down;
3585 cci2_0_default: cci2-0-default-state {
3586 sda-pins {
3589 drive-strength = <2>;
3590 bias-pull-up = <2200>;
3593 scl-pins {
3596 drive-strength = <2>;
3597 bias-pull-up = <2200>;
3601 cci2_0_sleep: cci2-0-sleep-state {
3602 sda-pins {
3605 drive-strength = <2>;
3606 bias-pull-down;
3609 scl-pins {
3612 drive-strength = <2>;
3613 bias-pull-down;
3617 cci2_1_default: cci2-1-default-state {
3618 sda-pins {
3621 drive-strength = <2>;
3622 bias-pull-up = <2200>;
3625 scl-pins {
3628 drive-strength = <2>;
3629 bias-pull-up = <2200>;
3633 cci2_1_sleep: cci2-1-sleep-state {
3634 sda-pins {
3637 drive-strength = <2>;
3638 bias-pull-down;
3641 scl-pins {
3644 drive-strength = <2>;
3645 bias-pull-down;
3649 hub_i2c0_data_clk: hub-i2c0-data-clk-state {
3653 drive-strength = <2>;
3654 bias-pull-up;
3657 hub_i2c1_data_clk: hub-i2c1-data-clk-state {
3661 drive-strength = <2>;
3662 bias-pull-up;
3665 hub_i2c2_data_clk: hub-i2c2-data-clk-state {
3669 drive-strength = <2>;
3670 bias-pull-up;
3673 hub_i2c3_data_clk: hub-i2c3-data-clk-state {
3677 drive-strength = <2>;
3678 bias-pull-up;
3681 hub_i2c4_data_clk: hub-i2c4-data-clk-state {
3685 drive-strength = <2>;
3686 bias-pull-up;
3689 hub_i2c5_data_clk: hub-i2c5-data-clk-state {
3693 drive-strength = <2>;
3694 bias-pull-up;
3697 hub_i2c6_data_clk: hub-i2c6-data-clk-state {
3701 drive-strength = <2>;
3702 bias-pull-up;
3705 hub_i2c7_data_clk: hub-i2c7-data-clk-state {
3709 drive-strength = <2>;
3710 bias-pull-up;
3713 hub_i2c8_data_clk: hub-i2c8-data-clk-state {
3717 drive-strength = <2>;
3718 bias-pull-up;
3721 hub_i2c9_data_clk: hub-i2c9-data-clk-state {
3725 drive-strength = <2>;
3726 bias-pull-up;
3729 pcie0_default_state: pcie0-default-state {
3730 perst-pins {
3733 drive-strength = <2>;
3734 bias-pull-down;
3737 clkreq-pins {
3740 drive-strength = <2>;
3741 bias-pull-up;
3744 wake-pins {
3747 drive-strength = <2>;
3748 bias-pull-up;
3752 pcie1_default_state: pcie1-default-state {
3753 perst-pins {
3756 drive-strength = <2>;
3757 bias-pull-down;
3760 clkreq-pins {
3763 drive-strength = <2>;
3764 bias-pull-up;
3767 wake-pins {
3770 drive-strength = <2>;
3771 bias-pull-up;
3775 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3779 drive-strength = <2>;
3780 bias-pull-up = <2200>;
3783 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3787 drive-strength = <2>;
3788 bias-pull-up = <2200>;
3791 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3795 drive-strength = <2>;
3796 bias-pull-up = <2200>;
3799 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3803 drive-strength = <2>;
3804 bias-pull-up = <2200>;
3807 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3811 drive-strength = <2>;
3812 bias-pull-up = <2200>;
3815 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3819 drive-strength = <2>;
3820 bias-pull-up = <2200>;
3823 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3827 drive-strength = <2>;
3828 bias-pull-up = <2200>;
3831 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3832 scl-pins {
3835 drive-strength = <2>;
3836 bias-pull-up = <2200>;
3839 sda-pins {
3842 drive-strength = <2>;
3843 bias-pull-up = <2200>;
3847 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3851 drive-strength = <2>;
3852 bias-pull-up = <2200>;
3855 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3859 drive-strength = <2>;
3860 bias-pull-up = <2200>;
3863 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3867 drive-strength = <2>;
3868 bias-pull-up = <2200>;
3871 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3875 drive-strength = <2>;
3876 bias-pull-up = <2200>;
3879 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3883 drive-strength = <2>;
3884 bias-pull-up = <2200>;
3887 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3891 drive-strength = <2>;
3892 bias-pull-up = <2200>;
3895 qup_spi0_cs: qup-spi0-cs-state {
3898 drive-strength = <6>;
3899 bias-disable;
3902 qup_spi0_data_clk: qup-spi0-data-clk-state {
3906 drive-strength = <6>;
3907 bias-disable;
3910 qup_spi1_cs: qup-spi1-cs-state {
3913 drive-strength = <6>;
3914 bias-disable;
3917 qup_spi1_data_clk: qup-spi1-data-clk-state {
3921 drive-strength = <6>;
3922 bias-disable;
3925 qup_spi2_cs: qup-spi2-cs-state {
3928 drive-strength = <6>;
3929 bias-disable;
3932 qup_spi2_data_clk: qup-spi2-data-clk-state {
3936 drive-strength = <6>;
3937 bias-disable;
3940 qup_spi3_cs: qup-spi3-cs-state {
3943 drive-strength = <6>;
3944 bias-disable;
3947 qup_spi3_data_clk: qup-spi3-data-clk-state {
3951 drive-strength = <6>;
3952 bias-disable;
3955 qup_spi4_cs: qup-spi4-cs-state {
3958 drive-strength = <6>;
3959 bias-disable;
3962 qup_spi4_data_clk: qup-spi4-data-clk-state {
3966 drive-strength = <6>;
3967 bias-disable;
3970 qup_spi5_cs: qup-spi5-cs-state {
3973 drive-strength = <6>;
3974 bias-disable;
3977 qup_spi5_data_clk: qup-spi5-data-clk-state {
3981 drive-strength = <6>;
3982 bias-disable;
3985 qup_spi6_cs: qup-spi6-cs-state {
3988 drive-strength = <6>;
3989 bias-disable;
3992 qup_spi6_data_clk: qup-spi6-data-clk-state {
3996 drive-strength = <6>;
3997 bias-disable;
4000 qup_spi8_cs: qup-spi8-cs-state {
4003 drive-strength = <6>;
4004 bias-disable;
4007 qup_spi8_data_clk: qup-spi8-data-clk-state {
4011 drive-strength = <6>;
4012 bias-disable;
4015 qup_spi9_cs: qup-spi9-cs-state {
4018 drive-strength = <6>;
4019 bias-disable;
4022 qup_spi9_data_clk: qup-spi9-data-clk-state {
4026 drive-strength = <6>;
4027 bias-disable;
4030 qup_spi10_cs: qup-spi10-cs-state {
4033 drive-strength = <6>;
4034 bias-disable;
4037 qup_spi10_data_clk: qup-spi10-data-clk-state {
4041 drive-strength = <6>;
4042 bias-disable;
4045 qup_spi11_cs: qup-spi11-cs-state {
4048 drive-strength = <6>;
4049 bias-disable;
4052 qup_spi11_data_clk: qup-spi11-data-clk-state {
4056 drive-strength = <6>;
4057 bias-disable;
4060 qup_spi12_cs: qup-spi12-cs-state {
4063 drive-strength = <6>;
4064 bias-disable;
4067 qup_spi12_data_clk: qup-spi12-data-clk-state {
4071 drive-strength = <6>;
4072 bias-disable;
4075 qup_spi13_cs: qup-spi13-cs-state {
4078 drive-strength = <6>;
4079 bias-disable;
4082 qup_spi13_data_clk: qup-spi13-data-clk-state {
4086 drive-strength = <6>;
4087 bias-disable;
4090 qup_spi15_cs: qup-spi15-cs-state {
4093 drive-strength = <6>;
4094 bias-disable;
4097 qup_spi15_data_clk: qup-spi15-data-clk-state {
4101 drive-strength = <6>;
4102 bias-disable;
4105 qup_uart7_default: qup-uart7-default-state {
4109 drive-strength = <2>;
4110 bias-disable;
4113 qup_uart14_default: qup-uart14-default-state {
4117 drive-strength = <2>;
4118 bias-pull-up;
4121 qup_uart14_cts_rts: qup-uart14-cts-rts-state {
4125 drive-strength = <2>;
4126 bias-pull-down;
4129 sdc2_sleep: sdc2-sleep-state {
4130 clk-pins {
4132 bias-disable;
4133 drive-strength = <2>;
4136 cmd-pins {
4138 bias-pull-up;
4139 drive-strength = <2>;
4142 data-pins {
4144 bias-pull-up;
4145 drive-strength = <2>;
4149 sdc2_default: sdc2-default-state {
4150 clk-pins {
4152 bias-disable;
4153 drive-strength = <16>;
4156 cmd-pins {
4158 bias-pull-up;
4159 drive-strength = <10>;
4162 data-pins {
4164 bias-pull-up;
4165 drive-strength = <10>;
4171 compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500";
4173 #iommu-cells = <2>;
4174 #global-interrupts = <1>;
4272 dma-coherent;
4275 intc: interrupt-controller@17100000 {
4276 compatible = "arm,gic-v3";
4280 #interrupt-cells = <3>;
4281 interrupt-controller;
4282 #redistributor-regions = <1>;
4283 redistributor-stride = <0 0x40000>;
4285 #address-cells = <2>;
4286 #size-cells = <2>;
4288 gic_its: msi-controller@17140000 {
4289 compatible = "arm,gic-v3-its";
4291 msi-controller;
4292 #msi-cells = <1>;
4297 compatible = "arm,armv7-timer-mem";
4300 #address-cells = <1>;
4301 #size-cells = <1>;
4306 frame-number = <0>;
4313 frame-number = <1>;
4320 frame-number = <2>;
4327 frame-number = <3>;
4334 frame-number = <4>;
4341 frame-number = <5>;
4348 frame-number = <6>;
4356 compatible = "qcom,rpmh-rsc";
4361 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4365 qcom,tcs-offset = <0xd00>;
4366 qcom,drv-id = <2>;
4367 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
4369 power-domains = <&cluster_pd>;
4371 apps_bcm_voter: bcm-voter {
4372 compatible = "qcom,bcm-voter";
4375 rpmhcc: clock-controller {
4376 compatible = "qcom,sm8550-rpmh-clk";
4377 #clock-cells = <1>;
4378 clock-names = "xo";
4382 rpmhpd: power-controller {
4383 compatible = "qcom,sm8550-rpmhpd";
4384 #power-domain-cells = <1>;
4385 operating-points-v2 = <&rpmhpd_opp_table>;
4387 rpmhpd_opp_table: opp-table {
4388 compatible = "operating-points-v2";
4390 rpmhpd_opp_ret: opp-16 {
4391 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4394 rpmhpd_opp_min_svs: opp-48 {
4395 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4398 rpmhpd_opp_low_svs_d2: opp-52 {
4399 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
4402 rpmhpd_opp_low_svs_d1: opp-56 {
4403 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
4406 rpmhpd_opp_low_svs_d0: opp-60 {
4407 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
4410 rpmhpd_opp_low_svs: opp-64 {
4411 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4414 rpmhpd_opp_low_svs_l1: opp-80 {
4415 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
4418 rpmhpd_opp_svs: opp-128 {
4419 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4422 rpmhpd_opp_svs_l0: opp-144 {
4423 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
4426 rpmhpd_opp_svs_l1: opp-192 {
4427 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4430 rpmhpd_opp_nom: opp-256 {
4431 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4434 rpmhpd_opp_nom_l1: opp-320 {
4435 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4438 rpmhpd_opp_nom_l2: opp-336 {
4439 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4442 rpmhpd_opp_turbo: opp-384 {
4443 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4446 rpmhpd_opp_turbo_l1: opp-416 {
4447 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4454 compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss";
4458 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
4460 clock-names = "xo", "alternate";
4464 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4465 #freq-domain-cells = <1>;
4466 #clock-cells = <1>;
4470 compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
4475 operating-points-v2 = <&llcc_bwmon_opp_table>;
4477 llcc_bwmon_opp_table: opp-table {
4478 compatible = "operating-points-v2";
4480 opp-0 {
4481 opp-peak-kBps = <2086000>;
4484 opp-1 {
4485 opp-peak-kBps = <2929000>;
4488 opp-2 {
4489 opp-peak-kBps = <5931000>;
4492 opp-3 {
4493 opp-peak-kBps = <6515000>;
4496 opp-4 {
4497 opp-peak-kBps = <7980000>;
4500 opp-5 {
4501 opp-peak-kBps = <10437000>;
4504 opp-6 {
4505 opp-peak-kBps = <12157000>;
4508 opp-7 {
4509 opp-peak-kBps = <14060000>;
4512 opp-8 {
4513 opp-peak-kBps = <16113000>;
4519 compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon";
4524 operating-points-v2 = <&cpu_bwmon_opp_table>;
4526 cpu_bwmon_opp_table: opp-table {
4527 compatible = "operating-points-v2";
4529 opp-0 {
4530 opp-peak-kBps = <4577000>;
4533 opp-1 {
4534 opp-peak-kBps = <7110000>;
4537 opp-2 {
4538 opp-peak-kBps = <9155000>;
4541 opp-3 {
4542 opp-peak-kBps = <12298000>;
4545 opp-4 {
4546 opp-peak-kBps = <14236000>;
4549 opp-5 {
4550 opp-peak-kBps = <16265000>;
4556 compatible = "qcom,sm8550-gem-noc";
4558 #interconnect-cells = <2>;
4559 qcom,bcm-voters = <&apps_bcm_voter>;
4562 system-cache-controller@25000000 {
4563 compatible = "qcom,sm8550-llcc";
4570 reg-names = "llcc0_base",
4580 compatible = "qcom,sm8550-adsp-pas";
4583 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
4588 interrupt-names = "wdog", "fatal", "ready",
4589 "handover", "stop-ack";
4592 clock-names = "xo";
4594 power-domains = <&rpmhpd RPMHPD_LCX>,
4596 power-domain-names = "lcx", "lmx";
4600 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
4604 qcom,smem-states = <&smp2p_adsp_out 0>;
4605 qcom,smem-state-names = "stop";
4609 remoteproc_adsp_glink: glink-edge {
4610 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
4617 qcom,remote-pid = <2>;
4621 qcom,glink-channels = "fastrpcglink-apps-dsp";
4623 qcom,non-secure-domain;
4624 #address-cells = <1>;
4625 #size-cells = <0>;
4627 compute-cb@3 {
4628 compatible = "qcom,fastrpc-compute-cb";
4632 dma-coherent;
4635 compute-cb@4 {
4636 compatible = "qcom,fastrpc-compute-cb";
4640 dma-coherent;
4643 compute-cb@5 {
4644 compatible = "qcom,fastrpc-compute-cb";
4648 dma-coherent;
4651 compute-cb@6 {
4652 compatible = "qcom,fastrpc-compute-cb";
4656 dma-coherent;
4659 compute-cb@7 {
4660 compatible = "qcom,fastrpc-compute-cb";
4664 dma-coherent;
4670 qcom,glink-channels = "adsp_apps";
4673 #address-cells = <1>;
4674 #size-cells = <0>;
4679 #sound-dai-cells = <0>;
4680 qcom,protection-domain = "avs/audio",
4684 compatible = "qcom,q6apm-dais";
4690 compatible = "qcom,q6apm-lpass-dais";
4691 #sound-dai-cells = <1>;
4698 qcom,protection-domain = "avs/audio",
4701 q6prmcc: clock-controller {
4702 compatible = "qcom,q6prm-lpass-clocks";
4703 #clock-cells = <2>;
4711 compatible = "qcom,sm8550-nsp-noc";
4713 #interconnect-cells = <2>;
4714 qcom,bcm-voters = <&apps_bcm_voter>;
4718 compatible = "qcom,sm8550-cdsp-pas";
4721 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
4726 interrupt-names = "wdog", "fatal", "ready",
4727 "handover", "stop-ack";
4730 clock-names = "xo";
4732 power-domains = <&rpmhpd RPMHPD_CX>,
4735 power-domain-names = "cx", "mxc", "nsp";
4739 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>;
4743 qcom,smem-states = <&smp2p_cdsp_out 0>;
4744 qcom,smem-state-names = "stop";
4748 glink-edge {
4749 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
4756 qcom,remote-pid = <5>;
4760 qcom,glink-channels = "fastrpcglink-apps-dsp";
4762 qcom,non-secure-domain;
4763 #address-cells = <1>;
4764 #size-cells = <0>;
4766 compute-cb@1 {
4767 compatible = "qcom,fastrpc-compute-cb";
4772 dma-coherent;
4775 compute-cb@2 {
4776 compatible = "qcom,fastrpc-compute-cb";
4781 dma-coherent;
4784 compute-cb@3 {
4785 compatible = "qcom,fastrpc-compute-cb";
4790 dma-coherent;
4793 compute-cb@4 {
4794 compatible = "qcom,fastrpc-compute-cb";
4799 dma-coherent;
4802 compute-cb@5 {
4803 compatible = "qcom,fastrpc-compute-cb";
4808 dma-coherent;
4811 compute-cb@6 {
4812 compatible = "qcom,fastrpc-compute-cb";
4817 dma-coherent;
4820 compute-cb@7 {
4821 compatible = "qcom,fastrpc-compute-cb";
4826 dma-coherent;
4829 compute-cb@8 {
4830 compatible = "qcom,fastrpc-compute-cb";
4835 dma-coherent;
4844 thermal-zones {
4845 aoss0-thermal {
4846 thermal-sensors = <&tsens0 0>;
4849 thermal-engine-config {
4855 reset-mon-config {
4863 cpuss0-thermal {
4864 thermal-sensors = <&tsens0 1>;
4867 thermal-engine-config {
4873 reset-mon-config {
4881 cpuss1-thermal {
4882 thermal-sensors = <&tsens0 2>;
4885 thermal-engine-config {
4891 reset-mon-config {
4899 cpuss2-thermal {
4900 thermal-sensors = <&tsens0 3>;
4903 thermal-engine-config {
4909 reset-mon-config {
4917 cpuss3-thermal {
4918 thermal-sensors = <&tsens0 4>;
4921 thermal-engine-config {
4927 reset-mon-config {
4935 cpu3-top-thermal {
4936 thermal-sensors = <&tsens0 5>;
4939 cpu3_top_alert0: trip-point0 {
4945 cpu3_top_alert1: trip-point1 {
4951 cpu3_top_crit: cpu-critical {
4959 cpu3-bottom-thermal {
4960 thermal-sensors = <&tsens0 6>;
4963 cpu3_bottom_alert0: trip-point0 {
4969 cpu3_bottom_alert1: trip-point1 {
4975 cpu3_bottom_crit: cpu-critical {
4983 cpu4-top-thermal {
4984 thermal-sensors = <&tsens0 7>;
4987 cpu4_top_alert0: trip-point0 {
4993 cpu4_top_alert1: trip-point1 {
4999 cpu4_top_crit: cpu-critical {
5007 cpu4-bottom-thermal {
5008 thermal-sensors = <&tsens0 8>;
5011 cpu4_bottom_alert0: trip-point0 {
5017 cpu4_bottom_alert1: trip-point1 {
5023 cpu4_bottom_crit: cpu-critical {
5031 cpu5-top-thermal {
5032 thermal-sensors = <&tsens0 9>;
5035 cpu5_top_alert0: trip-point0 {
5041 cpu5_top_alert1: trip-point1 {
5047 cpu5_top_crit: cpu-critical {
5055 cpu5-bottom-thermal {
5056 thermal-sensors = <&tsens0 10>;
5059 cpu5_bottom_alert0: trip-point0 {
5065 cpu5_bottom_alert1: trip-point1 {
5071 cpu5_bottom_crit: cpu-critical {
5079 cpu6-top-thermal {
5080 thermal-sensors = <&tsens0 11>;
5083 cpu6_top_alert0: trip-point0 {
5089 cpu6_top_alert1: trip-point1 {
5095 cpu6_top_crit: cpu-critical {
5103 cpu6-bottom-thermal {
5104 thermal-sensors = <&tsens0 12>;
5107 cpu6_bottom_alert0: trip-point0 {
5113 cpu6_bottom_alert1: trip-point1 {
5119 cpu6_bottom_crit: cpu-critical {
5127 cpu7-top-thermal {
5128 thermal-sensors = <&tsens0 13>;
5131 cpu7_top_alert0: trip-point0 {
5137 cpu7_top_alert1: trip-point1 {
5143 cpu7_top_crit: cpu-critical {
5151 cpu7-middle-thermal {
5152 thermal-sensors = <&tsens0 14>;
5155 cpu7_middle_alert0: trip-point0 {
5161 cpu7_middle_alert1: trip-point1 {
5167 cpu7_middle_crit: cpu-critical {
5175 cpu7-bottom-thermal {
5176 thermal-sensors = <&tsens0 15>;
5179 cpu7_bottom_alert0: trip-point0 {
5185 cpu7_bottom_alert1: trip-point1 {
5191 cpu7_bottom_crit: cpu-critical {
5199 aoss1-thermal {
5200 thermal-sensors = <&tsens1 0>;
5203 thermal-engine-config {
5209 reset-mon-config {
5217 cpu0-thermal {
5218 thermal-sensors = <&tsens1 1>;
5221 cpu0_alert0: trip-point0 {
5227 cpu0_alert1: trip-point1 {
5233 cpu0_crit: cpu-critical {
5241 cpu1-thermal {
5242 thermal-sensors = <&tsens1 2>;
5245 cpu1_alert0: trip-point0 {
5251 cpu1_alert1: trip-point1 {
5257 cpu1_crit: cpu-critical {
5265 cpu2-thermal {
5266 thermal-sensors = <&tsens1 3>;
5269 cpu2_alert0: trip-point0 {
5275 cpu2_alert1: trip-point1 {
5281 cpu2_crit: cpu-critical {
5289 cdsp0-thermal {
5290 polling-delay-passive = <10>;
5292 thermal-sensors = <&tsens2 4>;
5295 thermal-engine-config {
5301 thermal-hal-config {
5307 reset-mon-config {
5313 cdsp0_junction_config: junction-config {
5321 cdsp1-thermal {
5322 polling-delay-passive = <10>;
5324 thermal-sensors = <&tsens2 5>;
5327 thermal-engine-config {
5333 thermal-hal-config {
5339 reset-mon-config {
5345 cdsp1_junction_config: junction-config {
5353 cdsp2-thermal {
5354 polling-delay-passive = <10>;
5356 thermal-sensors = <&tsens2 6>;
5359 thermal-engine-config {
5365 thermal-hal-config {
5371 reset-mon-config {
5377 cdsp2_junction_config: junction-config {
5385 cdsp3-thermal {
5386 polling-delay-passive = <10>;
5388 thermal-sensors = <&tsens2 7>;
5391 thermal-engine-config {
5397 thermal-hal-config {
5403 reset-mon-config {
5409 cdsp3_junction_config: junction-config {
5417 video-thermal {
5418 thermal-sensors = <&tsens1 8>;
5421 thermal-engine-config {
5427 reset-mon-config {
5435 mem-thermal {
5436 polling-delay-passive = <10>;
5438 thermal-sensors = <&tsens1 9>;
5441 thermal-engine-config {
5447 ddr_config0: ddr0-config {
5453 reset-mon-config {
5461 modem0-thermal {
5462 thermal-sensors = <&tsens1 10>;
5465 thermal-engine-config {
5471 mdmss0_config0: mdmss0-config0 {
5477 mdmss0_config1: mdmss0-config1 {
5483 reset-mon-config {
5491 modem1-thermal {
5492 thermal-sensors = <&tsens1 11>;
5495 thermal-engine-config {
5501 mdmss1_config0: mdmss1-config0 {
5507 mdmss1_config1: mdmss1-config1 {
5513 reset-mon-config {
5521 modem2-thermal {
5522 thermal-sensors = <&tsens1 12>;
5525 thermal-engine-config {
5531 mdmss2_config0: mdmss2-config0 {
5537 mdmss2_config1: mdmss2-config1 {
5543 reset-mon-config {
5551 modem3-thermal {
5552 thermal-sensors = <&tsens1 13>;
5555 thermal-engine-config {
5561 mdmss3_config0: mdmss3-config0 {
5567 mdmss3_config1: mdmss3-config1 {
5573 reset-mon-config {
5581 camera0-thermal {
5582 thermal-sensors = <&tsens1 14>;
5585 thermal-engine-config {
5591 reset-mon-config {
5599 camera1-thermal {
5600 thermal-sensors = <&tsens1 15>;
5603 thermal-engine-config {
5609 reset-mon-config {
5617 aoss2-thermal {
5618 thermal-sensors = <&tsens2 0>;
5621 thermal-engine-config {
5627 reset-mon-config {
5635 gpuss-0-thermal {
5636 polling-delay-passive = <10>;
5638 thermal-sensors = <&tsens2 1>;
5640 cooling-maps {
5643 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5648 gpu0_alert0: trip-point0 {
5654 trip-point1 {
5660 trip-point2 {
5668 gpuss-1-thermal {
5669 polling-delay-passive = <10>;
5671 thermal-sensors = <&tsens2 2>;
5673 cooling-maps {
5676 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5681 gpu1_alert0: trip-point0 {
5687 trip-point1 {
5693 trip-point2 {
5701 gpuss-2-thermal {
5702 polling-delay-passive = <10>;
5704 thermal-sensors = <&tsens2 3>;
5706 cooling-maps {
5709 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5714 gpu2_alert0: trip-point0 {
5720 trip-point1 {
5726 trip-point2 {
5734 gpuss-3-thermal {
5735 polling-delay-passive = <10>;
5737 thermal-sensors = <&tsens2 4>;
5739 cooling-maps {
5742 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5747 gpu3_alert0: trip-point0 {
5753 trip-point1 {
5759 trip-point2 {
5767 gpuss-4-thermal {
5768 polling-delay-passive = <10>;
5770 thermal-sensors = <&tsens2 5>;
5772 cooling-maps {
5775 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5780 gpu4_alert0: trip-point0 {
5786 trip-point1 {
5792 trip-point2 {
5800 gpuss-5-thermal {
5801 polling-delay-passive = <10>;
5803 thermal-sensors = <&tsens2 6>;
5805 cooling-maps {
5808 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5813 gpu5_alert0: trip-point0 {
5819 trip-point1 {
5825 trip-point2 {
5833 gpuss-6-thermal {
5834 polling-delay-passive = <10>;
5836 thermal-sensors = <&tsens2 7>;
5838 cooling-maps {
5841 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5846 gpu6_alert0: trip-point0 {
5852 trip-point1 {
5858 trip-point2 {
5866 gpuss-7-thermal {
5867 polling-delay-passive = <10>;
5869 thermal-sensors = <&tsens2 8>;
5871 cooling-maps {
5874 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5879 gpu7_alert0: trip-point0 {
5885 trip-point1 {
5891 trip-point2 {
5901 compatible = "arm,armv8-timer";