Lines Matching +full:sm8550 +full:- +full:aggre1 +full:- +full:noc
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
8 #include <dt-bindings/clock/qcom,sm8550-camcc.h>
9 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
10 #include <dt-bindings/clock/qcom,sm8550-gpucc.h>
11 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
12 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
18 #include <dt-bindings/mailbox/qcom-ipcc.h>
19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/power/qcom,rpmhpd.h>
21 #include <dt-bindings/soc/qcom,gpr.h>
22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
23 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
24 #include <dt-bindings/phy/phy-qcom-qmp.h>
25 #include <dt-bindings/thermal/thermal.h>
28 interrupt-parent = <&intc>;
30 #address-cells = <2>;
31 #size-cells = <2>;
36 xo_board: xo-board {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
41 sleep_clk: sleep-clk {
42 compatible = "fixed-clock";
43 #clock-cells = <0>;
46 bi_tcxo_div2: bi-tcxo-div2-clk {
47 #clock-cells = <0>;
48 compatible = "fixed-factor-clock";
50 clock-mult = <1>;
51 clock-div = <2>;
54 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
55 #clock-cells = <0>;
56 compatible = "fixed-factor-clock";
58 clock-mult = <1>;
59 clock-div = <2>;
64 #address-cells = <2>;
65 #size-cells = <0>;
69 compatible = "arm,cortex-a510";
72 enable-method = "psci";
73 next-level-cache = <&L2_0>;
74 power-domains = <&CPU_PD0>;
75 power-domain-names = "psci";
76 qcom,freq-domain = <&cpufreq_hw 0>;
77 capacity-dmips-mhz = <1024>;
78 dynamic-power-coefficient = <100>;
79 #cooling-cells = <2>;
80 L2_0: l2-cache {
82 cache-level = <2>;
83 cache-unified;
84 next-level-cache = <&L3_0>;
85 L3_0: l3-cache {
87 cache-level = <3>;
88 cache-unified;
95 compatible = "arm,cortex-a510";
98 enable-method = "psci";
99 next-level-cache = <&L2_100>;
100 power-domains = <&CPU_PD1>;
101 power-domain-names = "psci";
102 qcom,freq-domain = <&cpufreq_hw 0>;
103 capacity-dmips-mhz = <1024>;
104 dynamic-power-coefficient = <100>;
105 #cooling-cells = <2>;
106 L2_100: l2-cache {
108 cache-level = <2>;
109 cache-unified;
110 next-level-cache = <&L3_0>;
116 compatible = "arm,cortex-a510";
119 enable-method = "psci";
120 next-level-cache = <&L2_200>;
121 power-domains = <&CPU_PD2>;
122 power-domain-names = "psci";
123 qcom,freq-domain = <&cpufreq_hw 0>;
124 capacity-dmips-mhz = <1024>;
125 dynamic-power-coefficient = <100>;
126 #cooling-cells = <2>;
127 L2_200: l2-cache {
129 cache-level = <2>;
130 cache-unified;
131 next-level-cache = <&L3_0>;
137 compatible = "arm,cortex-a715";
140 enable-method = "psci";
141 next-level-cache = <&L2_300>;
142 power-domains = <&CPU_PD3>;
143 power-domain-names = "psci";
144 qcom,freq-domain = <&cpufreq_hw 1>;
145 capacity-dmips-mhz = <1792>;
146 dynamic-power-coefficient = <270>;
147 #cooling-cells = <2>;
148 L2_300: l2-cache {
150 cache-level = <2>;
151 cache-unified;
152 next-level-cache = <&L3_0>;
158 compatible = "arm,cortex-a715";
161 enable-method = "psci";
162 next-level-cache = <&L2_400>;
163 power-domains = <&CPU_PD4>;
164 power-domain-names = "psci";
165 qcom,freq-domain = <&cpufreq_hw 1>;
166 capacity-dmips-mhz = <1792>;
167 dynamic-power-coefficient = <270>;
168 #cooling-cells = <2>;
169 L2_400: l2-cache {
171 cache-level = <2>;
172 cache-unified;
173 next-level-cache = <&L3_0>;
179 compatible = "arm,cortex-a710";
182 enable-method = "psci";
183 next-level-cache = <&L2_500>;
184 power-domains = <&CPU_PD5>;
185 power-domain-names = "psci";
186 qcom,freq-domain = <&cpufreq_hw 1>;
187 capacity-dmips-mhz = <1792>;
188 dynamic-power-coefficient = <270>;
189 #cooling-cells = <2>;
190 L2_500: l2-cache {
192 cache-level = <2>;
193 cache-unified;
194 next-level-cache = <&L3_0>;
200 compatible = "arm,cortex-a710";
203 enable-method = "psci";
204 next-level-cache = <&L2_600>;
205 power-domains = <&CPU_PD6>;
206 power-domain-names = "psci";
207 qcom,freq-domain = <&cpufreq_hw 1>;
208 capacity-dmips-mhz = <1792>;
209 dynamic-power-coefficient = <270>;
210 #cooling-cells = <2>;
211 L2_600: l2-cache {
213 cache-level = <2>;
214 cache-unified;
215 next-level-cache = <&L3_0>;
221 compatible = "arm,cortex-x3";
224 enable-method = "psci";
225 next-level-cache = <&L2_700>;
226 power-domains = <&CPU_PD7>;
227 power-domain-names = "psci";
228 qcom,freq-domain = <&cpufreq_hw 2>;
229 capacity-dmips-mhz = <1894>;
230 dynamic-power-coefficient = <588>;
231 #cooling-cells = <2>;
232 L2_700: l2-cache {
234 cache-level = <2>;
235 cache-unified;
236 next-level-cache = <&L3_0>;
240 cpu-map {
276 idle-states {
277 entry-method = "psci";
279 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
280 compatible = "arm,idle-state";
281 idle-state-name = "silver-rail-power-collapse";
282 arm,psci-suspend-param = <0x40000004>;
283 entry-latency-us = <550>;
284 exit-latency-us = <750>;
285 min-residency-us = <6700>;
286 local-timer-stop;
289 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
290 compatible = "arm,idle-state";
291 idle-state-name = "gold-rail-power-collapse";
292 arm,psci-suspend-param = <0x40000004>;
293 entry-latency-us = <600>;
294 exit-latency-us = <1300>;
295 min-residency-us = <8136>;
296 local-timer-stop;
299 PRIME_CPU_SLEEP_0: cpu-sleep-2-0 {
300 compatible = "arm,idle-state";
301 idle-state-name = "goldplus-rail-power-collapse";
302 arm,psci-suspend-param = <0x40000004>;
303 entry-latency-us = <500>;
304 exit-latency-us = <1350>;
305 min-residency-us = <7480>;
306 local-timer-stop;
310 domain-idle-states {
311 CLUSTER_SLEEP_0: cluster-sleep-0 {
312 compatible = "domain-idle-state";
313 arm,psci-suspend-param = <0x41000044>;
314 entry-latency-us = <750>;
315 exit-latency-us = <2350>;
316 min-residency-us = <9144>;
319 CLUSTER_SLEEP_1: cluster-sleep-1 {
320 compatible = "domain-idle-state";
321 arm,psci-suspend-param = <0x4100c344>;
322 entry-latency-us = <2800>;
323 exit-latency-us = <4400>;
324 min-residency-us = <10150>;
331 compatible = "qcom,scm-sm8550", "qcom,scm";
332 qcom,dload-mode = <&tcsr 0x19000>;
337 clk_virt: interconnect-0 {
338 compatible = "qcom,sm8550-clk-virt";
339 #interconnect-cells = <2>;
340 qcom,bcm-voters = <&apps_bcm_voter>;
343 mc_virt: interconnect-1 {
344 compatible = "qcom,sm8550-mc-virt";
345 #interconnect-cells = <2>;
346 qcom,bcm-voters = <&apps_bcm_voter>;
355 pmu-a510 {
356 compatible = "arm,cortex-a510-pmu";
360 pmu-a710 {
361 compatible = "arm,cortex-a710-pmu";
365 pmu-a715 {
366 compatible = "arm,cortex-a715-pmu";
370 pmu-x3 {
371 compatible = "arm,cortex-x3-pmu";
376 compatible = "arm,psci-1.0";
379 CPU_PD0: power-domain-cpu0 {
380 #power-domain-cells = <0>;
381 power-domains = <&CLUSTER_PD>;
382 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
385 CPU_PD1: power-domain-cpu1 {
386 #power-domain-cells = <0>;
387 power-domains = <&CLUSTER_PD>;
388 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
391 CPU_PD2: power-domain-cpu2 {
392 #power-domain-cells = <0>;
393 power-domains = <&CLUSTER_PD>;
394 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
397 CPU_PD3: power-domain-cpu3 {
398 #power-domain-cells = <0>;
399 power-domains = <&CLUSTER_PD>;
400 domain-idle-states = <&BIG_CPU_SLEEP_0>;
403 CPU_PD4: power-domain-cpu4 {
404 #power-domain-cells = <0>;
405 power-domains = <&CLUSTER_PD>;
406 domain-idle-states = <&BIG_CPU_SLEEP_0>;
409 CPU_PD5: power-domain-cpu5 {
410 #power-domain-cells = <0>;
411 power-domains = <&CLUSTER_PD>;
412 domain-idle-states = <&BIG_CPU_SLEEP_0>;
415 CPU_PD6: power-domain-cpu6 {
416 #power-domain-cells = <0>;
417 power-domains = <&CLUSTER_PD>;
418 domain-idle-states = <&BIG_CPU_SLEEP_0>;
421 CPU_PD7: power-domain-cpu7 {
422 #power-domain-cells = <0>;
423 power-domains = <&CLUSTER_PD>;
424 domain-idle-states = <&PRIME_CPU_SLEEP_0>;
427 CLUSTER_PD: power-domain-cluster {
428 #power-domain-cells = <0>;
429 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
433 reserved_memory: reserved-memory {
434 #address-cells = <2>;
435 #size-cells = <2>;
438 hyp_mem: hyp-region@80000000 {
440 no-map;
443 cpusys_vm_mem: cpusys-vm-region@80a00000 {
445 no-map;
448 hyp_tags_mem: hyp-tags-region@80e00000 {
450 no-map;
453 xbl_sc_mem: xbl-sc-region@d8100000 {
455 no-map;
458 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 {
460 no-map;
464 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 {
466 no-map;
469 aop_cmd_db_mem: aop-cmd-db-region@81c60000 {
470 compatible = "qcom,cmd-db";
472 no-map;
476 aop_config_merged_mem: aop-config-merged-region@81c80000 {
478 no-map;
486 no-map;
489 adsp_mhi_mem: adsp-mhi-region@81f00000 {
491 no-map;
494 global_sync_mem: global-sync-region@82600000 {
496 no-map;
499 tz_stat_mem: tz-stat-region@82700000 {
501 no-map;
504 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 {
506 no-map;
509 mpss_mem: mpss-region@8a800000 {
511 no-map;
514 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 {
516 no-map;
519 ipa_fw_mem: ipa-fw-region@9b080000 {
521 no-map;
524 ipa_gsi_mem: ipa-gsi-region@9b090000 {
526 no-map;
529 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 {
531 no-map;
534 spss_region_mem: spss-region@9b100000 {
536 no-map;
540 spu_tz_shared_mem: spu-tz-shared-region@9b280000 {
542 no-map;
546 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 {
548 no-map;
551 camera_mem: camera-region@9b300000 {
553 no-map;
556 video_mem: video-region@9bb00000 {
558 no-map;
561 cvp_mem: cvp-region@9c200000 {
563 no-map;
566 cdsp_mem: cdsp-region@9c900000 {
568 no-map;
571 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 {
573 no-map;
576 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 {
578 no-map;
581 adspslpi_mem: adspslpi-region@9ea00000 {
583 no-map;
590 rmtfs_mem: rmtfs-region@d4a80000 {
591 compatible = "qcom,rmtfs-mem";
593 no-map;
595 qcom,client-id = <1>;
599 mpss_dsm_mem: mpss-dsm-region@d4d00000 {
601 no-map;
604 tz_reserved_mem: tz-reserved-region@d8000000 {
606 no-map;
609 cpucp_fw_mem: cpucp-fw-region@d8140000 {
611 no-map;
614 qtee_mem: qtee-region@d8300000 {
616 no-map;
619 ta_mem: ta-region@d8800000 {
621 no-map;
624 tz_tags_mem: tz-tags-region@e1200000 {
626 no-map;
629 hwfence_shbuf: hwfence-shbuf-region@e6440000 {
631 no-map;
634 trust_ui_vm_mem: trust-ui-vm-region@f3600000 {
636 no-map;
639 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 {
641 no-map;
644 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 {
646 no-map;
649 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 {
651 no-map;
654 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 {
656 no-map;
659 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 {
661 no-map;
664 oem_vm_mem: oem-vm-region@f8400000 {
666 no-map;
669 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 {
671 no-map;
674 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 {
676 no-map;
679 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 {
681 no-map;
684 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 {
686 no-map;
690 smp2p-adsp {
693 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
699 qcom,local-pid = <0>;
700 qcom,remote-pid = <2>;
702 smp2p_adsp_out: master-kernel {
703 qcom,entry-name = "master-kernel";
704 #qcom,smem-state-cells = <1>;
707 smp2p_adsp_in: slave-kernel {
708 qcom,entry-name = "slave-kernel";
709 interrupt-controller;
710 #interrupt-cells = <2>;
714 smp2p-cdsp {
717 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
723 qcom,local-pid = <0>;
724 qcom,remote-pid = <5>;
726 smp2p_cdsp_out: master-kernel {
727 qcom,entry-name = "master-kernel";
728 #qcom,smem-state-cells = <1>;
731 smp2p_cdsp_in: slave-kernel {
732 qcom,entry-name = "slave-kernel";
733 interrupt-controller;
734 #interrupt-cells = <2>;
738 smp2p-modem {
741 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
747 qcom,local-pid = <0>;
748 qcom,remote-pid = <1>;
750 smp2p_modem_out: master-kernel {
751 qcom,entry-name = "master-kernel";
752 #qcom,smem-state-cells = <1>;
755 smp2p_modem_in: slave-kernel {
756 qcom,entry-name = "slave-kernel";
757 interrupt-controller;
758 #interrupt-cells = <2>;
761 ipa_smp2p_out: ipa-ap-to-modem {
762 qcom,entry-name = "ipa";
763 #qcom,smem-state-cells = <1>;
766 ipa_smp2p_in: ipa-modem-to-ap {
767 qcom,entry-name = "ipa";
768 interrupt-controller;
769 #interrupt-cells = <2>;
774 compatible = "simple-bus";
776 dma-ranges = <0 0 0 0 0x10 0>;
778 #address-cells = <2>;
779 #size-cells = <2>;
781 gcc: clock-controller@100000 {
782 compatible = "qcom,sm8550-gcc";
784 #clock-cells = <1>;
785 #reset-cells = <1>;
786 #power-domain-cells = <1>;
798 compatible = "qcom,sm8550-ipcc", "qcom,ipcc";
801 interrupt-controller;
802 #interrupt-cells = <3>;
803 #mbox-cells = <2>;
806 gpi_dma2: dma-controller@800000 {
807 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
808 #dma-cells = <3>;
822 dma-channels = <12>;
823 dma-channel-mask = <0x3e>;
825 dma-coherent;
830 compatible = "qcom,geni-se-qup";
833 clock-names = "m-ahb", "s-ahb";
837 dma-coherent;
838 #address-cells = <2>;
839 #size-cells = <2>;
843 compatible = "qcom,geni-i2c";
845 clock-names = "se";
847 pinctrl-names = "default";
848 pinctrl-0 = <&qup_i2c8_data_clk>;
850 #address-cells = <1>;
851 #size-cells = <0>;
855 interconnect-names = "qup-core", "qup-config", "qup-memory";
858 dma-names = "tx", "rx";
863 compatible = "qcom,geni-spi";
865 clock-names = "se";
868 pinctrl-names = "default";
869 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
873 interconnect-names = "qup-core", "qup-config", "qup-memory";
876 dma-names = "tx", "rx";
877 #address-cells = <1>;
878 #size-cells = <0>;
883 compatible = "qcom,geni-i2c";
885 clock-names = "se";
887 pinctrl-names = "default";
888 pinctrl-0 = <&qup_i2c9_data_clk>;
890 #address-cells = <1>;
891 #size-cells = <0>;
895 interconnect-names = "qup-core", "qup-config", "qup-memory";
898 dma-names = "tx", "rx";
903 compatible = "qcom,geni-spi";
905 clock-names = "se";
908 pinctrl-names = "default";
909 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
913 interconnect-names = "qup-core", "qup-config", "qup-memory";
916 dma-names = "tx", "rx";
917 #address-cells = <1>;
918 #size-cells = <0>;
923 compatible = "qcom,geni-i2c";
925 clock-names = "se";
927 pinctrl-names = "default";
928 pinctrl-0 = <&qup_i2c10_data_clk>;
930 #address-cells = <1>;
931 #size-cells = <0>;
935 interconnect-names = "qup-core", "qup-config", "qup-memory";
938 dma-names = "tx", "rx";
943 compatible = "qcom,geni-spi";
945 clock-names = "se";
948 pinctrl-names = "default";
949 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
953 interconnect-names = "qup-core", "qup-config", "qup-memory";
956 dma-names = "tx", "rx";
957 #address-cells = <1>;
958 #size-cells = <0>;
963 compatible = "qcom,geni-i2c";
965 clock-names = "se";
967 pinctrl-names = "default";
968 pinctrl-0 = <&qup_i2c11_data_clk>;
970 #address-cells = <1>;
971 #size-cells = <0>;
975 interconnect-names = "qup-core", "qup-config", "qup-memory";
978 dma-names = "tx", "rx";
983 compatible = "qcom,geni-spi";
985 clock-names = "se";
988 pinctrl-names = "default";
989 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
993 interconnect-names = "qup-core", "qup-config", "qup-memory";
996 dma-names = "tx", "rx";
997 #address-cells = <1>;
998 #size-cells = <0>;
1003 compatible = "qcom,geni-i2c";
1005 clock-names = "se";
1007 pinctrl-names = "default";
1008 pinctrl-0 = <&qup_i2c12_data_clk>;
1010 #address-cells = <1>;
1011 #size-cells = <0>;
1015 interconnect-names = "qup-core", "qup-config", "qup-memory";
1018 dma-names = "tx", "rx";
1023 compatible = "qcom,geni-spi";
1025 clock-names = "se";
1028 pinctrl-names = "default";
1029 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1033 interconnect-names = "qup-core", "qup-config", "qup-memory";
1036 dma-names = "tx", "rx";
1037 #address-cells = <1>;
1038 #size-cells = <0>;
1043 compatible = "qcom,geni-i2c";
1045 clock-names = "se";
1047 pinctrl-names = "default";
1048 pinctrl-0 = <&qup_i2c13_data_clk>;
1050 #address-cells = <1>;
1051 #size-cells = <0>;
1055 interconnect-names = "qup-core", "qup-config", "qup-memory";
1058 dma-names = "tx", "rx";
1063 compatible = "qcom,geni-spi";
1065 clock-names = "se";
1068 pinctrl-names = "default";
1069 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1073 interconnect-names = "qup-core", "qup-config", "qup-memory";
1076 dma-names = "tx", "rx";
1077 #address-cells = <1>;
1078 #size-cells = <0>;
1083 compatible = "qcom,geni-uart";
1085 clock-names = "se";
1087 pinctrl-names = "default";
1088 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
1092 interconnect-names = "qup-core", "qup-config";
1097 compatible = "qcom,geni-i2c";
1099 clock-names = "se";
1101 pinctrl-names = "default";
1102 pinctrl-0 = <&qup_i2c15_data_clk>;
1104 #address-cells = <1>;
1105 #size-cells = <0>;
1109 interconnect-names = "qup-core", "qup-config", "qup-memory";
1112 dma-names = "tx", "rx";
1117 compatible = "qcom,geni-spi";
1119 clock-names = "se";
1122 pinctrl-names = "default";
1123 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1127 interconnect-names = "qup-core", "qup-config", "qup-memory";
1130 dma-names = "tx", "rx";
1131 #address-cells = <1>;
1132 #size-cells = <0>;
1138 compatible = "qcom,geni-se-i2c-master-hub";
1140 clock-names = "s-ahb";
1142 #address-cells = <2>;
1143 #size-cells = <2>;
1148 compatible = "qcom,geni-i2c-master-hub";
1150 clock-names = "se", "core";
1153 pinctrl-names = "default";
1154 pinctrl-0 = <&hub_i2c0_data_clk>;
1156 #address-cells = <1>;
1157 #size-cells = <0>;
1160 interconnect-names = "qup-core", "qup-config";
1165 compatible = "qcom,geni-i2c-master-hub";
1167 clock-names = "se", "core";
1170 pinctrl-names = "default";
1171 pinctrl-0 = <&hub_i2c1_data_clk>;
1173 #address-cells = <1>;
1174 #size-cells = <0>;
1177 interconnect-names = "qup-core", "qup-config";
1182 compatible = "qcom,geni-i2c-master-hub";
1184 clock-names = "se", "core";
1187 pinctrl-names = "default";
1188 pinctrl-0 = <&hub_i2c2_data_clk>;
1190 #address-cells = <1>;
1191 #size-cells = <0>;
1194 interconnect-names = "qup-core", "qup-config";
1199 compatible = "qcom,geni-i2c-master-hub";
1201 clock-names = "se", "core";
1204 pinctrl-names = "default";
1205 pinctrl-0 = <&hub_i2c3_data_clk>;
1207 #address-cells = <1>;
1208 #size-cells = <0>;
1211 interconnect-names = "qup-core", "qup-config";
1216 compatible = "qcom,geni-i2c-master-hub";
1218 clock-names = "se", "core";
1221 pinctrl-names = "default";
1222 pinctrl-0 = <&hub_i2c4_data_clk>;
1224 #address-cells = <1>;
1225 #size-cells = <0>;
1228 interconnect-names = "qup-core", "qup-config";
1233 compatible = "qcom,geni-i2c-master-hub";
1235 clock-names = "se", "core";
1238 pinctrl-names = "default";
1239 pinctrl-0 = <&hub_i2c5_data_clk>;
1241 #address-cells = <1>;
1242 #size-cells = <0>;
1245 interconnect-names = "qup-core", "qup-config";
1250 compatible = "qcom,geni-i2c-master-hub";
1252 clock-names = "se", "core";
1255 pinctrl-names = "default";
1256 pinctrl-0 = <&hub_i2c6_data_clk>;
1258 #address-cells = <1>;
1259 #size-cells = <0>;
1262 interconnect-names = "qup-core", "qup-config";
1267 compatible = "qcom,geni-i2c-master-hub";
1269 clock-names = "se", "core";
1272 pinctrl-names = "default";
1273 pinctrl-0 = <&hub_i2c7_data_clk>;
1275 #address-cells = <1>;
1276 #size-cells = <0>;
1279 interconnect-names = "qup-core", "qup-config";
1284 compatible = "qcom,geni-i2c-master-hub";
1286 clock-names = "se", "core";
1289 pinctrl-names = "default";
1290 pinctrl-0 = <&hub_i2c8_data_clk>;
1292 #address-cells = <1>;
1293 #size-cells = <0>;
1296 interconnect-names = "qup-core", "qup-config";
1301 compatible = "qcom,geni-i2c-master-hub";
1303 clock-names = "se", "core";
1306 pinctrl-names = "default";
1307 pinctrl-0 = <&hub_i2c9_data_clk>;
1309 #address-cells = <1>;
1310 #size-cells = <0>;
1313 interconnect-names = "qup-core", "qup-config";
1318 gpi_dma1: dma-controller@a00000 {
1319 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
1320 #dma-cells = <3>;
1334 dma-channels = <12>;
1335 dma-channel-mask = <0x1e>;
1337 dma-coherent;
1342 compatible = "qcom,geni-se-qup";
1345 clock-names = "m-ahb", "s-ahb";
1350 interconnect-names = "qup-core";
1351 dma-coherent;
1352 #address-cells = <2>;
1353 #size-cells = <2>;
1357 compatible = "qcom,geni-i2c";
1359 clock-names = "se";
1361 pinctrl-names = "default";
1362 pinctrl-0 = <&qup_i2c0_data_clk>;
1364 #address-cells = <1>;
1365 #size-cells = <0>;
1369 interconnect-names = "qup-core", "qup-config", "qup-memory";
1372 dma-names = "tx", "rx";
1377 compatible = "qcom,geni-spi";
1379 clock-names = "se";
1382 pinctrl-names = "default";
1383 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1387 interconnect-names = "qup-core", "qup-config", "qup-memory";
1390 dma-names = "tx", "rx";
1391 #address-cells = <1>;
1392 #size-cells = <0>;
1397 compatible = "qcom,geni-i2c";
1399 clock-names = "se";
1401 pinctrl-names = "default";
1402 pinctrl-0 = <&qup_i2c1_data_clk>;
1404 #address-cells = <1>;
1405 #size-cells = <0>;
1409 interconnect-names = "qup-core", "qup-config", "qup-memory";
1412 dma-names = "tx", "rx";
1417 compatible = "qcom,geni-spi";
1419 clock-names = "se";
1422 pinctrl-names = "default";
1423 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1427 interconnect-names = "qup-core", "qup-config", "qup-memory";
1430 dma-names = "tx", "rx";
1431 #address-cells = <1>;
1432 #size-cells = <0>;
1437 compatible = "qcom,geni-i2c";
1439 clock-names = "se";
1441 pinctrl-names = "default";
1442 pinctrl-0 = <&qup_i2c2_data_clk>;
1444 #address-cells = <1>;
1445 #size-cells = <0>;
1449 interconnect-names = "qup-core", "qup-config", "qup-memory";
1452 dma-names = "tx", "rx";
1457 compatible = "qcom,geni-spi";
1459 clock-names = "se";
1462 pinctrl-names = "default";
1463 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1467 interconnect-names = "qup-core", "qup-config", "qup-memory";
1470 dma-names = "tx", "rx";
1471 #address-cells = <1>;
1472 #size-cells = <0>;
1477 compatible = "qcom,geni-i2c";
1479 clock-names = "se";
1481 pinctrl-names = "default";
1482 pinctrl-0 = <&qup_i2c3_data_clk>;
1484 #address-cells = <1>;
1485 #size-cells = <0>;
1489 interconnect-names = "qup-core", "qup-config", "qup-memory";
1492 dma-names = "tx", "rx";
1497 compatible = "qcom,geni-spi";
1499 clock-names = "se";
1502 pinctrl-names = "default";
1503 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1507 interconnect-names = "qup-core", "qup-config", "qup-memory";
1510 dma-names = "tx", "rx";
1511 #address-cells = <1>;
1512 #size-cells = <0>;
1517 compatible = "qcom,geni-i2c";
1519 clock-names = "se";
1521 pinctrl-names = "default";
1522 pinctrl-0 = <&qup_i2c4_data_clk>;
1524 #address-cells = <1>;
1525 #size-cells = <0>;
1529 interconnect-names = "qup-core", "qup-config", "qup-memory";
1532 dma-names = "tx", "rx";
1537 compatible = "qcom,geni-spi";
1539 clock-names = "se";
1542 pinctrl-names = "default";
1543 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1547 interconnect-names = "qup-core", "qup-config", "qup-memory";
1550 dma-names = "tx", "rx";
1551 #address-cells = <1>;
1552 #size-cells = <0>;
1557 compatible = "qcom,geni-i2c";
1559 clock-names = "se";
1561 pinctrl-names = "default";
1562 pinctrl-0 = <&qup_i2c5_data_clk>;
1567 interconnect-names = "qup-core", "qup-config", "qup-memory";
1570 dma-names = "tx", "rx";
1571 #address-cells = <1>;
1572 #size-cells = <0>;
1577 compatible = "qcom,geni-spi";
1579 clock-names = "se";
1582 pinctrl-names = "default";
1583 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1587 interconnect-names = "qup-core", "qup-config", "qup-memory";
1590 dma-names = "tx", "rx";
1591 #address-cells = <1>;
1592 #size-cells = <0>;
1597 compatible = "qcom,geni-i2c";
1599 clock-names = "se";
1601 pinctrl-names = "default";
1602 pinctrl-0 = <&qup_i2c6_data_clk>;
1607 interconnect-names = "qup-core", "qup-config", "qup-memory";
1610 dma-names = "tx", "rx";
1611 #address-cells = <1>;
1612 #size-cells = <0>;
1617 compatible = "qcom,geni-spi";
1619 clock-names = "se";
1622 pinctrl-names = "default";
1623 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1627 interconnect-names = "qup-core", "qup-config", "qup-memory";
1630 dma-names = "tx", "rx";
1631 #address-cells = <1>;
1632 #size-cells = <0>;
1637 compatible = "qcom,geni-debug-uart";
1639 clock-names = "se";
1641 pinctrl-names = "default";
1642 pinctrl-0 = <&qup_uart7_default>;
1644 interconnect-names = "qup-core", "qup-config";
1652 compatible = "qcom,sm8550-cnoc-main";
1654 #interconnect-cells = <2>;
1655 qcom,bcm-voters = <&apps_bcm_voter>;
1659 compatible = "qcom,sm8550-config-noc";
1661 #interconnect-cells = <2>;
1662 qcom,bcm-voters = <&apps_bcm_voter>;
1666 compatible = "qcom,sm8550-system-noc";
1668 #interconnect-cells = <2>;
1669 qcom,bcm-voters = <&apps_bcm_voter>;
1673 compatible = "qcom,sm8550-pcie-anoc";
1675 #interconnect-cells = <2>;
1678 qcom,bcm-voters = <&apps_bcm_voter>;
1682 compatible = "qcom,sm8550-aggre1-noc";
1684 #interconnect-cells = <2>;
1687 qcom,bcm-voters = <&apps_bcm_voter>;
1691 compatible = "qcom,sm8550-aggre2-noc";
1693 #interconnect-cells = <2>;
1695 qcom,bcm-voters = <&apps_bcm_voter>;
1699 compatible = "qcom,sm8550-mmss-noc";
1701 #interconnect-cells = <2>;
1702 qcom,bcm-voters = <&apps_bcm_voter>;
1706 compatible = "qcom,sm8550-trng", "qcom,trng";
1712 compatible = "qcom,pcie-sm8550";
1718 reg-names = "parf", "dbi", "elbi", "atu", "config";
1719 #address-cells = <3>;
1720 #size-cells = <2>;
1723 bus-range = <0x00 0xff>;
1725 dma-coherent;
1727 linux,pci-domain = <0>;
1728 num-lanes = <2>;
1738 interrupt-names = "msi0",
1746 #interrupt-cells = <1>;
1747 interrupt-map-mask = <0 0 0 0x7>;
1748 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1760 clock-names = "aux",
1770 interconnect-names = "pcie-mem", "cpu-pcie";
1772 msi-map = <0x0 &gic_its 0x1400 0x1>,
1774 iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
1778 reset-names = "pci";
1780 power-domains = <&gcc PCIE_0_GDSC>;
1783 phy-names = "pciephy";
1790 bus-range = <0x01 0xff>;
1792 #address-cells = <3>;
1793 #size-cells = <2>;
1799 compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy";
1807 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1811 reset-names = "phy";
1813 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1814 assigned-clock-rates = <100000000>;
1816 power-domains = <&gcc PCIE_0_PHY_GDSC>;
1818 #clock-cells = <0>;
1819 clock-output-names = "pcie0_pipe_clk";
1821 #phy-cells = <0>;
1828 compatible = "qcom,pcie-sm8550";
1834 reg-names = "parf", "dbi", "elbi", "atu", "config";
1835 #address-cells = <3>;
1836 #size-cells = <2>;
1839 bus-range = <0x00 0xff>;
1841 dma-coherent;
1843 linux,pci-domain = <1>;
1844 num-lanes = <2>;
1854 interrupt-names = "msi0",
1862 #interrupt-cells = <1>;
1863 interrupt-map-mask = <0 0 0 0x7>;
1864 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1877 clock-names = "aux",
1886 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1887 assigned-clock-rates = <19200000>;
1891 interconnect-names = "pcie-mem", "cpu-pcie";
1893 msi-map = <0x0 &gic_its 0x1480 0x1>,
1895 iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
1900 reset-names = "pci", "link_down";
1902 power-domains = <&gcc PCIE_1_GDSC>;
1905 phy-names = "pciephy";
1912 bus-range = <0x01 0xff>;
1914 #address-cells = <3>;
1915 #size-cells = <2>;
1921 compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy";
1929 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1934 reset-names = "phy", "phy_nocsr";
1936 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
1937 assigned-clock-rates = <100000000>;
1939 power-domains = <&gcc PCIE_1_PHY_GDSC>;
1941 #clock-cells = <1>;
1942 clock-output-names = "pcie1_pipe_clk";
1944 #phy-cells = <0>;
1949 cryptobam: dma-controller@1dc4000 {
1950 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
1953 #dma-cells = <1>;
1955 qcom,controlled-remotely;
1961 compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce";
1964 dma-names = "rx", "tx";
1968 interconnect-names = "memory";
1972 compatible = "qcom,sm8550-qmp-ufs-phy";
1977 clock-names = "ref",
1981 power-domains = <&gcc UFS_MEM_PHY_GDSC>;
1984 reset-names = "ufsphy";
1986 #clock-cells = <1>;
1987 #phy-cells = <0>;
1993 compatible = "qcom,sm8550-ufshc", "qcom,ufshc",
1994 "jedec,ufs-2.0";
1998 phy-names = "ufsphy";
1999 lanes-per-direction = <2>;
2000 #reset-cells = <1>;
2002 reset-names = "rst";
2004 power-domains = <&gcc UFS_PHY_GDSC>;
2005 required-opps = <&rpmhpd_opp_nom>;
2008 dma-coherent;
2010 operating-points-v2 = <&ufs_opp_table>;
2014 interconnect-names = "ufs-ddr", "cpu-ufs";
2015 clock-names = "core_clk",
2035 ufs_opp_table: opp-table {
2036 compatible = "operating-points-v2";
2038 opp-75000000 {
2039 opp-hz = /bits/ 64 <75000000>,
2047 required-opps = <&rpmhpd_opp_low_svs>;
2050 opp-150000000 {
2051 opp-hz = /bits/ 64 <150000000>,
2059 required-opps = <&rpmhpd_opp_svs>;
2062 opp-300000000 {
2063 opp-hz = /bits/ 64 <300000000>,
2071 required-opps = <&rpmhpd_opp_nom>;
2077 compatible = "qcom,sm8550-inline-crypto-engine",
2078 "qcom,inline-crypto-engine";
2084 compatible = "qcom,tcsr-mutex";
2086 #hwlock-cells = <1>;
2089 tcsr: clock-controller@1fc0000 {
2090 compatible = "qcom,sm8550-tcsr", "syscon";
2093 #clock-cells = <1>;
2094 #reset-cells = <1>;
2098 compatible = "qcom,adreno-43050a01", "qcom,adreno";
2102 reg-names = "kgsl_3d0_reg_memory",
2111 operating-points-v2 = <&gpu_opp_table>;
2114 #cooling-cells = <2>;
2118 zap-shader {
2119 memory-region = <&gpu_micro_code_mem>;
2123 gpu_opp_table: opp-table {
2124 compatible = "operating-points-v2";
2126 opp-680000000 {
2127 opp-hz = /bits/ 64 <680000000>;
2128 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2131 opp-615000000 {
2132 opp-hz = /bits/ 64 <615000000>;
2133 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2136 opp-550000000 {
2137 opp-hz = /bits/ 64 <550000000>;
2138 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2141 opp-475000000 {
2142 opp-hz = /bits/ 64 <475000000>;
2143 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
2146 opp-401000000 {
2147 opp-hz = /bits/ 64 <401000000>;
2148 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2151 opp-348000000 {
2152 opp-hz = /bits/ 64 <348000000>;
2153 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
2156 opp-295000000 {
2157 opp-hz = /bits/ 64 <295000000>;
2158 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2161 opp-220000000 {
2162 opp-hz = /bits/ 64 <220000000>;
2163 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
2169 compatible = "qcom,adreno-gmu-740.1", "qcom,adreno-gmu";
2173 reg-names = "gmu", "rscc", "gmu_pdc";
2177 interrupt-names = "hfi", "gmu";
2186 clock-names = "ahb",
2194 power-domains = <&gpucc GPU_CC_CX_GDSC>,
2196 power-domain-names = "cx",
2203 operating-points-v2 = <&gmu_opp_table>;
2205 gmu_opp_table: opp-table {
2206 compatible = "operating-points-v2";
2208 opp-500000000 {
2209 opp-hz = /bits/ 64 <500000000>;
2210 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2213 opp-200000000 {
2214 opp-hz = /bits/ 64 <200000000>;
2215 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2220 gpucc: clock-controller@3d90000 {
2221 compatible = "qcom,sm8550-gpucc";
2226 #clock-cells = <1>;
2227 #reset-cells = <1>;
2228 #power-domain-cells = <1>;
2232 compatible = "qcom,sm8550-smmu-500", "qcom,adreno-smmu",
2233 "qcom,smmu-500", "arm,mmu-500";
2235 #iommu-cells = <2>;
2236 #global-interrupts = <1>;
2267 clock-names = "hlos",
2271 power-domains = <&gpucc GPU_CC_CX_GDSC>;
2272 dma-coherent;
2276 compatible = "qcom,sm8550-ipa";
2283 reg-names = "ipa-reg",
2284 "ipa-shared",
2287 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
2291 interrupt-names = "ipa",
2293 "ipa-clock-query",
2294 "ipa-setup-ready";
2297 clock-names = "core";
2301 interconnect-names = "memory",
2306 qcom,smem-states = <&ipa_smp2p_out 0>,
2308 qcom,smem-state-names = "ipa-clock-enabled-valid",
2309 "ipa-clock-enabled";
2315 compatible = "qcom,sm8550-mpss-pas";
2318 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2324 interrupt-names = "wdog", "fatal", "ready", "handover",
2325 "stop-ack", "shutdown-ack";
2328 clock-names = "xo";
2330 power-domains = <&rpmhpd RPMHPD_CX>,
2332 power-domain-names = "cx", "mss";
2336 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>;
2340 qcom,smem-states = <&smp2p_modem_out 0>;
2341 qcom,smem-state-names = "stop";
2345 glink-edge {
2346 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2352 qcom,remote-pid = <1>;
2357 compatible = "qcom,sm8550-lpass-wsa-macro";
2363 clock-names = "mclk", "macro", "dcodec", "fsgen";
2365 #clock-cells = <0>;
2366 clock-output-names = "wsa2-mclk";
2367 #sound-dai-cells = <1>;
2371 compatible = "qcom,soundwire-v2.0.0";
2375 clock-names = "iface";
2378 pinctrl-0 = <&wsa2_swr_active>;
2379 pinctrl-names = "default";
2381 qcom,din-ports = <4>;
2382 qcom,dout-ports = <9>;
2384 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
2385 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2386 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2387 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2388 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2389 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
2390 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
2391 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2392 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2394 #address-cells = <2>;
2395 #size-cells = <0>;
2396 #sound-dai-cells = <1>;
2401 compatible = "qcom,sm8550-lpass-rx-macro";
2407 clock-names = "mclk", "macro", "dcodec", "fsgen";
2409 #clock-cells = <0>;
2410 clock-output-names = "mclk";
2411 #sound-dai-cells = <1>;
2415 compatible = "qcom,soundwire-v2.0.0";
2419 clock-names = "iface";
2422 pinctrl-0 = <&rx_swr_active>;
2423 pinctrl-names = "default";
2425 qcom,din-ports = <1>;
2426 qcom,dout-ports = <11>;
2428 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff 0xff 0xff>;
2429 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2430 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2431 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>;
2432 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>;
2433 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff 0xff 0xff>;
2434 …qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff 0xff 0xff…
2435 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0x…
2436 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2438 #address-cells = <2>;
2439 #size-cells = <0>;
2440 #sound-dai-cells = <1>;
2445 compatible = "qcom,sm8550-lpass-tx-macro";
2451 clock-names = "mclk", "macro", "dcodec", "fsgen";
2453 #clock-cells = <0>;
2454 clock-output-names = "mclk";
2455 #sound-dai-cells = <1>;
2459 compatible = "qcom,sm8550-lpass-wsa-macro";
2465 clock-names = "mclk", "macro", "dcodec", "fsgen";
2467 #clock-cells = <0>;
2468 clock-output-names = "mclk";
2469 #sound-dai-cells = <1>;
2473 compatible = "qcom,soundwire-v2.0.0";
2477 clock-names = "iface";
2480 pinctrl-0 = <&wsa_swr_active>;
2481 pinctrl-names = "default";
2483 qcom,din-ports = <4>;
2484 qcom,dout-ports = <9>;
2486 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
2487 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2488 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2489 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2490 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2491 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
2492 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
2493 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2494 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2496 #address-cells = <2>;
2497 #size-cells = <0>;
2498 #sound-dai-cells = <1>;
2503 compatible = "qcom,soundwire-v2.0.0";
2507 interrupt-names = "core", "wakeup";
2509 clock-names = "iface";
2512 pinctrl-0 = <&tx_swr_active>;
2513 pinctrl-names = "default";
2515 qcom,din-ports = <4>;
2516 qcom,dout-ports = <0>;
2517 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2518 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2519 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2520 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2521 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2522 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2523 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2524 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2525 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2527 #address-cells = <2>;
2528 #size-cells = <0>;
2529 #sound-dai-cells = <1>;
2534 compatible = "qcom,sm8550-lpass-va-macro";
2539 clock-names = "mclk", "macro", "dcodec";
2541 #clock-cells = <0>;
2542 clock-output-names = "fsgen";
2543 #sound-dai-cells = <1>;
2547 compatible = "qcom,sm8550-lpass-lpi-pinctrl";
2550 gpio-controller;
2551 #gpio-cells = <2>;
2552 gpio-ranges = <&lpass_tlmm 0 0 23>;
2556 clock-names = "core", "audio";
2558 tx_swr_active: tx-swr-active-state {
2559 clk-pins {
2562 drive-strength = <2>;
2563 slew-rate = <1>;
2564 bias-disable;
2567 data-pins {
2570 drive-strength = <2>;
2571 slew-rate = <1>;
2572 bias-bus-hold;
2576 rx_swr_active: rx-swr-active-state {
2577 clk-pins {
2580 drive-strength = <2>;
2581 slew-rate = <1>;
2582 bias-disable;
2585 data-pins {
2588 drive-strength = <2>;
2589 slew-rate = <1>;
2590 bias-bus-hold;
2594 dmic01_default: dmic01-default-state {
2595 clk-pins {
2598 drive-strength = <8>;
2599 output-high;
2602 data-pins {
2605 drive-strength = <8>;
2606 input-enable;
2610 dmic23_default: dmic23-default-state {
2611 clk-pins {
2614 drive-strength = <8>;
2615 output-high;
2618 data-pins {
2621 drive-strength = <8>;
2622 input-enable;
2626 wsa_swr_active: wsa-swr-active-state {
2627 clk-pins {
2630 drive-strength = <2>;
2631 slew-rate = <1>;
2632 bias-disable;
2635 data-pins {
2638 drive-strength = <2>;
2639 slew-rate = <1>;
2640 bias-bus-hold;
2644 wsa2_swr_active: wsa2-swr-active-state {
2645 clk-pins {
2648 drive-strength = <2>;
2649 slew-rate = <1>;
2650 bias-disable;
2653 data-pins {
2656 drive-strength = <2>;
2657 slew-rate = <1>;
2658 bias-bus-hold;
2664 compatible = "qcom,sm8550-lpass-lpiaon-noc";
2666 #interconnect-cells = <2>;
2667 qcom,bcm-voters = <&apps_bcm_voter>;
2671 compatible = "qcom,sm8550-lpass-lpicx-noc";
2673 #interconnect-cells = <2>;
2674 qcom,bcm-voters = <&apps_bcm_voter>;
2678 compatible = "qcom,sm8550-lpass-ag-noc";
2680 #interconnect-cells = <2>;
2681 qcom,bcm-voters = <&apps_bcm_voter>;
2685 compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5";
2690 interrupt-names = "hc_irq", "pwr_irq";
2695 clock-names = "iface", "core", "xo";
2697 qcom,dll-config = <0x0007642c>;
2698 qcom,ddr-config = <0x80040868>;
2699 power-domains = <&rpmhpd RPMHPD_CX>;
2700 operating-points-v2 = <&sdhc2_opp_table>;
2704 interconnect-names = "sdhc-ddr", "cpu-sdhc";
2705 bus-width = <4>;
2706 dma-coherent;
2708 /* Forbid SDR104/SDR50 - broken hw! */
2709 sdhci-caps-mask = <0x3 0>;
2713 sdhc2_opp_table: opp-table {
2714 compatible = "operating-points-v2";
2716 opp-19200000 {
2717 opp-hz = /bits/ 64 <19200000>;
2718 required-opps = <&rpmhpd_opp_min_svs>;
2721 opp-50000000 {
2722 opp-hz = /bits/ 64 <50000000>;
2723 required-opps = <&rpmhpd_opp_low_svs>;
2726 opp-100000000 {
2727 opp-hz = /bits/ 64 <100000000>;
2728 required-opps = <&rpmhpd_opp_svs>;
2731 opp-202000000 {
2732 opp-hz = /bits/ 64 <202000000>;
2733 required-opps = <&rpmhpd_opp_svs_l1>;
2738 videocc: clock-controller@aaf0000 {
2739 compatible = "qcom,sm8550-videocc";
2743 power-domains = <&rpmhpd RPMHPD_MMCX>;
2744 required-opps = <&rpmhpd_opp_low_svs>;
2745 #clock-cells = <1>;
2746 #reset-cells = <1>;
2747 #power-domain-cells = <1>;
2751 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci";
2754 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
2758 clock-names = "camnoc_axi",
2761 pinctrl-0 = <&cci0_0_default &cci0_1_default>;
2762 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
2763 pinctrl-names = "default", "sleep";
2765 #address-cells = <1>;
2766 #size-cells = <0>;
2768 cci0_i2c0: i2c-bus@0 {
2770 clock-frequency = <1000000>;
2771 #address-cells = <1>;
2772 #size-cells = <0>;
2775 cci0_i2c1: i2c-bus@1 {
2777 clock-frequency = <1000000>;
2778 #address-cells = <1>;
2779 #size-cells = <0>;
2784 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci";
2787 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
2791 clock-names = "camnoc_axi",
2794 pinctrl-0 = <&cci1_0_default>;
2795 pinctrl-1 = <&cci1_0_sleep>;
2796 pinctrl-names = "default", "sleep";
2798 #address-cells = <1>;
2799 #size-cells = <0>;
2801 cci1_i2c0: i2c-bus@0 {
2803 clock-frequency = <1000000>;
2804 #address-cells = <1>;
2805 #size-cells = <0>;
2810 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci";
2813 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
2817 clock-names = "camnoc_axi",
2820 pinctrl-0 = <&cci2_0_default &cci2_1_default>;
2821 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>;
2822 pinctrl-names = "default", "sleep";
2824 #address-cells = <1>;
2825 #size-cells = <0>;
2827 cci2_i2c0: i2c-bus@0 {
2829 clock-frequency = <1000000>;
2830 #address-cells = <1>;
2831 #size-cells = <0>;
2834 cci2_i2c1: i2c-bus@1 {
2836 clock-frequency = <1000000>;
2837 #address-cells = <1>;
2838 #size-cells = <0>;
2842 camcc: clock-controller@ade0000 {
2843 compatible = "qcom,sm8550-camcc";
2849 power-domains = <&rpmhpd SM8550_MMCX>;
2850 required-opps = <&rpmhpd_opp_low_svs>;
2851 #clock-cells = <1>;
2852 #reset-cells = <1>;
2853 #power-domain-cells = <1>;
2856 mdss: display-subsystem@ae00000 {
2857 compatible = "qcom,sm8550-mdss";
2859 reg-names = "mdss";
2862 interrupt-controller;
2863 #interrupt-cells = <1>;
2872 power-domains = <&dispcc MDSS_GDSC>;
2876 interconnect-names = "mdp0-mem", "mdp1-mem";
2880 #address-cells = <2>;
2881 #size-cells = <2>;
2886 mdss_mdp: display-controller@ae01000 {
2887 compatible = "qcom,sm8550-dpu";
2890 reg-names = "mdp", "vbif";
2892 interrupt-parent = <&mdss>;
2901 clock-names = "bus",
2908 power-domains = <&rpmhpd RPMHPD_MMCX>;
2910 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2911 assigned-clock-rates = <19200000>;
2913 operating-points-v2 = <&mdp_opp_table>;
2916 #address-cells = <1>;
2917 #size-cells = <0>;
2922 remote-endpoint = <&mdss_dsi0_in>;
2929 remote-endpoint = <&mdss_dsi1_in>;
2936 remote-endpoint = <&mdss_dp0_in>;
2941 mdp_opp_table: opp-table {
2942 compatible = "operating-points-v2";
2944 opp-200000000 {
2945 opp-hz = /bits/ 64 <200000000>;
2946 required-opps = <&rpmhpd_opp_low_svs>;
2949 opp-325000000 {
2950 opp-hz = /bits/ 64 <325000000>;
2951 required-opps = <&rpmhpd_opp_svs>;
2954 opp-375000000 {
2955 opp-hz = /bits/ 64 <375000000>;
2956 required-opps = <&rpmhpd_opp_svs_l1>;
2959 opp-514000000 {
2960 opp-hz = /bits/ 64 <514000000>;
2961 required-opps = <&rpmhpd_opp_nom>;
2966 mdss_dp0: displayport-controller@ae90000 {
2967 compatible = "qcom,sm8550-dp", "qcom,sm8350-dp";
2973 interrupt-parent = <&mdss>;
2980 clock-names = "core_iface",
2986 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
2988 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2992 phy-names = "dp";
2994 #sound-dai-cells = <0>;
2996 operating-points-v2 = <&dp_opp_table>;
2997 power-domains = <&rpmhpd RPMHPD_MMCX>;
3002 #address-cells = <1>;
3003 #size-cells = <0>;
3008 remote-endpoint = <&dpu_intf0_out>;
3015 remote-endpoint = <&usb_dp_qmpphy_dp_in>;
3020 dp_opp_table: opp-table {
3021 compatible = "operating-points-v2";
3023 opp-162000000 {
3024 opp-hz = /bits/ 64 <162000000>;
3025 required-opps = <&rpmhpd_opp_low_svs_d1>;
3028 opp-270000000 {
3029 opp-hz = /bits/ 64 <270000000>;
3030 required-opps = <&rpmhpd_opp_low_svs>;
3033 opp-540000000 {
3034 opp-hz = /bits/ 64 <540000000>;
3035 required-opps = <&rpmhpd_opp_svs_l1>;
3038 opp-810000000 {
3039 opp-hz = /bits/ 64 <810000000>;
3040 required-opps = <&rpmhpd_opp_nom>;
3046 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3048 reg-names = "dsi_ctrl";
3050 interrupt-parent = <&mdss>;
3059 clock-names = "byte",
3066 power-domains = <&rpmhpd RPMHPD_MMCX>;
3068 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
3070 assigned-clock-parents = <&mdss_dsi0_phy 0>,
3073 operating-points-v2 = <&mdss_dsi_opp_table>;
3076 phy-names = "dsi";
3078 #address-cells = <1>;
3079 #size-cells = <0>;
3084 #address-cells = <1>;
3085 #size-cells = <0>;
3090 remote-endpoint = <&dpu_intf1_out>;
3101 mdss_dsi_opp_table: opp-table {
3102 compatible = "operating-points-v2";
3104 opp-187500000 {
3105 opp-hz = /bits/ 64 <187500000>;
3106 required-opps = <&rpmhpd_opp_low_svs>;
3109 opp-300000000 {
3110 opp-hz = /bits/ 64 <300000000>;
3111 required-opps = <&rpmhpd_opp_svs>;
3114 opp-358000000 {
3115 opp-hz = /bits/ 64 <358000000>;
3116 required-opps = <&rpmhpd_opp_svs_l1>;
3122 compatible = "qcom,sm8550-dsi-phy-4nm";
3126 reg-names = "dsi_phy",
3132 clock-names = "iface", "ref";
3134 #clock-cells = <1>;
3135 #phy-cells = <0>;
3141 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3143 reg-names = "dsi_ctrl";
3145 interrupt-parent = <&mdss>;
3154 clock-names = "byte",
3161 power-domains = <&rpmhpd RPMHPD_MMCX>;
3163 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
3165 assigned-clock-parents = <&mdss_dsi1_phy 0>,
3168 operating-points-v2 = <&mdss_dsi_opp_table>;
3171 phy-names = "dsi";
3173 #address-cells = <1>;
3174 #size-cells = <0>;
3179 #address-cells = <1>;
3180 #size-cells = <0>;
3185 remote-endpoint = <&dpu_intf2_out>;
3198 compatible = "qcom,sm8550-dsi-phy-4nm";
3202 reg-names = "dsi_phy",
3208 clock-names = "iface", "ref";
3210 #clock-cells = <1>;
3211 #phy-cells = <0>;
3217 dispcc: clock-controller@af00000 {
3218 compatible = "qcom,sm8550-dispcc";
3236 power-domains = <&rpmhpd RPMHPD_MMCX>;
3237 required-opps = <&rpmhpd_opp_low_svs>;
3238 #clock-cells = <1>;
3239 #reset-cells = <1>;
3240 #power-domain-cells = <1>;
3244 compatible = "qcom,sm8550-snps-eusb2-phy";
3246 #phy-cells = <0>;
3249 clock-names = "ref";
3257 compatible = "qcom,sm8550-qmp-usb3-dp-phy";
3264 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3266 power-domains = <&gcc USB3_PHY_GDSC>;
3270 reset-names = "phy", "common";
3272 #clock-cells = <1>;
3273 #phy-cells = <1>;
3275 orientation-switch;
3280 #address-cells = <1>;
3281 #size-cells = <0>;
3294 remote-endpoint = <&usb_1_dwc3_ss>;
3302 remote-endpoint = <&mdss_dp0_out>;
3309 compatible = "qcom,sm8550-dwc3", "qcom,dwc3";
3311 #address-cells = <2>;
3312 #size-cells = <2>;
3321 clock-names = "cfg_noc",
3328 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3330 assigned-clock-rates = <19200000>, <200000000>;
3332 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3337 interrupt-names = "pwr_event",
3343 power-domains = <&gcc USB30_PRIM_GDSC>;
3344 required-opps = <&rpmhpd_opp_nom>;
3350 interconnect-names = "usb-ddr", "apps-usb";
3361 phy-names = "usb2-phy", "usb3-phy";
3362 snps,hird-threshold = /bits/ 8 <0x0>;
3363 snps,usb2-gadget-lpm-disable;
3366 snps,dis-u1-entry-quirk;
3367 snps,dis-u2-entry-quirk;
3368 snps,is-utmi-l1-suspend;
3370 snps,usb2-lpm-disable;
3371 snps,has-lpm-erratum;
3372 tx-fifo-resize;
3373 dma-coherent;
3374 usb-role-switch;
3377 #address-cells = <1>;
3378 #size-cells = <0>;
3391 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
3398 pdc: interrupt-controller@b220000 {
3399 compatible = "qcom,sm8550-pdc", "qcom,pdc";
3401 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
3404 #interrupt-cells = <2>;
3405 interrupt-parent = <&intc>;
3406 interrupt-controller;
3409 tsens0: thermal-sensor@c271000 {
3410 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
3416 interrupt-names = "uplow", "critical";
3417 #thermal-sensor-cells = <1>;
3420 tsens1: thermal-sensor@c272000 {
3421 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
3427 interrupt-names = "uplow", "critical";
3428 #thermal-sensor-cells = <1>;
3431 tsens2: thermal-sensor@c273000 {
3432 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
3438 interrupt-names = "uplow", "critical";
3439 #thermal-sensor-cells = <1>;
3442 aoss_qmp: power-management@c300000 {
3443 compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp";
3445 interrupt-parent = <&ipcc>;
3446 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3450 #clock-cells = <0>;
3454 compatible = "qcom,rpmh-stats";
3459 compatible = "qcom,spmi-pmic-arb";
3465 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3466 interrupt-names = "periph_irq";
3467 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3470 qcom,bus-id = <0>;
3471 #address-cells = <2>;
3472 #size-cells = <0>;
3473 interrupt-controller;
3474 #interrupt-cells = <4>;
3478 compatible = "qcom,sm8550-tlmm";
3481 gpio-controller;
3482 #gpio-cells = <2>;
3483 interrupt-controller;
3484 #interrupt-cells = <2>;
3485 gpio-ranges = <&tlmm 0 0 211>;
3486 wakeup-parent = <&pdc>;
3488 cci0_0_default: cci0-0-default-state {
3489 sda-pins {
3492 drive-strength = <2>;
3493 bias-pull-up = <2200>;
3496 scl-pins {
3499 drive-strength = <2>;
3500 bias-pull-up = <2200>;
3504 cci0_0_sleep: cci0-0-sleep-state {
3505 sda-pins {
3508 drive-strength = <2>;
3509 bias-pull-down;
3512 scl-pins {
3515 drive-strength = <2>;
3516 bias-pull-down;
3520 cci0_1_default: cci0-1-default-state {
3521 sda-pins {
3524 drive-strength = <2>;
3525 bias-pull-up = <2200>;
3528 scl-pins {
3531 drive-strength = <2>;
3532 bias-pull-up = <2200>;
3536 cci0_1_sleep: cci0-1-sleep-state {
3537 sda-pins {
3540 drive-strength = <2>;
3541 bias-pull-down;
3544 scl-pins {
3547 drive-strength = <2>;
3548 bias-pull-down;
3552 cci1_0_default: cci1-0-default-state {
3553 sda-pins {
3556 drive-strength = <2>;
3557 bias-pull-up = <2200>;
3560 scl-pins {
3563 drive-strength = <2>;
3564 bias-pull-up = <2200>;
3568 cci1_0_sleep: cci1-0-sleep-state {
3569 sda-pins {
3572 drive-strength = <2>;
3573 bias-pull-down;
3576 scl-pins {
3579 drive-strength = <2>;
3580 bias-pull-down;
3584 cci2_0_default: cci2-0-default-state {
3585 sda-pins {
3588 drive-strength = <2>;
3589 bias-pull-up = <2200>;
3592 scl-pins {
3595 drive-strength = <2>;
3596 bias-pull-up = <2200>;
3600 cci2_0_sleep: cci2-0-sleep-state {
3601 sda-pins {
3604 drive-strength = <2>;
3605 bias-pull-down;
3608 scl-pins {
3611 drive-strength = <2>;
3612 bias-pull-down;
3616 cci2_1_default: cci2-1-default-state {
3617 sda-pins {
3620 drive-strength = <2>;
3621 bias-pull-up = <2200>;
3624 scl-pins {
3627 drive-strength = <2>;
3628 bias-pull-up = <2200>;
3632 cci2_1_sleep: cci2-1-sleep-state {
3633 sda-pins {
3636 drive-strength = <2>;
3637 bias-pull-down;
3640 scl-pins {
3643 drive-strength = <2>;
3644 bias-pull-down;
3648 hub_i2c0_data_clk: hub-i2c0-data-clk-state {
3652 drive-strength = <2>;
3653 bias-pull-up;
3656 hub_i2c1_data_clk: hub-i2c1-data-clk-state {
3660 drive-strength = <2>;
3661 bias-pull-up;
3664 hub_i2c2_data_clk: hub-i2c2-data-clk-state {
3668 drive-strength = <2>;
3669 bias-pull-up;
3672 hub_i2c3_data_clk: hub-i2c3-data-clk-state {
3676 drive-strength = <2>;
3677 bias-pull-up;
3680 hub_i2c4_data_clk: hub-i2c4-data-clk-state {
3684 drive-strength = <2>;
3685 bias-pull-up;
3688 hub_i2c5_data_clk: hub-i2c5-data-clk-state {
3692 drive-strength = <2>;
3693 bias-pull-up;
3696 hub_i2c6_data_clk: hub-i2c6-data-clk-state {
3700 drive-strength = <2>;
3701 bias-pull-up;
3704 hub_i2c7_data_clk: hub-i2c7-data-clk-state {
3708 drive-strength = <2>;
3709 bias-pull-up;
3712 hub_i2c8_data_clk: hub-i2c8-data-clk-state {
3716 drive-strength = <2>;
3717 bias-pull-up;
3720 hub_i2c9_data_clk: hub-i2c9-data-clk-state {
3724 drive-strength = <2>;
3725 bias-pull-up;
3728 pcie0_default_state: pcie0-default-state {
3729 perst-pins {
3732 drive-strength = <2>;
3733 bias-pull-down;
3736 clkreq-pins {
3739 drive-strength = <2>;
3740 bias-pull-up;
3743 wake-pins {
3746 drive-strength = <2>;
3747 bias-pull-up;
3751 pcie1_default_state: pcie1-default-state {
3752 perst-pins {
3755 drive-strength = <2>;
3756 bias-pull-down;
3759 clkreq-pins {
3762 drive-strength = <2>;
3763 bias-pull-up;
3766 wake-pins {
3769 drive-strength = <2>;
3770 bias-pull-up;
3774 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3778 drive-strength = <2>;
3779 bias-pull-up = <2200>;
3782 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3786 drive-strength = <2>;
3787 bias-pull-up = <2200>;
3790 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3794 drive-strength = <2>;
3795 bias-pull-up = <2200>;
3798 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3802 drive-strength = <2>;
3803 bias-pull-up = <2200>;
3806 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3810 drive-strength = <2>;
3811 bias-pull-up = <2200>;
3814 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3818 drive-strength = <2>;
3819 bias-pull-up = <2200>;
3822 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3826 drive-strength = <2>;
3827 bias-pull-up = <2200>;
3830 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3831 scl-pins {
3834 drive-strength = <2>;
3835 bias-pull-up = <2200>;
3838 sda-pins {
3841 drive-strength = <2>;
3842 bias-pull-up = <2200>;
3846 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3850 drive-strength = <2>;
3851 bias-pull-up = <2200>;
3854 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3858 drive-strength = <2>;
3859 bias-pull-up = <2200>;
3862 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3866 drive-strength = <2>;
3867 bias-pull-up = <2200>;
3870 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3874 drive-strength = <2>;
3875 bias-pull-up = <2200>;
3878 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3882 drive-strength = <2>;
3883 bias-pull-up = <2200>;
3886 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3890 drive-strength = <2>;
3891 bias-pull-up = <2200>;
3894 qup_spi0_cs: qup-spi0-cs-state {
3897 drive-strength = <6>;
3898 bias-disable;
3901 qup_spi0_data_clk: qup-spi0-data-clk-state {
3905 drive-strength = <6>;
3906 bias-disable;
3909 qup_spi1_cs: qup-spi1-cs-state {
3912 drive-strength = <6>;
3913 bias-disable;
3916 qup_spi1_data_clk: qup-spi1-data-clk-state {
3920 drive-strength = <6>;
3921 bias-disable;
3924 qup_spi2_cs: qup-spi2-cs-state {
3927 drive-strength = <6>;
3928 bias-disable;
3931 qup_spi2_data_clk: qup-spi2-data-clk-state {
3935 drive-strength = <6>;
3936 bias-disable;
3939 qup_spi3_cs: qup-spi3-cs-state {
3942 drive-strength = <6>;
3943 bias-disable;
3946 qup_spi3_data_clk: qup-spi3-data-clk-state {
3950 drive-strength = <6>;
3951 bias-disable;
3954 qup_spi4_cs: qup-spi4-cs-state {
3957 drive-strength = <6>;
3958 bias-disable;
3961 qup_spi4_data_clk: qup-spi4-data-clk-state {
3965 drive-strength = <6>;
3966 bias-disable;
3969 qup_spi5_cs: qup-spi5-cs-state {
3972 drive-strength = <6>;
3973 bias-disable;
3976 qup_spi5_data_clk: qup-spi5-data-clk-state {
3980 drive-strength = <6>;
3981 bias-disable;
3984 qup_spi6_cs: qup-spi6-cs-state {
3987 drive-strength = <6>;
3988 bias-disable;
3991 qup_spi6_data_clk: qup-spi6-data-clk-state {
3995 drive-strength = <6>;
3996 bias-disable;
3999 qup_spi8_cs: qup-spi8-cs-state {
4002 drive-strength = <6>;
4003 bias-disable;
4006 qup_spi8_data_clk: qup-spi8-data-clk-state {
4010 drive-strength = <6>;
4011 bias-disable;
4014 qup_spi9_cs: qup-spi9-cs-state {
4017 drive-strength = <6>;
4018 bias-disable;
4021 qup_spi9_data_clk: qup-spi9-data-clk-state {
4025 drive-strength = <6>;
4026 bias-disable;
4029 qup_spi10_cs: qup-spi10-cs-state {
4032 drive-strength = <6>;
4033 bias-disable;
4036 qup_spi10_data_clk: qup-spi10-data-clk-state {
4040 drive-strength = <6>;
4041 bias-disable;
4044 qup_spi11_cs: qup-spi11-cs-state {
4047 drive-strength = <6>;
4048 bias-disable;
4051 qup_spi11_data_clk: qup-spi11-data-clk-state {
4055 drive-strength = <6>;
4056 bias-disable;
4059 qup_spi12_cs: qup-spi12-cs-state {
4062 drive-strength = <6>;
4063 bias-disable;
4066 qup_spi12_data_clk: qup-spi12-data-clk-state {
4070 drive-strength = <6>;
4071 bias-disable;
4074 qup_spi13_cs: qup-spi13-cs-state {
4077 drive-strength = <6>;
4078 bias-disable;
4081 qup_spi13_data_clk: qup-spi13-data-clk-state {
4085 drive-strength = <6>;
4086 bias-disable;
4089 qup_spi15_cs: qup-spi15-cs-state {
4092 drive-strength = <6>;
4093 bias-disable;
4096 qup_spi15_data_clk: qup-spi15-data-clk-state {
4100 drive-strength = <6>;
4101 bias-disable;
4104 qup_uart7_default: qup-uart7-default-state {
4108 drive-strength = <2>;
4109 bias-disable;
4112 qup_uart14_default: qup-uart14-default-state {
4116 drive-strength = <2>;
4117 bias-pull-up;
4120 qup_uart14_cts_rts: qup-uart14-cts-rts-state {
4124 drive-strength = <2>;
4125 bias-pull-down;
4128 sdc2_sleep: sdc2-sleep-state {
4129 clk-pins {
4131 bias-disable;
4132 drive-strength = <2>;
4135 cmd-pins {
4137 bias-pull-up;
4138 drive-strength = <2>;
4141 data-pins {
4143 bias-pull-up;
4144 drive-strength = <2>;
4148 sdc2_default: sdc2-default-state {
4149 clk-pins {
4151 bias-disable;
4152 drive-strength = <16>;
4155 cmd-pins {
4157 bias-pull-up;
4158 drive-strength = <10>;
4161 data-pins {
4163 bias-pull-up;
4164 drive-strength = <10>;
4170 compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500";
4172 #iommu-cells = <2>;
4173 #global-interrupts = <1>;
4271 dma-coherent;
4274 intc: interrupt-controller@17100000 {
4275 compatible = "arm,gic-v3";
4279 #interrupt-cells = <3>;
4280 interrupt-controller;
4281 #redistributor-regions = <1>;
4282 redistributor-stride = <0 0x40000>;
4284 #address-cells = <2>;
4285 #size-cells = <2>;
4287 gic_its: msi-controller@17140000 {
4288 compatible = "arm,gic-v3-its";
4290 msi-controller;
4291 #msi-cells = <1>;
4296 compatible = "arm,armv7-timer-mem";
4299 #address-cells = <1>;
4300 #size-cells = <1>;
4305 frame-number = <0>;
4312 frame-number = <1>;
4319 frame-number = <2>;
4326 frame-number = <3>;
4333 frame-number = <4>;
4340 frame-number = <5>;
4347 frame-number = <6>;
4355 compatible = "qcom,rpmh-rsc";
4360 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4364 qcom,tcs-offset = <0xd00>;
4365 qcom,drv-id = <2>;
4366 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
4368 power-domains = <&CLUSTER_PD>;
4370 apps_bcm_voter: bcm-voter {
4371 compatible = "qcom,bcm-voter";
4374 rpmhcc: clock-controller {
4375 compatible = "qcom,sm8550-rpmh-clk";
4376 #clock-cells = <1>;
4377 clock-names = "xo";
4381 rpmhpd: power-controller {
4382 compatible = "qcom,sm8550-rpmhpd";
4383 #power-domain-cells = <1>;
4384 operating-points-v2 = <&rpmhpd_opp_table>;
4386 rpmhpd_opp_table: opp-table {
4387 compatible = "operating-points-v2";
4389 rpmhpd_opp_ret: opp-16 {
4390 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4393 rpmhpd_opp_min_svs: opp-48 {
4394 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4397 rpmhpd_opp_low_svs_d2: opp-52 {
4398 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
4401 rpmhpd_opp_low_svs_d1: opp-56 {
4402 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
4405 rpmhpd_opp_low_svs_d0: opp-60 {
4406 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
4409 rpmhpd_opp_low_svs: opp-64 {
4410 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4413 rpmhpd_opp_low_svs_l1: opp-80 {
4414 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
4417 rpmhpd_opp_svs: opp-128 {
4418 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4421 rpmhpd_opp_svs_l0: opp-144 {
4422 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
4425 rpmhpd_opp_svs_l1: opp-192 {
4426 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4429 rpmhpd_opp_nom: opp-256 {
4430 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4433 rpmhpd_opp_nom_l1: opp-320 {
4434 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4437 rpmhpd_opp_nom_l2: opp-336 {
4438 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4441 rpmhpd_opp_turbo: opp-384 {
4442 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4445 rpmhpd_opp_turbo_l1: opp-416 {
4446 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4453 compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss";
4457 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
4459 clock-names = "xo", "alternate";
4463 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4464 #freq-domain-cells = <1>;
4465 #clock-cells = <1>;
4469 compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
4474 operating-points-v2 = <&llcc_bwmon_opp_table>;
4476 llcc_bwmon_opp_table: opp-table {
4477 compatible = "operating-points-v2";
4479 opp-0 {
4480 opp-peak-kBps = <2086000>;
4483 opp-1 {
4484 opp-peak-kBps = <2929000>;
4487 opp-2 {
4488 opp-peak-kBps = <5931000>;
4491 opp-3 {
4492 opp-peak-kBps = <6515000>;
4495 opp-4 {
4496 opp-peak-kBps = <7980000>;
4499 opp-5 {
4500 opp-peak-kBps = <10437000>;
4503 opp-6 {
4504 opp-peak-kBps = <12157000>;
4507 opp-7 {
4508 opp-peak-kBps = <14060000>;
4511 opp-8 {
4512 opp-peak-kBps = <16113000>;
4518 compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon";
4523 operating-points-v2 = <&cpu_bwmon_opp_table>;
4525 cpu_bwmon_opp_table: opp-table {
4526 compatible = "operating-points-v2";
4528 opp-0 {
4529 opp-peak-kBps = <4577000>;
4532 opp-1 {
4533 opp-peak-kBps = <7110000>;
4536 opp-2 {
4537 opp-peak-kBps = <9155000>;
4540 opp-3 {
4541 opp-peak-kBps = <12298000>;
4544 opp-4 {
4545 opp-peak-kBps = <14236000>;
4548 opp-5 {
4549 opp-peak-kBps = <16265000>;
4555 compatible = "qcom,sm8550-gem-noc";
4557 #interconnect-cells = <2>;
4558 qcom,bcm-voters = <&apps_bcm_voter>;
4561 system-cache-controller@25000000 {
4562 compatible = "qcom,sm8550-llcc";
4569 reg-names = "llcc0_base",
4579 compatible = "qcom,sm8550-adsp-pas";
4582 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
4587 interrupt-names = "wdog", "fatal", "ready",
4588 "handover", "stop-ack";
4591 clock-names = "xo";
4593 power-domains = <&rpmhpd RPMHPD_LCX>,
4595 power-domain-names = "lcx", "lmx";
4599 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
4603 qcom,smem-states = <&smp2p_adsp_out 0>;
4604 qcom,smem-state-names = "stop";
4608 remoteproc_adsp_glink: glink-edge {
4609 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
4616 qcom,remote-pid = <2>;
4620 qcom,glink-channels = "fastrpcglink-apps-dsp";
4622 qcom,non-secure-domain;
4623 #address-cells = <1>;
4624 #size-cells = <0>;
4626 compute-cb@3 {
4627 compatible = "qcom,fastrpc-compute-cb";
4631 dma-coherent;
4634 compute-cb@4 {
4635 compatible = "qcom,fastrpc-compute-cb";
4639 dma-coherent;
4642 compute-cb@5 {
4643 compatible = "qcom,fastrpc-compute-cb";
4647 dma-coherent;
4650 compute-cb@6 {
4651 compatible = "qcom,fastrpc-compute-cb";
4655 dma-coherent;
4658 compute-cb@7 {
4659 compatible = "qcom,fastrpc-compute-cb";
4663 dma-coherent;
4669 qcom,glink-channels = "adsp_apps";
4672 #address-cells = <1>;
4673 #size-cells = <0>;
4678 #sound-dai-cells = <0>;
4679 qcom,protection-domain = "avs/audio",
4683 compatible = "qcom,q6apm-dais";
4689 compatible = "qcom,q6apm-lpass-dais";
4690 #sound-dai-cells = <1>;
4697 qcom,protection-domain = "avs/audio",
4700 q6prmcc: clock-controller {
4701 compatible = "qcom,q6prm-lpass-clocks";
4702 #clock-cells = <2>;
4710 compatible = "qcom,sm8550-nsp-noc";
4712 #interconnect-cells = <2>;
4713 qcom,bcm-voters = <&apps_bcm_voter>;
4717 compatible = "qcom,sm8550-cdsp-pas";
4720 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
4725 interrupt-names = "wdog", "fatal", "ready",
4726 "handover", "stop-ack";
4729 clock-names = "xo";
4731 power-domains = <&rpmhpd RPMHPD_CX>,
4734 power-domain-names = "cx", "mxc", "nsp";
4738 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>;
4742 qcom,smem-states = <&smp2p_cdsp_out 0>;
4743 qcom,smem-state-names = "stop";
4747 glink-edge {
4748 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
4755 qcom,remote-pid = <5>;
4759 qcom,glink-channels = "fastrpcglink-apps-dsp";
4761 qcom,non-secure-domain;
4762 #address-cells = <1>;
4763 #size-cells = <0>;
4765 compute-cb@1 {
4766 compatible = "qcom,fastrpc-compute-cb";
4771 dma-coherent;
4774 compute-cb@2 {
4775 compatible = "qcom,fastrpc-compute-cb";
4780 dma-coherent;
4783 compute-cb@3 {
4784 compatible = "qcom,fastrpc-compute-cb";
4789 dma-coherent;
4792 compute-cb@4 {
4793 compatible = "qcom,fastrpc-compute-cb";
4798 dma-coherent;
4801 compute-cb@5 {
4802 compatible = "qcom,fastrpc-compute-cb";
4807 dma-coherent;
4810 compute-cb@6 {
4811 compatible = "qcom,fastrpc-compute-cb";
4816 dma-coherent;
4819 compute-cb@7 {
4820 compatible = "qcom,fastrpc-compute-cb";
4825 dma-coherent;
4828 compute-cb@8 {
4829 compatible = "qcom,fastrpc-compute-cb";
4834 dma-coherent;
4843 thermal-zones {
4844 aoss0-thermal {
4845 thermal-sensors = <&tsens0 0>;
4848 thermal-engine-config {
4854 reset-mon-config {
4862 cpuss0-thermal {
4863 thermal-sensors = <&tsens0 1>;
4866 thermal-engine-config {
4872 reset-mon-config {
4880 cpuss1-thermal {
4881 thermal-sensors = <&tsens0 2>;
4884 thermal-engine-config {
4890 reset-mon-config {
4898 cpuss2-thermal {
4899 thermal-sensors = <&tsens0 3>;
4902 thermal-engine-config {
4908 reset-mon-config {
4916 cpuss3-thermal {
4917 thermal-sensors = <&tsens0 4>;
4920 thermal-engine-config {
4926 reset-mon-config {
4934 cpu3-top-thermal {
4935 thermal-sensors = <&tsens0 5>;
4938 cpu3_top_alert0: trip-point0 {
4944 cpu3_top_alert1: trip-point1 {
4950 cpu3_top_crit: cpu-critical {
4958 cpu3-bottom-thermal {
4959 thermal-sensors = <&tsens0 6>;
4962 cpu3_bottom_alert0: trip-point0 {
4968 cpu3_bottom_alert1: trip-point1 {
4974 cpu3_bottom_crit: cpu-critical {
4982 cpu4-top-thermal {
4983 thermal-sensors = <&tsens0 7>;
4986 cpu4_top_alert0: trip-point0 {
4992 cpu4_top_alert1: trip-point1 {
4998 cpu4_top_crit: cpu-critical {
5006 cpu4-bottom-thermal {
5007 thermal-sensors = <&tsens0 8>;
5010 cpu4_bottom_alert0: trip-point0 {
5016 cpu4_bottom_alert1: trip-point1 {
5022 cpu4_bottom_crit: cpu-critical {
5030 cpu5-top-thermal {
5031 thermal-sensors = <&tsens0 9>;
5034 cpu5_top_alert0: trip-point0 {
5040 cpu5_top_alert1: trip-point1 {
5046 cpu5_top_crit: cpu-critical {
5054 cpu5-bottom-thermal {
5055 thermal-sensors = <&tsens0 10>;
5058 cpu5_bottom_alert0: trip-point0 {
5064 cpu5_bottom_alert1: trip-point1 {
5070 cpu5_bottom_crit: cpu-critical {
5078 cpu6-top-thermal {
5079 thermal-sensors = <&tsens0 11>;
5082 cpu6_top_alert0: trip-point0 {
5088 cpu6_top_alert1: trip-point1 {
5094 cpu6_top_crit: cpu-critical {
5102 cpu6-bottom-thermal {
5103 thermal-sensors = <&tsens0 12>;
5106 cpu6_bottom_alert0: trip-point0 {
5112 cpu6_bottom_alert1: trip-point1 {
5118 cpu6_bottom_crit: cpu-critical {
5126 cpu7-top-thermal {
5127 thermal-sensors = <&tsens0 13>;
5130 cpu7_top_alert0: trip-point0 {
5136 cpu7_top_alert1: trip-point1 {
5142 cpu7_top_crit: cpu-critical {
5150 cpu7-middle-thermal {
5151 thermal-sensors = <&tsens0 14>;
5154 cpu7_middle_alert0: trip-point0 {
5160 cpu7_middle_alert1: trip-point1 {
5166 cpu7_middle_crit: cpu-critical {
5174 cpu7-bottom-thermal {
5175 thermal-sensors = <&tsens0 15>;
5178 cpu7_bottom_alert0: trip-point0 {
5184 cpu7_bottom_alert1: trip-point1 {
5190 cpu7_bottom_crit: cpu-critical {
5198 aoss1-thermal {
5199 thermal-sensors = <&tsens1 0>;
5202 thermal-engine-config {
5208 reset-mon-config {
5216 cpu0-thermal {
5217 thermal-sensors = <&tsens1 1>;
5220 cpu0_alert0: trip-point0 {
5226 cpu0_alert1: trip-point1 {
5232 cpu0_crit: cpu-critical {
5240 cpu1-thermal {
5241 thermal-sensors = <&tsens1 2>;
5244 cpu1_alert0: trip-point0 {
5250 cpu1_alert1: trip-point1 {
5256 cpu1_crit: cpu-critical {
5264 cpu2-thermal {
5265 thermal-sensors = <&tsens1 3>;
5268 cpu2_alert0: trip-point0 {
5274 cpu2_alert1: trip-point1 {
5280 cpu2_crit: cpu-critical {
5288 cdsp0-thermal {
5289 polling-delay-passive = <10>;
5291 thermal-sensors = <&tsens2 4>;
5294 thermal-engine-config {
5300 thermal-hal-config {
5306 reset-mon-config {
5312 cdsp0_junction_config: junction-config {
5320 cdsp1-thermal {
5321 polling-delay-passive = <10>;
5323 thermal-sensors = <&tsens2 5>;
5326 thermal-engine-config {
5332 thermal-hal-config {
5338 reset-mon-config {
5344 cdsp1_junction_config: junction-config {
5352 cdsp2-thermal {
5353 polling-delay-passive = <10>;
5355 thermal-sensors = <&tsens2 6>;
5358 thermal-engine-config {
5364 thermal-hal-config {
5370 reset-mon-config {
5376 cdsp2_junction_config: junction-config {
5384 cdsp3-thermal {
5385 polling-delay-passive = <10>;
5387 thermal-sensors = <&tsens2 7>;
5390 thermal-engine-config {
5396 thermal-hal-config {
5402 reset-mon-config {
5408 cdsp3_junction_config: junction-config {
5416 video-thermal {
5417 thermal-sensors = <&tsens1 8>;
5420 thermal-engine-config {
5426 reset-mon-config {
5434 mem-thermal {
5435 polling-delay-passive = <10>;
5437 thermal-sensors = <&tsens1 9>;
5440 thermal-engine-config {
5446 ddr_config0: ddr0-config {
5452 reset-mon-config {
5460 modem0-thermal {
5461 thermal-sensors = <&tsens1 10>;
5464 thermal-engine-config {
5470 mdmss0_config0: mdmss0-config0 {
5476 mdmss0_config1: mdmss0-config1 {
5482 reset-mon-config {
5490 modem1-thermal {
5491 thermal-sensors = <&tsens1 11>;
5494 thermal-engine-config {
5500 mdmss1_config0: mdmss1-config0 {
5506 mdmss1_config1: mdmss1-config1 {
5512 reset-mon-config {
5520 modem2-thermal {
5521 thermal-sensors = <&tsens1 12>;
5524 thermal-engine-config {
5530 mdmss2_config0: mdmss2-config0 {
5536 mdmss2_config1: mdmss2-config1 {
5542 reset-mon-config {
5550 modem3-thermal {
5551 thermal-sensors = <&tsens1 13>;
5554 thermal-engine-config {
5560 mdmss3_config0: mdmss3-config0 {
5566 mdmss3_config1: mdmss3-config1 {
5572 reset-mon-config {
5580 camera0-thermal {
5581 thermal-sensors = <&tsens1 14>;
5584 thermal-engine-config {
5590 reset-mon-config {
5598 camera1-thermal {
5599 thermal-sensors = <&tsens1 15>;
5602 thermal-engine-config {
5608 reset-mon-config {
5616 aoss2-thermal {
5617 thermal-sensors = <&tsens2 0>;
5620 thermal-engine-config {
5626 reset-mon-config {
5634 gpuss-0-thermal {
5635 polling-delay-passive = <10>;
5637 thermal-sensors = <&tsens2 1>;
5639 cooling-maps {
5642 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5647 gpu0_alert0: trip-point0 {
5653 trip-point1 {
5659 trip-point2 {
5667 gpuss-1-thermal {
5668 polling-delay-passive = <10>;
5670 thermal-sensors = <&tsens2 2>;
5672 cooling-maps {
5675 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5680 gpu1_alert0: trip-point0 {
5686 trip-point1 {
5692 trip-point2 {
5700 gpuss-2-thermal {
5701 polling-delay-passive = <10>;
5703 thermal-sensors = <&tsens2 3>;
5705 cooling-maps {
5708 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5713 gpu2_alert0: trip-point0 {
5719 trip-point1 {
5725 trip-point2 {
5733 gpuss-3-thermal {
5734 polling-delay-passive = <10>;
5736 thermal-sensors = <&tsens2 4>;
5738 cooling-maps {
5741 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5746 gpu3_alert0: trip-point0 {
5752 trip-point1 {
5758 trip-point2 {
5766 gpuss-4-thermal {
5767 polling-delay-passive = <10>;
5769 thermal-sensors = <&tsens2 5>;
5771 cooling-maps {
5774 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5779 gpu4_alert0: trip-point0 {
5785 trip-point1 {
5791 trip-point2 {
5799 gpuss-5-thermal {
5800 polling-delay-passive = <10>;
5802 thermal-sensors = <&tsens2 6>;
5804 cooling-maps {
5807 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5812 gpu5_alert0: trip-point0 {
5818 trip-point1 {
5824 trip-point2 {
5832 gpuss-6-thermal {
5833 polling-delay-passive = <10>;
5835 thermal-sensors = <&tsens2 7>;
5837 cooling-maps {
5840 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5845 gpu6_alert0: trip-point0 {
5851 trip-point1 {
5857 trip-point2 {
5865 gpuss-7-thermal {
5866 polling-delay-passive = <10>;
5868 thermal-sensors = <&tsens2 8>;
5870 cooling-maps {
5873 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5878 gpu7_alert0: trip-point0 {
5884 trip-point1 {
5890 trip-point2 {
5900 compatible = "arm,armv8-timer";