Lines Matching +full:1 +full:d84000
52 clock-mult = <1>;
60 clock-mult = <1>;
141 clocks = <&cpufreq_hw 1>;
146 qcom,freq-domain = <&cpufreq_hw 1>;
162 clocks = <&cpufreq_hw 1>;
167 qcom,freq-domain = <&cpufreq_hw 1>;
183 clocks = <&cpufreq_hw 1>;
188 qcom,freq-domain = <&cpufreq_hw 1>;
204 clocks = <&cpufreq_hw 1>;
209 qcom,freq-domain = <&cpufreq_hw 1>;
291 big_cpu_sleep_0: cpu-sleep-1-0 {
321 cluster_sleep_1: cluster-sleep-1 {
346 mc_virt: interconnect-1 {
640 qcom,client-id = <1>;
749 #qcom,smem-state-cells = <1>;
773 #qcom,smem-state-cells = <1>;
793 qcom,remote-pid = <1>;
797 #qcom,smem-state-cells = <1>;
808 #qcom,smem-state-cells = <1>;
829 #clock-cells = <1>;
830 #reset-cells = <1>;
831 #power-domain-cells = <1>;
837 <&ufs_mem_phy 1>,
895 #address-cells = <1>;
905 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
928 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
932 #address-cells = <1>;
945 #address-cells = <1>;
954 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
955 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
977 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
978 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
982 #address-cells = <1>;
995 #address-cells = <1>;
1005 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1028 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1032 #address-cells = <1>;
1045 #address-cells = <1>;
1055 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1078 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1082 #address-cells = <1>;
1095 #address-cells = <1>;
1105 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1128 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1132 #address-cells = <1>;
1145 #address-cells = <1>;
1155 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1178 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1182 #address-cells = <1>;
1213 #address-cells = <1>;
1223 <&gpi_dma2 1 7 QCOM_GPI_I2C>;
1246 <&gpi_dma2 1 7 QCOM_GPI_SPI>;
1250 #address-cells = <1>;
1275 #address-cells = <1>;
1296 #address-cells = <1>;
1317 #address-cells = <1>;
1338 #address-cells = <1>;
1359 #address-cells = <1>;
1380 #address-cells = <1>;
1401 #address-cells = <1>;
1422 #address-cells = <1>;
1443 #address-cells = <1>;
1464 #address-cells = <1>;
1524 #address-cells = <1>;
1534 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1557 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1561 #address-cells = <1>;
1574 #address-cells = <1>;
1583 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1584 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1606 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1607 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1611 #address-cells = <1>;
1624 #address-cells = <1>;
1634 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1657 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1661 #address-cells = <1>;
1674 #address-cells = <1>;
1684 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1707 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1711 #address-cells = <1>;
1724 #address-cells = <1>;
1734 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1757 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1761 #address-cells = <1>;
1782 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1786 #address-cells = <1>;
1807 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1811 #address-cells = <1>;
1832 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1836 #address-cells = <1>;
1857 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1861 #address-cells = <1>;
1944 pcie0: pcie@1c00000 {
1982 #interrupt-cells = <1>;
1984 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2030 /* GEN 1 x1 */
2034 opp-peak-kBps = <250000 1>;
2037 /* GEN 1 x2 and GEN 2 x1 */
2041 opp-peak-kBps = <500000 1>;
2048 opp-peak-kBps = <1000000 1>;
2055 opp-peak-kBps = <984500 1>;
2062 opp-peak-kBps = <1969000 1>;
2077 pcie0_phy: phy@1c06000 {
2105 pcie1: pcie@1c08000 {
2122 linux,pci-domain = <1>;
2143 #interrupt-cells = <1>;
2145 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2197 /* GEN 1 x1 */
2201 opp-peak-kBps = <250000 1>;
2204 /* GEN 1 x2 and GEN 2 x1 */
2208 opp-peak-kBps = <500000 1>;
2215 opp-peak-kBps = <1000000 1>;
2222 opp-peak-kBps = <984500 1>;
2229 opp-peak-kBps = <1969000 1>;
2236 opp-peak-kBps = <3938000 1>;
2251 pcie1_phy: phy@1c0e000 {
2272 #clock-cells = <1>;
2280 cryptobam: dma-controller@1dc4000 {
2284 #dma-cells = <1>;
2293 crypto: crypto@1dfa000 {
2305 ufs_mem_phy: phy@1d80000 {
2320 #clock-cells = <1>;
2326 ufs_mem_hc: ufshc@1d84000 {
2334 #reset-cells = <1>;
2412 ice: crypto@1d88000 {
2420 tcsr_mutex: hwlock@1f40000 {
2423 #hwlock-cells = <1>;
2426 tcsr: clock-controller@1fc0000 {
2430 #clock-cells = <1>;
2431 #reset-cells = <1>;
2446 <&adreno_smmu 1 0x0>;
2575 #clock-cells = <1>;
2576 #reset-cells = <1>;
2577 #power-domain-cells = <1>;
2585 #global-interrupts = <1>;
2639 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2658 <&ipa_smp2p_out 1>;
2671 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2704 qcom,remote-pid = <1>;
2714 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2754 #address-cells = <1>;
2803 #address-cells = <1>;
2806 q6apm: service@1 {
2821 #sound-dai-cells = <1>;
2851 #sound-dai-cells = <1>;
2880 #sound-dai-cells = <1>;
2895 #sound-dai-cells = <1>;
2909 qcom,din-ports = <1>;
2924 #sound-dai-cells = <1>;
2939 #sound-dai-cells = <1>;
2953 #sound-dai-cells = <1>;
2982 #sound-dai-cells = <1>;
3013 #sound-dai-cells = <1>;
3027 #sound-dai-cells = <1>;
3047 slew-rate = <1>;
3055 slew-rate = <1>;
3065 slew-rate = <1>;
3073 slew-rate = <1>;
3115 slew-rate = <1>;
3123 slew-rate = <1>;
3133 slew-rate = <1>;
3141 slew-rate = <1>;
3312 #clock-cells = <1>;
3313 #reset-cells = <1>;
3314 #power-domain-cells = <1>;
3329 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
3332 #address-cells = <1>;
3338 #address-cells = <1>;
3342 cci0_i2c1: i2c-bus@1 {
3343 reg = <1>;
3345 #address-cells = <1>;
3362 pinctrl-1 = <&cci1_0_sleep>;
3365 #address-cells = <1>;
3371 #address-cells = <1>;
3388 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>;
3391 #address-cells = <1>;
3397 #address-cells = <1>;
3401 cci2_i2c1: i2c-bus@1 {
3402 reg = <1>;
3404 #address-cells = <1>;
3582 #address-cells = <1>;
3589 port@1 {
3590 reg = <1>;
3628 #clock-cells = <1>;
3629 #reset-cells = <1>;
3630 #power-domain-cells = <1>;
3640 #interrupt-cells = <1>;
3695 #address-cells = <1>;
3705 port@1 {
3706 reg = <1>;
3781 #address-cells = <1>;
3791 port@1 {
3792 reg = <1>;
3857 #address-cells = <1>;
3863 #address-cells = <1>;
3873 port@1 {
3874 reg = <1>;
3913 #clock-cells = <1>;
3952 #address-cells = <1>;
3958 #address-cells = <1>;
3968 port@1 {
3969 reg = <1>;
3989 #clock-cells = <1>;
4017 #clock-cells = <1>;
4018 #reset-cells = <1>;
4019 #power-domain-cells = <1>;
4051 #clock-cells = <1>;
4052 #phy-cells = <1>;
4059 #address-cells = <1>;
4069 port@1 {
4070 reg = <1>;
4158 #address-cells = <1>;
4168 port@1 {
4169 reg = <1>;
4183 <125 63 1>, <126 716 12>,
4198 #thermal-sensor-cells = <1>;
4209 #thermal-sensor-cells = <1>;
4220 #thermal-sensor-cells = <1>;
4249 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4302 cci0_1_default: cci0-1-default-state {
4318 cci0_1_sleep: cci0-1-sleep-state {
4398 cci2_1_default: cci2-1-default-state {
4414 cci2_1_sleep: cci2-1-sleep-state {
4955 #global-interrupts = <1>;
5063 #redistributor-regions = <1>;
5073 #msi-cells = <1>;
5081 #address-cells = <1>;
5082 #size-cells = <1>;
5094 frame-number = <1>;
5142 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
5158 #clock-cells = <1>;
5165 #power-domain-cells = <1>;
5245 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
5246 #freq-domain-cells = <1>;
5247 #clock-cells = <1>;
5266 opp-1 {
5316 opp-1 {
5375 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
5416 #address-cells = <1>;
5419 compute-cb@1 {
5421 reg = <1>;
5517 thermal-sensors = <&tsens0 1>;
5871 thermal-sensors = <&tsens1 1>;
6291 thermal-sensors = <&tsens2 1>;
6321 gpuss-1-thermal {