Lines Matching +full:0 +full:xae91400
39 #clock-cells = <0>;
44 #clock-cells = <0>;
48 #clock-cells = <0>;
56 #clock-cells = <0>;
66 #size-cells = <0>;
68 cpu0: cpu@0 {
71 reg = <0 0>;
72 clocks = <&cpufreq_hw 0>;
77 qcom,freq-domain = <&cpufreq_hw 0>;
97 reg = <0 0x100>;
98 clocks = <&cpufreq_hw 0>;
103 qcom,freq-domain = <&cpufreq_hw 0>;
118 reg = <0 0x200>;
119 clocks = <&cpufreq_hw 0>;
124 qcom,freq-domain = <&cpufreq_hw 0>;
139 reg = <0 0x300>;
160 reg = <0 0x400>;
181 reg = <0 0x500>;
202 reg = <0 0x600>;
223 reg = <0 0x700>;
280 little_cpu_sleep_0: cpu-sleep-0-0 {
283 arm,psci-suspend-param = <0x40000004>;
290 big_cpu_sleep_0: cpu-sleep-1-0 {
293 arm,psci-suspend-param = <0x40000004>;
300 prime_cpu_sleep_0: cpu-sleep-2-0 {
303 arm,psci-suspend-param = <0x40000004>;
312 cluster_sleep_0: cluster-sleep-0 {
314 arm,psci-suspend-param = <0x41000044>;
322 arm,psci-suspend-param = <0x4100c344>;
333 qcom,dload-mode = <&tcsr 0x19000>;
334 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
338 clk_virt: interconnect-0 {
353 reg = <0 0xa0000000 0 0>;
381 #power-domain-cells = <0>;
387 #power-domain-cells = <0>;
393 #power-domain-cells = <0>;
399 #power-domain-cells = <0>;
405 #power-domain-cells = <0>;
411 #power-domain-cells = <0>;
417 #power-domain-cells = <0>;
423 #power-domain-cells = <0>;
429 #power-domain-cells = <0>;
440 reg = <0 0x80000000 0 0xa00000>;
445 reg = <0 0x80a00000 0 0x400000>;
450 reg = <0 0x80e00000 0 0x3d0000>;
455 reg = <0 0xd8100000 0 0x40000>;
460 reg = <0 0x811d0000 0 0x30000>;
466 reg = <0 0x81a00000 0 0x260000>;
472 reg = <0 0x81c60000 0 0x20000>;
478 reg = <0 0x81c80000 0 0x74000>;
485 reg = <0 0x81d00000 0 0x200000>;
491 reg = <0 0x81f00000 0 0x20000>;
496 reg = <0 0x82600000 0 0x100000>;
501 reg = <0 0x82700000 0 0x100000>;
506 reg = <0 0x82800000 0 0x4600000>;
511 reg = <0 0x8a800000 0 0x10800000>;
516 reg = <0 0x9b000000 0 0x80000>;
521 reg = <0 0x9b080000 0 0x10000>;
526 reg = <0 0x9b090000 0 0xa000>;
531 reg = <0 0x9b09a000 0 0x2000>;
536 reg = <0 0x9b100000 0 0x180000>;
542 reg = <0 0x9b280000 0 0x60000>;
548 reg = <0 0x9b2e0000 0 0x20000>;
553 reg = <0 0x9b300000 0 0x800000>;
558 reg = <0 0x9bb00000 0 0x700000>;
563 reg = <0 0x9c200000 0 0x700000>;
568 reg = <0 0x9c900000 0 0x2000000>;
573 reg = <0 0x9e900000 0 0x80000>;
578 reg = <0 0x9e980000 0 0x80000>;
583 reg = <0 0x9ea00000 0 0x4080000>;
589 /* Linux kernel image is loaded at 0xa8000000 */
593 reg = <0x0 0xd4a80000 0x0 0x280000>;
601 reg = <0 0xd4d00000 0 0x3300000>;
606 reg = <0 0xd8000000 0 0x100000>;
611 reg = <0 0xd8140000 0 0x1c0000>;
616 reg = <0 0xd8300000 0 0x500000>;
621 reg = <0 0xd8800000 0 0x8a00000>;
626 reg = <0 0xe1200000 0 0x2740000>;
631 reg = <0 0xe6440000 0 0x279000>;
636 reg = <0 0xf3600000 0 0x4aee000>;
641 reg = <0 0xf80ee000 0 0x1000>;
646 reg = <0 0xf80ef000 0 0x9000>;
651 reg = <0 0xf80f8000 0 0x4000>;
656 reg = <0 0xf80fc000 0 0x4000>;
661 reg = <0 0xf8100000 0 0x100000>;
666 reg = <0 0xf8400000 0 0x4800000>;
671 reg = <0 0xfcc00000 0 0x4000>;
676 reg = <0 0xfcc04000 0 0x100000>;
681 reg = <0 0xfce00000 0 0x2900000>;
686 reg = <0 0xff700000 0 0x100000>;
700 qcom,local-pid = <0>;
724 qcom,local-pid = <0>;
748 qcom,local-pid = <0>;
774 soc: soc@0 {
776 ranges = <0 0 0 0 0x10 0>;
777 dma-ranges = <0 0 0 0 0x10 0>;
784 reg = <0 0x00100000 0 0x1f4200>;
792 <&ufs_mem_phy 0>,
800 reg = <0 0x00408000 0 0x1000>;
810 reg = <0 0x00800000 0 0x60000>;
824 dma-channel-mask = <0x3e>;
825 iommus = <&apps_smmu 0x436 0>;
832 reg = <0 0x008c0000 0 0x2000>;
837 iommus = <&apps_smmu 0x423 0>;
845 reg = <0 0x00880000 0 0x4000>;
849 pinctrl-0 = <&qup_i2c8_data_clk>;
852 #size-cells = <0>;
853 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
854 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
855 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
857 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
858 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
865 reg = <0 0x00880000 0 0x4000>;
870 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
871 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
872 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
873 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
875 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
876 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
879 #size-cells = <0>;
885 reg = <0 0x00884000 0 0x4000>;
889 pinctrl-0 = <&qup_i2c9_data_clk>;
892 #size-cells = <0>;
893 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
894 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
895 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
897 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
905 reg = <0 0x00884000 0 0x4000>;
910 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
911 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
912 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
913 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
915 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
919 #size-cells = <0>;
925 reg = <0 0x00888000 0 0x4000>;
929 pinctrl-0 = <&qup_i2c10_data_clk>;
932 #size-cells = <0>;
933 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
934 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
935 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
937 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
945 reg = <0 0x00888000 0 0x4000>;
950 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
951 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
952 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
953 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
955 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
959 #size-cells = <0>;
965 reg = <0 0x0088c000 0 0x4000>;
969 pinctrl-0 = <&qup_i2c11_data_clk>;
972 #size-cells = <0>;
973 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
974 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
975 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
977 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
985 reg = <0 0x0088c000 0 0x4000>;
990 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
991 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
992 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
993 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
995 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
999 #size-cells = <0>;
1005 reg = <0 0x00890000 0 0x4000>;
1009 pinctrl-0 = <&qup_i2c12_data_clk>;
1012 #size-cells = <0>;
1013 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1014 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1015 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1017 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1025 reg = <0 0x00890000 0 0x4000>;
1030 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1031 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1032 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1033 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1035 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1039 #size-cells = <0>;
1045 reg = <0 0x00894000 0 0x4000>;
1049 pinctrl-0 = <&qup_i2c13_data_clk>;
1052 #size-cells = <0>;
1053 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1054 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1055 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1057 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1065 reg = <0 0x00894000 0 0x4000>;
1070 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1071 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1072 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1073 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1075 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1079 #size-cells = <0>;
1085 reg = <0 0x898000 0 0x4000>;
1089 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
1091 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1092 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
1099 reg = <0 0x0089c000 0 0x4000>;
1103 pinctrl-0 = <&qup_i2c15_data_clk>;
1106 #size-cells = <0>;
1107 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1108 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1109 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1111 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
1119 reg = <0 0x0089c000 0 0x4000>;
1124 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1125 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1126 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1127 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1129 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
1133 #size-cells = <0>;
1140 reg = <0x0 0x009c0000 0x0 0x2000>;
1150 reg = <0x0 0x00980000 0x0 0x4000>;
1155 pinctrl-0 = <&hub_i2c0_data_clk>;
1158 #size-cells = <0>;
1159 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1160 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1167 reg = <0x0 0x00984000 0x0 0x4000>;
1172 pinctrl-0 = <&hub_i2c1_data_clk>;
1175 #size-cells = <0>;
1176 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1177 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1184 reg = <0x0 0x00988000 0x0 0x4000>;
1189 pinctrl-0 = <&hub_i2c2_data_clk>;
1192 #size-cells = <0>;
1193 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1194 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1201 reg = <0x0 0x0098c000 0x0 0x4000>;
1206 pinctrl-0 = <&hub_i2c3_data_clk>;
1209 #size-cells = <0>;
1210 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1211 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1218 reg = <0x0 0x00990000 0x0 0x4000>;
1223 pinctrl-0 = <&hub_i2c4_data_clk>;
1226 #size-cells = <0>;
1227 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1228 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1235 reg = <0 0x00994000 0 0x4000>;
1240 pinctrl-0 = <&hub_i2c5_data_clk>;
1243 #size-cells = <0>;
1244 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1245 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1252 reg = <0 0x00998000 0 0x4000>;
1257 pinctrl-0 = <&hub_i2c6_data_clk>;
1260 #size-cells = <0>;
1261 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1262 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1269 reg = <0 0x0099c000 0 0x4000>;
1274 pinctrl-0 = <&hub_i2c7_data_clk>;
1277 #size-cells = <0>;
1278 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1279 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1286 reg = <0 0x009a0000 0 0x4000>;
1291 pinctrl-0 = <&hub_i2c8_data_clk>;
1294 #size-cells = <0>;
1295 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1296 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1303 reg = <0 0x009a4000 0 0x4000>;
1308 pinctrl-0 = <&hub_i2c9_data_clk>;
1311 #size-cells = <0>;
1312 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1313 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1322 reg = <0 0x00a00000 0 0x60000>;
1336 dma-channel-mask = <0x1e>;
1337 iommus = <&apps_smmu 0xb6 0>;
1344 reg = <0 0x00ac0000 0 0x2000>;
1349 iommus = <&apps_smmu 0xa3 0>;
1350 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1359 reg = <0 0x00a80000 0 0x4000>;
1363 pinctrl-0 = <&qup_i2c0_data_clk>;
1366 #size-cells = <0>;
1367 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1368 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1369 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1371 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1372 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1379 reg = <0 0x00a80000 0 0x4000>;
1384 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1385 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1386 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1387 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1389 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1390 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1393 #size-cells = <0>;
1399 reg = <0 0x00a84000 0 0x4000>;
1403 pinctrl-0 = <&qup_i2c1_data_clk>;
1406 #size-cells = <0>;
1407 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1408 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1409 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1411 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1419 reg = <0 0x00a84000 0 0x4000>;
1424 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1425 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1426 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1427 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1429 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1433 #size-cells = <0>;
1439 reg = <0 0x00a88000 0 0x4000>;
1443 pinctrl-0 = <&qup_i2c2_data_clk>;
1446 #size-cells = <0>;
1447 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1448 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1449 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1451 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1459 reg = <0 0x00a88000 0 0x4000>;
1464 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1465 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1466 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1467 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1469 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1473 #size-cells = <0>;
1479 reg = <0 0x00a8c000 0 0x4000>;
1483 pinctrl-0 = <&qup_i2c3_data_clk>;
1486 #size-cells = <0>;
1487 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1488 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1489 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1491 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1499 reg = <0 0x00a8c000 0 0x4000>;
1504 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1505 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1506 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1507 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1509 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1513 #size-cells = <0>;
1519 reg = <0 0x00a90000 0 0x4000>;
1523 pinctrl-0 = <&qup_i2c4_data_clk>;
1526 #size-cells = <0>;
1527 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1528 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1529 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1531 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1539 reg = <0 0x00a90000 0 0x4000>;
1544 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1545 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1546 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1547 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1549 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1553 #size-cells = <0>;
1559 reg = <0 0x00a94000 0 0x4000>;
1563 pinctrl-0 = <&qup_i2c5_data_clk>;
1565 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1566 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1567 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1569 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1573 #size-cells = <0>;
1579 reg = <0 0x00a94000 0 0x4000>;
1584 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1585 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1586 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1587 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1589 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1593 #size-cells = <0>;
1599 reg = <0 0x00a98000 0 0x4000>;
1603 pinctrl-0 = <&qup_i2c6_data_clk>;
1605 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1606 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1607 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1609 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1613 #size-cells = <0>;
1619 reg = <0 0x00a98000 0 0x4000>;
1624 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1625 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1626 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1627 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1629 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1633 #size-cells = <0>;
1639 reg = <0 0x00a9c000 0 0x4000>;
1643 pinctrl-0 = <&qup_uart7_default>;
1646 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1647 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1654 reg = <0 0x01500000 0 0x13080>;
1661 reg = <0 0x01600000 0 0x6200>;
1668 reg = <0 0x01680000 0 0x1d080>;
1675 reg = <0 0x016c0000 0 0x12200>;
1684 reg = <0 0x016e0000 0 0x14400>;
1693 reg = <0 0x01700000 0 0x1e400>;
1701 reg = <0 0x01780000 0 0x5b800>;
1708 reg = <0 0x010c3000 0 0x1000>;
1714 reg = <0 0x01c00000 0 0x3000>,
1715 <0 0x60000000 0 0xf1d>,
1716 <0 0x60000f20 0 0xa8>,
1717 <0 0x60001000 0 0x1000>,
1718 <0 0x60100000 0 0x100000>;
1722 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1723 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1724 bus-range = <0x00 0xff>;
1728 linux,pci-domain = <0>;
1750 interrupt-map-mask = <0 0 0 0x7>;
1751 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1752 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1753 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1754 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1771 interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
1772 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>;
1775 msi-map = <0x0 &gic_its 0x1400 0x1>,
1776 <0x100 &gic_its 0x1401 0x1>;
1777 iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
1778 <0x100 &apps_smmu 0x1401 0x1>;
1790 pcieport0: pcie@0 {
1792 reg = <0x0 0x0 0x0 0x0 0x0>;
1793 bus-range = <0x01 0xff>;
1803 reg = <0 0x01c06000 0 0x2000>;
1821 #clock-cells = <0>;
1824 #phy-cells = <0>;
1832 reg = <0x0 0x01c08000 0x0 0x3000>,
1833 <0x0 0x40000000 0x0 0xf1d>,
1834 <0x0 0x40000f20 0x0 0xa8>,
1835 <0x0 0x40001000 0x0 0x1000>,
1836 <0x0 0x40100000 0x0 0x100000>;
1840 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1841 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1842 bus-range = <0x00 0xff>;
1868 interrupt-map-mask = <0 0 0 0x7>;
1869 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1870 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1871 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1872 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1894 interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
1895 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>;
1898 msi-map = <0x0 &gic_its 0x1480 0x1>,
1899 <0x100 &gic_its 0x1481 0x1>;
1900 iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
1901 <0x100 &apps_smmu 0x1481 0x1>;
1914 pcie@0 {
1916 reg = <0x0 0x0 0x0 0x0 0x0>;
1917 bus-range = <0x01 0xff>;
1927 reg = <0x0 0x01c0e000 0x0 0x2000>;
1949 #phy-cells = <0>;
1956 reg = <0x0 0x01dc4000 0x0 0x28000>;
1959 qcom,ee = <0>;
1961 iommus = <&apps_smmu 0x480 0x0>,
1962 <&apps_smmu 0x481 0x0>;
1967 reg = <0x0 0x01dfa000 0x0 0x6000>;
1970 iommus = <&apps_smmu 0x480 0x0>,
1971 <&apps_smmu 0x481 0x0>;
1972 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
1978 reg = <0x0 0x01d80000 0x0 0x2000>;
1988 resets = <&ufs_mem_hc 0>;
1992 #phy-cells = <0>;
2000 reg = <0x0 0x01d84000 0x0 0x3000>;
2012 iommus = <&apps_smmu 0x60 0x0>;
2016 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
2017 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
2045 /bits/ 64 <0>,
2046 /bits/ 64 <0>,
2048 /bits/ 64 <0>,
2049 /bits/ 64 <0>,
2050 /bits/ 64 <0>,
2051 /bits/ 64 <0>;
2057 /bits/ 64 <0>,
2058 /bits/ 64 <0>,
2060 /bits/ 64 <0>,
2061 /bits/ 64 <0>,
2062 /bits/ 64 <0>,
2063 /bits/ 64 <0>;
2069 /bits/ 64 <0>,
2070 /bits/ 64 <0>,
2072 /bits/ 64 <0>,
2073 /bits/ 64 <0>,
2074 /bits/ 64 <0>,
2075 /bits/ 64 <0>;
2084 reg = <0 0x01d88000 0 0x18000>;
2091 reg = <0 0x01f40000 0 0x20000>;
2097 reg = <0 0x01fc0000 0 0x30000>;
2105 reg = <0x0 0x03d00000 0x0 0x40000>,
2106 <0x0 0x03d9e000 0x0 0x1000>,
2107 <0x0 0x03d61000 0x0 0x800>;
2114 iommus = <&adreno_smmu 0 0x0>,
2115 <&adreno_smmu 1 0x0>;
2188 reg = <0x0 0x03d6a000 0x0 0x35000>,
2189 <0x0 0x03d50000 0x0 0x10000>,
2190 <0x0 0x0b280000 0x0 0x10000>;
2217 iommus = <&adreno_smmu 5 0x0>;
2240 reg = <0 0x03d90000 0 0xa000>;
2252 reg = <0x0 0x03da0000 0x0 0x40000>;
2296 iommus = <&apps_smmu 0x4a0 0x0>,
2297 <&apps_smmu 0x4a2 0x0>;
2298 reg = <0 0x3f40000 0 0x10000>,
2299 <0 0x3f50000 0 0x5000>,
2300 <0 0x3e04000 0 0xfc000>;
2307 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2317 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
2318 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2324 qcom,smem-states = <&ipa_smp2p_out 0>,
2334 reg = <0x0 0x04080000 0x0 0x10000>;
2337 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2352 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
2358 qcom,smem-states = <&smp2p_modem_out 0>;
2376 reg = <0x0 0x06800000 0x0 0x10000>;
2379 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2393 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>;
2399 qcom,smem-states = <&smp2p_adsp_out 0>;
2420 #size-cells = <0>;
2425 iommus = <&apps_smmu 0x1003 0x80>,
2426 <&apps_smmu 0x1063 0x0>;
2433 iommus = <&apps_smmu 0x1004 0x80>,
2434 <&apps_smmu 0x1064 0x0>;
2441 iommus = <&apps_smmu 0x1005 0x80>,
2442 <&apps_smmu 0x1065 0x0>;
2449 iommus = <&apps_smmu 0x1006 0x80>,
2450 <&apps_smmu 0x1066 0x0>;
2457 iommus = <&apps_smmu 0x1007 0x80>,
2458 <&apps_smmu 0x1067 0x0>;
2469 #size-cells = <0>;
2474 #sound-dai-cells = <0>;
2480 iommus = <&apps_smmu 0x1001 0x80>,
2481 <&apps_smmu 0x1061 0x0>;
2507 reg = <0 0x06aa0000 0 0x1000>;
2514 #clock-cells = <0>;
2521 reg = <0 0x06ab0000 0 0x10000>;
2527 pinctrl-0 = <&wsa2_swr_active>;
2533 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
2534 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2535 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2536 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2537 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2538 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
2539 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
2540 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2541 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2544 #size-cells = <0>;
2551 reg = <0 0x06ac0000 0 0x1000>;
2558 #clock-cells = <0>;
2565 reg = <0 0x06ad0000 0 0x10000>;
2571 pinctrl-0 = <&rx_swr_active>;
2577 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff 0xff 0xff>;
2578 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2579 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2580 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>;
2581 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>;
2582 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff 0xff 0xff>;
2583 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2584 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2585 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2588 #size-cells = <0>;
2595 reg = <0 0x06ae0000 0 0x1000>;
2602 #clock-cells = <0>;
2609 reg = <0 0x06b00000 0 0x1000>;
2616 #clock-cells = <0>;
2623 reg = <0 0x06b10000 0 0x10000>;
2629 pinctrl-0 = <&wsa_swr_active>;
2635 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
2636 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2637 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2638 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2639 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2640 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
2641 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
2642 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2643 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2646 #size-cells = <0>;
2653 reg = <0 0x06d30000 0 0x10000>;
2661 pinctrl-0 = <&tx_swr_active>;
2665 qcom,dout-ports = <0>;
2666 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2667 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2668 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2669 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2670 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2671 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2672 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2673 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2674 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2677 #size-cells = <0>;
2684 reg = <0 0x06d44000 0 0x1000>;
2690 #clock-cells = <0>;
2697 reg = <0 0x06e80000 0 0x20000>,
2698 <0 0x07250000 0 0x10000>;
2701 gpio-ranges = <&lpass_tlmm 0 0 23>;
2814 reg = <0 0x07400000 0 0x19080>;
2821 reg = <0 0x07430000 0 0x3a200>;
2828 reg = <0 0x07e40000 0 0xe080>;
2835 reg = <0 0x08804000 0 0x1000>;
2845 iommus = <&apps_smmu 0x540 0>;
2846 qcom,dll-config = <0x0007642c>;
2847 qcom,ddr-config = <0x80040868>;
2851 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2852 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2858 sdhci-caps-mask = <0x3 0>;
2889 reg = <0 0x0aaf0000 0 0x10000>;
2901 reg = <0 0x0ac15000 0 0x1000>;
2910 pinctrl-0 = <&cci0_0_default &cci0_1_default>;
2915 #size-cells = <0>;
2917 cci0_i2c0: i2c-bus@0 {
2918 reg = <0>;
2921 #size-cells = <0>;
2928 #size-cells = <0>;
2934 reg = <0 0x0ac16000 0 0x1000>;
2943 pinctrl-0 = <&cci1_0_default>;
2948 #size-cells = <0>;
2950 cci1_i2c0: i2c-bus@0 {
2951 reg = <0>;
2954 #size-cells = <0>;
2960 reg = <0 0x0ac17000 0 0x1000>;
2969 pinctrl-0 = <&cci2_0_default &cci2_1_default>;
2974 #size-cells = <0>;
2976 cci2_i2c0: i2c-bus@0 {
2977 reg = <0>;
2980 #size-cells = <0>;
2987 #size-cells = <0>;
2993 reg = <0 0x0ade0000 0 0x20000>;
3007 reg = <0 0x0ae00000 0 0x1000>;
3023 interconnects = <&mmss_noc MASTER_MDP 0 &mc_virt SLAVE_EBI1 0>;
3026 iommus = <&apps_smmu 0x1c00 0x2>;
3036 reg = <0 0x0ae01000 0 0x8f000>,
3037 <0 0x0aeb0000 0 0x2008>;
3041 interrupts = <0>;
3065 #size-cells = <0>;
3067 port@0 {
3068 reg = <0>;
3116 reg = <0 0xae90000 0 0x200>,
3117 <0 0xae90200 0 0x200>,
3118 <0 0xae90400 0 0xc00>,
3119 <0 0xae91000 0 0x400>,
3120 <0 0xae91400 0 0x400>;
3142 #sound-dai-cells = <0>;
3151 #size-cells = <0>;
3153 port@0 {
3154 reg = <0>;
3195 reg = <0 0x0ae94000 0 0x400>;
3218 assigned-clock-parents = <&mdss_dsi0_phy 0>,
3227 #size-cells = <0>;
3233 #size-cells = <0>;
3235 port@0 {
3236 reg = <0>;
3271 reg = <0 0x0ae95000 0 0x200>,
3272 <0 0x0ae95200 0 0x280>,
3273 <0 0x0ae95500 0 0x400>;
3283 #phy-cells = <0>;
3290 reg = <0 0x0ae96000 0 0x400>;
3313 assigned-clock-parents = <&mdss_dsi1_phy 0>,
3322 #size-cells = <0>;
3328 #size-cells = <0>;
3330 port@0 {
3331 reg = <0>;
3347 reg = <0 0x0ae97000 0 0x200>,
3348 <0 0x0ae97200 0 0x280>,
3349 <0 0x0ae97500 0 0x400>;
3359 #phy-cells = <0>;
3367 reg = <0 0x0af00000 0 0x20000>;
3372 <&mdss_dsi0_phy 0>,
3374 <&mdss_dsi1_phy 0>,
3378 <0>, /* dp1 */
3379 <0>,
3380 <0>, /* dp2 */
3381 <0>,
3382 <0>, /* dp3 */
3383 <0>;
3393 reg = <0x0 0x088e3000 0x0 0x154>;
3394 #phy-cells = <0>;
3406 reg = <0x0 0x088e8000 0x0 0x3000>;
3429 #size-cells = <0>;
3431 port@0 {
3432 reg = <0>;
3458 reg = <0x0 0x0a6f8800 0x0 0x400>;
3496 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
3497 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
3504 reg = <0x0 0x0a600000 0x0 0xcd00>;
3506 iommus = <&apps_smmu 0x40 0x0>;
3510 snps,hird-threshold = /bits/ 8 <0x0>;
3526 #size-cells = <0>;
3528 port@0 {
3529 reg = <0>;
3548 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
3549 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
3559 reg = <0 0x0c271000 0 0x1000>, /* TM */
3560 <0 0x0c222000 0 0x1000>; /* SROT */
3570 reg = <0 0x0c272000 0 0x1000>, /* TM */
3571 <0 0x0c223000 0 0x1000>; /* SROT */
3581 reg = <0 0x0c273000 0 0x1000>, /* TM */
3582 <0 0x0c224000 0 0x1000>; /* SROT */
3592 reg = <0 0x0c300000 0 0x400>;
3598 #clock-cells = <0>;
3603 reg = <0 0x0c3f0000 0 0x400>;
3608 reg = <0 0x0c400000 0 0x3000>,
3609 <0 0x0c500000 0 0x400000>,
3610 <0 0x0c440000 0 0x80000>,
3611 <0 0x0c4c0000 0 0x20000>,
3612 <0 0x0c42d000 0 0x4000>;
3616 qcom,ee = <0>;
3617 qcom,channel = <0>;
3618 qcom,bus-id = <0>;
3620 #size-cells = <0>;
3627 reg = <0 0x0f100000 0 0x300000>;
3633 gpio-ranges = <&tlmm 0 0 211>;
3636 cci0_0_default: cci0-0-default-state {
3652 cci0_0_sleep: cci0-0-sleep-state {
3700 cci1_0_default: cci1-0-default-state {
3716 cci1_0_sleep: cci1-0-sleep-state {
3732 cci2_0_default: cci2-0-default-state {
3748 cci2_0_sleep: cci2-0-sleep-state {
4319 reg = <0 0x15000000 0 0x100000>;
4424 reg = <0 0x17100000 0 0x10000>, /* GICD */
4425 <0 0x17180000 0 0x200000>; /* GICR * 8 */
4430 redistributor-stride = <0 0x40000>;
4437 reg = <0 0x17140000 0 0x20000>;
4445 reg = <0 0x17420000 0 0x1000>;
4446 ranges = <0 0 0 0x20000000>;
4451 reg = <0x17421000 0x1000>,
4452 <0x17422000 0x1000>;
4453 frame-number = <0>;
4459 reg = <0x17423000 0x1000>;
4466 reg = <0x17425000 0x1000>;
4473 reg = <0x17427000 0x1000>;
4480 reg = <0x17429000 0x1000>;
4487 reg = <0x1742b000 0x1000>;
4494 reg = <0x1742d000 0x1000>;
4504 reg = <0 0x17a00000 0 0x10000>,
4505 <0 0x17a10000 0 0x10000>,
4506 <0 0x17a20000 0 0x10000>,
4507 <0 0x17a30000 0 0x10000>;
4508 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4512 qcom,tcs-offset = <0xd00>;
4515 <WAKE_TCS 2>, <CONTROL_TCS 0>;
4602 reg = <0 0x17d91000 0 0x1000>,
4603 <0 0x17d92000 0 0x1000>,
4604 <0 0x17d93000 0 0x1000>;
4611 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4618 reg = <0 0x24091000 0 0x1000>;
4627 opp-0 {
4667 reg = <0 0x240b6400 0 0x600>;
4676 opp-0 {
4704 reg = <0 0x24100000 0 0xbb800>;
4711 reg = <0 0x25000000 0 0x200000>,
4712 <0 0x25200000 0 0x200000>,
4713 <0 0x25400000 0 0x200000>,
4714 <0 0x25600000 0 0x200000>,
4715 <0 0x25800000 0 0x200000>,
4716 <0 0x25a00000 0 0x200000>;
4728 reg = <0 0x320c0000 0 0xe080>;
4735 reg = <0x0 0x32300000 0x0 0x10000>;
4738 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
4753 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
4759 qcom,smem-states = <&smp2p_cdsp_out 0>;
4780 #size-cells = <0>;
4785 iommus = <&apps_smmu 0x1961 0x0>,
4786 <&apps_smmu 0x0c01 0x20>,
4787 <&apps_smmu 0x19c1 0x10>;
4794 iommus = <&apps_smmu 0x1962 0x0>,
4795 <&apps_smmu 0x0c02 0x20>,
4796 <&apps_smmu 0x19c2 0x10>;
4803 iommus = <&apps_smmu 0x1963 0x0>,
4804 <&apps_smmu 0x0c03 0x20>,
4805 <&apps_smmu 0x19c3 0x10>;
4812 iommus = <&apps_smmu 0x1964 0x0>,
4813 <&apps_smmu 0x0c04 0x20>,
4814 <&apps_smmu 0x19c4 0x10>;
4821 iommus = <&apps_smmu 0x1965 0x0>,
4822 <&apps_smmu 0x0c05 0x20>,
4823 <&apps_smmu 0x19c5 0x10>;
4830 iommus = <&apps_smmu 0x1966 0x0>,
4831 <&apps_smmu 0x0c06 0x20>,
4832 <&apps_smmu 0x19c6 0x10>;
4839 iommus = <&apps_smmu 0x1967 0x0>,
4840 <&apps_smmu 0x0c07 0x20>,
4841 <&apps_smmu 0x19c7 0x10>;
4848 iommus = <&apps_smmu 0x1968 0x0>,
4849 <&apps_smmu 0x0c08 0x20>,
4850 <&apps_smmu 0x19c8 0x10>;
4862 thermal-sensors = <&tsens0 0>;
5216 thermal-sensors = <&tsens1 0>;
5634 thermal-sensors = <&tsens2 0>;
5651 gpuss-0-thermal {