Lines Matching +full:0 +full:x03d90000
38 #clock-cells = <0>;
43 #clock-cells = <0>;
47 #clock-cells = <0>;
55 #clock-cells = <0>;
65 #size-cells = <0>;
67 CPU0: cpu@0 {
70 reg = <0 0>;
71 clocks = <&cpufreq_hw 0>;
76 qcom,freq-domain = <&cpufreq_hw 0>;
96 reg = <0 0x100>;
97 clocks = <&cpufreq_hw 0>;
102 qcom,freq-domain = <&cpufreq_hw 0>;
117 reg = <0 0x200>;
118 clocks = <&cpufreq_hw 0>;
123 qcom,freq-domain = <&cpufreq_hw 0>;
138 reg = <0 0x300>;
159 reg = <0 0x400>;
180 reg = <0 0x500>;
201 reg = <0 0x600>;
222 reg = <0 0x700>;
279 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
282 arm,psci-suspend-param = <0x40000004>;
289 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
292 arm,psci-suspend-param = <0x40000004>;
299 PRIME_CPU_SLEEP_0: cpu-sleep-2-0 {
302 arm,psci-suspend-param = <0x40000004>;
311 CLUSTER_SLEEP_0: cluster-sleep-0 {
313 arm,psci-suspend-param = <0x41000044>;
321 arm,psci-suspend-param = <0x4100c344>;
332 qcom,dload-mode = <&tcsr 0x19000>;
333 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
337 clk_virt: interconnect-0 {
352 reg = <0 0xa0000000 0 0>;
380 #power-domain-cells = <0>;
386 #power-domain-cells = <0>;
392 #power-domain-cells = <0>;
398 #power-domain-cells = <0>;
404 #power-domain-cells = <0>;
410 #power-domain-cells = <0>;
416 #power-domain-cells = <0>;
422 #power-domain-cells = <0>;
428 #power-domain-cells = <0>;
439 reg = <0 0x80000000 0 0xa00000>;
444 reg = <0 0x80a00000 0 0x400000>;
449 reg = <0 0x80e00000 0 0x3d0000>;
454 reg = <0 0xd8100000 0 0x40000>;
459 reg = <0 0x811d0000 0 0x30000>;
465 reg = <0 0x81a00000 0 0x260000>;
471 reg = <0 0x81c60000 0 0x20000>;
477 reg = <0 0x81c80000 0 0x74000>;
484 reg = <0 0x81d00000 0 0x200000>;
490 reg = <0 0x81f00000 0 0x20000>;
495 reg = <0 0x82600000 0 0x100000>;
500 reg = <0 0x82700000 0 0x100000>;
505 reg = <0 0x82800000 0 0x4600000>;
510 reg = <0 0x8a800000 0 0x10800000>;
515 reg = <0 0x9b000000 0 0x80000>;
520 reg = <0 0x9b080000 0 0x10000>;
525 reg = <0 0x9b090000 0 0xa000>;
530 reg = <0 0x9b09a000 0 0x2000>;
535 reg = <0 0x9b100000 0 0x180000>;
541 reg = <0 0x9b280000 0 0x60000>;
547 reg = <0 0x9b2e0000 0 0x20000>;
552 reg = <0 0x9b300000 0 0x800000>;
557 reg = <0 0x9bb00000 0 0x700000>;
562 reg = <0 0x9c200000 0 0x700000>;
567 reg = <0 0x9c900000 0 0x2000000>;
572 reg = <0 0x9e900000 0 0x80000>;
577 reg = <0 0x9e980000 0 0x80000>;
582 reg = <0 0x9ea00000 0 0x4080000>;
588 /* Linux kernel image is loaded at 0xa8000000 */
592 reg = <0x0 0xd4a80000 0x0 0x280000>;
600 reg = <0 0xd4d00000 0 0x3300000>;
605 reg = <0 0xd8000000 0 0x100000>;
610 reg = <0 0xd8140000 0 0x1c0000>;
615 reg = <0 0xd8300000 0 0x500000>;
620 reg = <0 0xd8800000 0 0x8a00000>;
625 reg = <0 0xe1200000 0 0x2740000>;
630 reg = <0 0xe6440000 0 0x279000>;
635 reg = <0 0xf3600000 0 0x4aee000>;
640 reg = <0 0xf80ee000 0 0x1000>;
645 reg = <0 0xf80ef000 0 0x9000>;
650 reg = <0 0xf80f8000 0 0x4000>;
655 reg = <0 0xf80fc000 0 0x4000>;
660 reg = <0 0xf8100000 0 0x100000>;
665 reg = <0 0xf8400000 0 0x4800000>;
670 reg = <0 0xfcc00000 0 0x4000>;
675 reg = <0 0xfcc04000 0 0x100000>;
680 reg = <0 0xfce00000 0 0x2900000>;
685 reg = <0 0xff700000 0 0x100000>;
699 qcom,local-pid = <0>;
723 qcom,local-pid = <0>;
747 qcom,local-pid = <0>;
773 soc: soc@0 {
775 ranges = <0 0 0 0 0x10 0>;
776 dma-ranges = <0 0 0 0 0x10 0>;
783 reg = <0 0x00100000 0 0x1f4200>;
791 <&ufs_mem_phy 0>,
799 reg = <0 0x00408000 0 0x1000>;
809 reg = <0 0x00800000 0 0x60000>;
823 dma-channel-mask = <0x3e>;
824 iommus = <&apps_smmu 0x436 0>;
831 reg = <0 0x008c0000 0 0x2000>;
836 iommus = <&apps_smmu 0x423 0>;
844 reg = <0 0x00880000 0 0x4000>;
848 pinctrl-0 = <&qup_i2c8_data_clk>;
851 #size-cells = <0>;
852 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
853 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
854 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
856 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
857 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
864 reg = <0 0x00880000 0 0x4000>;
869 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
870 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
871 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
872 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
874 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
875 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
878 #size-cells = <0>;
884 reg = <0 0x00884000 0 0x4000>;
888 pinctrl-0 = <&qup_i2c9_data_clk>;
891 #size-cells = <0>;
892 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
893 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
894 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
896 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
904 reg = <0 0x00884000 0 0x4000>;
909 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
910 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
911 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
912 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
914 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
918 #size-cells = <0>;
924 reg = <0 0x00888000 0 0x4000>;
928 pinctrl-0 = <&qup_i2c10_data_clk>;
931 #size-cells = <0>;
932 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
933 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
934 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
936 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
944 reg = <0 0x00888000 0 0x4000>;
949 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
950 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
951 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
952 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
954 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
958 #size-cells = <0>;
964 reg = <0 0x0088c000 0 0x4000>;
968 pinctrl-0 = <&qup_i2c11_data_clk>;
971 #size-cells = <0>;
972 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
973 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
974 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
976 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
984 reg = <0 0x0088c000 0 0x4000>;
989 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
990 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
991 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
992 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
994 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
998 #size-cells = <0>;
1004 reg = <0 0x00890000 0 0x4000>;
1008 pinctrl-0 = <&qup_i2c12_data_clk>;
1011 #size-cells = <0>;
1012 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1013 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1014 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1016 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1024 reg = <0 0x00890000 0 0x4000>;
1029 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1030 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1031 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1032 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1034 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1038 #size-cells = <0>;
1044 reg = <0 0x00894000 0 0x4000>;
1048 pinctrl-0 = <&qup_i2c13_data_clk>;
1051 #size-cells = <0>;
1052 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1053 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1054 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1056 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1064 reg = <0 0x00894000 0 0x4000>;
1069 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1070 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1071 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1072 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1074 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1078 #size-cells = <0>;
1084 reg = <0 0x898000 0 0x4000>;
1088 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
1090 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1091 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
1098 reg = <0 0x0089c000 0 0x4000>;
1102 pinctrl-0 = <&qup_i2c15_data_clk>;
1105 #size-cells = <0>;
1106 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1107 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1108 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1110 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
1118 reg = <0 0x0089c000 0 0x4000>;
1123 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1124 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1125 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1126 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1128 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
1132 #size-cells = <0>;
1139 reg = <0x0 0x009c0000 0x0 0x2000>;
1149 reg = <0x0 0x00980000 0x0 0x4000>;
1154 pinctrl-0 = <&hub_i2c0_data_clk>;
1157 #size-cells = <0>;
1158 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1159 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1166 reg = <0x0 0x00984000 0x0 0x4000>;
1171 pinctrl-0 = <&hub_i2c1_data_clk>;
1174 #size-cells = <0>;
1175 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1176 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1183 reg = <0x0 0x00988000 0x0 0x4000>;
1188 pinctrl-0 = <&hub_i2c2_data_clk>;
1191 #size-cells = <0>;
1192 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1193 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1200 reg = <0x0 0x0098c000 0x0 0x4000>;
1205 pinctrl-0 = <&hub_i2c3_data_clk>;
1208 #size-cells = <0>;
1209 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1210 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1217 reg = <0x0 0x00990000 0x0 0x4000>;
1222 pinctrl-0 = <&hub_i2c4_data_clk>;
1225 #size-cells = <0>;
1226 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1227 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1234 reg = <0 0x00994000 0 0x4000>;
1239 pinctrl-0 = <&hub_i2c5_data_clk>;
1242 #size-cells = <0>;
1243 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1244 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1251 reg = <0 0x00998000 0 0x4000>;
1256 pinctrl-0 = <&hub_i2c6_data_clk>;
1259 #size-cells = <0>;
1260 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1261 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1268 reg = <0 0x0099c000 0 0x4000>;
1273 pinctrl-0 = <&hub_i2c7_data_clk>;
1276 #size-cells = <0>;
1277 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1278 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1285 reg = <0 0x009a0000 0 0x4000>;
1290 pinctrl-0 = <&hub_i2c8_data_clk>;
1293 #size-cells = <0>;
1294 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1295 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1302 reg = <0 0x009a4000 0 0x4000>;
1307 pinctrl-0 = <&hub_i2c9_data_clk>;
1310 #size-cells = <0>;
1311 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1312 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1321 reg = <0 0x00a00000 0 0x60000>;
1335 dma-channel-mask = <0x1e>;
1336 iommus = <&apps_smmu 0xb6 0>;
1343 reg = <0 0x00ac0000 0 0x2000>;
1348 iommus = <&apps_smmu 0xa3 0>;
1349 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1358 reg = <0 0x00a80000 0 0x4000>;
1362 pinctrl-0 = <&qup_i2c0_data_clk>;
1365 #size-cells = <0>;
1366 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1367 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1368 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1370 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1371 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1378 reg = <0 0x00a80000 0 0x4000>;
1383 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1384 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1385 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1386 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1388 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1389 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1392 #size-cells = <0>;
1398 reg = <0 0x00a84000 0 0x4000>;
1402 pinctrl-0 = <&qup_i2c1_data_clk>;
1405 #size-cells = <0>;
1406 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1407 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1408 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1410 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1418 reg = <0 0x00a84000 0 0x4000>;
1423 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1424 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1425 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1426 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1428 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1432 #size-cells = <0>;
1438 reg = <0 0x00a88000 0 0x4000>;
1442 pinctrl-0 = <&qup_i2c2_data_clk>;
1445 #size-cells = <0>;
1446 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1447 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1448 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1450 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1458 reg = <0 0x00a88000 0 0x4000>;
1463 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1464 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1465 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1466 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1468 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1472 #size-cells = <0>;
1478 reg = <0 0x00a8c000 0 0x4000>;
1482 pinctrl-0 = <&qup_i2c3_data_clk>;
1485 #size-cells = <0>;
1486 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1487 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1488 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1490 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1498 reg = <0 0x00a8c000 0 0x4000>;
1503 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1504 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1505 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1506 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1508 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1512 #size-cells = <0>;
1518 reg = <0 0x00a90000 0 0x4000>;
1522 pinctrl-0 = <&qup_i2c4_data_clk>;
1525 #size-cells = <0>;
1526 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1527 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1528 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1530 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1538 reg = <0 0x00a90000 0 0x4000>;
1543 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1544 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1545 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1546 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1548 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1552 #size-cells = <0>;
1558 reg = <0 0x00a94000 0 0x4000>;
1562 pinctrl-0 = <&qup_i2c5_data_clk>;
1564 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1565 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1566 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1568 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1572 #size-cells = <0>;
1578 reg = <0 0x00a94000 0 0x4000>;
1583 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1584 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1585 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1586 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1588 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1592 #size-cells = <0>;
1598 reg = <0 0x00a98000 0 0x4000>;
1602 pinctrl-0 = <&qup_i2c6_data_clk>;
1604 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1605 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1606 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1608 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1612 #size-cells = <0>;
1618 reg = <0 0x00a98000 0 0x4000>;
1623 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1624 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1625 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1626 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1628 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1632 #size-cells = <0>;
1638 reg = <0 0x00a9c000 0 0x4000>;
1642 pinctrl-0 = <&qup_uart7_default>;
1645 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1646 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1653 reg = <0 0x01500000 0 0x13080>;
1660 reg = <0 0x01600000 0 0x6200>;
1667 reg = <0 0x01680000 0 0x1d080>;
1674 reg = <0 0x016c0000 0 0x12200>;
1683 reg = <0 0x016e0000 0 0x14400>;
1692 reg = <0 0x01700000 0 0x1e400>;
1700 reg = <0 0x01780000 0 0x5b800>;
1707 reg = <0 0x010c3000 0 0x1000>;
1713 reg = <0 0x01c00000 0 0x3000>,
1714 <0 0x60000000 0 0xf1d>,
1715 <0 0x60000f20 0 0xa8>,
1716 <0 0x60001000 0 0x1000>,
1717 <0 0x60100000 0 0x100000>;
1721 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1722 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1723 bus-range = <0x00 0xff>;
1727 linux,pci-domain = <0>;
1747 interrupt-map-mask = <0 0 0 0x7>;
1748 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1749 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1750 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1751 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1768 interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
1769 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>;
1772 msi-map = <0x0 &gic_its 0x1400 0x1>,
1773 <0x100 &gic_its 0x1401 0x1>;
1774 iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
1775 <0x100 &apps_smmu 0x1401 0x1>;
1787 pcieport0: pcie@0 {
1789 reg = <0x0 0x0 0x0 0x0 0x0>;
1790 bus-range = <0x01 0xff>;
1800 reg = <0 0x01c06000 0 0x2000>;
1818 #clock-cells = <0>;
1821 #phy-cells = <0>;
1829 reg = <0x0 0x01c08000 0x0 0x3000>,
1830 <0x0 0x40000000 0x0 0xf1d>,
1831 <0x0 0x40000f20 0x0 0xa8>,
1832 <0x0 0x40001000 0x0 0x1000>,
1833 <0x0 0x40100000 0x0 0x100000>;
1837 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1838 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1839 bus-range = <0x00 0xff>;
1863 interrupt-map-mask = <0 0 0 0x7>;
1864 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1865 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1866 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1867 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1889 interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
1890 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>;
1893 msi-map = <0x0 &gic_its 0x1480 0x1>,
1894 <0x100 &gic_its 0x1481 0x1>;
1895 iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
1896 <0x100 &apps_smmu 0x1481 0x1>;
1909 pcie@0 {
1911 reg = <0x0 0x0 0x0 0x0 0x0>;
1912 bus-range = <0x01 0xff>;
1922 reg = <0x0 0x01c0e000 0x0 0x2000>;
1944 #phy-cells = <0>;
1951 reg = <0x0 0x01dc4000 0x0 0x28000>;
1954 qcom,ee = <0>;
1956 iommus = <&apps_smmu 0x480 0x0>,
1957 <&apps_smmu 0x481 0x0>;
1962 reg = <0x0 0x01dfa000 0x0 0x6000>;
1965 iommus = <&apps_smmu 0x480 0x0>,
1966 <&apps_smmu 0x481 0x0>;
1967 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
1973 reg = <0x0 0x01d80000 0x0 0x2000>;
1983 resets = <&ufs_mem_hc 0>;
1987 #phy-cells = <0>;
1995 reg = <0x0 0x01d84000 0x0 0x3000>;
2007 iommus = <&apps_smmu 0x60 0x0>;
2011 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
2012 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
2040 /bits/ 64 <0>,
2041 /bits/ 64 <0>,
2043 /bits/ 64 <0>,
2044 /bits/ 64 <0>,
2045 /bits/ 64 <0>,
2046 /bits/ 64 <0>;
2052 /bits/ 64 <0>,
2053 /bits/ 64 <0>,
2055 /bits/ 64 <0>,
2056 /bits/ 64 <0>,
2057 /bits/ 64 <0>,
2058 /bits/ 64 <0>;
2064 /bits/ 64 <0>,
2065 /bits/ 64 <0>,
2067 /bits/ 64 <0>,
2068 /bits/ 64 <0>,
2069 /bits/ 64 <0>,
2070 /bits/ 64 <0>;
2079 reg = <0 0x01d88000 0 0x8000>;
2085 reg = <0 0x01f40000 0 0x20000>;
2091 reg = <0 0x01fc0000 0 0x30000>;
2099 reg = <0x0 0x03d00000 0x0 0x40000>,
2100 <0x0 0x03d9e000 0x0 0x1000>,
2101 <0x0 0x03d61000 0x0 0x800>;
2108 iommus = <&adreno_smmu 0 0x0>,
2109 <&adreno_smmu 1 0x0>;
2170 reg = <0x0 0x03d6a000 0x0 0x35000>,
2171 <0x0 0x03d50000 0x0 0x10000>,
2172 <0x0 0x0b280000 0x0 0x10000>;
2199 iommus = <&adreno_smmu 5 0x0>;
2222 reg = <0 0x03d90000 0 0xa000>;
2234 reg = <0x0 0x03da0000 0x0 0x40000>;
2278 iommus = <&apps_smmu 0x4a0 0x0>,
2279 <&apps_smmu 0x4a2 0x0>;
2280 reg = <0 0x3f40000 0 0x10000>,
2281 <0 0x3f50000 0 0x5000>,
2282 <0 0x3e04000 0 0xfc000>;
2289 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2299 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
2300 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2306 qcom,smem-states = <&ipa_smp2p_out 0>,
2316 reg = <0x0 0x04080000 0x0 0x4040>;
2319 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2334 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
2340 qcom,smem-states = <&smp2p_modem_out 0>;
2358 reg = <0 0x06aa0000 0 0x1000>;
2365 #clock-cells = <0>;
2372 reg = <0 0x06ab0000 0 0x10000>;
2378 pinctrl-0 = <&wsa2_swr_active>;
2384 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
2385 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2386 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2387 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2388 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2389 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
2390 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
2391 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2392 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2395 #size-cells = <0>;
2402 reg = <0 0x06ac0000 0 0x1000>;
2409 #clock-cells = <0>;
2416 reg = <0 0x06ad0000 0 0x10000>;
2422 pinctrl-0 = <&rx_swr_active>;
2428 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff 0xff 0xff>;
2429 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2430 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2431 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>;
2432 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>;
2433 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff 0xff 0xff>;
2434 …qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff 0xff 0xff…
2435 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0x…
2436 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2439 #size-cells = <0>;
2446 reg = <0 0x06ae0000 0 0x1000>;
2453 #clock-cells = <0>;
2460 reg = <0 0x06b00000 0 0x1000>;
2467 #clock-cells = <0>;
2474 reg = <0 0x06b10000 0 0x10000>;
2480 pinctrl-0 = <&wsa_swr_active>;
2486 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
2487 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2488 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2489 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2490 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2491 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
2492 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
2493 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2494 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2497 #size-cells = <0>;
2504 reg = <0 0x06d30000 0 0x10000>;
2512 pinctrl-0 = <&tx_swr_active>;
2516 qcom,dout-ports = <0>;
2517 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2518 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2519 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2520 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2521 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2522 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2523 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2524 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2525 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2528 #size-cells = <0>;
2535 reg = <0 0x06d44000 0 0x1000>;
2541 #clock-cells = <0>;
2548 reg = <0 0x06e80000 0 0x20000>,
2549 <0 0x07250000 0 0x10000>;
2552 gpio-ranges = <&lpass_tlmm 0 0 23>;
2665 reg = <0 0x07400000 0 0x19080>;
2672 reg = <0 0x07430000 0 0x3a200>;
2679 reg = <0 0x07e40000 0 0xe080>;
2686 reg = <0 0x08804000 0 0x1000>;
2696 iommus = <&apps_smmu 0x540 0>;
2697 qcom,dll-config = <0x0007642c>;
2698 qcom,ddr-config = <0x80040868>;
2702 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2703 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2709 sdhci-caps-mask = <0x3 0>;
2740 reg = <0 0x0aaf0000 0 0x10000>;
2752 reg = <0 0x0ac15000 0 0x1000>;
2761 pinctrl-0 = <&cci0_0_default &cci0_1_default>;
2766 #size-cells = <0>;
2768 cci0_i2c0: i2c-bus@0 {
2769 reg = <0>;
2772 #size-cells = <0>;
2779 #size-cells = <0>;
2785 reg = <0 0x0ac16000 0 0x1000>;
2794 pinctrl-0 = <&cci1_0_default>;
2799 #size-cells = <0>;
2801 cci1_i2c0: i2c-bus@0 {
2802 reg = <0>;
2805 #size-cells = <0>;
2811 reg = <0 0x0ac17000 0 0x1000>;
2820 pinctrl-0 = <&cci2_0_default &cci2_1_default>;
2825 #size-cells = <0>;
2827 cci2_i2c0: i2c-bus@0 {
2828 reg = <0>;
2831 #size-cells = <0>;
2838 #size-cells = <0>;
2844 reg = <0 0x0ade0000 0 0x20000>;
2858 reg = <0 0x0ae00000 0 0x1000>;
2874 interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
2875 <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
2878 iommus = <&apps_smmu 0x1c00 0x2>;
2888 reg = <0 0x0ae01000 0 0x8f000>,
2889 <0 0x0aeb0000 0 0x2008>;
2893 interrupts = <0>;
2917 #size-cells = <0>;
2919 port@0 {
2920 reg = <0>;
2968 reg = <0 0xae90000 0 0x200>,
2969 <0 0xae90200 0 0x200>,
2970 <0 0xae90400 0 0xc00>,
2971 <0 0xae91000 0 0x400>,
2972 <0 0xae91400 0 0x400>;
2994 #sound-dai-cells = <0>;
3003 #size-cells = <0>;
3005 port@0 {
3006 reg = <0>;
3047 reg = <0 0x0ae94000 0 0x400>;
3070 assigned-clock-parents = <&mdss_dsi0_phy 0>,
3079 #size-cells = <0>;
3085 #size-cells = <0>;
3087 port@0 {
3088 reg = <0>;
3123 reg = <0 0x0ae95000 0 0x200>,
3124 <0 0x0ae95200 0 0x280>,
3125 <0 0x0ae95500 0 0x400>;
3135 #phy-cells = <0>;
3142 reg = <0 0x0ae96000 0 0x400>;
3165 assigned-clock-parents = <&mdss_dsi1_phy 0>,
3174 #size-cells = <0>;
3180 #size-cells = <0>;
3182 port@0 {
3183 reg = <0>;
3199 reg = <0 0x0ae97000 0 0x200>,
3200 <0 0x0ae97200 0 0x280>,
3201 <0 0x0ae97500 0 0x400>;
3211 #phy-cells = <0>;
3219 reg = <0 0x0af00000 0 0x20000>;
3224 <&mdss_dsi0_phy 0>,
3226 <&mdss_dsi1_phy 0>,
3230 <0>, /* dp1 */
3231 <0>,
3232 <0>, /* dp2 */
3233 <0>,
3234 <0>, /* dp3 */
3235 <0>;
3245 reg = <0x0 0x088e3000 0x0 0x154>;
3246 #phy-cells = <0>;
3258 reg = <0x0 0x088e8000 0x0 0x3000>;
3281 #size-cells = <0>;
3283 port@0 {
3284 reg = <0>;
3310 reg = <0x0 0x0a6f8800 0x0 0x400>;
3348 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
3349 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
3356 reg = <0x0 0x0a600000 0x0 0xcd00>;
3358 iommus = <&apps_smmu 0x40 0x0>;
3362 snps,hird-threshold = /bits/ 8 <0x0>;
3378 #size-cells = <0>;
3380 port@0 {
3381 reg = <0>;
3400 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
3401 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
3411 reg = <0 0x0c271000 0 0x1000>, /* TM */
3412 <0 0x0c222000 0 0x1000>; /* SROT */
3422 reg = <0 0x0c272000 0 0x1000>, /* TM */
3423 <0 0x0c223000 0 0x1000>; /* SROT */
3433 reg = <0 0x0c273000 0 0x1000>, /* TM */
3434 <0 0x0c224000 0 0x1000>; /* SROT */
3444 reg = <0 0x0c300000 0 0x400>;
3450 #clock-cells = <0>;
3455 reg = <0 0x0c3f0000 0 0x400>;
3460 reg = <0 0x0c400000 0 0x3000>,
3461 <0 0x0c500000 0 0x400000>,
3462 <0 0x0c440000 0 0x80000>,
3463 <0 0x0c4c0000 0 0x20000>,
3464 <0 0x0c42d000 0 0x4000>;
3468 qcom,ee = <0>;
3469 qcom,channel = <0>;
3470 qcom,bus-id = <0>;
3472 #size-cells = <0>;
3479 reg = <0 0x0f100000 0 0x300000>;
3485 gpio-ranges = <&tlmm 0 0 211>;
3488 cci0_0_default: cci0-0-default-state {
3504 cci0_0_sleep: cci0-0-sleep-state {
3552 cci1_0_default: cci1-0-default-state {
3568 cci1_0_sleep: cci1-0-sleep-state {
3584 cci2_0_default: cci2-0-default-state {
3600 cci2_0_sleep: cci2-0-sleep-state {
4171 reg = <0 0x15000000 0 0x100000>;
4276 reg = <0 0x17100000 0 0x10000>, /* GICD */
4277 <0 0x17180000 0 0x200000>; /* GICR * 8 */
4282 redistributor-stride = <0 0x40000>;
4289 reg = <0 0x17140000 0 0x20000>;
4297 reg = <0 0x17420000 0 0x1000>;
4298 ranges = <0 0 0 0x20000000>;
4303 reg = <0x17421000 0x1000>,
4304 <0x17422000 0x1000>;
4305 frame-number = <0>;
4311 reg = <0x17423000 0x1000>;
4318 reg = <0x17425000 0x1000>;
4325 reg = <0x17427000 0x1000>;
4332 reg = <0x17429000 0x1000>;
4339 reg = <0x1742b000 0x1000>;
4346 reg = <0x1742d000 0x1000>;
4356 reg = <0 0x17a00000 0 0x10000>,
4357 <0 0x17a10000 0 0x10000>,
4358 <0 0x17a20000 0 0x10000>,
4359 <0 0x17a30000 0 0x10000>;
4360 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4364 qcom,tcs-offset = <0xd00>;
4367 <WAKE_TCS 2>, <CONTROL_TCS 0>;
4454 reg = <0 0x17d91000 0 0x1000>,
4455 <0 0x17d92000 0 0x1000>,
4456 <0 0x17d93000 0 0x1000>;
4463 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4470 reg = <0 0x24091000 0 0x1000>;
4479 opp-0 {
4519 reg = <0 0x240b6400 0 0x600>;
4528 opp-0 {
4556 reg = <0 0x24100000 0 0xbb800>;
4563 reg = <0 0x25000000 0 0x200000>,
4564 <0 0x25200000 0 0x200000>,
4565 <0 0x25400000 0 0x200000>,
4566 <0 0x25600000 0 0x200000>,
4567 <0 0x25800000 0 0x200000>,
4568 <0 0x25a00000 0 0x200000>;
4580 reg = <0x0 0x30000000 0x0 0x100>;
4583 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
4597 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>;
4603 qcom,smem-states = <&smp2p_adsp_out 0>;
4624 #size-cells = <0>;
4629 iommus = <&apps_smmu 0x1003 0x80>,
4630 <&apps_smmu 0x1063 0x0>;
4637 iommus = <&apps_smmu 0x1004 0x80>,
4638 <&apps_smmu 0x1064 0x0>;
4645 iommus = <&apps_smmu 0x1005 0x80>,
4646 <&apps_smmu 0x1065 0x0>;
4653 iommus = <&apps_smmu 0x1006 0x80>,
4654 <&apps_smmu 0x1066 0x0>;
4661 iommus = <&apps_smmu 0x1007 0x80>,
4662 <&apps_smmu 0x1067 0x0>;
4673 #size-cells = <0>;
4678 #sound-dai-cells = <0>;
4684 iommus = <&apps_smmu 0x1001 0x80>,
4685 <&apps_smmu 0x1061 0x0>;
4711 reg = <0 0x320c0000 0 0xe080>;
4718 reg = <0x0 0x32300000 0x0 0x1400000>;
4721 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
4736 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
4742 qcom,smem-states = <&smp2p_cdsp_out 0>;
4763 #size-cells = <0>;
4768 iommus = <&apps_smmu 0x1961 0x0>,
4769 <&apps_smmu 0x0c01 0x20>,
4770 <&apps_smmu 0x19c1 0x10>;
4777 iommus = <&apps_smmu 0x1962 0x0>,
4778 <&apps_smmu 0x0c02 0x20>,
4779 <&apps_smmu 0x19c2 0x10>;
4786 iommus = <&apps_smmu 0x1963 0x0>,
4787 <&apps_smmu 0x0c03 0x20>,
4788 <&apps_smmu 0x19c3 0x10>;
4795 iommus = <&apps_smmu 0x1964 0x0>,
4796 <&apps_smmu 0x0c04 0x20>,
4797 <&apps_smmu 0x19c4 0x10>;
4804 iommus = <&apps_smmu 0x1965 0x0>,
4805 <&apps_smmu 0x0c05 0x20>,
4806 <&apps_smmu 0x19c5 0x10>;
4813 iommus = <&apps_smmu 0x1966 0x0>,
4814 <&apps_smmu 0x0c06 0x20>,
4815 <&apps_smmu 0x19c6 0x10>;
4822 iommus = <&apps_smmu 0x1967 0x0>,
4823 <&apps_smmu 0x0c07 0x20>,
4824 <&apps_smmu 0x19c7 0x10>;
4831 iommus = <&apps_smmu 0x1968 0x0>,
4832 <&apps_smmu 0x0c08 0x20>,
4833 <&apps_smmu 0x19c8 0x10>;
4845 thermal-sensors = <&tsens0 0>;
5199 thermal-sensors = <&tsens1 0>;
5617 thermal-sensors = <&tsens2 0>;
5634 gpuss-0-thermal {