Lines Matching +full:sm6350 +full:- +full:dispcc
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/clock/qcom,sm8450-camcc.h>
10 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
11 #include <dt-bindings/clock/qcom,sm8450-gpucc.h>
12 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/interconnect/qcom,icc.h>
21 #include <dt-bindings/interconnect/qcom,sm8450.h>
22 #include <dt-bindings/reset/qcom,sm8450-gpucc.h>
23 #include <dt-bindings/soc/qcom,gpr.h>
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
26 #include <dt-bindings/thermal/thermal.h>
29 interrupt-parent = <&intc>;
31 #address-cells = <2>;
32 #size-cells = <2>;
37 xo_board: xo-board {
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <76800000>;
43 sleep_clk: sleep-clk {
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
46 clock-frequency = <32000>;
51 #address-cells = <2>;
52 #size-cells = <0>;
58 enable-method = "psci";
59 next-level-cache = <&L2_0>;
60 power-domains = <&CPU_PD0>;
61 power-domain-names = "psci";
62 qcom,freq-domain = <&cpufreq_hw 0>;
63 #cooling-cells = <2>;
65 L2_0: l2-cache {
67 cache-level = <2>;
68 cache-unified;
69 next-level-cache = <&L3_0>;
70 L3_0: l3-cache {
72 cache-level = <3>;
73 cache-unified;
82 enable-method = "psci";
83 next-level-cache = <&L2_100>;
84 power-domains = <&CPU_PD1>;
85 power-domain-names = "psci";
86 qcom,freq-domain = <&cpufreq_hw 0>;
87 #cooling-cells = <2>;
89 L2_100: l2-cache {
91 cache-level = <2>;
92 cache-unified;
93 next-level-cache = <&L3_0>;
101 enable-method = "psci";
102 next-level-cache = <&L2_200>;
103 power-domains = <&CPU_PD2>;
104 power-domain-names = "psci";
105 qcom,freq-domain = <&cpufreq_hw 0>;
106 #cooling-cells = <2>;
108 L2_200: l2-cache {
110 cache-level = <2>;
111 cache-unified;
112 next-level-cache = <&L3_0>;
120 enable-method = "psci";
121 next-level-cache = <&L2_300>;
122 power-domains = <&CPU_PD3>;
123 power-domain-names = "psci";
124 qcom,freq-domain = <&cpufreq_hw 0>;
125 #cooling-cells = <2>;
127 L2_300: l2-cache {
129 cache-level = <2>;
130 cache-unified;
131 next-level-cache = <&L3_0>;
139 enable-method = "psci";
140 next-level-cache = <&L2_400>;
141 power-domains = <&CPU_PD4>;
142 power-domain-names = "psci";
143 qcom,freq-domain = <&cpufreq_hw 1>;
144 #cooling-cells = <2>;
146 L2_400: l2-cache {
148 cache-level = <2>;
149 cache-unified;
150 next-level-cache = <&L3_0>;
158 enable-method = "psci";
159 next-level-cache = <&L2_500>;
160 power-domains = <&CPU_PD5>;
161 power-domain-names = "psci";
162 qcom,freq-domain = <&cpufreq_hw 1>;
163 #cooling-cells = <2>;
165 L2_500: l2-cache {
167 cache-level = <2>;
168 cache-unified;
169 next-level-cache = <&L3_0>;
177 enable-method = "psci";
178 next-level-cache = <&L2_600>;
179 power-domains = <&CPU_PD6>;
180 power-domain-names = "psci";
181 qcom,freq-domain = <&cpufreq_hw 1>;
182 #cooling-cells = <2>;
184 L2_600: l2-cache {
186 cache-level = <2>;
187 cache-unified;
188 next-level-cache = <&L3_0>;
196 enable-method = "psci";
197 next-level-cache = <&L2_700>;
198 power-domains = <&CPU_PD7>;
199 power-domain-names = "psci";
200 qcom,freq-domain = <&cpufreq_hw 2>;
201 #cooling-cells = <2>;
203 L2_700: l2-cache {
205 cache-level = <2>;
206 cache-unified;
207 next-level-cache = <&L3_0>;
211 cpu-map {
247 idle-states {
248 entry-method = "psci";
250 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
251 compatible = "arm,idle-state";
252 idle-state-name = "silver-rail-power-collapse";
253 arm,psci-suspend-param = <0x40000004>;
254 entry-latency-us = <800>;
255 exit-latency-us = <750>;
256 min-residency-us = <4090>;
257 local-timer-stop;
260 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
261 compatible = "arm,idle-state";
262 idle-state-name = "gold-rail-power-collapse";
263 arm,psci-suspend-param = <0x40000004>;
264 entry-latency-us = <600>;
265 exit-latency-us = <1550>;
266 min-residency-us = <4791>;
267 local-timer-stop;
271 domain-idle-states {
272 CLUSTER_SLEEP_0: cluster-sleep-0 {
273 compatible = "domain-idle-state";
274 arm,psci-suspend-param = <0x41000044>;
275 entry-latency-us = <1050>;
276 exit-latency-us = <2500>;
277 min-residency-us = <5309>;
280 CLUSTER_SLEEP_1: cluster-sleep-1 {
281 compatible = "domain-idle-state";
282 arm,psci-suspend-param = <0x4100c344>;
283 entry-latency-us = <2700>;
284 exit-latency-us = <3500>;
285 min-residency-us = <13959>;
292 compatible = "qcom,scm-sm8450", "qcom,scm";
293 qcom,dload-mode = <&tcsr 0x13000>;
295 #reset-cells = <1>;
299 clk_virt: interconnect-0 {
300 compatible = "qcom,sm8450-clk-virt";
301 #interconnect-cells = <2>;
302 qcom,bcm-voters = <&apps_bcm_voter>;
305 mc_virt: interconnect-1 {
306 compatible = "qcom,sm8450-mc-virt";
307 #interconnect-cells = <2>;
308 qcom,bcm-voters = <&apps_bcm_voter>;
318 compatible = "arm,armv8-pmuv3";
323 compatible = "arm,psci-1.0";
326 CPU_PD0: power-domain-cpu0 {
327 #power-domain-cells = <0>;
328 power-domains = <&CLUSTER_PD>;
329 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
332 CPU_PD1: power-domain-cpu1 {
333 #power-domain-cells = <0>;
334 power-domains = <&CLUSTER_PD>;
335 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
338 CPU_PD2: power-domain-cpu2 {
339 #power-domain-cells = <0>;
340 power-domains = <&CLUSTER_PD>;
341 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
344 CPU_PD3: power-domain-cpu3 {
345 #power-domain-cells = <0>;
346 power-domains = <&CLUSTER_PD>;
347 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
350 CPU_PD4: power-domain-cpu4 {
351 #power-domain-cells = <0>;
352 power-domains = <&CLUSTER_PD>;
353 domain-idle-states = <&BIG_CPU_SLEEP_0>;
356 CPU_PD5: power-domain-cpu5 {
357 #power-domain-cells = <0>;
358 power-domains = <&CLUSTER_PD>;
359 domain-idle-states = <&BIG_CPU_SLEEP_0>;
362 CPU_PD6: power-domain-cpu6 {
363 #power-domain-cells = <0>;
364 power-domains = <&CLUSTER_PD>;
365 domain-idle-states = <&BIG_CPU_SLEEP_0>;
368 CPU_PD7: power-domain-cpu7 {
369 #power-domain-cells = <0>;
370 power-domains = <&CLUSTER_PD>;
371 domain-idle-states = <&BIG_CPU_SLEEP_0>;
374 CLUSTER_PD: power-domain-cpu-cluster0 {
375 #power-domain-cells = <0>;
376 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
380 qup_opp_table_100mhz: opp-table-qup {
381 compatible = "operating-points-v2";
383 opp-50000000 {
384 opp-hz = /bits/ 64 <50000000>;
385 required-opps = <&rpmhpd_opp_min_svs>;
388 opp-75000000 {
389 opp-hz = /bits/ 64 <75000000>;
390 required-opps = <&rpmhpd_opp_low_svs>;
393 opp-100000000 {
394 opp-hz = /bits/ 64 <100000000>;
395 required-opps = <&rpmhpd_opp_svs>;
399 reserved_memory: reserved-memory {
400 #address-cells = <2>;
401 #size-cells = <2>;
406 no-map;
411 no-map;
416 no-map;
421 no-map;
426 no-map;
430 compatible = "qcom,cmd-db";
432 no-map;
437 no-map;
442 no-map;
447 no-map;
452 no-map;
460 no-map;
465 no-map;
470 no-map;
475 no-map;
480 no-map;
485 no-map;
490 no-map;
495 no-map;
500 no-map;
505 no-map;
510 no-map;
516 no-map;
522 no-map;
527 no-map;
532 no-map;
537 no-map;
541 compatible = "qcom,rmtfs-mem";
543 no-map;
545 qcom,client-id = <1>;
551 no-map;
556 no-map;
565 no-map;
570 no-map;
575 no-map;
580 no-map;
585 no-map;
590 no-map;
595 no-map;
600 no-map;
605 no-map;
610 no-map;
615 no-map;
620 no-map;
625 no-map;
630 no-map;
634 smp2p-adsp {
637 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
643 qcom,local-pid = <0>;
644 qcom,remote-pid = <2>;
646 smp2p_adsp_out: master-kernel {
647 qcom,entry-name = "master-kernel";
648 #qcom,smem-state-cells = <1>;
651 smp2p_adsp_in: slave-kernel {
652 qcom,entry-name = "slave-kernel";
653 interrupt-controller;
654 #interrupt-cells = <2>;
658 smp2p-cdsp {
661 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
667 qcom,local-pid = <0>;
668 qcom,remote-pid = <5>;
670 smp2p_cdsp_out: master-kernel {
671 qcom,entry-name = "master-kernel";
672 #qcom,smem-state-cells = <1>;
675 smp2p_cdsp_in: slave-kernel {
676 qcom,entry-name = "slave-kernel";
677 interrupt-controller;
678 #interrupt-cells = <2>;
682 smp2p-modem {
685 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
691 qcom,local-pid = <0>;
692 qcom,remote-pid = <1>;
694 smp2p_modem_out: master-kernel {
695 qcom,entry-name = "master-kernel";
696 #qcom,smem-state-cells = <1>;
699 smp2p_modem_in: slave-kernel {
700 qcom,entry-name = "slave-kernel";
701 interrupt-controller;
702 #interrupt-cells = <2>;
705 ipa_smp2p_out: ipa-ap-to-modem {
706 qcom,entry-name = "ipa";
707 #qcom,smem-state-cells = <1>;
710 ipa_smp2p_in: ipa-modem-to-ap {
711 qcom,entry-name = "ipa";
712 interrupt-controller;
713 #interrupt-cells = <2>;
717 smp2p-slpi {
720 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
726 qcom,local-pid = <0>;
727 qcom,remote-pid = <3>;
729 smp2p_slpi_out: master-kernel {
730 qcom,entry-name = "master-kernel";
731 #qcom,smem-state-cells = <1>;
734 smp2p_slpi_in: slave-kernel {
735 qcom,entry-name = "slave-kernel";
736 interrupt-controller;
737 #interrupt-cells = <2>;
742 #address-cells = <2>;
743 #size-cells = <2>;
745 dma-ranges = <0 0 0 0 0x10 0>;
746 compatible = "simple-bus";
748 gcc: clock-controller@100000 {
749 compatible = "qcom,gcc-sm8450";
751 #clock-cells = <1>;
752 #reset-cells = <1>;
753 #power-domain-cells = <1>;
763 clock-names = "bi_tcxo",
774 gpi_dma2: dma-controller@800000 {
775 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
776 #dma-cells = <3>;
790 dma-channels = <12>;
791 dma-channel-mask = <0x7e>;
797 compatible = "qcom,geni-se-qup";
799 clock-names = "m-ahb", "s-ahb";
803 #address-cells = <2>;
804 #size-cells = <2>;
809 compatible = "qcom,geni-i2c";
811 clock-names = "se";
813 pinctrl-names = "default";
814 pinctrl-0 = <&qup_i2c15_data_clk>;
816 #address-cells = <1>;
817 #size-cells = <0>;
821 interconnect-names = "qup-core", "qup-config", "qup-memory";
824 dma-names = "tx", "rx";
829 compatible = "qcom,geni-spi";
831 clock-names = "se";
834 pinctrl-names = "default";
835 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
838 interconnect-names = "qup-core", "qup-config";
841 dma-names = "tx", "rx";
842 #address-cells = <1>;
843 #size-cells = <0>;
848 compatible = "qcom,geni-i2c";
850 clock-names = "se";
852 pinctrl-names = "default";
853 pinctrl-0 = <&qup_i2c16_data_clk>;
855 #address-cells = <1>;
856 #size-cells = <0>;
860 interconnect-names = "qup-core", "qup-config", "qup-memory";
863 dma-names = "tx", "rx";
868 compatible = "qcom,geni-spi";
870 clock-names = "se";
873 pinctrl-names = "default";
874 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
877 interconnect-names = "qup-core", "qup-config";
880 dma-names = "tx", "rx";
881 #address-cells = <1>;
882 #size-cells = <0>;
887 compatible = "qcom,geni-i2c";
889 clock-names = "se";
891 pinctrl-names = "default";
892 pinctrl-0 = <&qup_i2c17_data_clk>;
894 #address-cells = <1>;
895 #size-cells = <0>;
899 interconnect-names = "qup-core", "qup-config", "qup-memory";
902 dma-names = "tx", "rx";
907 compatible = "qcom,geni-spi";
909 clock-names = "se";
912 pinctrl-names = "default";
913 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
916 interconnect-names = "qup-core", "qup-config";
919 dma-names = "tx", "rx";
920 #address-cells = <1>;
921 #size-cells = <0>;
926 compatible = "qcom,geni-i2c";
928 clock-names = "se";
930 pinctrl-names = "default";
931 pinctrl-0 = <&qup_i2c18_data_clk>;
933 #address-cells = <1>;
934 #size-cells = <0>;
938 interconnect-names = "qup-core", "qup-config", "qup-memory";
941 dma-names = "tx", "rx";
946 compatible = "qcom,geni-spi";
948 clock-names = "se";
951 pinctrl-names = "default";
952 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
955 interconnect-names = "qup-core", "qup-config";
958 dma-names = "tx", "rx";
959 #address-cells = <1>;
960 #size-cells = <0>;
965 compatible = "qcom,geni-i2c";
967 clock-names = "se";
969 pinctrl-names = "default";
970 pinctrl-0 = <&qup_i2c19_data_clk>;
972 #address-cells = <1>;
973 #size-cells = <0>;
977 interconnect-names = "qup-core", "qup-config", "qup-memory";
980 dma-names = "tx", "rx";
985 compatible = "qcom,geni-spi";
987 clock-names = "se";
990 pinctrl-names = "default";
991 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
994 interconnect-names = "qup-core", "qup-config";
997 dma-names = "tx", "rx";
998 #address-cells = <1>;
999 #size-cells = <0>;
1004 compatible = "qcom,geni-i2c";
1006 clock-names = "se";
1008 pinctrl-names = "default";
1009 pinctrl-0 = <&qup_i2c20_data_clk>;
1011 #address-cells = <1>;
1012 #size-cells = <0>;
1016 interconnect-names = "qup-core", "qup-config", "qup-memory";
1019 dma-names = "tx", "rx";
1024 compatible = "qcom,geni-uart";
1026 clock-names = "se";
1028 pinctrl-names = "default";
1029 pinctrl-0 = <&qup_uart20_default>;
1035 interconnect-names = "qup-core",
1036 "qup-config";
1041 compatible = "qcom,geni-spi";
1043 clock-names = "se";
1046 pinctrl-names = "default";
1047 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1050 interconnect-names = "qup-core", "qup-config";
1053 dma-names = "tx", "rx";
1054 #address-cells = <1>;
1055 #size-cells = <0>;
1060 compatible = "qcom,geni-i2c";
1062 clock-names = "se";
1064 pinctrl-names = "default";
1065 pinctrl-0 = <&qup_i2c21_data_clk>;
1067 #address-cells = <1>;
1068 #size-cells = <0>;
1072 interconnect-names = "qup-core", "qup-config", "qup-memory";
1075 dma-names = "tx", "rx";
1080 compatible = "qcom,geni-spi";
1082 clock-names = "se";
1085 pinctrl-names = "default";
1086 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1089 interconnect-names = "qup-core", "qup-config";
1092 dma-names = "tx", "rx";
1093 #address-cells = <1>;
1094 #size-cells = <0>;
1099 gpi_dma0: dma-controller@900000 {
1100 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1101 #dma-cells = <3>;
1115 dma-channels = <12>;
1116 dma-channel-mask = <0x7e>;
1122 compatible = "qcom,geni-se-qup";
1124 clock-names = "m-ahb", "s-ahb";
1129 interconnect-names = "qup-core";
1130 #address-cells = <2>;
1131 #size-cells = <2>;
1136 compatible = "qcom,geni-i2c";
1138 clock-names = "se";
1140 pinctrl-names = "default";
1141 pinctrl-0 = <&qup_i2c0_data_clk>;
1143 #address-cells = <1>;
1144 #size-cells = <0>;
1148 interconnect-names = "qup-core", "qup-config", "qup-memory";
1151 dma-names = "tx", "rx";
1156 compatible = "qcom,geni-spi";
1158 clock-names = "se";
1161 pinctrl-names = "default";
1162 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1163 power-domains = <&rpmhpd RPMHPD_CX>;
1164 operating-points-v2 = <&qup_opp_table_100mhz>;
1168 interconnect-names = "qup-core", "qup-config", "qup-memory";
1171 dma-names = "tx", "rx";
1172 #address-cells = <1>;
1173 #size-cells = <0>;
1178 compatible = "qcom,geni-i2c";
1180 clock-names = "se";
1182 pinctrl-names = "default";
1183 pinctrl-0 = <&qup_i2c1_data_clk>;
1185 #address-cells = <1>;
1186 #size-cells = <0>;
1190 interconnect-names = "qup-core", "qup-config", "qup-memory";
1193 dma-names = "tx", "rx";
1198 compatible = "qcom,geni-spi";
1200 clock-names = "se";
1203 pinctrl-names = "default";
1204 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1208 interconnect-names = "qup-core", "qup-config", "qup-memory";
1211 dma-names = "tx", "rx";
1212 #address-cells = <1>;
1213 #size-cells = <0>;
1218 compatible = "qcom,geni-i2c";
1220 clock-names = "se";
1222 pinctrl-names = "default";
1223 pinctrl-0 = <&qup_i2c2_data_clk>;
1225 #address-cells = <1>;
1226 #size-cells = <0>;
1230 interconnect-names = "qup-core", "qup-config", "qup-memory";
1233 dma-names = "tx", "rx";
1238 compatible = "qcom,geni-spi";
1240 clock-names = "se";
1243 pinctrl-names = "default";
1244 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1248 interconnect-names = "qup-core", "qup-config", "qup-memory";
1251 dma-names = "tx", "rx";
1252 #address-cells = <1>;
1253 #size-cells = <0>;
1259 compatible = "qcom,geni-i2c";
1261 clock-names = "se";
1263 pinctrl-names = "default";
1264 pinctrl-0 = <&qup_i2c3_data_clk>;
1266 #address-cells = <1>;
1267 #size-cells = <0>;
1271 interconnect-names = "qup-core", "qup-config", "qup-memory";
1274 dma-names = "tx", "rx";
1279 compatible = "qcom,geni-spi";
1281 clock-names = "se";
1284 pinctrl-names = "default";
1285 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1289 interconnect-names = "qup-core", "qup-config", "qup-memory";
1292 dma-names = "tx", "rx";
1293 #address-cells = <1>;
1294 #size-cells = <0>;
1299 compatible = "qcom,geni-i2c";
1301 clock-names = "se";
1303 pinctrl-names = "default";
1304 pinctrl-0 = <&qup_i2c4_data_clk>;
1306 #address-cells = <1>;
1307 #size-cells = <0>;
1311 interconnect-names = "qup-core", "qup-config", "qup-memory";
1314 dma-names = "tx", "rx";
1319 compatible = "qcom,geni-spi";
1321 clock-names = "se";
1324 pinctrl-names = "default";
1325 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1326 power-domains = <&rpmhpd RPMHPD_CX>;
1327 operating-points-v2 = <&qup_opp_table_100mhz>;
1331 interconnect-names = "qup-core", "qup-config", "qup-memory";
1334 dma-names = "tx", "rx";
1335 #address-cells = <1>;
1336 #size-cells = <0>;
1341 compatible = "qcom,geni-i2c";
1343 clock-names = "se";
1345 pinctrl-names = "default";
1346 pinctrl-0 = <&qup_i2c5_data_clk>;
1348 #address-cells = <1>;
1349 #size-cells = <0>;
1353 interconnect-names = "qup-core", "qup-config", "qup-memory";
1356 dma-names = "tx", "rx";
1361 compatible = "qcom,geni-spi";
1363 clock-names = "se";
1366 pinctrl-names = "default";
1367 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1371 interconnect-names = "qup-core", "qup-config", "qup-memory";
1374 dma-names = "tx", "rx";
1375 #address-cells = <1>;
1376 #size-cells = <0>;
1382 compatible = "qcom,geni-i2c";
1384 clock-names = "se";
1386 pinctrl-names = "default";
1387 pinctrl-0 = <&qup_i2c6_data_clk>;
1389 #address-cells = <1>;
1390 #size-cells = <0>;
1394 interconnect-names = "qup-core", "qup-config", "qup-memory";
1397 dma-names = "tx", "rx";
1402 compatible = "qcom,geni-spi";
1404 clock-names = "se";
1407 pinctrl-names = "default";
1408 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1412 interconnect-names = "qup-core", "qup-config", "qup-memory";
1415 dma-names = "tx", "rx";
1416 #address-cells = <1>;
1417 #size-cells = <0>;
1422 compatible = "qcom,geni-debug-uart";
1424 clock-names = "se";
1426 pinctrl-names = "default";
1427 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1433 interconnect-names = "qup-core",
1434 "qup-config";
1439 gpi_dma1: dma-controller@a00000 {
1440 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1441 #dma-cells = <3>;
1455 dma-channels = <12>;
1456 dma-channel-mask = <0x7e>;
1462 compatible = "qcom,geni-se-qup";
1464 clock-names = "m-ahb", "s-ahb";
1469 interconnect-names = "qup-core";
1470 #address-cells = <2>;
1471 #size-cells = <2>;
1476 compatible = "qcom,geni-i2c";
1478 clock-names = "se";
1480 pinctrl-names = "default";
1481 pinctrl-0 = <&qup_i2c8_data_clk>;
1483 #address-cells = <1>;
1484 #size-cells = <0>;
1488 interconnect-names = "qup-core", "qup-config", "qup-memory";
1491 dma-names = "tx", "rx";
1496 compatible = "qcom,geni-spi";
1498 clock-names = "se";
1501 pinctrl-names = "default";
1502 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1506 interconnect-names = "qup-core", "qup-config", "qup-memory";
1509 dma-names = "tx", "rx";
1510 #address-cells = <1>;
1511 #size-cells = <0>;
1516 compatible = "qcom,geni-i2c";
1518 clock-names = "se";
1520 pinctrl-names = "default";
1521 pinctrl-0 = <&qup_i2c9_data_clk>;
1523 #address-cells = <1>;
1524 #size-cells = <0>;
1528 interconnect-names = "qup-core", "qup-config", "qup-memory";
1531 dma-names = "tx", "rx";
1536 compatible = "qcom,geni-spi";
1538 clock-names = "se";
1541 pinctrl-names = "default";
1542 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1546 interconnect-names = "qup-core", "qup-config", "qup-memory";
1549 dma-names = "tx", "rx";
1550 #address-cells = <1>;
1551 #size-cells = <0>;
1556 compatible = "qcom,geni-i2c";
1558 clock-names = "se";
1560 pinctrl-names = "default";
1561 pinctrl-0 = <&qup_i2c10_data_clk>;
1563 #address-cells = <1>;
1564 #size-cells = <0>;
1568 interconnect-names = "qup-core", "qup-config", "qup-memory";
1571 dma-names = "tx", "rx";
1576 compatible = "qcom,geni-spi";
1578 clock-names = "se";
1581 pinctrl-names = "default";
1582 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1586 interconnect-names = "qup-core", "qup-config", "qup-memory";
1589 dma-names = "tx", "rx";
1590 #address-cells = <1>;
1591 #size-cells = <0>;
1596 compatible = "qcom,geni-i2c";
1598 clock-names = "se";
1600 pinctrl-names = "default";
1601 pinctrl-0 = <&qup_i2c11_data_clk>;
1603 #address-cells = <1>;
1604 #size-cells = <0>;
1608 interconnect-names = "qup-core", "qup-config", "qup-memory";
1611 dma-names = "tx", "rx";
1616 compatible = "qcom,geni-spi";
1618 clock-names = "se";
1621 pinctrl-names = "default";
1622 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1626 interconnect-names = "qup-core", "qup-config", "qup-memory";
1629 dma-names = "tx", "rx";
1630 #address-cells = <1>;
1631 #size-cells = <0>;
1636 compatible = "qcom,geni-i2c";
1638 clock-names = "se";
1640 pinctrl-names = "default";
1641 pinctrl-0 = <&qup_i2c12_data_clk>;
1643 #address-cells = <1>;
1644 #size-cells = <0>;
1648 interconnect-names = "qup-core", "qup-config", "qup-memory";
1651 dma-names = "tx", "rx";
1656 compatible = "qcom,geni-spi";
1658 clock-names = "se";
1661 pinctrl-names = "default";
1662 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1666 interconnect-names = "qup-core", "qup-config", "qup-memory";
1669 dma-names = "tx", "rx";
1670 #address-cells = <1>;
1671 #size-cells = <0>;
1676 compatible = "qcom,geni-i2c";
1678 clock-names = "se";
1680 pinctrl-names = "default";
1681 pinctrl-0 = <&qup_i2c13_data_clk>;
1686 interconnect-names = "qup-core", "qup-config", "qup-memory";
1689 dma-names = "tx", "rx";
1690 #address-cells = <1>;
1691 #size-cells = <0>;
1696 compatible = "qcom,geni-spi";
1698 clock-names = "se";
1701 pinctrl-names = "default";
1702 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1706 interconnect-names = "qup-core", "qup-config", "qup-memory";
1709 dma-names = "tx", "rx";
1710 #address-cells = <1>;
1711 #size-cells = <0>;
1716 compatible = "qcom,geni-i2c";
1718 clock-names = "se";
1720 pinctrl-names = "default";
1721 pinctrl-0 = <&qup_i2c14_data_clk>;
1726 interconnect-names = "qup-core", "qup-config", "qup-memory";
1729 dma-names = "tx", "rx";
1730 #address-cells = <1>;
1731 #size-cells = <0>;
1736 compatible = "qcom,geni-spi";
1738 clock-names = "se";
1741 pinctrl-names = "default";
1742 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1746 interconnect-names = "qup-core", "qup-config", "qup-memory";
1749 dma-names = "tx", "rx";
1750 #address-cells = <1>;
1751 #size-cells = <0>;
1757 compatible = "qcom,sm8450-trng", "qcom,trng";
1762 compatible = "qcom,pcie-sm8450-pcie0";
1768 reg-names = "parf", "dbi", "elbi", "atu", "config";
1770 linux,pci-domain = <0>;
1771 bus-range = <0x00 0xff>;
1772 num-lanes = <1>;
1774 #address-cells = <3>;
1775 #size-cells = <2>;
1780 msi-map = <0x0 &gic_its 0x5980 0x1>,
1782 msi-map-mask = <0xff00>;
1791 interrupt-names = "msi0",
1799 #interrupt-cells = <1>;
1800 interrupt-map-mask = <0 0 0 0x7>;
1801 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1810 interconnect-names = "pcie-mem", "cpu-pcie";
1824 clock-names = "pipe",
1837 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1841 reset-names = "pci";
1843 power-domains = <&gcc PCIE_0_GDSC>;
1846 phy-names = "pciephy";
1848 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
1849 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
1851 pinctrl-names = "default";
1852 pinctrl-0 = <&pcie0_default_state>;
1854 operating-points-v2 = <&pcie0_opp_table>;
1858 pcie0_opp_table: opp-table {
1859 compatible = "operating-points-v2";
1862 opp-2500000 {
1863 opp-hz = /bits/ 64 <2500000>;
1864 required-opps = <&rpmhpd_opp_low_svs>;
1865 opp-peak-kBps = <250000 1>;
1869 opp-5000000 {
1870 opp-hz = /bits/ 64 <5000000>;
1871 required-opps = <&rpmhpd_opp_low_svs>;
1872 opp-peak-kBps = <500000 1>;
1876 opp-8000000 {
1877 opp-hz = /bits/ 64 <8000000>;
1878 required-opps = <&rpmhpd_opp_nom>;
1879 opp-peak-kBps = <984500 1>;
1886 bus-range = <0x01 0xff>;
1888 #address-cells = <3>;
1889 #size-cells = <2>;
1895 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
1903 clock-names = "aux",
1909 clock-output-names = "pcie_0_pipe_clk";
1910 #clock-cells = <0>;
1912 #phy-cells = <0>;
1915 reset-names = "phy";
1917 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1918 assigned-clock-rates = <100000000>;
1924 compatible = "qcom,pcie-sm8450-pcie1";
1930 reg-names = "parf", "dbi", "elbi", "atu", "config";
1932 linux,pci-domain = <1>;
1933 bus-range = <0x00 0xff>;
1934 num-lanes = <2>;
1936 #address-cells = <3>;
1937 #size-cells = <2>;
1942 msi-map = <0x0 &gic_its 0x5a00 0x1>,
1944 msi-map-mask = <0xff00>;
1953 interrupt-names = "msi0",
1961 #interrupt-cells = <1>;
1962 interrupt-map-mask = <0 0 0 0x7>;
1963 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1972 interconnect-names = "pcie-mem", "cpu-pcie";
1985 clock-names = "pipe",
1997 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2001 reset-names = "pci";
2003 power-domains = <&gcc PCIE_1_GDSC>;
2006 phy-names = "pciephy";
2008 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
2009 wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
2011 pinctrl-names = "default";
2012 pinctrl-0 = <&pcie1_default_state>;
2014 operating-points-v2 = <&pcie1_opp_table>;
2018 pcie1_opp_table: opp-table {
2019 compatible = "operating-points-v2";
2022 opp-2500000 {
2023 opp-hz = /bits/ 64 <2500000>;
2024 required-opps = <&rpmhpd_opp_low_svs>;
2025 opp-peak-kBps = <250000 1>;
2029 opp-5000000 {
2030 opp-hz = /bits/ 64 <5000000>;
2031 required-opps = <&rpmhpd_opp_low_svs>;
2032 opp-peak-kBps = <500000 1>;
2036 opp-10000000 {
2037 opp-hz = /bits/ 64 <10000000>;
2038 required-opps = <&rpmhpd_opp_low_svs>;
2039 opp-peak-kBps = <1000000 1>;
2043 opp-8000000 {
2044 opp-hz = /bits/ 64 <8000000>;
2045 required-opps = <&rpmhpd_opp_nom>;
2046 opp-peak-kBps = <984500 1>;
2050 opp-16000000 {
2051 opp-hz = /bits/ 64 <16000000>;
2052 required-opps = <&rpmhpd_opp_nom>;
2053 opp-peak-kBps = <1969000 1>;
2057 opp-32000000 {
2058 opp-hz = /bits/ 64 <32000000>;
2059 required-opps = <&rpmhpd_opp_nom>;
2060 opp-peak-kBps = <3938000 1>;
2067 bus-range = <0x01 0xff>;
2069 #address-cells = <3>;
2070 #size-cells = <2>;
2076 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
2084 clock-names = "aux",
2090 clock-output-names = "pcie_1_pipe_clk";
2091 #clock-cells = <1>;
2093 #phy-cells = <0>;
2096 reset-names = "phy";
2098 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2099 assigned-clock-rates = <100000000>;
2105 compatible = "qcom,sm8450-config-noc";
2107 #interconnect-cells = <2>;
2108 qcom,bcm-voters = <&apps_bcm_voter>;
2112 compatible = "qcom,sm8450-system-noc";
2114 #interconnect-cells = <2>;
2115 qcom,bcm-voters = <&apps_bcm_voter>;
2119 compatible = "qcom,sm8450-pcie-anoc";
2121 #interconnect-cells = <2>;
2122 qcom,bcm-voters = <&apps_bcm_voter>;
2126 compatible = "qcom,sm8450-aggre1-noc";
2128 #interconnect-cells = <2>;
2131 qcom,bcm-voters = <&apps_bcm_voter>;
2135 compatible = "qcom,sm8450-aggre2-noc";
2137 #interconnect-cells = <2>;
2138 qcom,bcm-voters = <&apps_bcm_voter>;
2146 compatible = "qcom,sm8450-mmss-noc";
2148 #interconnect-cells = <2>;
2149 qcom,bcm-voters = <&apps_bcm_voter>;
2153 compatible = "qcom,tcsr-mutex";
2155 #hwlock-cells = <1>;
2159 compatible = "qcom,sm8450-tcsr", "syscon";
2164 compatible = "qcom,adreno-730.1", "qcom,adreno";
2168 reg-names = "kgsl_3d0_reg_memory",
2177 operating-points-v2 = <&gpu_opp_table>;
2180 #cooling-cells = <2>;
2184 zap-shader {
2185 memory-region = <&gpu_micro_code_mem>;
2188 gpu_opp_table: opp-table {
2189 compatible = "operating-points-v2";
2191 opp-818000000 {
2192 opp-hz = /bits/ 64 <818000000>;
2193 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2196 opp-791000000 {
2197 opp-hz = /bits/ 64 <791000000>;
2198 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2201 opp-734000000 {
2202 opp-hz = /bits/ 64 <734000000>;
2203 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2206 opp-640000000 {
2207 opp-hz = /bits/ 64 <640000000>;
2208 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2211 opp-599000000 {
2212 opp-hz = /bits/ 64 <599000000>;
2213 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2216 opp-545000000 {
2217 opp-hz = /bits/ 64 <545000000>;
2218 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2221 opp-492000000 {
2222 opp-hz = /bits/ 64 <492000000>;
2223 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2226 opp-421000000 {
2227 opp-hz = /bits/ 64 <421000000>;
2228 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
2231 opp-350000000 {
2232 opp-hz = /bits/ 64 <350000000>;
2233 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2236 opp-317000000 {
2237 opp-hz = /bits/ 64 <317000000>;
2238 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2241 opp-285000000 {
2242 opp-hz = /bits/ 64 <285000000>;
2243 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2246 opp-220000000 {
2247 opp-hz = /bits/ 64 <220000000>;
2248 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2254 compatible = "qcom,adreno-gmu-730.1", "qcom,adreno-gmu";
2258 reg-names = "gmu", "rscc", "gmu_pdc";
2262 interrupt-names = "hfi", "gmu";
2271 clock-names = "ahb",
2279 power-domains = <&gpucc GPU_CX_GDSC>,
2281 power-domain-names = "cx",
2288 operating-points-v2 = <&gmu_opp_table>;
2290 gmu_opp_table: opp-table {
2291 compatible = "operating-points-v2";
2293 opp-500000000 {
2294 opp-hz = /bits/ 64 <500000000>;
2295 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2298 opp-200000000 {
2299 opp-hz = /bits/ 64 <200000000>;
2300 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2305 gpucc: clock-controller@3d90000 {
2306 compatible = "qcom,sm8450-gpucc";
2311 #clock-cells = <1>;
2312 #reset-cells = <1>;
2313 #power-domain-cells = <1>;
2317 compatible = "qcom,sm8450-smmu-500", "qcom,adreno-smmu",
2318 "qcom,smmu-500", "arm,mmu-500";
2320 #iommu-cells = <2>;
2321 #global-interrupts = <1>;
2354 clock-names = "gmu",
2360 power-domains = <&gpucc GPU_CX_GDSC>;
2361 dma-coherent;
2365 compatible = "qcom,sm8450-usb-hs-phy",
2366 "qcom,usb-snps-hs-7nm-phy";
2369 #phy-cells = <0>;
2372 clock-names = "ref";
2378 compatible = "qcom,sm8450-qmp-usb3-dp-phy";
2385 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2389 reset-names = "phy", "common";
2391 #clock-cells = <1>;
2392 #phy-cells = <1>;
2394 orientation-switch;
2399 #address-cells = <1>;
2400 #size-cells = <0>;
2413 remote-endpoint = <&usb_1_dwc3_ss>;
2421 remote-endpoint = <&mdss_dp0_out>;
2428 compatible = "qcom,sm8450-slpi-pas";
2431 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2436 interrupt-names = "wdog", "fatal", "ready",
2437 "handover", "stop-ack";
2440 clock-names = "xo";
2442 power-domains = <&rpmhpd RPMHPD_LCX>,
2444 power-domain-names = "lcx", "lmx";
2446 memory-region = <&slpi_mem>;
2450 qcom,smem-states = <&smp2p_slpi_out 0>;
2451 qcom,smem-state-names = "stop";
2455 glink-edge {
2456 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2463 qcom,remote-pid = <3>;
2467 qcom,glink-channels = "fastrpcglink-apps-dsp";
2469 qcom,non-secure-domain;
2470 #address-cells = <1>;
2471 #size-cells = <0>;
2473 compute-cb@1 {
2474 compatible = "qcom,fastrpc-compute-cb";
2479 compute-cb@2 {
2480 compatible = "qcom,fastrpc-compute-cb";
2485 compute-cb@3 {
2486 compatible = "qcom,fastrpc-compute-cb";
2489 /* note: shared-cb = <4> in downstream */
2496 compatible = "qcom,sm8450-lpass-wsa-macro";
2503 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2505 #clock-cells = <0>;
2506 clock-output-names = "wsa2-mclk";
2507 #sound-dai-cells = <1>;
2511 compatible = "qcom,soundwire-v1.7.0";
2515 clock-names = "iface";
2518 pinctrl-0 = <&wsa2_swr_active>;
2519 pinctrl-names = "default";
2521 qcom,din-ports = <2>;
2522 qcom,dout-ports = <6>;
2524 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2525 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2526 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2527 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2528 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2529 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2530 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2531 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2532 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2534 #address-cells = <2>;
2535 #size-cells = <0>;
2536 #sound-dai-cells = <1>;
2541 compatible = "qcom,sm8450-lpass-rx-macro";
2548 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2550 #clock-cells = <0>;
2551 clock-output-names = "mclk";
2552 #sound-dai-cells = <1>;
2556 compatible = "qcom,soundwire-v1.7.0";
2560 clock-names = "iface";
2562 qcom,din-ports = <0>;
2563 qcom,dout-ports = <5>;
2565 pinctrl-0 = <&rx_swr_active>;
2566 pinctrl-names = "default";
2568 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2569 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2570 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2571 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2572 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2573 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2574 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2575 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2576 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2578 #address-cells = <2>;
2579 #size-cells = <0>;
2580 #sound-dai-cells = <1>;
2585 compatible = "qcom,sm8450-lpass-tx-macro";
2592 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2594 #clock-cells = <0>;
2595 clock-output-names = "mclk";
2596 #sound-dai-cells = <1>;
2600 compatible = "qcom,sm8450-lpass-wsa-macro";
2607 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2609 #clock-cells = <0>;
2610 clock-output-names = "mclk";
2611 #sound-dai-cells = <1>;
2615 compatible = "qcom,soundwire-v1.7.0";
2619 clock-names = "iface";
2622 pinctrl-0 = <&wsa_swr_active>;
2623 pinctrl-names = "default";
2625 qcom,din-ports = <2>;
2626 qcom,dout-ports = <6>;
2628 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2629 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2630 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2631 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2632 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2633 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2634 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2635 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2636 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2638 #address-cells = <2>;
2639 #size-cells = <0>;
2640 #sound-dai-cells = <1>;
2645 compatible = "qcom,soundwire-v1.7.0";
2649 interrupt-names = "core", "wakeup";
2652 clock-names = "iface";
2655 pinctrl-0 = <&tx_swr_active>;
2656 pinctrl-names = "default";
2658 qcom,din-ports = <4>;
2659 qcom,dout-ports = <0>;
2660 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2661 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2662 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2663 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2664 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2665 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2666 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2667 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2668 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2670 #address-cells = <2>;
2671 #size-cells = <0>;
2672 #sound-dai-cells = <1>;
2677 compatible = "qcom,sm8450-lpass-va-macro";
2683 clock-names = "mclk", "macro", "dcodec", "npl";
2685 #clock-cells = <0>;
2686 clock-output-names = "fsgen";
2687 #sound-dai-cells = <1>;
2692 compatible = "qcom,sm8450-adsp-pas";
2695 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2700 interrupt-names = "wdog", "fatal", "ready",
2701 "handover", "stop-ack";
2704 clock-names = "xo";
2706 power-domains = <&rpmhpd RPMHPD_LCX>,
2708 power-domain-names = "lcx", "lmx";
2710 memory-region = <&adsp_mem>;
2714 qcom,smem-states = <&smp2p_adsp_out 0>;
2715 qcom,smem-state-names = "stop";
2719 remoteproc_adsp_glink: glink-edge {
2720 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2727 qcom,remote-pid = <2>;
2731 qcom,glink-channels = "adsp_apps";
2734 #address-cells = <1>;
2735 #size-cells = <0>;
2740 #sound-dai-cells = <0>;
2741 qcom,protection-domain = "avs/audio",
2745 compatible = "qcom,q6apm-dais";
2750 compatible = "qcom,q6apm-lpass-dais";
2751 #sound-dai-cells = <1>;
2758 qcom,protection-domain = "avs/audio",
2761 q6prmcc: clock-controller {
2762 compatible = "qcom,q6prm-lpass-clocks";
2763 #clock-cells = <2>;
2770 qcom,glink-channels = "fastrpcglink-apps-dsp";
2772 qcom,non-secure-domain;
2773 #address-cells = <1>;
2774 #size-cells = <0>;
2776 compute-cb@3 {
2777 compatible = "qcom,fastrpc-compute-cb";
2782 compute-cb@4 {
2783 compatible = "qcom,fastrpc-compute-cb";
2788 compute-cb@5 {
2789 compatible = "qcom,fastrpc-compute-cb";
2798 compatible = "qcom,sm8450-cdsp-pas";
2801 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2806 interrupt-names = "wdog", "fatal", "ready",
2807 "handover", "stop-ack";
2810 clock-names = "xo";
2812 power-domains = <&rpmhpd RPMHPD_CX>,
2814 power-domain-names = "cx", "mxc";
2816 memory-region = <&cdsp_mem>;
2820 qcom,smem-states = <&smp2p_cdsp_out 0>;
2821 qcom,smem-state-names = "stop";
2825 glink-edge {
2826 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2833 qcom,remote-pid = <5>;
2837 qcom,glink-channels = "fastrpcglink-apps-dsp";
2839 qcom,non-secure-domain;
2840 #address-cells = <1>;
2841 #size-cells = <0>;
2843 compute-cb@1 {
2844 compatible = "qcom,fastrpc-compute-cb";
2850 compute-cb@2 {
2851 compatible = "qcom,fastrpc-compute-cb";
2857 compute-cb@3 {
2858 compatible = "qcom,fastrpc-compute-cb";
2864 compute-cb@4 {
2865 compatible = "qcom,fastrpc-compute-cb";
2871 compute-cb@5 {
2872 compatible = "qcom,fastrpc-compute-cb";
2878 compute-cb@6 {
2879 compatible = "qcom,fastrpc-compute-cb";
2885 compute-cb@7 {
2886 compatible = "qcom,fastrpc-compute-cb";
2892 compute-cb@8 {
2893 compatible = "qcom,fastrpc-compute-cb";
2905 compatible = "qcom,sm8450-mpss-pas";
2908 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2914 interrupt-names = "wdog", "fatal", "ready", "handover",
2915 "stop-ack", "shutdown-ack";
2918 clock-names = "xo";
2920 power-domains = <&rpmhpd RPMHPD_CX>,
2922 power-domain-names = "cx", "mss";
2924 memory-region = <&mpss_mem>;
2928 qcom,smem-states = <&smp2p_modem_out 0>;
2929 qcom,smem-state-names = "stop";
2933 glink-edge {
2934 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2940 qcom,remote-pid = <1>;
2944 videocc: clock-controller@aaf0000 {
2945 compatible = "qcom,sm8450-videocc";
2949 power-domains = <&rpmhpd RPMHPD_MMCX>;
2950 required-opps = <&rpmhpd_opp_low_svs>;
2951 #clock-cells = <1>;
2952 #reset-cells = <1>;
2953 #power-domain-cells = <1>;
2957 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2960 power-domains = <&camcc TITAN_TOP_GDSC>;
2967 clock-names = "camnoc_axi",
2972 pinctrl-0 = <&cci0_default &cci1_default>;
2973 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
2974 pinctrl-names = "default", "sleep";
2977 #address-cells = <1>;
2978 #size-cells = <0>;
2980 cci0_i2c0: i2c-bus@0 {
2982 clock-frequency = <1000000>;
2983 #address-cells = <1>;
2984 #size-cells = <0>;
2987 cci0_i2c1: i2c-bus@1 {
2989 clock-frequency = <1000000>;
2990 #address-cells = <1>;
2991 #size-cells = <0>;
2996 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2999 power-domains = <&camcc TITAN_TOP_GDSC>;
3006 clock-names = "camnoc_axi",
3011 pinctrl-0 = <&cci2_default &cci3_default>;
3012 pinctrl-1 = <&cci2_sleep &cci3_sleep>;
3013 pinctrl-names = "default", "sleep";
3016 #address-cells = <1>;
3017 #size-cells = <0>;
3019 cci1_i2c0: i2c-bus@0 {
3021 clock-frequency = <1000000>;
3022 #address-cells = <1>;
3023 #size-cells = <0>;
3026 cci1_i2c1: i2c-bus@1 {
3028 clock-frequency = <1000000>;
3029 #address-cells = <1>;
3030 #size-cells = <0>;
3034 camcc: clock-controller@ade0000 {
3035 compatible = "qcom,sm8450-camcc";
3041 power-domains = <&rpmhpd RPMHPD_MMCX>;
3042 required-opps = <&rpmhpd_opp_low_svs>;
3043 #clock-cells = <1>;
3044 #reset-cells = <1>;
3045 #power-domain-cells = <1>;
3049 mdss: display-subsystem@ae00000 {
3050 compatible = "qcom,sm8450-mdss";
3052 reg-names = "mdss";
3059 interconnect-names = "mdp0-mem",
3060 "mdp1-mem",
3061 "cpu-cfg";
3063 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
3065 power-domains = <&dispcc MDSS_GDSC>;
3067 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3070 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3073 interrupt-controller;
3074 #interrupt-cells = <1>;
3078 #address-cells = <2>;
3079 #size-cells = <2>;
3084 mdss_mdp: display-controller@ae01000 {
3085 compatible = "qcom,sm8450-dpu";
3088 reg-names = "mdp", "vbif";
3092 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3093 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
3094 <&dispcc DISP_CC_MDSS_MDP_CLK>,
3095 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3096 clock-names = "bus",
3103 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3104 assigned-clock-rates = <19200000>;
3106 operating-points-v2 = <&mdp_opp_table>;
3107 power-domains = <&rpmhpd RPMHPD_MMCX>;
3109 interrupt-parent = <&mdss>;
3113 #address-cells = <1>;
3114 #size-cells = <0>;
3119 remote-endpoint = <&mdss_dsi0_in>;
3126 remote-endpoint = <&mdss_dsi1_in>;
3133 remote-endpoint = <&mdss_dp0_in>;
3138 mdp_opp_table: opp-table {
3139 compatible = "operating-points-v2";
3141 opp-172000000 {
3142 opp-hz = /bits/ 64 <172000000>;
3143 required-opps = <&rpmhpd_opp_low_svs_d1>;
3146 opp-200000000 {
3147 opp-hz = /bits/ 64 <200000000>;
3148 required-opps = <&rpmhpd_opp_low_svs>;
3151 opp-325000000 {
3152 opp-hz = /bits/ 64 <325000000>;
3153 required-opps = <&rpmhpd_opp_svs>;
3156 opp-375000000 {
3157 opp-hz = /bits/ 64 <375000000>;
3158 required-opps = <&rpmhpd_opp_svs_l1>;
3161 opp-500000000 {
3162 opp-hz = /bits/ 64 <500000000>;
3163 required-opps = <&rpmhpd_opp_nom>;
3168 mdss_dp0: displayport-controller@ae90000 {
3169 compatible = "qcom,sm8450-dp", "qcom,sm8350-dp";
3175 interrupt-parent = <&mdss>;
3177 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3178 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
3179 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
3180 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
3181 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
3182 clock-names = "core_iface",
3188 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
3189 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
3190 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3194 phy-names = "dp";
3196 #sound-dai-cells = <0>;
3198 operating-points-v2 = <&dp_opp_table>;
3199 power-domains = <&rpmhpd RPMHPD_MMCX>;
3204 #address-cells = <1>;
3205 #size-cells = <0>;
3210 remote-endpoint = <&dpu_intf0_out>;
3218 remote-endpoint = <&usb_1_qmpphy_dp_in>;
3223 dp_opp_table: opp-table {
3224 compatible = "operating-points-v2";
3226 opp-160000000 {
3227 opp-hz = /bits/ 64 <160000000>;
3228 required-opps = <&rpmhpd_opp_low_svs>;
3231 opp-270000000 {
3232 opp-hz = /bits/ 64 <270000000>;
3233 required-opps = <&rpmhpd_opp_svs>;
3236 opp-540000000 {
3237 opp-hz = /bits/ 64 <540000000>;
3238 required-opps = <&rpmhpd_opp_svs_l1>;
3241 opp-810000000 {
3242 opp-hz = /bits/ 64 <810000000>;
3243 required-opps = <&rpmhpd_opp_nom>;
3249 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3251 reg-names = "dsi_ctrl";
3253 interrupt-parent = <&mdss>;
3256 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3257 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3258 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3259 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3260 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3262 clock-names = "byte",
3269 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3270 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3272 operating-points-v2 = <&mdss_dsi_opp_table>;
3273 power-domains = <&rpmhpd RPMHPD_MMCX>;
3276 phy-names = "dsi";
3278 #address-cells = <1>;
3279 #size-cells = <0>;
3284 #address-cells = <1>;
3285 #size-cells = <0>;
3290 remote-endpoint = <&dpu_intf1_out>;
3301 mdss_dsi_opp_table: opp-table {
3302 compatible = "operating-points-v2";
3304 opp-187500000 {
3305 opp-hz = /bits/ 64 <187500000>;
3306 required-opps = <&rpmhpd_opp_low_svs>;
3309 opp-300000000 {
3310 opp-hz = /bits/ 64 <300000000>;
3311 required-opps = <&rpmhpd_opp_svs>;
3314 opp-358000000 {
3315 opp-hz = /bits/ 64 <358000000>;
3316 required-opps = <&rpmhpd_opp_svs_l1>;
3322 compatible = "qcom,sm8450-dsi-phy-5nm";
3326 reg-names = "dsi_phy",
3330 #clock-cells = <1>;
3331 #phy-cells = <0>;
3333 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3335 clock-names = "iface", "ref";
3341 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3343 reg-names = "dsi_ctrl";
3345 interrupt-parent = <&mdss>;
3348 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
3349 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
3350 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
3351 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
3352 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3354 clock-names = "byte",
3361 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
3362 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
3364 operating-points-v2 = <&mdss_dsi_opp_table>;
3365 power-domains = <&rpmhpd RPMHPD_MMCX>;
3368 phy-names = "dsi";
3370 #address-cells = <1>;
3371 #size-cells = <0>;
3376 #address-cells = <1>;
3377 #size-cells = <0>;
3382 remote-endpoint = <&dpu_intf2_out>;
3395 compatible = "qcom,sm8450-dsi-phy-5nm";
3399 reg-names = "dsi_phy",
3403 #clock-cells = <1>;
3404 #phy-cells = <0>;
3406 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3408 clock-names = "iface", "ref";
3414 dispcc: clock-controller@af00000 { label
3415 compatible = "qcom,sm8450-dispcc";
3433 power-domains = <&rpmhpd RPMHPD_MMCX>;
3434 required-opps = <&rpmhpd_opp_low_svs>;
3435 #clock-cells = <1>;
3436 #reset-cells = <1>;
3437 #power-domain-cells = <1>;
3441 pdc: interrupt-controller@b220000 {
3442 compatible = "qcom,sm8450-pdc", "qcom,pdc";
3444 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
3446 #interrupt-cells = <2>;
3447 interrupt-parent = <&intc>;
3448 interrupt-controller;
3451 tsens0: thermal-sensor@c263000 {
3452 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3458 interrupt-names = "uplow", "critical";
3459 #thermal-sensor-cells = <1>;
3462 tsens1: thermal-sensor@c265000 {
3463 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3469 interrupt-names = "uplow", "critical";
3470 #thermal-sensor-cells = <1>;
3473 aoss_qmp: power-management@c300000 {
3474 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
3476 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3480 #clock-cells = <0>;
3484 compatible = "qcom,rpmh-stats";
3489 compatible = "qcom,spmi-pmic-arb";
3495 reg-names = "core",
3500 interrupt-names = "periph_irq";
3501 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3504 interrupt-controller;
3505 #interrupt-cells = <4>;
3506 #address-cells = <2>;
3507 #size-cells = <0>;
3511 compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
3514 interrupt-controller;
3515 #interrupt-cells = <3>;
3516 #mbox-cells = <2>;
3520 compatible = "qcom,sm8450-tlmm";
3523 gpio-controller;
3524 #gpio-cells = <2>;
3525 interrupt-controller;
3526 #interrupt-cells = <2>;
3527 gpio-ranges = <&tlmm 0 0 211>;
3528 wakeup-parent = <&pdc>;
3530 sdc2_default_state: sdc2-default-state {
3531 clk-pins {
3533 drive-strength = <16>;
3534 bias-disable;
3537 cmd-pins {
3539 drive-strength = <16>;
3540 bias-pull-up;
3543 data-pins {
3545 drive-strength = <16>;
3546 bias-pull-up;
3550 sdc2_sleep_state: sdc2-sleep-state {
3551 clk-pins {
3553 drive-strength = <2>;
3554 bias-disable;
3557 cmd-pins {
3559 drive-strength = <2>;
3560 bias-pull-up;
3563 data-pins {
3565 drive-strength = <2>;
3566 bias-pull-up;
3570 cci0_default: cci0-default-state {
3574 drive-strength = <2>;
3575 bias-pull-up;
3578 cci0_sleep: cci0-sleep-state {
3582 drive-strength = <2>;
3583 bias-pull-down;
3586 cci1_default: cci1-default-state {
3590 drive-strength = <2>;
3591 bias-pull-up;
3594 cci1_sleep: cci1-sleep-state {
3598 drive-strength = <2>;
3599 bias-pull-down;
3602 cci2_default: cci2-default-state {
3606 drive-strength = <2>;
3607 bias-pull-up;
3610 cci2_sleep: cci2-sleep-state {
3614 drive-strength = <2>;
3615 bias-pull-down;
3618 cci3_default: cci3-default-state {
3622 drive-strength = <2>;
3623 bias-pull-up;
3626 cci3_sleep: cci3-sleep-state {
3630 drive-strength = <2>;
3631 bias-pull-down;
3634 pcie0_default_state: pcie0-default-state {
3635 perst-pins {
3638 drive-strength = <2>;
3639 bias-pull-down;
3642 clkreq-pins {
3645 drive-strength = <2>;
3646 bias-pull-up;
3649 wake-pins {
3652 drive-strength = <2>;
3653 bias-pull-up;
3657 pcie1_default_state: pcie1-default-state {
3658 perst-pins {
3661 drive-strength = <2>;
3662 bias-pull-down;
3665 clkreq-pins {
3668 drive-strength = <2>;
3669 bias-pull-up;
3672 wake-pins {
3675 drive-strength = <2>;
3676 bias-pull-up;
3680 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3685 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3690 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3695 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3700 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3705 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3710 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3715 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3720 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3725 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3730 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3735 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3740 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3743 drive-strength = <2>;
3744 bias-pull-up;
3747 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
3750 drive-strength = <2>;
3751 bias-pull-up;
3754 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3759 qup_i2c16_data_clk: qup-i2c16-data-clk-state {
3764 qup_i2c17_data_clk: qup-i2c17-data-clk-state {
3769 qup_i2c18_data_clk: qup-i2c18-data-clk-state {
3774 qup_i2c19_data_clk: qup-i2c19-data-clk-state {
3779 qup_i2c20_data_clk: qup-i2c20-data-clk-state {
3784 qup_i2c21_data_clk: qup-i2c21-data-clk-state {
3789 qup_spi0_cs: qup-spi0-cs-state {
3794 qup_spi0_data_clk: qup-spi0-data-clk-state {
3799 qup_spi1_cs: qup-spi1-cs-state {
3804 qup_spi1_data_clk: qup-spi1-data-clk-state {
3809 qup_spi2_cs: qup-spi2-cs-state {
3814 qup_spi2_data_clk: qup-spi2-data-clk-state {
3819 qup_spi3_cs: qup-spi3-cs-state {
3824 qup_spi3_data_clk: qup-spi3-data-clk-state {
3829 qup_spi4_cs: qup-spi4-cs-state {
3832 drive-strength = <6>;
3833 bias-disable;
3836 qup_spi4_data_clk: qup-spi4-data-clk-state {
3841 qup_spi5_cs: qup-spi5-cs-state {
3846 qup_spi5_data_clk: qup-spi5-data-clk-state {
3851 qup_spi6_cs: qup-spi6-cs-state {
3856 qup_spi6_data_clk: qup-spi6-data-clk-state {
3861 qup_spi8_cs: qup-spi8-cs-state {
3866 qup_spi8_data_clk: qup-spi8-data-clk-state {
3871 qup_spi9_cs: qup-spi9-cs-state {
3876 qup_spi9_data_clk: qup-spi9-data-clk-state {
3881 qup_spi10_cs: qup-spi10-cs-state {
3886 qup_spi10_data_clk: qup-spi10-data-clk-state {
3891 qup_spi11_cs: qup-spi11-cs-state {
3896 qup_spi11_data_clk: qup-spi11-data-clk-state {
3901 qup_spi12_cs: qup-spi12-cs-state {
3906 qup_spi12_data_clk: qup-spi12-data-clk-state {
3911 qup_spi13_cs: qup-spi13-cs-state {
3916 qup_spi13_data_clk: qup-spi13-data-clk-state {
3921 qup_spi14_cs: qup-spi14-cs-state {
3926 qup_spi14_data_clk: qup-spi14-data-clk-state {
3931 qup_spi15_cs: qup-spi15-cs-state {
3936 qup_spi15_data_clk: qup-spi15-data-clk-state {
3941 qup_spi16_cs: qup-spi16-cs-state {
3946 qup_spi16_data_clk: qup-spi16-data-clk-state {
3951 qup_spi17_cs: qup-spi17-cs-state {
3956 qup_spi17_data_clk: qup-spi17-data-clk-state {
3961 qup_spi18_cs: qup-spi18-cs-state {
3964 drive-strength = <6>;
3965 bias-disable;
3968 qup_spi18_data_clk: qup-spi18-data-clk-state {
3971 drive-strength = <6>;
3972 bias-disable;
3975 qup_spi19_cs: qup-spi19-cs-state {
3978 drive-strength = <6>;
3979 bias-disable;
3982 qup_spi19_data_clk: qup-spi19-data-clk-state {
3985 drive-strength = <6>;
3986 bias-disable;
3989 qup_spi20_cs: qup-spi20-cs-state {
3994 qup_spi20_data_clk: qup-spi20-data-clk-state {
3999 qup_spi21_cs: qup-spi21-cs-state {
4004 qup_spi21_data_clk: qup-spi21-data-clk-state {
4009 qup_uart7_rx: qup-uart7-rx-state {
4012 drive-strength = <2>;
4013 bias-disable;
4016 qup_uart7_tx: qup-uart7-tx-state {
4019 drive-strength = <2>;
4020 bias-disable;
4023 qup_uart20_default: qup-uart20-default-state {
4030 compatible = "qcom,sm8450-lpass-lpi-pinctrl";
4033 gpio-controller;
4034 #gpio-cells = <2>;
4035 gpio-ranges = <&lpass_tlmm 0 0 23>;
4039 clock-names = "core", "audio";
4041 tx_swr_active: tx-swr-active-state {
4042 clk-pins {
4045 drive-strength = <2>;
4046 slew-rate = <1>;
4047 bias-disable;
4050 data-pins {
4053 drive-strength = <2>;
4054 slew-rate = <1>;
4055 bias-bus-hold;
4059 rx_swr_active: rx-swr-active-state {
4060 clk-pins {
4063 drive-strength = <2>;
4064 slew-rate = <1>;
4065 bias-disable;
4068 data-pins {
4071 drive-strength = <2>;
4072 slew-rate = <1>;
4073 bias-bus-hold;
4077 dmic01_default: dmic01-default-state {
4078 clk-pins {
4081 drive-strength = <8>;
4082 output-high;
4085 data-pins {
4088 drive-strength = <8>;
4092 dmic23_default: dmic23-default-state {
4093 clk-pins {
4096 drive-strength = <8>;
4097 output-high;
4100 data-pins {
4103 drive-strength = <8>;
4107 wsa_swr_active: wsa-swr-active-state {
4108 clk-pins {
4111 drive-strength = <2>;
4112 slew-rate = <1>;
4113 bias-disable;
4116 data-pins {
4119 drive-strength = <2>;
4120 slew-rate = <1>;
4121 bias-bus-hold;
4125 wsa2_swr_active: wsa2-swr-active-state {
4126 clk-pins {
4129 drive-strength = <2>;
4130 slew-rate = <1>;
4131 bias-disable;
4134 data-pins {
4137 drive-strength = <2>;
4138 slew-rate = <1>;
4139 bias-bus-hold;
4145 compatible = "qcom,sm8450-imem", "syscon", "simple-mfd";
4149 #address-cells = <1>;
4150 #size-cells = <1>;
4152 pil-reloc@94c {
4153 compatible = "qcom,pil-reloc-info";
4159 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
4161 #iommu-cells = <2>;
4162 #global-interrupts = <1>;
4262 intc: interrupt-controller@17100000 {
4263 compatible = "arm,gic-v3";
4264 #interrupt-cells = <3>;
4265 interrupt-controller;
4266 #redistributor-regions = <1>;
4267 redistributor-stride = <0x0 0x40000>;
4271 #address-cells = <2>;
4272 #size-cells = <2>;
4275 gic_its: msi-controller@17140000 {
4276 compatible = "arm,gic-v3-its";
4278 msi-controller;
4279 #msi-cells = <1>;
4284 compatible = "arm,armv7-timer-mem";
4285 #address-cells = <1>;
4286 #size-cells = <1>;
4289 clock-frequency = <19200000>;
4292 frame-number = <0>;
4300 frame-number = <1>;
4307 frame-number = <2>;
4314 frame-number = <3>;
4321 frame-number = <4>;
4328 frame-number = <5>;
4335 frame-number = <6>;
4344 compatible = "qcom,rpmh-rsc";
4349 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4353 qcom,tcs-offset = <0xd00>;
4354 qcom,drv-id = <2>;
4355 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
4357 power-domains = <&CLUSTER_PD>;
4359 apps_bcm_voter: bcm-voter {
4360 compatible = "qcom,bcm-voter";
4363 rpmhcc: clock-controller {
4364 compatible = "qcom,sm8450-rpmh-clk";
4365 #clock-cells = <1>;
4366 clock-names = "xo";
4370 rpmhpd: power-controller {
4371 compatible = "qcom,sm8450-rpmhpd";
4372 #power-domain-cells = <1>;
4373 operating-points-v2 = <&rpmhpd_opp_table>;
4375 rpmhpd_opp_table: opp-table {
4376 compatible = "operating-points-v2";
4379 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4383 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4387 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
4391 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4395 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
4399 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4403 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
4407 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4411 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
4415 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4419 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4423 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4427 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4431 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4438 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
4442 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
4444 clock-names = "xo", "alternate";
4448 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4449 #freq-domain-cells = <1>;
4450 #clock-cells = <1>;
4454 compatible = "qcom,sm8450-gem-noc";
4456 #interconnect-cells = <2>;
4457 qcom,bcm-voters = <&apps_bcm_voter>;
4460 system-cache-controller@19200000 {
4461 compatible = "qcom,sm8450-llcc";
4465 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
4472 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
4473 "jedec,ufs-2.0";
4477 phy-names = "ufsphy";
4478 lanes-per-direction = <2>;
4479 #reset-cells = <1>;
4481 reset-names = "rst";
4483 power-domains = <&gcc UFS_PHY_GDSC>;
4486 dma-coherent;
4490 interconnect-names = "ufs-ddr", "cpu-ufs";
4491 clock-names =
4509 freq-table-hz =
4524 compatible = "qcom,sm8450-qmp-ufs-phy";
4527 clock-names = "ref", "ref_aux", "qref";
4532 power-domains = <&gcc UFS_PHY_GDSC>;
4535 reset-names = "ufsphy";
4537 #clock-cells = <1>;
4538 #phy-cells = <0>;
4544 compatible = "qcom,sm8450-inline-crypto-engine",
4545 "qcom,inline-crypto-engine";
4550 cryptobam: dma-controller@1dc4000 {
4551 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
4554 #dma-cells = <1>;
4556 qcom,controlled-remotely;
4565 compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce";
4568 dma-names = "rx", "tx";
4575 interconnect-names = "memory";
4579 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5";
4584 interrupt-names = "hc_irq", "pwr_irq";
4589 clock-names = "iface", "core", "xo";
4593 interconnect-names = "sdhc-ddr","cpu-sdhc";
4595 power-domains = <&rpmhpd RPMHPD_CX>;
4596 operating-points-v2 = <&sdhc2_opp_table>;
4597 bus-width = <4>;
4598 dma-coherent;
4600 /* Forbid SDR104/SDR50 - broken hw! */
4601 sdhci-caps-mask = <0x3 0x0>;
4605 sdhc2_opp_table: opp-table {
4606 compatible = "operating-points-v2";
4608 opp-100000000 {
4609 opp-hz = /bits/ 64 <100000000>;
4610 required-opps = <&rpmhpd_opp_low_svs>;
4613 opp-202000000 {
4614 opp-hz = /bits/ 64 <202000000>;
4615 required-opps = <&rpmhpd_opp_svs_l1>;
4621 compatible = "qcom,sm8450-dwc3", "qcom,dwc3";
4624 #address-cells = <2>;
4625 #size-cells = <2>;
4634 clock-names = "cfg_noc",
4641 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4643 assigned-clock-rates = <19200000>, <200000000>;
4645 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4650 interrupt-names = "pwr_event",
4656 power-domains = <&gcc USB30_PRIM_GDSC>;
4662 interconnect-names = "usb-ddr", "apps-usb";
4672 phy-names = "usb2-phy", "usb3-phy";
4675 #address-cells = <1>;
4676 #size-cells = <0>;
4689 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
4697 compatible = "qcom,sm8450-nsp-noc";
4699 #interconnect-cells = <2>;
4700 qcom,bcm-voters = <&apps_bcm_voter>;
4704 compatible = "qcom,sm8450-lpass-ag-noc";
4706 #interconnect-cells = <2>;
4707 qcom,bcm-voters = <&apps_bcm_voter>;
4714 thermal-zones {
4715 aoss0-thermal {
4716 thermal-sensors = <&tsens0 0>;
4719 thermal-engine-config {
4725 reset-mon-cfg {
4733 cpuss0-thermal {
4734 thermal-sensors = <&tsens0 1>;
4737 thermal-engine-config {
4743 reset-mon-cfg {
4751 cpuss1-thermal {
4752 thermal-sensors = <&tsens0 2>;
4755 thermal-engine-config {
4761 reset-mon-cfg {
4769 cpuss3-thermal {
4770 thermal-sensors = <&tsens0 3>;
4773 thermal-engine-config {
4779 reset-mon-cfg {
4787 cpuss4-thermal {
4788 thermal-sensors = <&tsens0 4>;
4791 thermal-engine-config {
4797 reset-mon-cfg {
4805 cpu4-top-thermal {
4806 thermal-sensors = <&tsens0 5>;
4809 cpu4_top_alert0: trip-point0 {
4815 cpu4_top_alert1: trip-point1 {
4821 cpu4_top_crit: cpu-crit {
4829 cpu4-bottom-thermal {
4830 thermal-sensors = <&tsens0 6>;
4833 cpu4_bottom_alert0: trip-point0 {
4839 cpu4_bottom_alert1: trip-point1 {
4845 cpu4_bottom_crit: cpu-crit {
4853 cpu5-top-thermal {
4854 thermal-sensors = <&tsens0 7>;
4857 cpu5_top_alert0: trip-point0 {
4863 cpu5_top_alert1: trip-point1 {
4869 cpu5_top_crit: cpu-crit {
4877 cpu5-bottom-thermal {
4878 thermal-sensors = <&tsens0 8>;
4881 cpu5_bottom_alert0: trip-point0 {
4887 cpu5_bottom_alert1: trip-point1 {
4893 cpu5_bottom_crit: cpu-crit {
4901 cpu6-top-thermal {
4902 thermal-sensors = <&tsens0 9>;
4905 cpu6_top_alert0: trip-point0 {
4911 cpu6_top_alert1: trip-point1 {
4917 cpu6_top_crit: cpu-crit {
4925 cpu6-bottom-thermal {
4926 thermal-sensors = <&tsens0 10>;
4929 cpu6_bottom_alert0: trip-point0 {
4935 cpu6_bottom_alert1: trip-point1 {
4941 cpu6_bottom_crit: cpu-crit {
4949 cpu7-top-thermal {
4950 thermal-sensors = <&tsens0 11>;
4953 cpu7_top_alert0: trip-point0 {
4959 cpu7_top_alert1: trip-point1 {
4965 cpu7_top_crit: cpu-crit {
4973 cpu7-middle-thermal {
4974 thermal-sensors = <&tsens0 12>;
4977 cpu7_middle_alert0: trip-point0 {
4983 cpu7_middle_alert1: trip-point1 {
4989 cpu7_middle_crit: cpu-crit {
4997 cpu7-bottom-thermal {
4998 thermal-sensors = <&tsens0 13>;
5001 cpu7_bottom_alert0: trip-point0 {
5007 cpu7_bottom_alert1: trip-point1 {
5013 cpu7_bottom_crit: cpu-crit {
5021 gpu-top-thermal {
5022 polling-delay-passive = <10>;
5024 thermal-sensors = <&tsens0 14>;
5026 cooling-maps {
5029 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5034 gpu_top_alert0: trip-point0 {
5040 trip-point1 {
5046 trip-point2 {
5054 gpu-bottom-thermal {
5055 polling-delay-passive = <10>;
5057 thermal-sensors = <&tsens0 15>;
5059 cooling-maps {
5062 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5067 gpu_bottom_alert0: trip-point0 {
5073 trip-point1 {
5079 trip-point2 {
5087 aoss1-thermal {
5088 thermal-sensors = <&tsens1 0>;
5091 thermal-engine-config {
5097 reset-mon-cfg {
5105 cpu0-thermal {
5106 thermal-sensors = <&tsens1 1>;
5109 cpu0_alert0: trip-point0 {
5115 cpu0_alert1: trip-point1 {
5121 cpu0_crit: cpu-crit {
5129 cpu1-thermal {
5130 thermal-sensors = <&tsens1 2>;
5133 cpu1_alert0: trip-point0 {
5139 cpu1_alert1: trip-point1 {
5145 cpu1_crit: cpu-crit {
5153 cpu2-thermal {
5154 thermal-sensors = <&tsens1 3>;
5157 cpu2_alert0: trip-point0 {
5163 cpu2_alert1: trip-point1 {
5169 cpu2_crit: cpu-crit {
5177 cpu3-thermal {
5178 thermal-sensors = <&tsens1 4>;
5181 cpu3_alert0: trip-point0 {
5187 cpu3_alert1: trip-point1 {
5193 cpu3_crit: cpu-crit {
5201 cdsp0-thermal {
5202 polling-delay-passive = <10>;
5204 thermal-sensors = <&tsens1 5>;
5207 thermal-engine-config {
5213 thermal-hal-config {
5219 reset-mon-cfg {
5225 cdsp_0_config: junction-config {
5233 cdsp1-thermal {
5234 polling-delay-passive = <10>;
5236 thermal-sensors = <&tsens1 6>;
5239 thermal-engine-config {
5245 thermal-hal-config {
5251 reset-mon-cfg {
5257 cdsp_1_config: junction-config {
5265 cdsp2-thermal {
5266 polling-delay-passive = <10>;
5268 thermal-sensors = <&tsens1 7>;
5271 thermal-engine-config {
5277 thermal-hal-config {
5283 reset-mon-cfg {
5289 cdsp_2_config: junction-config {
5297 video-thermal {
5298 thermal-sensors = <&tsens1 8>;
5301 thermal-engine-config {
5307 reset-mon-cfg {
5315 mem-thermal {
5316 polling-delay-passive = <10>;
5318 thermal-sensors = <&tsens1 9>;
5321 thermal-engine-config {
5327 ddr_config0: ddr0-config {
5333 reset-mon-cfg {
5341 modem0-thermal {
5342 thermal-sensors = <&tsens1 10>;
5345 thermal-engine-config {
5351 mdmss0_config0: mdmss0-config0 {
5357 mdmss0_config1: mdmss0-config1 {
5363 reset-mon-cfg {
5371 modem1-thermal {
5372 thermal-sensors = <&tsens1 11>;
5375 thermal-engine-config {
5381 mdmss1_config0: mdmss1-config0 {
5387 mdmss1_config1: mdmss1-config1 {
5393 reset-mon-cfg {
5401 modem2-thermal {
5402 thermal-sensors = <&tsens1 12>;
5405 thermal-engine-config {
5411 mdmss2_config0: mdmss2-config0 {
5417 mdmss2_config1: mdmss2-config1 {
5423 reset-mon-cfg {
5431 modem3-thermal {
5432 thermal-sensors = <&tsens1 13>;
5435 thermal-engine-config {
5441 mdmss3_config0: mdmss3-config0 {
5447 mdmss3_config1: mdmss3-config1 {
5453 reset-mon-cfg {
5461 camera0-thermal {
5462 thermal-sensors = <&tsens1 14>;
5465 thermal-engine-config {
5471 reset-mon-cfg {
5479 camera1-thermal {
5480 thermal-sensors = <&tsens1 15>;
5483 thermal-engine-config {
5489 reset-mon-cfg {
5499 compatible = "arm,armv8-timer";
5504 clock-frequency = <19200000>;