Lines Matching +full:opp +full:- +full:160000000
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
8 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/clock/qcom,sm8450-camcc.h>
11 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
12 #include <dt-bindings/clock/qcom,sm8450-gpucc.h>
13 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
14 #include <dt-bindings/dma/qcom-gpi.h>
15 #include <dt-bindings/firmware/qcom,scm.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/mailbox/qcom-ipcc.h>
18 #include <dt-bindings/phy/phy-qcom-qmp.h>
19 #include <dt-bindings/power/qcom,rpmhpd.h>
20 #include <dt-bindings/power/qcom-rpmpd.h>
21 #include <dt-bindings/interconnect/qcom,icc.h>
22 #include <dt-bindings/interconnect/qcom,sm8450.h>
23 #include <dt-bindings/reset/qcom,sm8450-gpucc.h>
24 #include <dt-bindings/soc/qcom,gpr.h>
25 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
26 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
27 #include <dt-bindings/thermal/thermal.h>
30 interrupt-parent = <&intc>;
32 #address-cells = <2>;
33 #size-cells = <2>;
38 xo_board: xo-board {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 clock-frequency = <76800000>;
44 sleep_clk: sleep-clk {
45 compatible = "fixed-clock";
46 #clock-cells = <0>;
47 clock-frequency = <32764>;
52 #address-cells = <2>;
53 #size-cells = <0>;
59 enable-method = "psci";
60 next-level-cache = <&l2_0>;
61 power-domains = <&cpu_pd0>;
62 power-domain-names = "psci";
63 qcom,freq-domain = <&cpufreq_hw 0>;
64 #cooling-cells = <2>;
66 l2_0: l2-cache {
68 cache-level = <2>;
69 cache-unified;
70 next-level-cache = <&l3_0>;
71 l3_0: l3-cache {
73 cache-level = <3>;
74 cache-unified;
83 enable-method = "psci";
84 next-level-cache = <&l2_100>;
85 power-domains = <&cpu_pd1>;
86 power-domain-names = "psci";
87 qcom,freq-domain = <&cpufreq_hw 0>;
88 #cooling-cells = <2>;
90 l2_100: l2-cache {
92 cache-level = <2>;
93 cache-unified;
94 next-level-cache = <&l3_0>;
102 enable-method = "psci";
103 next-level-cache = <&l2_200>;
104 power-domains = <&cpu_pd2>;
105 power-domain-names = "psci";
106 qcom,freq-domain = <&cpufreq_hw 0>;
107 #cooling-cells = <2>;
109 l2_200: l2-cache {
111 cache-level = <2>;
112 cache-unified;
113 next-level-cache = <&l3_0>;
121 enable-method = "psci";
122 next-level-cache = <&l2_300>;
123 power-domains = <&cpu_pd3>;
124 power-domain-names = "psci";
125 qcom,freq-domain = <&cpufreq_hw 0>;
126 #cooling-cells = <2>;
128 l2_300: l2-cache {
130 cache-level = <2>;
131 cache-unified;
132 next-level-cache = <&l3_0>;
140 enable-method = "psci";
141 next-level-cache = <&l2_400>;
142 power-domains = <&cpu_pd4>;
143 power-domain-names = "psci";
144 qcom,freq-domain = <&cpufreq_hw 1>;
145 #cooling-cells = <2>;
147 l2_400: l2-cache {
149 cache-level = <2>;
150 cache-unified;
151 next-level-cache = <&l3_0>;
159 enable-method = "psci";
160 next-level-cache = <&l2_500>;
161 power-domains = <&cpu_pd5>;
162 power-domain-names = "psci";
163 qcom,freq-domain = <&cpufreq_hw 1>;
164 #cooling-cells = <2>;
166 l2_500: l2-cache {
168 cache-level = <2>;
169 cache-unified;
170 next-level-cache = <&l3_0>;
178 enable-method = "psci";
179 next-level-cache = <&l2_600>;
180 power-domains = <&cpu_pd6>;
181 power-domain-names = "psci";
182 qcom,freq-domain = <&cpufreq_hw 1>;
183 #cooling-cells = <2>;
185 l2_600: l2-cache {
187 cache-level = <2>;
188 cache-unified;
189 next-level-cache = <&l3_0>;
197 enable-method = "psci";
198 next-level-cache = <&l2_700>;
199 power-domains = <&cpu_pd7>;
200 power-domain-names = "psci";
201 qcom,freq-domain = <&cpufreq_hw 2>;
202 #cooling-cells = <2>;
204 l2_700: l2-cache {
206 cache-level = <2>;
207 cache-unified;
208 next-level-cache = <&l3_0>;
212 cpu-map {
248 idle-states {
249 entry-method = "psci";
251 little_cpu_sleep_0: cpu-sleep-0-0 {
252 compatible = "arm,idle-state";
253 idle-state-name = "silver-rail-power-collapse";
254 arm,psci-suspend-param = <0x40000004>;
255 entry-latency-us = <800>;
256 exit-latency-us = <750>;
257 min-residency-us = <4090>;
258 local-timer-stop;
261 big_cpu_sleep_0: cpu-sleep-1-0 {
262 compatible = "arm,idle-state";
263 idle-state-name = "gold-rail-power-collapse";
264 arm,psci-suspend-param = <0x40000004>;
265 entry-latency-us = <600>;
266 exit-latency-us = <1550>;
267 min-residency-us = <4791>;
268 local-timer-stop;
272 domain-idle-states {
273 cluster_sleep_0: cluster-sleep-0 {
274 compatible = "domain-idle-state";
275 arm,psci-suspend-param = <0x41000044>;
276 entry-latency-us = <1050>;
277 exit-latency-us = <2500>;
278 min-residency-us = <5309>;
281 cluster_sleep_1: cluster-sleep-1 {
282 compatible = "domain-idle-state";
283 arm,psci-suspend-param = <0x4100c344>;
284 entry-latency-us = <2700>;
285 exit-latency-us = <3500>;
286 min-residency-us = <13959>;
291 ete-0 {
292 compatible = "arm,embedded-trace-extension";
295 out-ports {
298 remote-endpoint = <&funnel_ete_in_ete0>;
304 ete-1 {
305 compatible = "arm,embedded-trace-extension";
308 out-ports {
311 remote-endpoint = <&funnel_ete_in_ete1>;
317 ete-2 {
318 compatible = "arm,embedded-trace-extension";
321 out-ports {
324 remote-endpoint = <&funnel_ete_in_ete2>;
330 ete-3 {
331 compatible = "arm,embedded-trace-extension";
334 out-ports {
337 remote-endpoint = <&funnel_ete_in_ete3>;
343 ete-4 {
344 compatible = "arm,embedded-trace-extension";
347 out-ports {
350 remote-endpoint = <&funnel_ete_in_ete4>;
356 ete-5 {
357 compatible = "arm,embedded-trace-extension";
360 out-ports {
363 remote-endpoint = <&funnel_ete_in_ete5>;
369 ete-6 {
370 compatible = "arm,embedded-trace-extension";
373 out-ports {
376 remote-endpoint = <&funnel_ete_in_ete6>;
382 ete-7 {
383 compatible = "arm,embedded-trace-extension";
386 out-ports {
389 remote-endpoint = <&funnel_ete_in_ete7>;
395 funnel-ete {
396 compatible = "arm,coresight-static-funnel";
398 out-ports {
401 remote-endpoint =
407 in-ports {
408 #address-cells = <1>;
409 #size-cells = <0>;
414 remote-endpoint =
422 remote-endpoint =
430 remote-endpoint =
438 remote-endpoint =
446 remote-endpoint =
454 remote-endpoint =
462 remote-endpoint =
470 remote-endpoint =
479 compatible = "qcom,scm-sm8450", "qcom,scm";
480 qcom,dload-mode = <&tcsr 0x13000>;
482 #reset-cells = <1>;
486 clk_virt: interconnect-0 {
487 compatible = "qcom,sm8450-clk-virt";
488 #interconnect-cells = <2>;
489 qcom,bcm-voters = <&apps_bcm_voter>;
492 mc_virt: interconnect-1 {
493 compatible = "qcom,sm8450-mc-virt";
494 #interconnect-cells = <2>;
495 qcom,bcm-voters = <&apps_bcm_voter>;
505 compatible = "arm,armv8-pmuv3";
510 compatible = "arm,psci-1.0";
513 cpu_pd0: power-domain-cpu0 {
514 #power-domain-cells = <0>;
515 power-domains = <&cluster_pd>;
516 domain-idle-states = <&little_cpu_sleep_0>;
519 cpu_pd1: power-domain-cpu1 {
520 #power-domain-cells = <0>;
521 power-domains = <&cluster_pd>;
522 domain-idle-states = <&little_cpu_sleep_0>;
525 cpu_pd2: power-domain-cpu2 {
526 #power-domain-cells = <0>;
527 power-domains = <&cluster_pd>;
528 domain-idle-states = <&little_cpu_sleep_0>;
531 cpu_pd3: power-domain-cpu3 {
532 #power-domain-cells = <0>;
533 power-domains = <&cluster_pd>;
534 domain-idle-states = <&little_cpu_sleep_0>;
537 cpu_pd4: power-domain-cpu4 {
538 #power-domain-cells = <0>;
539 power-domains = <&cluster_pd>;
540 domain-idle-states = <&big_cpu_sleep_0>;
543 cpu_pd5: power-domain-cpu5 {
544 #power-domain-cells = <0>;
545 power-domains = <&cluster_pd>;
546 domain-idle-states = <&big_cpu_sleep_0>;
549 cpu_pd6: power-domain-cpu6 {
550 #power-domain-cells = <0>;
551 power-domains = <&cluster_pd>;
552 domain-idle-states = <&big_cpu_sleep_0>;
555 cpu_pd7: power-domain-cpu7 {
556 #power-domain-cells = <0>;
557 power-domains = <&cluster_pd>;
558 domain-idle-states = <&big_cpu_sleep_0>;
561 cluster_pd: power-domain-cpu-cluster0 {
562 #power-domain-cells = <0>;
563 domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>;
567 qup_opp_table_100mhz: opp-table-qup {
568 compatible = "operating-points-v2";
570 opp-50000000 {
571 opp-hz = /bits/ 64 <50000000>;
572 required-opps = <&rpmhpd_opp_min_svs>;
575 opp-75000000 {
576 opp-hz = /bits/ 64 <75000000>;
577 required-opps = <&rpmhpd_opp_low_svs>;
580 opp-100000000 {
581 opp-hz = /bits/ 64 <100000000>;
582 required-opps = <&rpmhpd_opp_svs>;
586 reserved_memory: reserved-memory {
587 #address-cells = <2>;
588 #size-cells = <2>;
593 no-map;
598 no-map;
603 no-map;
608 no-map;
613 no-map;
617 compatible = "qcom,cmd-db";
619 no-map;
624 no-map;
629 no-map;
634 no-map;
639 no-map;
647 no-map;
652 no-map;
657 no-map;
662 no-map;
667 no-map;
672 no-map;
677 no-map;
682 no-map;
687 no-map;
692 no-map;
697 no-map;
703 no-map;
709 no-map;
714 no-map;
719 no-map;
724 no-map;
728 compatible = "qcom,rmtfs-mem";
730 no-map;
732 qcom,client-id = <1>;
738 no-map;
743 no-map;
752 no-map;
757 no-map;
762 no-map;
767 no-map;
772 no-map;
777 no-map;
782 no-map;
787 no-map;
792 no-map;
797 no-map;
802 no-map;
807 no-map;
812 no-map;
817 no-map;
821 smp2p-adsp {
824 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
830 qcom,local-pid = <0>;
831 qcom,remote-pid = <2>;
833 smp2p_adsp_out: master-kernel {
834 qcom,entry-name = "master-kernel";
835 #qcom,smem-state-cells = <1>;
838 smp2p_adsp_in: slave-kernel {
839 qcom,entry-name = "slave-kernel";
840 interrupt-controller;
841 #interrupt-cells = <2>;
845 smp2p-cdsp {
848 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
854 qcom,local-pid = <0>;
855 qcom,remote-pid = <5>;
857 smp2p_cdsp_out: master-kernel {
858 qcom,entry-name = "master-kernel";
859 #qcom,smem-state-cells = <1>;
862 smp2p_cdsp_in: slave-kernel {
863 qcom,entry-name = "slave-kernel";
864 interrupt-controller;
865 #interrupt-cells = <2>;
869 smp2p-modem {
872 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
878 qcom,local-pid = <0>;
879 qcom,remote-pid = <1>;
881 smp2p_modem_out: master-kernel {
882 qcom,entry-name = "master-kernel";
883 #qcom,smem-state-cells = <1>;
886 smp2p_modem_in: slave-kernel {
887 qcom,entry-name = "slave-kernel";
888 interrupt-controller;
889 #interrupt-cells = <2>;
892 ipa_smp2p_out: ipa-ap-to-modem {
893 qcom,entry-name = "ipa";
894 #qcom,smem-state-cells = <1>;
897 ipa_smp2p_in: ipa-modem-to-ap {
898 qcom,entry-name = "ipa";
899 interrupt-controller;
900 #interrupt-cells = <2>;
904 smp2p-slpi {
907 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
913 qcom,local-pid = <0>;
914 qcom,remote-pid = <3>;
916 smp2p_slpi_out: master-kernel {
917 qcom,entry-name = "master-kernel";
918 #qcom,smem-state-cells = <1>;
921 smp2p_slpi_in: slave-kernel {
922 qcom,entry-name = "slave-kernel";
923 interrupt-controller;
924 #interrupt-cells = <2>;
929 #address-cells = <2>;
930 #size-cells = <2>;
932 dma-ranges = <0 0 0 0 0x10 0>;
933 compatible = "simple-bus";
935 gcc: clock-controller@100000 {
936 compatible = "qcom,gcc-sm8450";
938 #clock-cells = <1>;
939 #reset-cells = <1>;
940 #power-domain-cells = <1>;
950 clock-names = "bi_tcxo",
961 gpi_dma2: dma-controller@800000 {
962 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
963 #dma-cells = <3>;
977 dma-channels = <12>;
978 dma-channel-mask = <0x7e>;
984 compatible = "qcom,geni-se-qup";
986 clock-names = "m-ahb", "s-ahb";
990 #address-cells = <2>;
991 #size-cells = <2>;
996 compatible = "qcom,geni-i2c";
998 clock-names = "se";
1000 pinctrl-names = "default";
1001 pinctrl-0 = <&qup_i2c15_data_clk>;
1003 #address-cells = <1>;
1004 #size-cells = <0>;
1008 interconnect-names = "qup-core", "qup-config", "qup-memory";
1011 dma-names = "tx", "rx";
1016 compatible = "qcom,geni-spi";
1018 clock-names = "se";
1021 pinctrl-names = "default";
1022 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1025 interconnect-names = "qup-core", "qup-config";
1028 dma-names = "tx", "rx";
1029 #address-cells = <1>;
1030 #size-cells = <0>;
1035 compatible = "qcom,geni-i2c";
1037 clock-names = "se";
1039 pinctrl-names = "default";
1040 pinctrl-0 = <&qup_i2c16_data_clk>;
1042 #address-cells = <1>;
1043 #size-cells = <0>;
1047 interconnect-names = "qup-core", "qup-config", "qup-memory";
1050 dma-names = "tx", "rx";
1055 compatible = "qcom,geni-spi";
1057 clock-names = "se";
1060 pinctrl-names = "default";
1061 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
1064 interconnect-names = "qup-core", "qup-config";
1067 dma-names = "tx", "rx";
1068 #address-cells = <1>;
1069 #size-cells = <0>;
1074 compatible = "qcom,geni-i2c";
1076 clock-names = "se";
1078 pinctrl-names = "default";
1079 pinctrl-0 = <&qup_i2c17_data_clk>;
1081 #address-cells = <1>;
1082 #size-cells = <0>;
1086 interconnect-names = "qup-core", "qup-config", "qup-memory";
1089 dma-names = "tx", "rx";
1094 compatible = "qcom,geni-spi";
1096 clock-names = "se";
1099 pinctrl-names = "default";
1100 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
1103 interconnect-names = "qup-core", "qup-config";
1106 dma-names = "tx", "rx";
1107 #address-cells = <1>;
1108 #size-cells = <0>;
1113 compatible = "qcom,geni-i2c";
1115 clock-names = "se";
1117 pinctrl-names = "default";
1118 pinctrl-0 = <&qup_i2c18_data_clk>;
1120 #address-cells = <1>;
1121 #size-cells = <0>;
1125 interconnect-names = "qup-core", "qup-config", "qup-memory";
1128 dma-names = "tx", "rx";
1133 compatible = "qcom,geni-spi";
1135 clock-names = "se";
1138 pinctrl-names = "default";
1139 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
1142 interconnect-names = "qup-core", "qup-config";
1145 dma-names = "tx", "rx";
1146 #address-cells = <1>;
1147 #size-cells = <0>;
1152 compatible = "qcom,geni-i2c";
1154 clock-names = "se";
1156 pinctrl-names = "default";
1157 pinctrl-0 = <&qup_i2c19_data_clk>;
1159 #address-cells = <1>;
1160 #size-cells = <0>;
1164 interconnect-names = "qup-core", "qup-config", "qup-memory";
1167 dma-names = "tx", "rx";
1172 compatible = "qcom,geni-spi";
1174 clock-names = "se";
1177 pinctrl-names = "default";
1178 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
1181 interconnect-names = "qup-core", "qup-config";
1184 dma-names = "tx", "rx";
1185 #address-cells = <1>;
1186 #size-cells = <0>;
1191 compatible = "qcom,geni-i2c";
1193 clock-names = "se";
1195 pinctrl-names = "default";
1196 pinctrl-0 = <&qup_i2c20_data_clk>;
1198 #address-cells = <1>;
1199 #size-cells = <0>;
1203 interconnect-names = "qup-core", "qup-config", "qup-memory";
1206 dma-names = "tx", "rx";
1211 compatible = "qcom,geni-uart";
1213 clock-names = "se";
1215 pinctrl-names = "default";
1216 pinctrl-0 = <&qup_uart20_default>;
1222 interconnect-names = "qup-core",
1223 "qup-config";
1228 compatible = "qcom,geni-spi";
1230 clock-names = "se";
1233 pinctrl-names = "default";
1234 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1237 interconnect-names = "qup-core", "qup-config";
1240 dma-names = "tx", "rx";
1241 #address-cells = <1>;
1242 #size-cells = <0>;
1247 compatible = "qcom,geni-i2c";
1249 clock-names = "se";
1251 pinctrl-names = "default";
1252 pinctrl-0 = <&qup_i2c21_data_clk>;
1254 #address-cells = <1>;
1255 #size-cells = <0>;
1259 interconnect-names = "qup-core", "qup-config", "qup-memory";
1262 dma-names = "tx", "rx";
1267 compatible = "qcom,geni-spi";
1269 clock-names = "se";
1272 pinctrl-names = "default";
1273 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1276 interconnect-names = "qup-core", "qup-config";
1279 dma-names = "tx", "rx";
1280 #address-cells = <1>;
1281 #size-cells = <0>;
1286 gpi_dma0: dma-controller@900000 {
1287 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1288 #dma-cells = <3>;
1302 dma-channels = <12>;
1303 dma-channel-mask = <0x7e>;
1309 compatible = "qcom,geni-se-qup";
1311 clock-names = "m-ahb", "s-ahb";
1316 interconnect-names = "qup-core";
1317 #address-cells = <2>;
1318 #size-cells = <2>;
1323 compatible = "qcom,geni-i2c";
1325 clock-names = "se";
1327 pinctrl-names = "default";
1328 pinctrl-0 = <&qup_i2c0_data_clk>;
1330 #address-cells = <1>;
1331 #size-cells = <0>;
1335 interconnect-names = "qup-core", "qup-config", "qup-memory";
1338 dma-names = "tx", "rx";
1343 compatible = "qcom,geni-spi";
1345 clock-names = "se";
1348 pinctrl-names = "default";
1349 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1350 power-domains = <&rpmhpd RPMHPD_CX>;
1351 operating-points-v2 = <&qup_opp_table_100mhz>;
1355 interconnect-names = "qup-core", "qup-config", "qup-memory";
1358 dma-names = "tx", "rx";
1359 #address-cells = <1>;
1360 #size-cells = <0>;
1365 compatible = "qcom,geni-i2c";
1367 clock-names = "se";
1369 pinctrl-names = "default";
1370 pinctrl-0 = <&qup_i2c1_data_clk>;
1372 #address-cells = <1>;
1373 #size-cells = <0>;
1377 interconnect-names = "qup-core", "qup-config", "qup-memory";
1380 dma-names = "tx", "rx";
1385 compatible = "qcom,geni-spi";
1387 clock-names = "se";
1390 pinctrl-names = "default";
1391 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1395 interconnect-names = "qup-core", "qup-config", "qup-memory";
1398 dma-names = "tx", "rx";
1399 #address-cells = <1>;
1400 #size-cells = <0>;
1405 compatible = "qcom,geni-i2c";
1407 clock-names = "se";
1409 pinctrl-names = "default";
1410 pinctrl-0 = <&qup_i2c2_data_clk>;
1412 #address-cells = <1>;
1413 #size-cells = <0>;
1417 interconnect-names = "qup-core", "qup-config", "qup-memory";
1420 dma-names = "tx", "rx";
1425 compatible = "qcom,geni-spi";
1427 clock-names = "se";
1430 pinctrl-names = "default";
1431 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1435 interconnect-names = "qup-core", "qup-config", "qup-memory";
1438 dma-names = "tx", "rx";
1439 #address-cells = <1>;
1440 #size-cells = <0>;
1446 compatible = "qcom,geni-i2c";
1448 clock-names = "se";
1450 pinctrl-names = "default";
1451 pinctrl-0 = <&qup_i2c3_data_clk>;
1453 #address-cells = <1>;
1454 #size-cells = <0>;
1458 interconnect-names = "qup-core", "qup-config", "qup-memory";
1461 dma-names = "tx", "rx";
1466 compatible = "qcom,geni-spi";
1468 clock-names = "se";
1471 pinctrl-names = "default";
1472 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1476 interconnect-names = "qup-core", "qup-config", "qup-memory";
1479 dma-names = "tx", "rx";
1480 #address-cells = <1>;
1481 #size-cells = <0>;
1486 compatible = "qcom,geni-i2c";
1488 clock-names = "se";
1490 pinctrl-names = "default";
1491 pinctrl-0 = <&qup_i2c4_data_clk>;
1493 #address-cells = <1>;
1494 #size-cells = <0>;
1498 interconnect-names = "qup-core", "qup-config", "qup-memory";
1501 dma-names = "tx", "rx";
1506 compatible = "qcom,geni-spi";
1508 clock-names = "se";
1511 pinctrl-names = "default";
1512 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1513 power-domains = <&rpmhpd RPMHPD_CX>;
1514 operating-points-v2 = <&qup_opp_table_100mhz>;
1518 interconnect-names = "qup-core", "qup-config", "qup-memory";
1521 dma-names = "tx", "rx";
1522 #address-cells = <1>;
1523 #size-cells = <0>;
1528 compatible = "qcom,geni-i2c";
1530 clock-names = "se";
1532 pinctrl-names = "default";
1533 pinctrl-0 = <&qup_i2c5_data_clk>;
1535 #address-cells = <1>;
1536 #size-cells = <0>;
1540 interconnect-names = "qup-core", "qup-config", "qup-memory";
1543 dma-names = "tx", "rx";
1548 compatible = "qcom,geni-spi";
1550 clock-names = "se";
1553 pinctrl-names = "default";
1554 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1558 interconnect-names = "qup-core", "qup-config", "qup-memory";
1561 dma-names = "tx", "rx";
1562 #address-cells = <1>;
1563 #size-cells = <0>;
1569 compatible = "qcom,geni-i2c";
1571 clock-names = "se";
1573 pinctrl-names = "default";
1574 pinctrl-0 = <&qup_i2c6_data_clk>;
1576 #address-cells = <1>;
1577 #size-cells = <0>;
1581 interconnect-names = "qup-core", "qup-config", "qup-memory";
1584 dma-names = "tx", "rx";
1589 compatible = "qcom,geni-spi";
1591 clock-names = "se";
1594 pinctrl-names = "default";
1595 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1599 interconnect-names = "qup-core", "qup-config", "qup-memory";
1602 dma-names = "tx", "rx";
1603 #address-cells = <1>;
1604 #size-cells = <0>;
1609 compatible = "qcom,geni-debug-uart";
1611 clock-names = "se";
1613 pinctrl-names = "default";
1614 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1620 interconnect-names = "qup-core",
1621 "qup-config";
1626 gpi_dma1: dma-controller@a00000 {
1627 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1628 #dma-cells = <3>;
1642 dma-channels = <12>;
1643 dma-channel-mask = <0x7e>;
1649 compatible = "qcom,geni-se-qup";
1651 clock-names = "m-ahb", "s-ahb";
1656 interconnect-names = "qup-core";
1657 #address-cells = <2>;
1658 #size-cells = <2>;
1663 compatible = "qcom,geni-i2c";
1665 clock-names = "se";
1667 pinctrl-names = "default";
1668 pinctrl-0 = <&qup_i2c8_data_clk>;
1670 #address-cells = <1>;
1671 #size-cells = <0>;
1675 interconnect-names = "qup-core", "qup-config", "qup-memory";
1678 dma-names = "tx", "rx";
1683 compatible = "qcom,geni-spi";
1685 clock-names = "se";
1688 pinctrl-names = "default";
1689 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1693 interconnect-names = "qup-core", "qup-config", "qup-memory";
1696 dma-names = "tx", "rx";
1697 #address-cells = <1>;
1698 #size-cells = <0>;
1703 compatible = "qcom,geni-i2c";
1705 clock-names = "se";
1707 pinctrl-names = "default";
1708 pinctrl-0 = <&qup_i2c9_data_clk>;
1710 #address-cells = <1>;
1711 #size-cells = <0>;
1715 interconnect-names = "qup-core", "qup-config", "qup-memory";
1718 dma-names = "tx", "rx";
1723 compatible = "qcom,geni-spi";
1725 clock-names = "se";
1728 pinctrl-names = "default";
1729 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1733 interconnect-names = "qup-core", "qup-config", "qup-memory";
1736 dma-names = "tx", "rx";
1737 #address-cells = <1>;
1738 #size-cells = <0>;
1743 compatible = "qcom,geni-i2c";
1745 clock-names = "se";
1747 pinctrl-names = "default";
1748 pinctrl-0 = <&qup_i2c10_data_clk>;
1750 #address-cells = <1>;
1751 #size-cells = <0>;
1755 interconnect-names = "qup-core", "qup-config", "qup-memory";
1758 dma-names = "tx", "rx";
1763 compatible = "qcom,geni-spi";
1765 clock-names = "se";
1768 pinctrl-names = "default";
1769 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1773 interconnect-names = "qup-core", "qup-config", "qup-memory";
1776 dma-names = "tx", "rx";
1777 #address-cells = <1>;
1778 #size-cells = <0>;
1783 compatible = "qcom,geni-i2c";
1785 clock-names = "se";
1787 pinctrl-names = "default";
1788 pinctrl-0 = <&qup_i2c11_data_clk>;
1790 #address-cells = <1>;
1791 #size-cells = <0>;
1795 interconnect-names = "qup-core", "qup-config", "qup-memory";
1798 dma-names = "tx", "rx";
1803 compatible = "qcom,geni-spi";
1805 clock-names = "se";
1808 pinctrl-names = "default";
1809 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1813 interconnect-names = "qup-core", "qup-config", "qup-memory";
1816 dma-names = "tx", "rx";
1817 #address-cells = <1>;
1818 #size-cells = <0>;
1823 compatible = "qcom,geni-i2c";
1825 clock-names = "se";
1827 pinctrl-names = "default";
1828 pinctrl-0 = <&qup_i2c12_data_clk>;
1830 #address-cells = <1>;
1831 #size-cells = <0>;
1835 interconnect-names = "qup-core", "qup-config", "qup-memory";
1838 dma-names = "tx", "rx";
1843 compatible = "qcom,geni-spi";
1845 clock-names = "se";
1848 pinctrl-names = "default";
1849 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1853 interconnect-names = "qup-core", "qup-config", "qup-memory";
1856 dma-names = "tx", "rx";
1857 #address-cells = <1>;
1858 #size-cells = <0>;
1863 compatible = "qcom,geni-i2c";
1865 clock-names = "se";
1867 pinctrl-names = "default";
1868 pinctrl-0 = <&qup_i2c13_data_clk>;
1873 interconnect-names = "qup-core", "qup-config", "qup-memory";
1876 dma-names = "tx", "rx";
1877 #address-cells = <1>;
1878 #size-cells = <0>;
1883 compatible = "qcom,geni-spi";
1885 clock-names = "se";
1888 pinctrl-names = "default";
1889 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1893 interconnect-names = "qup-core", "qup-config", "qup-memory";
1896 dma-names = "tx", "rx";
1897 #address-cells = <1>;
1898 #size-cells = <0>;
1903 compatible = "qcom,geni-i2c";
1905 clock-names = "se";
1907 pinctrl-names = "default";
1908 pinctrl-0 = <&qup_i2c14_data_clk>;
1913 interconnect-names = "qup-core", "qup-config", "qup-memory";
1916 dma-names = "tx", "rx";
1917 #address-cells = <1>;
1918 #size-cells = <0>;
1923 compatible = "qcom,geni-spi";
1925 clock-names = "se";
1928 pinctrl-names = "default";
1929 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1933 interconnect-names = "qup-core", "qup-config", "qup-memory";
1936 dma-names = "tx", "rx";
1937 #address-cells = <1>;
1938 #size-cells = <0>;
1944 compatible = "qcom,sm8450-trng", "qcom,trng";
1949 compatible = "qcom,pcie-sm8450-pcie0";
1955 reg-names = "parf", "dbi", "elbi", "atu", "config";
1957 linux,pci-domain = <0>;
1958 bus-range = <0x00 0xff>;
1959 num-lanes = <1>;
1961 #address-cells = <3>;
1962 #size-cells = <2>;
1967 msi-map = <0x0 &gic_its 0x5980 0x1>,
1969 msi-map-mask = <0xff00>;
1979 interrupt-names = "msi0",
1988 #interrupt-cells = <1>;
1989 interrupt-map-mask = <0 0 0 0x7>;
1990 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1999 interconnect-names = "pcie-mem", "cpu-pcie";
2013 clock-names = "pipe",
2026 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2030 reset-names = "pci";
2032 power-domains = <&gcc PCIE_0_GDSC>;
2035 phy-names = "pciephy";
2037 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
2038 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
2040 pinctrl-names = "default";
2041 pinctrl-0 = <&pcie0_default_state>;
2043 operating-points-v2 = <&pcie0_opp_table>;
2047 pcie0_opp_table: opp-table {
2048 compatible = "operating-points-v2";
2051 opp-2500000 {
2052 opp-hz = /bits/ 64 <2500000>;
2053 required-opps = <&rpmhpd_opp_low_svs>;
2054 opp-peak-kBps = <250000 1>;
2058 opp-5000000 {
2059 opp-hz = /bits/ 64 <5000000>;
2060 required-opps = <&rpmhpd_opp_low_svs>;
2061 opp-peak-kBps = <500000 1>;
2065 opp-8000000 {
2066 opp-hz = /bits/ 64 <8000000>;
2067 required-opps = <&rpmhpd_opp_nom>;
2068 opp-peak-kBps = <984500 1>;
2075 bus-range = <0x01 0xff>;
2077 #address-cells = <3>;
2078 #size-cells = <2>;
2084 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
2092 clock-names = "aux",
2098 clock-output-names = "pcie_0_pipe_clk";
2099 #clock-cells = <0>;
2101 #phy-cells = <0>;
2104 reset-names = "phy";
2106 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
2107 assigned-clock-rates = <100000000>;
2113 compatible = "qcom,pcie-sm8450-pcie1";
2119 reg-names = "parf", "dbi", "elbi", "atu", "config";
2121 linux,pci-domain = <1>;
2122 bus-range = <0x00 0xff>;
2123 num-lanes = <2>;
2125 #address-cells = <3>;
2126 #size-cells = <2>;
2131 msi-map = <0x0 &gic_its 0x5a00 0x1>,
2133 msi-map-mask = <0xff00>;
2143 interrupt-names = "msi0",
2152 #interrupt-cells = <1>;
2153 interrupt-map-mask = <0 0 0 0x7>;
2154 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2163 interconnect-names = "pcie-mem", "cpu-pcie";
2176 clock-names = "pipe",
2188 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2192 reset-names = "pci";
2194 power-domains = <&gcc PCIE_1_GDSC>;
2197 phy-names = "pciephy";
2199 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
2200 wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
2202 pinctrl-names = "default";
2203 pinctrl-0 = <&pcie1_default_state>;
2205 operating-points-v2 = <&pcie1_opp_table>;
2209 pcie1_opp_table: opp-table {
2210 compatible = "operating-points-v2";
2213 opp-2500000 {
2214 opp-hz = /bits/ 64 <2500000>;
2215 required-opps = <&rpmhpd_opp_low_svs>;
2216 opp-peak-kBps = <250000 1>;
2220 opp-5000000 {
2221 opp-hz = /bits/ 64 <5000000>;
2222 required-opps = <&rpmhpd_opp_low_svs>;
2223 opp-peak-kBps = <500000 1>;
2227 opp-10000000 {
2228 opp-hz = /bits/ 64 <10000000>;
2229 required-opps = <&rpmhpd_opp_low_svs>;
2230 opp-peak-kBps = <1000000 1>;
2234 opp-8000000 {
2235 opp-hz = /bits/ 64 <8000000>;
2236 required-opps = <&rpmhpd_opp_nom>;
2237 opp-peak-kBps = <984500 1>;
2241 opp-16000000 {
2242 opp-hz = /bits/ 64 <16000000>;
2243 required-opps = <&rpmhpd_opp_nom>;
2244 opp-peak-kBps = <1969000 1>;
2248 opp-32000000 {
2249 opp-hz = /bits/ 64 <32000000>;
2250 required-opps = <&rpmhpd_opp_nom>;
2251 opp-peak-kBps = <3938000 1>;
2258 bus-range = <0x01 0xff>;
2260 #address-cells = <3>;
2261 #size-cells = <2>;
2266 pcie1_ep: pcie-ep@1c08000 {
2267 compatible = "qcom,sm8450-pcie-ep";
2275 reg-names = "parf",
2291 clock-names = "aux",
2303 interrupt-names = "global",
2311 interconnect-names = "pcie-mem",
2312 "cpu-pcie";
2316 reset-names = "core";
2317 power-domains = <&gcc PCIE_1_GDSC>;
2319 phy-names = "pciephy";
2320 num-lanes = <2>;
2322 pinctrl-names = "default";
2323 pinctrl-0 = <&pcie1_default_state>;
2329 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
2337 clock-names = "aux",
2343 clock-output-names = "pcie_1_pipe_clk";
2344 #clock-cells = <1>;
2346 #phy-cells = <0>;
2349 reset-names = "phy";
2351 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2352 assigned-clock-rates = <100000000>;
2358 compatible = "qcom,sm8450-config-noc";
2360 #interconnect-cells = <2>;
2361 qcom,bcm-voters = <&apps_bcm_voter>;
2365 compatible = "qcom,sm8450-system-noc";
2367 #interconnect-cells = <2>;
2368 qcom,bcm-voters = <&apps_bcm_voter>;
2372 compatible = "qcom,sm8450-pcie-anoc";
2374 #interconnect-cells = <2>;
2375 qcom,bcm-voters = <&apps_bcm_voter>;
2379 compatible = "qcom,sm8450-aggre1-noc";
2381 #interconnect-cells = <2>;
2384 qcom,bcm-voters = <&apps_bcm_voter>;
2388 compatible = "qcom,sm8450-aggre2-noc";
2390 #interconnect-cells = <2>;
2391 qcom,bcm-voters = <&apps_bcm_voter>;
2399 compatible = "qcom,sm8450-mmss-noc";
2401 #interconnect-cells = <2>;
2402 qcom,bcm-voters = <&apps_bcm_voter>;
2406 compatible = "qcom,tcsr-mutex";
2408 #hwlock-cells = <1>;
2412 compatible = "qcom,sm8450-tcsr", "syscon";
2417 compatible = "qcom,adreno-730.1", "qcom,adreno";
2421 reg-names = "kgsl_3d0_reg_memory",
2430 operating-points-v2 = <&gpu_opp_table>;
2433 #cooling-cells = <2>;
2437 zap-shader {
2438 memory-region = <&gpu_micro_code_mem>;
2441 gpu_opp_table: opp-table {
2442 compatible = "operating-points-v2";
2444 opp-818000000 {
2445 opp-hz = /bits/ 64 <818000000>;
2446 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2449 opp-791000000 {
2450 opp-hz = /bits/ 64 <791000000>;
2451 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2454 opp-734000000 {
2455 opp-hz = /bits/ 64 <734000000>;
2456 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2459 opp-640000000 {
2460 opp-hz = /bits/ 64 <640000000>;
2461 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2464 opp-599000000 {
2465 opp-hz = /bits/ 64 <599000000>;
2466 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2469 opp-545000000 {
2470 opp-hz = /bits/ 64 <545000000>;
2471 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2474 opp-492000000 {
2475 opp-hz = /bits/ 64 <492000000>;
2476 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2479 opp-421000000 {
2480 opp-hz = /bits/ 64 <421000000>;
2481 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
2484 opp-350000000 {
2485 opp-hz = /bits/ 64 <350000000>;
2486 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2489 opp-317000000 {
2490 opp-hz = /bits/ 64 <317000000>;
2491 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2494 opp-285000000 {
2495 opp-hz = /bits/ 64 <285000000>;
2496 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2499 opp-220000000 {
2500 opp-hz = /bits/ 64 <220000000>;
2501 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2507 compatible = "qcom,adreno-gmu-730.1", "qcom,adreno-gmu";
2511 reg-names = "gmu", "rscc", "gmu_pdc";
2515 interrupt-names = "hfi", "gmu";
2524 clock-names = "ahb",
2532 power-domains = <&gpucc GPU_CX_GDSC>,
2534 power-domain-names = "cx",
2541 operating-points-v2 = <&gmu_opp_table>;
2543 gmu_opp_table: opp-table {
2544 compatible = "operating-points-v2";
2546 opp-500000000 {
2547 opp-hz = /bits/ 64 <500000000>;
2548 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2551 opp-200000000 {
2552 opp-hz = /bits/ 64 <200000000>;
2553 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2558 gpucc: clock-controller@3d90000 {
2559 compatible = "qcom,sm8450-gpucc";
2564 #clock-cells = <1>;
2565 #reset-cells = <1>;
2566 #power-domain-cells = <1>;
2570 compatible = "qcom,sm8450-smmu-500", "qcom,adreno-smmu",
2571 "qcom,smmu-500", "arm,mmu-500";
2573 #iommu-cells = <2>;
2574 #global-interrupts = <1>;
2607 clock-names = "gmu",
2613 power-domains = <&gpucc GPU_CX_GDSC>;
2614 dma-coherent;
2618 compatible = "qcom,sm8450-usb-hs-phy",
2619 "qcom,usb-snps-hs-7nm-phy";
2622 #phy-cells = <0>;
2625 clock-names = "ref";
2631 compatible = "qcom,sm8450-qmp-usb3-dp-phy";
2638 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2642 reset-names = "phy", "common";
2644 #clock-cells = <1>;
2645 #phy-cells = <1>;
2647 orientation-switch;
2652 #address-cells = <1>;
2653 #size-cells = <0>;
2666 remote-endpoint = <&usb_1_dwc3_ss>;
2674 remote-endpoint = <&mdss_dp0_out>;
2681 compatible = "qcom,sm8450-slpi-pas";
2684 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2689 interrupt-names = "wdog", "fatal", "ready",
2690 "handover", "stop-ack";
2693 clock-names = "xo";
2695 power-domains = <&rpmhpd RPMHPD_LCX>,
2697 power-domain-names = "lcx", "lmx";
2699 memory-region = <&slpi_mem>;
2703 qcom,smem-states = <&smp2p_slpi_out 0>;
2704 qcom,smem-state-names = "stop";
2708 glink-edge {
2709 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2716 qcom,remote-pid = <3>;
2720 qcom,glink-channels = "fastrpcglink-apps-dsp";
2722 qcom,non-secure-domain;
2723 #address-cells = <1>;
2724 #size-cells = <0>;
2726 compute-cb@1 {
2727 compatible = "qcom,fastrpc-compute-cb";
2732 compute-cb@2 {
2733 compatible = "qcom,fastrpc-compute-cb";
2738 compute-cb@3 {
2739 compatible = "qcom,fastrpc-compute-cb";
2742 /* note: shared-cb = <4> in downstream */
2749 compatible = "qcom,sm8450-adsp-pas";
2752 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2757 interrupt-names = "wdog", "fatal", "ready",
2758 "handover", "stop-ack";
2761 clock-names = "xo";
2763 power-domains = <&rpmhpd RPMHPD_LCX>,
2765 power-domain-names = "lcx", "lmx";
2767 memory-region = <&adsp_mem>;
2771 qcom,smem-states = <&smp2p_adsp_out 0>;
2772 qcom,smem-state-names = "stop";
2776 remoteproc_adsp_glink: glink-edge {
2777 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2784 qcom,remote-pid = <2>;
2788 qcom,glink-channels = "adsp_apps";
2791 #address-cells = <1>;
2792 #size-cells = <0>;
2797 #sound-dai-cells = <0>;
2798 qcom,protection-domain = "avs/audio",
2802 compatible = "qcom,q6apm-dais";
2807 compatible = "qcom,q6apm-lpass-dais";
2808 #sound-dai-cells = <1>;
2815 qcom,protection-domain = "avs/audio",
2818 q6prmcc: clock-controller {
2819 compatible = "qcom,q6prm-lpass-clocks";
2820 #clock-cells = <2>;
2827 qcom,glink-channels = "fastrpcglink-apps-dsp";
2829 qcom,non-secure-domain;
2830 #address-cells = <1>;
2831 #size-cells = <0>;
2833 compute-cb@3 {
2834 compatible = "qcom,fastrpc-compute-cb";
2839 compute-cb@4 {
2840 compatible = "qcom,fastrpc-compute-cb";
2845 compute-cb@5 {
2846 compatible = "qcom,fastrpc-compute-cb";
2855 compatible = "qcom,sm8450-lpass-wsa-macro";
2862 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2864 #clock-cells = <0>;
2865 clock-output-names = "wsa2-mclk";
2866 #sound-dai-cells = <1>;
2870 compatible = "qcom,soundwire-v1.7.0";
2874 clock-names = "iface";
2877 pinctrl-0 = <&wsa2_swr_active>;
2878 pinctrl-names = "default";
2880 qcom,din-ports = <2>;
2881 qcom,dout-ports = <6>;
2883 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2884 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2885 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2886 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2887 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2888 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2889 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2890 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2891 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2893 #address-cells = <2>;
2894 #size-cells = <0>;
2895 #sound-dai-cells = <1>;
2900 compatible = "qcom,sm8450-lpass-rx-macro";
2907 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2909 #clock-cells = <0>;
2910 clock-output-names = "mclk";
2911 #sound-dai-cells = <1>;
2915 compatible = "qcom,soundwire-v1.7.0";
2919 clock-names = "iface";
2921 qcom,din-ports = <0>;
2922 qcom,dout-ports = <5>;
2924 pinctrl-0 = <&rx_swr_active>;
2925 pinctrl-names = "default";
2927 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2928 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2929 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2930 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2931 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2932 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2933 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2934 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2935 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2937 #address-cells = <2>;
2938 #size-cells = <0>;
2939 #sound-dai-cells = <1>;
2944 compatible = "qcom,sm8450-lpass-tx-macro";
2951 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2953 #clock-cells = <0>;
2954 clock-output-names = "mclk";
2955 #sound-dai-cells = <1>;
2959 compatible = "qcom,sm8450-lpass-wsa-macro";
2966 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2968 #clock-cells = <0>;
2969 clock-output-names = "mclk";
2970 #sound-dai-cells = <1>;
2974 compatible = "qcom,soundwire-v1.7.0";
2978 clock-names = "iface";
2981 pinctrl-0 = <&wsa_swr_active>;
2982 pinctrl-names = "default";
2984 qcom,din-ports = <2>;
2985 qcom,dout-ports = <6>;
2987 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2988 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2989 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2990 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2991 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2992 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2993 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2994 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2995 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2997 #address-cells = <2>;
2998 #size-cells = <0>;
2999 #sound-dai-cells = <1>;
3004 compatible = "qcom,soundwire-v1.7.0";
3008 interrupt-names = "core", "wakeup";
3011 clock-names = "iface";
3014 pinctrl-0 = <&tx_swr_active>;
3015 pinctrl-names = "default";
3017 qcom,din-ports = <4>;
3018 qcom,dout-ports = <0>;
3019 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
3020 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
3021 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
3022 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
3023 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
3024 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
3025 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
3026 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
3027 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
3029 #address-cells = <2>;
3030 #size-cells = <0>;
3031 #sound-dai-cells = <1>;
3036 compatible = "qcom,sm8450-lpass-va-macro";
3042 clock-names = "mclk", "macro", "dcodec", "npl";
3044 #clock-cells = <0>;
3045 clock-output-names = "fsgen";
3046 #sound-dai-cells = <1>;
3051 compatible = "qcom,sm8450-cdsp-pas";
3054 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3059 interrupt-names = "wdog", "fatal", "ready",
3060 "handover", "stop-ack";
3063 clock-names = "xo";
3065 power-domains = <&rpmhpd RPMHPD_CX>,
3067 power-domain-names = "cx", "mxc";
3069 memory-region = <&cdsp_mem>;
3073 qcom,smem-states = <&smp2p_cdsp_out 0>;
3074 qcom,smem-state-names = "stop";
3078 glink-edge {
3079 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3086 qcom,remote-pid = <5>;
3090 qcom,glink-channels = "fastrpcglink-apps-dsp";
3092 qcom,non-secure-domain;
3093 #address-cells = <1>;
3094 #size-cells = <0>;
3096 compute-cb@1 {
3097 compatible = "qcom,fastrpc-compute-cb";
3103 compute-cb@2 {
3104 compatible = "qcom,fastrpc-compute-cb";
3110 compute-cb@3 {
3111 compatible = "qcom,fastrpc-compute-cb";
3117 compute-cb@4 {
3118 compatible = "qcom,fastrpc-compute-cb";
3124 compute-cb@5 {
3125 compatible = "qcom,fastrpc-compute-cb";
3131 compute-cb@6 {
3132 compatible = "qcom,fastrpc-compute-cb";
3138 compute-cb@7 {
3139 compatible = "qcom,fastrpc-compute-cb";
3145 compute-cb@8 {
3146 compatible = "qcom,fastrpc-compute-cb";
3158 compatible = "qcom,sm8450-mpss-pas";
3161 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
3167 interrupt-names = "wdog", "fatal", "ready", "handover",
3168 "stop-ack", "shutdown-ack";
3171 clock-names = "xo";
3173 power-domains = <&rpmhpd RPMHPD_CX>,
3175 power-domain-names = "cx", "mss";
3177 memory-region = <&mpss_mem>;
3181 qcom,smem-states = <&smp2p_modem_out 0>;
3182 qcom,smem-state-names = "stop";
3186 glink-edge {
3187 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
3193 qcom,remote-pid = <1>;
3197 videocc: clock-controller@aaf0000 {
3198 compatible = "qcom,sm8450-videocc";
3202 power-domains = <&rpmhpd RPMHPD_MMCX>;
3203 required-opps = <&rpmhpd_opp_low_svs>;
3204 #clock-cells = <1>;
3205 #reset-cells = <1>;
3206 #power-domain-cells = <1>;
3210 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
3213 power-domains = <&camcc TITAN_TOP_GDSC>;
3220 clock-names = "camnoc_axi",
3225 pinctrl-0 = <&cci0_default &cci1_default>;
3226 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
3227 pinctrl-names = "default", "sleep";
3230 #address-cells = <1>;
3231 #size-cells = <0>;
3233 cci0_i2c0: i2c-bus@0 {
3235 clock-frequency = <1000000>;
3236 #address-cells = <1>;
3237 #size-cells = <0>;
3240 cci0_i2c1: i2c-bus@1 {
3242 clock-frequency = <1000000>;
3243 #address-cells = <1>;
3244 #size-cells = <0>;
3249 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
3252 power-domains = <&camcc TITAN_TOP_GDSC>;
3259 clock-names = "camnoc_axi",
3264 pinctrl-0 = <&cci2_default &cci3_default>;
3265 pinctrl-1 = <&cci2_sleep &cci3_sleep>;
3266 pinctrl-names = "default", "sleep";
3269 #address-cells = <1>;
3270 #size-cells = <0>;
3272 cci1_i2c0: i2c-bus@0 {
3274 clock-frequency = <1000000>;
3275 #address-cells = <1>;
3276 #size-cells = <0>;
3279 cci1_i2c1: i2c-bus@1 {
3281 clock-frequency = <1000000>;
3282 #address-cells = <1>;
3283 #size-cells = <0>;
3287 camcc: clock-controller@ade0000 {
3288 compatible = "qcom,sm8450-camcc";
3294 power-domains = <&rpmhpd RPMHPD_MMCX>;
3295 required-opps = <&rpmhpd_opp_low_svs>;
3296 #clock-cells = <1>;
3297 #reset-cells = <1>;
3298 #power-domain-cells = <1>;
3302 mdss: display-subsystem@ae00000 {
3303 compatible = "qcom,sm8450-mdss";
3305 reg-names = "mdss";
3312 interconnect-names = "mdp0-mem",
3313 "mdp1-mem",
3314 "cpu-cfg";
3318 power-domains = <&dispcc MDSS_GDSC>;
3326 interrupt-controller;
3327 #interrupt-cells = <1>;
3331 #address-cells = <2>;
3332 #size-cells = <2>;
3337 mdss_mdp: display-controller@ae01000 {
3338 compatible = "qcom,sm8450-dpu";
3341 reg-names = "mdp", "vbif";
3349 clock-names = "bus",
3356 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3357 assigned-clock-rates = <19200000>;
3359 operating-points-v2 = <&mdp_opp_table>;
3360 power-domains = <&rpmhpd RPMHPD_MMCX>;
3362 interrupt-parent = <&mdss>;
3366 #address-cells = <1>;
3367 #size-cells = <0>;
3372 remote-endpoint = <&mdss_dsi0_in>;
3379 remote-endpoint = <&mdss_dsi1_in>;
3386 remote-endpoint = <&mdss_dp0_in>;
3391 mdp_opp_table: opp-table {
3392 compatible = "operating-points-v2";
3394 opp-172000000 {
3395 opp-hz = /bits/ 64 <172000000>;
3396 required-opps = <&rpmhpd_opp_low_svs_d1>;
3399 opp-200000000 {
3400 opp-hz = /bits/ 64 <200000000>;
3401 required-opps = <&rpmhpd_opp_low_svs>;
3404 opp-325000000 {
3405 opp-hz = /bits/ 64 <325000000>;
3406 required-opps = <&rpmhpd_opp_svs>;
3409 opp-375000000 {
3410 opp-hz = /bits/ 64 <375000000>;
3411 required-opps = <&rpmhpd_opp_svs_l1>;
3414 opp-500000000 {
3415 opp-hz = /bits/ 64 <500000000>;
3416 required-opps = <&rpmhpd_opp_nom>;
3421 mdss_dp0: displayport-controller@ae90000 {
3422 compatible = "qcom,sm8450-dp", "qcom,sm8350-dp";
3428 interrupt-parent = <&mdss>;
3435 clock-names = "core_iface",
3441 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
3443 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3447 phy-names = "dp";
3449 #sound-dai-cells = <0>;
3451 operating-points-v2 = <&dp_opp_table>;
3452 power-domains = <&rpmhpd RPMHPD_MMCX>;
3457 #address-cells = <1>;
3458 #size-cells = <0>;
3463 remote-endpoint = <&dpu_intf0_out>;
3471 remote-endpoint = <&usb_1_qmpphy_dp_in>;
3476 dp_opp_table: opp-table {
3477 compatible = "operating-points-v2";
3479 opp-160000000 {
3480 opp-hz = /bits/ 64 <160000000>;
3481 required-opps = <&rpmhpd_opp_low_svs>;
3484 opp-270000000 {
3485 opp-hz = /bits/ 64 <270000000>;
3486 required-opps = <&rpmhpd_opp_svs>;
3489 opp-540000000 {
3490 opp-hz = /bits/ 64 <540000000>;
3491 required-opps = <&rpmhpd_opp_svs_l1>;
3494 opp-810000000 {
3495 opp-hz = /bits/ 64 <810000000>;
3496 required-opps = <&rpmhpd_opp_nom>;
3502 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3504 reg-names = "dsi_ctrl";
3506 interrupt-parent = <&mdss>;
3515 clock-names = "byte",
3522 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
3524 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
3527 operating-points-v2 = <&mdss_dsi_opp_table>;
3528 power-domains = <&rpmhpd RPMHPD_MMCX>;
3531 phy-names = "dsi";
3533 #address-cells = <1>;
3534 #size-cells = <0>;
3539 #address-cells = <1>;
3540 #size-cells = <0>;
3545 remote-endpoint = <&dpu_intf1_out>;
3556 mdss_dsi_opp_table: opp-table {
3557 compatible = "operating-points-v2";
3559 opp-187500000 {
3560 opp-hz = /bits/ 64 <187500000>;
3561 required-opps = <&rpmhpd_opp_low_svs>;
3564 opp-300000000 {
3565 opp-hz = /bits/ 64 <300000000>;
3566 required-opps = <&rpmhpd_opp_svs>;
3569 opp-358000000 {
3570 opp-hz = /bits/ 64 <358000000>;
3571 required-opps = <&rpmhpd_opp_svs_l1>;
3577 compatible = "qcom,sm8450-dsi-phy-5nm";
3581 reg-names = "dsi_phy",
3585 #clock-cells = <1>;
3586 #phy-cells = <0>;
3590 clock-names = "iface", "ref";
3596 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3598 reg-names = "dsi_ctrl";
3600 interrupt-parent = <&mdss>;
3609 clock-names = "byte",
3616 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
3618 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
3621 operating-points-v2 = <&mdss_dsi_opp_table>;
3622 power-domains = <&rpmhpd RPMHPD_MMCX>;
3625 phy-names = "dsi";
3627 #address-cells = <1>;
3628 #size-cells = <0>;
3633 #address-cells = <1>;
3634 #size-cells = <0>;
3639 remote-endpoint = <&dpu_intf2_out>;
3652 compatible = "qcom,sm8450-dsi-phy-5nm";
3656 reg-names = "dsi_phy",
3660 #clock-cells = <1>;
3661 #phy-cells = <0>;
3665 clock-names = "iface", "ref";
3671 dispcc: clock-controller@af00000 {
3672 compatible = "qcom,sm8450-dispcc";
3690 power-domains = <&rpmhpd RPMHPD_MMCX>;
3691 required-opps = <&rpmhpd_opp_low_svs>;
3692 #clock-cells = <1>;
3693 #reset-cells = <1>;
3694 #power-domain-cells = <1>;
3697 pdc: interrupt-controller@b220000 {
3698 compatible = "qcom,sm8450-pdc", "qcom,pdc";
3700 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
3702 #interrupt-cells = <2>;
3703 interrupt-parent = <&intc>;
3704 interrupt-controller;
3707 tsens0: thermal-sensor@c263000 {
3708 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3714 interrupt-names = "uplow", "critical";
3715 #thermal-sensor-cells = <1>;
3718 tsens1: thermal-sensor@c265000 {
3719 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3725 interrupt-names = "uplow", "critical";
3726 #thermal-sensor-cells = <1>;
3729 aoss_qmp: power-management@c300000 {
3730 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
3732 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3736 #clock-cells = <0>;
3740 compatible = "qcom,rpmh-stats";
3746 compatible = "qcom,spmi-pmic-arb";
3752 reg-names = "core",
3757 interrupt-names = "periph_irq";
3758 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3761 interrupt-controller;
3762 #interrupt-cells = <4>;
3763 #address-cells = <2>;
3764 #size-cells = <0>;
3768 compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
3771 interrupt-controller;
3772 #interrupt-cells = <3>;
3773 #mbox-cells = <2>;
3777 compatible = "qcom,sm8450-tlmm";
3780 gpio-controller;
3781 #gpio-cells = <2>;
3782 interrupt-controller;
3783 #interrupt-cells = <2>;
3784 gpio-ranges = <&tlmm 0 0 211>;
3785 wakeup-parent = <&pdc>;
3787 sdc2_default_state: sdc2-default-state {
3788 clk-pins {
3790 drive-strength = <16>;
3791 bias-disable;
3794 cmd-pins {
3796 drive-strength = <16>;
3797 bias-pull-up;
3800 data-pins {
3802 drive-strength = <16>;
3803 bias-pull-up;
3807 sdc2_sleep_state: sdc2-sleep-state {
3808 clk-pins {
3810 drive-strength = <2>;
3811 bias-disable;
3814 cmd-pins {
3816 drive-strength = <2>;
3817 bias-pull-up;
3820 data-pins {
3822 drive-strength = <2>;
3823 bias-pull-up;
3827 cci0_default: cci0-default-state {
3831 drive-strength = <2>;
3832 bias-pull-up;
3835 cci0_sleep: cci0-sleep-state {
3839 drive-strength = <2>;
3840 bias-pull-down;
3843 cci1_default: cci1-default-state {
3847 drive-strength = <2>;
3848 bias-pull-up;
3851 cci1_sleep: cci1-sleep-state {
3855 drive-strength = <2>;
3856 bias-pull-down;
3859 cci2_default: cci2-default-state {
3863 drive-strength = <2>;
3864 bias-pull-up;
3867 cci2_sleep: cci2-sleep-state {
3871 drive-strength = <2>;
3872 bias-pull-down;
3875 cci3_default: cci3-default-state {
3879 drive-strength = <2>;
3880 bias-pull-up;
3883 cci3_sleep: cci3-sleep-state {
3887 drive-strength = <2>;
3888 bias-pull-down;
3891 pcie0_default_state: pcie0-default-state {
3892 perst-pins {
3895 drive-strength = <2>;
3896 bias-pull-down;
3899 clkreq-pins {
3902 drive-strength = <2>;
3903 bias-pull-up;
3906 wake-pins {
3909 drive-strength = <2>;
3910 bias-pull-up;
3914 pcie1_default_state: pcie1-default-state {
3915 perst-pins {
3918 drive-strength = <2>;
3919 bias-pull-down;
3922 clkreq-pins {
3925 drive-strength = <2>;
3926 bias-pull-up;
3929 wake-pins {
3932 drive-strength = <2>;
3933 bias-pull-up;
3937 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3942 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3947 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3952 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3957 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3962 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3967 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3972 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3977 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3982 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3987 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3992 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3997 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
4000 drive-strength = <2>;
4001 bias-pull-up;
4004 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
4007 drive-strength = <2>;
4008 bias-pull-up;
4011 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
4016 qup_i2c16_data_clk: qup-i2c16-data-clk-state {
4021 qup_i2c17_data_clk: qup-i2c17-data-clk-state {
4026 qup_i2c18_data_clk: qup-i2c18-data-clk-state {
4031 qup_i2c19_data_clk: qup-i2c19-data-clk-state {
4036 qup_i2c20_data_clk: qup-i2c20-data-clk-state {
4041 qup_i2c21_data_clk: qup-i2c21-data-clk-state {
4046 qup_spi0_cs: qup-spi0-cs-state {
4051 qup_spi0_data_clk: qup-spi0-data-clk-state {
4056 qup_spi1_cs: qup-spi1-cs-state {
4061 qup_spi1_data_clk: qup-spi1-data-clk-state {
4066 qup_spi2_cs: qup-spi2-cs-state {
4071 qup_spi2_data_clk: qup-spi2-data-clk-state {
4076 qup_spi3_cs: qup-spi3-cs-state {
4081 qup_spi3_data_clk: qup-spi3-data-clk-state {
4086 qup_spi4_cs: qup-spi4-cs-state {
4089 drive-strength = <6>;
4090 bias-disable;
4093 qup_spi4_data_clk: qup-spi4-data-clk-state {
4098 qup_spi5_cs: qup-spi5-cs-state {
4103 qup_spi5_data_clk: qup-spi5-data-clk-state {
4108 qup_spi6_cs: qup-spi6-cs-state {
4113 qup_spi6_data_clk: qup-spi6-data-clk-state {
4118 qup_spi8_cs: qup-spi8-cs-state {
4123 qup_spi8_data_clk: qup-spi8-data-clk-state {
4128 qup_spi9_cs: qup-spi9-cs-state {
4133 qup_spi9_data_clk: qup-spi9-data-clk-state {
4138 qup_spi10_cs: qup-spi10-cs-state {
4143 qup_spi10_data_clk: qup-spi10-data-clk-state {
4148 qup_spi11_cs: qup-spi11-cs-state {
4153 qup_spi11_data_clk: qup-spi11-data-clk-state {
4158 qup_spi12_cs: qup-spi12-cs-state {
4163 qup_spi12_data_clk: qup-spi12-data-clk-state {
4168 qup_spi13_cs: qup-spi13-cs-state {
4173 qup_spi13_data_clk: qup-spi13-data-clk-state {
4178 qup_spi14_cs: qup-spi14-cs-state {
4183 qup_spi14_data_clk: qup-spi14-data-clk-state {
4188 qup_spi15_cs: qup-spi15-cs-state {
4193 qup_spi15_data_clk: qup-spi15-data-clk-state {
4198 qup_spi16_cs: qup-spi16-cs-state {
4203 qup_spi16_data_clk: qup-spi16-data-clk-state {
4208 qup_spi17_cs: qup-spi17-cs-state {
4213 qup_spi17_data_clk: qup-spi17-data-clk-state {
4218 qup_spi18_cs: qup-spi18-cs-state {
4221 drive-strength = <6>;
4222 bias-disable;
4225 qup_spi18_data_clk: qup-spi18-data-clk-state {
4228 drive-strength = <6>;
4229 bias-disable;
4232 qup_spi19_cs: qup-spi19-cs-state {
4235 drive-strength = <6>;
4236 bias-disable;
4239 qup_spi19_data_clk: qup-spi19-data-clk-state {
4242 drive-strength = <6>;
4243 bias-disable;
4246 qup_spi20_cs: qup-spi20-cs-state {
4251 qup_spi20_data_clk: qup-spi20-data-clk-state {
4256 qup_spi21_cs: qup-spi21-cs-state {
4261 qup_spi21_data_clk: qup-spi21-data-clk-state {
4266 qup_uart7_rx: qup-uart7-rx-state {
4269 drive-strength = <2>;
4270 bias-disable;
4273 qup_uart7_tx: qup-uart7-tx-state {
4276 drive-strength = <2>;
4277 bias-disable;
4280 qup_uart20_default: qup-uart20-default-state {
4287 compatible = "qcom,sm8450-lpass-lpi-pinctrl";
4290 gpio-controller;
4291 #gpio-cells = <2>;
4292 gpio-ranges = <&lpass_tlmm 0 0 23>;
4296 clock-names = "core", "audio";
4298 tx_swr_active: tx-swr-active-state {
4299 clk-pins {
4302 drive-strength = <2>;
4303 slew-rate = <1>;
4304 bias-disable;
4307 data-pins {
4310 drive-strength = <2>;
4311 slew-rate = <1>;
4312 bias-bus-hold;
4316 rx_swr_active: rx-swr-active-state {
4317 clk-pins {
4320 drive-strength = <2>;
4321 slew-rate = <1>;
4322 bias-disable;
4325 data-pins {
4328 drive-strength = <2>;
4329 slew-rate = <1>;
4330 bias-bus-hold;
4334 dmic01_default: dmic01-default-state {
4335 clk-pins {
4338 drive-strength = <8>;
4339 output-high;
4342 data-pins {
4345 drive-strength = <8>;
4349 dmic23_default: dmic23-default-state {
4350 clk-pins {
4353 drive-strength = <8>;
4354 output-high;
4357 data-pins {
4360 drive-strength = <8>;
4364 wsa_swr_active: wsa-swr-active-state {
4365 clk-pins {
4368 drive-strength = <2>;
4369 slew-rate = <1>;
4370 bias-disable;
4373 data-pins {
4376 drive-strength = <2>;
4377 slew-rate = <1>;
4378 bias-bus-hold;
4382 wsa2_swr_active: wsa2-swr-active-state {
4383 clk-pins {
4386 drive-strength = <2>;
4387 slew-rate = <1>;
4388 bias-disable;
4391 data-pins {
4394 drive-strength = <2>;
4395 slew-rate = <1>;
4396 bias-bus-hold;
4402 compatible = "arm,coresight-stm", "arm,primecell";
4405 reg-names = "stm-base", "stm-stimulus-base";
4408 clock-names = "apb_pclk";
4410 out-ports {
4413 remote-endpoint =
4421 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
4425 clock-names = "apb_pclk";
4427 in-ports {
4428 #address-cells = <1>;
4429 #size-cells = <0>;
4434 remote-endpoint =
4440 out-ports {
4443 remote-endpoint =
4451 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
4456 clock-names = "apb_pclk";
4458 in-ports {
4459 #address-cells = <1>;
4460 #size-cells = <0>;
4465 remote-endpoint =
4473 remote-endpoint =
4479 out-ports {
4482 remote-endpoint =
4490 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
4494 clock-names = "apb_pclk";
4496 in-ports {
4497 #address-cells = <1>;
4498 #size-cells = <0>;
4503 remote-endpoint =
4511 remote-endpoint =
4517 out-ports {
4520 remote-endpoint =
4528 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
4532 clock-names = "apb_pclk";
4534 in-ports {
4537 remote-endpoint =
4543 out-ports {
4547 remote-endpoint =
4555 compatible = "arm,coresight-tmc", "arm,primecell";
4559 arm,buffer-size = <0x10000>;
4561 arm,scatter-gather;
4563 clock-names = "apb_pclk";
4565 in-ports {
4568 remote-endpoint =
4576 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
4580 clock-names = "apb_pclk";
4582 in-ports {
4585 remote-endpoint =
4591 out-ports {
4596 remote-endpoint =
4604 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
4609 clock-names = "apb_pclk";
4611 in-ports {
4612 #address-cells = <1>;
4613 #size-cells = <0>;
4618 remote-endpoint =
4626 remote-endpoint =
4632 out-ports {
4635 remote-endpoint =
4643 compatible = "arm,coresight-tmc", "arm,primecell";
4647 clock-names = "apb_pclk";
4649 in-ports {
4652 remote-endpoint =
4658 out-ports {
4661 remote-endpoint =
4669 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
4672 qcom,replicator-loses-context;
4674 clock-names = "apb_pclk";
4676 in-ports {
4679 remote-endpoint =
4685 out-ports {
4689 remote-endpoint =
4697 compatible = "qcom,coresight-tpda", "arm,primecell";
4702 clock-names = "apb_pclk";
4704 in-ports {
4706 #address-cells = <1>;
4707 #size-cells = <0>;
4712 remote-endpoint =
4720 remote-endpoint =
4726 out-ports {
4730 remote-endpoint =
4738 compatible = "qcom,coresight-tpdm", "arm,primecell";
4743 clock-names = "apb_pclk";
4745 out-ports {
4748 remote-endpoint =
4756 compatible = "qcom,coresight-tpdm", "arm,primecell";
4760 clock-names = "apb_pclk";
4762 out-ports {
4765 remote-endpoint =
4773 compatible = "qcom,coresight-tpdm", "arm,primecell";
4777 clock-names = "apb_pclk";
4779 out-ports {
4782 remote-endpoint =
4790 compatible = "qcom,coresight-tpdm", "arm,primecell";
4794 clock-names = "apb_pclk";
4796 out-ports {
4799 remote-endpoint =
4807 compatible = "arm,coresight-cti", "arm,primecell";
4811 clock-names = "apb_pclk";
4815 compatible = "arm,coresight-cti", "arm,primecell";
4819 clock-names = "apb_pclk";
4823 compatible = "qcom,coresight-tpda", "arm,primecell";
4827 clock-names = "apb_pclk";
4829 in-ports {
4831 #address-cells = <1>;
4832 #size-cells = <0>;
4837 remote-endpoint =
4845 remote-endpoint =
4851 out-ports {
4855 remote-endpoint =
4863 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
4867 clock-names = "apb_pclk";
4869 in-ports {
4873 remote-endpoint =
4879 out-ports {
4882 remote-endpoint =
4890 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
4895 clock-names = "apb_pclk";
4897 in-ports {
4901 remote-endpoint =
4907 out-ports {
4910 remote-endpoint =
4918 compatible = "arm,coresight-cti", "arm,primecell";
4922 clock-names = "apb_pclk";
4926 compatible = "arm,coresight-cti", "arm,primecell";
4930 clock-names = "apb_pclk";
4934 compatible = "arm,coresight-cti", "arm,primecell";
4938 clock-names = "apb_pclk";
4942 compatible = "qcom,sm8450-imem", "syscon", "simple-mfd";
4946 #address-cells = <1>;
4947 #size-cells = <1>;
4949 pil-reloc@94c {
4950 compatible = "qcom,pil-reloc-info";
4956 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
4958 #iommu-cells = <2>;
4959 #global-interrupts = <1>;
5057 dma-coherent;
5060 intc: interrupt-controller@17100000 {
5061 compatible = "arm,gic-v3";
5062 #interrupt-cells = <3>;
5063 interrupt-controller;
5064 #redistributor-regions = <1>;
5065 redistributor-stride = <0x0 0x40000>;
5069 #address-cells = <2>;
5070 #size-cells = <2>;
5073 gic_its: msi-controller@17140000 {
5074 compatible = "arm,gic-v3-its";
5076 msi-controller;
5077 #msi-cells = <1>;
5082 compatible = "arm,armv7-timer-mem";
5083 #address-cells = <1>;
5084 #size-cells = <1>;
5087 clock-frequency = <19200000>;
5090 frame-number = <0>;
5098 frame-number = <1>;
5105 frame-number = <2>;
5112 frame-number = <3>;
5119 frame-number = <4>;
5126 frame-number = <5>;
5133 frame-number = <6>;
5142 compatible = "qcom,rpmh-rsc";
5147 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
5151 qcom,tcs-offset = <0xd00>;
5152 qcom,drv-id = <2>;
5153 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
5155 power-domains = <&cluster_pd>;
5157 apps_bcm_voter: bcm-voter {
5158 compatible = "qcom,bcm-voter";
5161 rpmhcc: clock-controller {
5162 compatible = "qcom,sm8450-rpmh-clk";
5163 #clock-cells = <1>;
5164 clock-names = "xo";
5168 rpmhpd: power-controller {
5169 compatible = "qcom,sm8450-rpmhpd";
5170 #power-domain-cells = <1>;
5171 operating-points-v2 = <&rpmhpd_opp_table>;
5173 rpmhpd_opp_table: opp-table {
5174 compatible = "operating-points-v2";
5177 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5181 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5185 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
5189 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5193 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
5197 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5201 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
5205 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5209 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
5213 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5217 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5221 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5225 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5229 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5236 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
5240 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
5242 clock-names = "xo", "alternate";
5246 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
5247 #freq-domain-cells = <1>;
5248 #clock-cells = <1>;
5252 compatible = "qcom,sm8450-gem-noc";
5254 #interconnect-cells = <2>;
5255 qcom,bcm-voters = <&apps_bcm_voter>;
5258 system-cache-controller@19200000 {
5259 compatible = "qcom,sm8450-llcc";
5263 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
5270 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
5271 "jedec,ufs-2.0";
5275 phy-names = "ufsphy";
5276 lanes-per-direction = <2>;
5277 #reset-cells = <1>;
5279 reset-names = "rst";
5281 power-domains = <&gcc UFS_PHY_GDSC>;
5284 dma-coherent;
5288 interconnect-names = "ufs-ddr", "cpu-ufs";
5289 clock-names =
5307 freq-table-hz =
5322 compatible = "qcom,sm8450-qmp-ufs-phy";
5325 clock-names = "ref", "ref_aux", "qref";
5330 power-domains = <&gcc UFS_PHY_GDSC>;
5333 reset-names = "ufsphy";
5335 #clock-cells = <1>;
5336 #phy-cells = <0>;
5342 compatible = "qcom,sm8450-inline-crypto-engine",
5343 "qcom,inline-crypto-engine";
5348 cryptobam: dma-controller@1dc4000 {
5349 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
5352 #dma-cells = <1>;
5354 qcom,num-ees = <4>;
5355 num-channels = <16>;
5356 qcom,controlled-remotely;
5365 compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce";
5368 dma-names = "rx", "tx";
5375 interconnect-names = "memory";
5379 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5";
5384 interrupt-names = "hc_irq", "pwr_irq";
5389 clock-names = "iface", "core", "xo";
5393 interconnect-names = "sdhc-ddr","cpu-sdhc";
5395 power-domains = <&rpmhpd RPMHPD_CX>;
5396 operating-points-v2 = <&sdhc2_opp_table>;
5397 bus-width = <4>;
5398 dma-coherent;
5400 /* Forbid SDR104/SDR50 - broken hw! */
5401 sdhci-caps-mask = <0x3 0x0>;
5405 sdhc2_opp_table: opp-table {
5406 compatible = "operating-points-v2";
5408 opp-100000000 {
5409 opp-hz = /bits/ 64 <100000000>;
5410 required-opps = <&rpmhpd_opp_low_svs>;
5413 opp-202000000 {
5414 opp-hz = /bits/ 64 <202000000>;
5415 required-opps = <&rpmhpd_opp_svs_l1>;
5421 compatible = "qcom,sm8450-dwc3", "qcom,dwc3";
5424 #address-cells = <2>;
5425 #size-cells = <2>;
5434 clock-names = "cfg_noc",
5441 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
5443 assigned-clock-rates = <19200000>, <200000000>;
5445 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
5450 interrupt-names = "pwr_event",
5456 power-domains = <&gcc USB30_PRIM_GDSC>;
5462 interconnect-names = "usb-ddr", "apps-usb";
5472 snps,dis-u1-entry-quirk;
5473 snps,dis-u2-entry-quirk;
5475 phy-names = "usb2-phy", "usb3-phy";
5478 #address-cells = <1>;
5479 #size-cells = <0>;
5492 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
5500 compatible = "qcom,sm8450-nsp-noc";
5502 #interconnect-cells = <2>;
5503 qcom,bcm-voters = <&apps_bcm_voter>;
5507 compatible = "qcom,sm8450-lpass-ag-noc";
5509 #interconnect-cells = <2>;
5510 qcom,bcm-voters = <&apps_bcm_voter>;
5517 thermal-zones {
5518 aoss0-thermal {
5519 thermal-sensors = <&tsens0 0>;
5522 thermal-engine-config {
5528 reset-mon-cfg {
5536 cpuss0-thermal {
5537 thermal-sensors = <&tsens0 1>;
5540 thermal-engine-config {
5546 reset-mon-cfg {
5554 cpuss1-thermal {
5555 thermal-sensors = <&tsens0 2>;
5558 thermal-engine-config {
5564 reset-mon-cfg {
5572 cpuss3-thermal {
5573 thermal-sensors = <&tsens0 3>;
5576 thermal-engine-config {
5582 reset-mon-cfg {
5590 cpuss4-thermal {
5591 thermal-sensors = <&tsens0 4>;
5594 thermal-engine-config {
5600 reset-mon-cfg {
5608 cpu4-top-thermal {
5609 thermal-sensors = <&tsens0 5>;
5612 cpu4_top_alert0: trip-point0 {
5618 cpu4_top_alert1: trip-point1 {
5624 cpu4_top_crit: cpu-crit {
5632 cpu4-bottom-thermal {
5633 thermal-sensors = <&tsens0 6>;
5636 cpu4_bottom_alert0: trip-point0 {
5642 cpu4_bottom_alert1: trip-point1 {
5648 cpu4_bottom_crit: cpu-crit {
5656 cpu5-top-thermal {
5657 thermal-sensors = <&tsens0 7>;
5660 cpu5_top_alert0: trip-point0 {
5666 cpu5_top_alert1: trip-point1 {
5672 cpu5_top_crit: cpu-crit {
5680 cpu5-bottom-thermal {
5681 thermal-sensors = <&tsens0 8>;
5684 cpu5_bottom_alert0: trip-point0 {
5690 cpu5_bottom_alert1: trip-point1 {
5696 cpu5_bottom_crit: cpu-crit {
5704 cpu6-top-thermal {
5705 thermal-sensors = <&tsens0 9>;
5708 cpu6_top_alert0: trip-point0 {
5714 cpu6_top_alert1: trip-point1 {
5720 cpu6_top_crit: cpu-crit {
5728 cpu6-bottom-thermal {
5729 thermal-sensors = <&tsens0 10>;
5732 cpu6_bottom_alert0: trip-point0 {
5738 cpu6_bottom_alert1: trip-point1 {
5744 cpu6_bottom_crit: cpu-crit {
5752 cpu7-top-thermal {
5753 thermal-sensors = <&tsens0 11>;
5756 cpu7_top_alert0: trip-point0 {
5762 cpu7_top_alert1: trip-point1 {
5768 cpu7_top_crit: cpu-crit {
5776 cpu7-middle-thermal {
5777 thermal-sensors = <&tsens0 12>;
5780 cpu7_middle_alert0: trip-point0 {
5786 cpu7_middle_alert1: trip-point1 {
5792 cpu7_middle_crit: cpu-crit {
5800 cpu7-bottom-thermal {
5801 thermal-sensors = <&tsens0 13>;
5804 cpu7_bottom_alert0: trip-point0 {
5810 cpu7_bottom_alert1: trip-point1 {
5816 cpu7_bottom_crit: cpu-crit {
5824 gpu-top-thermal {
5825 polling-delay-passive = <10>;
5827 thermal-sensors = <&tsens0 14>;
5829 cooling-maps {
5832 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5837 gpu_top_alert0: trip-point0 {
5843 trip-point1 {
5849 trip-point2 {
5857 gpu-bottom-thermal {
5858 polling-delay-passive = <10>;
5860 thermal-sensors = <&tsens0 15>;
5862 cooling-maps {
5865 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5870 gpu_bottom_alert0: trip-point0 {
5876 trip-point1 {
5882 trip-point2 {
5890 aoss1-thermal {
5891 thermal-sensors = <&tsens1 0>;
5894 thermal-engine-config {
5900 reset-mon-cfg {
5908 cpu0-thermal {
5909 thermal-sensors = <&tsens1 1>;
5912 cpu0_alert0: trip-point0 {
5918 cpu0_alert1: trip-point1 {
5924 cpu0_crit: cpu-crit {
5932 cpu1-thermal {
5933 thermal-sensors = <&tsens1 2>;
5936 cpu1_alert0: trip-point0 {
5942 cpu1_alert1: trip-point1 {
5948 cpu1_crit: cpu-crit {
5956 cpu2-thermal {
5957 thermal-sensors = <&tsens1 3>;
5960 cpu2_alert0: trip-point0 {
5966 cpu2_alert1: trip-point1 {
5972 cpu2_crit: cpu-crit {
5980 cpu3-thermal {
5981 thermal-sensors = <&tsens1 4>;
5984 cpu3_alert0: trip-point0 {
5990 cpu3_alert1: trip-point1 {
5996 cpu3_crit: cpu-crit {
6004 cdsp0-thermal {
6005 polling-delay-passive = <10>;
6007 thermal-sensors = <&tsens1 5>;
6010 thermal-engine-config {
6016 thermal-hal-config {
6022 reset-mon-cfg {
6028 cdsp_0_config: junction-config {
6036 cdsp1-thermal {
6037 polling-delay-passive = <10>;
6039 thermal-sensors = <&tsens1 6>;
6042 thermal-engine-config {
6048 thermal-hal-config {
6054 reset-mon-cfg {
6060 cdsp_1_config: junction-config {
6068 cdsp2-thermal {
6069 polling-delay-passive = <10>;
6071 thermal-sensors = <&tsens1 7>;
6074 thermal-engine-config {
6080 thermal-hal-config {
6086 reset-mon-cfg {
6092 cdsp_2_config: junction-config {
6100 video-thermal {
6101 thermal-sensors = <&tsens1 8>;
6104 thermal-engine-config {
6110 reset-mon-cfg {
6118 mem-thermal {
6119 polling-delay-passive = <10>;
6121 thermal-sensors = <&tsens1 9>;
6124 thermal-engine-config {
6130 ddr_config0: ddr0-config {
6136 reset-mon-cfg {
6144 modem0-thermal {
6145 thermal-sensors = <&tsens1 10>;
6148 thermal-engine-config {
6154 mdmss0_config0: mdmss0-config0 {
6160 mdmss0_config1: mdmss0-config1 {
6166 reset-mon-cfg {
6174 modem1-thermal {
6175 thermal-sensors = <&tsens1 11>;
6178 thermal-engine-config {
6184 mdmss1_config0: mdmss1-config0 {
6190 mdmss1_config1: mdmss1-config1 {
6196 reset-mon-cfg {
6204 modem2-thermal {
6205 thermal-sensors = <&tsens1 12>;
6208 thermal-engine-config {
6214 mdmss2_config0: mdmss2-config0 {
6220 mdmss2_config1: mdmss2-config1 {
6226 reset-mon-cfg {
6234 modem3-thermal {
6235 thermal-sensors = <&tsens1 13>;
6238 thermal-engine-config {
6244 mdmss3_config0: mdmss3-config0 {
6250 mdmss3_config1: mdmss3-config1 {
6256 reset-mon-cfg {
6264 camera0-thermal {
6265 thermal-sensors = <&tsens1 14>;
6268 thermal-engine-config {
6274 reset-mon-cfg {
6282 camera1-thermal {
6283 thermal-sensors = <&tsens1 15>;
6286 thermal-engine-config {
6292 reset-mon-cfg {
6302 compatible = "arm,armv8-timer";
6307 clock-frequency = <19200000>;