Lines Matching +full:dload +full:- +full:mode
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
8 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/clock/qcom,sm8450-camcc.h>
11 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
12 #include <dt-bindings/clock/qcom,sm8450-gpucc.h>
13 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
14 #include <dt-bindings/dma/qcom-gpi.h>
15 #include <dt-bindings/firmware/qcom,scm.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/mailbox/qcom-ipcc.h>
18 #include <dt-bindings/phy/phy-qcom-qmp.h>
19 #include <dt-bindings/power/qcom,rpmhpd.h>
20 #include <dt-bindings/power/qcom-rpmpd.h>
21 #include <dt-bindings/interconnect/qcom,icc.h>
22 #include <dt-bindings/interconnect/qcom,sm8450.h>
23 #include <dt-bindings/reset/qcom,sm8450-gpucc.h>
24 #include <dt-bindings/soc/qcom,gpr.h>
25 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
26 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
27 #include <dt-bindings/thermal/thermal.h>
30 interrupt-parent = <&intc>;
32 #address-cells = <2>;
33 #size-cells = <2>;
38 xo_board: xo-board {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 clock-frequency = <76800000>;
44 sleep_clk: sleep-clk {
45 compatible = "fixed-clock";
46 #clock-cells = <0>;
47 clock-frequency = <32764>;
52 #address-cells = <2>;
53 #size-cells = <0>;
59 enable-method = "psci";
60 next-level-cache = <&l2_0>;
61 power-domains = <&cpu_pd0>;
62 power-domain-names = "psci";
63 qcom,freq-domain = <&cpufreq_hw 0>;
64 #cooling-cells = <2>;
66 l2_0: l2-cache {
68 cache-level = <2>;
69 cache-unified;
70 next-level-cache = <&l3_0>;
71 l3_0: l3-cache {
73 cache-level = <3>;
74 cache-unified;
83 enable-method = "psci";
84 next-level-cache = <&l2_100>;
85 power-domains = <&cpu_pd1>;
86 power-domain-names = "psci";
87 qcom,freq-domain = <&cpufreq_hw 0>;
88 #cooling-cells = <2>;
90 l2_100: l2-cache {
92 cache-level = <2>;
93 cache-unified;
94 next-level-cache = <&l3_0>;
102 enable-method = "psci";
103 next-level-cache = <&l2_200>;
104 power-domains = <&cpu_pd2>;
105 power-domain-names = "psci";
106 qcom,freq-domain = <&cpufreq_hw 0>;
107 #cooling-cells = <2>;
109 l2_200: l2-cache {
111 cache-level = <2>;
112 cache-unified;
113 next-level-cache = <&l3_0>;
121 enable-method = "psci";
122 next-level-cache = <&l2_300>;
123 power-domains = <&cpu_pd3>;
124 power-domain-names = "psci";
125 qcom,freq-domain = <&cpufreq_hw 0>;
126 #cooling-cells = <2>;
128 l2_300: l2-cache {
130 cache-level = <2>;
131 cache-unified;
132 next-level-cache = <&l3_0>;
140 enable-method = "psci";
141 next-level-cache = <&l2_400>;
142 power-domains = <&cpu_pd4>;
143 power-domain-names = "psci";
144 qcom,freq-domain = <&cpufreq_hw 1>;
145 #cooling-cells = <2>;
147 l2_400: l2-cache {
149 cache-level = <2>;
150 cache-unified;
151 next-level-cache = <&l3_0>;
159 enable-method = "psci";
160 next-level-cache = <&l2_500>;
161 power-domains = <&cpu_pd5>;
162 power-domain-names = "psci";
163 qcom,freq-domain = <&cpufreq_hw 1>;
164 #cooling-cells = <2>;
166 l2_500: l2-cache {
168 cache-level = <2>;
169 cache-unified;
170 next-level-cache = <&l3_0>;
178 enable-method = "psci";
179 next-level-cache = <&l2_600>;
180 power-domains = <&cpu_pd6>;
181 power-domain-names = "psci";
182 qcom,freq-domain = <&cpufreq_hw 1>;
183 #cooling-cells = <2>;
185 l2_600: l2-cache {
187 cache-level = <2>;
188 cache-unified;
189 next-level-cache = <&l3_0>;
197 enable-method = "psci";
198 next-level-cache = <&l2_700>;
199 power-domains = <&cpu_pd7>;
200 power-domain-names = "psci";
201 qcom,freq-domain = <&cpufreq_hw 2>;
202 #cooling-cells = <2>;
204 l2_700: l2-cache {
206 cache-level = <2>;
207 cache-unified;
208 next-level-cache = <&l3_0>;
212 cpu-map {
248 idle-states {
249 entry-method = "psci";
251 little_cpu_sleep_0: cpu-sleep-0-0 {
252 compatible = "arm,idle-state";
253 idle-state-name = "silver-rail-power-collapse";
254 arm,psci-suspend-param = <0x40000004>;
255 entry-latency-us = <800>;
256 exit-latency-us = <750>;
257 min-residency-us = <4090>;
258 local-timer-stop;
261 big_cpu_sleep_0: cpu-sleep-1-0 {
262 compatible = "arm,idle-state";
263 idle-state-name = "gold-rail-power-collapse";
264 arm,psci-suspend-param = <0x40000004>;
265 entry-latency-us = <600>;
266 exit-latency-us = <1550>;
267 min-residency-us = <4791>;
268 local-timer-stop;
272 domain-idle-states {
273 cluster_sleep_0: cluster-sleep-0 {
274 compatible = "domain-idle-state";
275 arm,psci-suspend-param = <0x41000044>;
276 entry-latency-us = <1050>;
277 exit-latency-us = <2500>;
278 min-residency-us = <5309>;
281 cluster_sleep_1: cluster-sleep-1 {
282 compatible = "domain-idle-state";
283 arm,psci-suspend-param = <0x4100c344>;
284 entry-latency-us = <2700>;
285 exit-latency-us = <3500>;
286 min-residency-us = <13959>;
291 ete-0 {
292 compatible = "arm,embedded-trace-extension";
295 out-ports {
298 remote-endpoint = <&funnel_ete_in_ete0>;
304 ete-1 {
305 compatible = "arm,embedded-trace-extension";
308 out-ports {
311 remote-endpoint = <&funnel_ete_in_ete1>;
317 ete-2 {
318 compatible = "arm,embedded-trace-extension";
321 out-ports {
324 remote-endpoint = <&funnel_ete_in_ete2>;
330 ete-3 {
331 compatible = "arm,embedded-trace-extension";
334 out-ports {
337 remote-endpoint = <&funnel_ete_in_ete3>;
343 ete-4 {
344 compatible = "arm,embedded-trace-extension";
347 out-ports {
350 remote-endpoint = <&funnel_ete_in_ete4>;
356 ete-5 {
357 compatible = "arm,embedded-trace-extension";
360 out-ports {
363 remote-endpoint = <&funnel_ete_in_ete5>;
369 ete-6 {
370 compatible = "arm,embedded-trace-extension";
373 out-ports {
376 remote-endpoint = <&funnel_ete_in_ete6>;
382 ete-7 {
383 compatible = "arm,embedded-trace-extension";
386 out-ports {
389 remote-endpoint = <&funnel_ete_in_ete7>;
395 funnel-ete {
396 compatible = "arm,coresight-static-funnel";
398 out-ports {
401 remote-endpoint =
407 in-ports {
408 #address-cells = <1>;
409 #size-cells = <0>;
414 remote-endpoint =
422 remote-endpoint =
430 remote-endpoint =
438 remote-endpoint =
446 remote-endpoint =
454 remote-endpoint =
462 remote-endpoint =
470 remote-endpoint =
479 compatible = "qcom,scm-sm8450", "qcom,scm";
480 qcom,dload-mode = <&tcsr 0x13000>;
482 #reset-cells = <1>;
486 clk_virt: interconnect-0 {
487 compatible = "qcom,sm8450-clk-virt";
488 #interconnect-cells = <2>;
489 qcom,bcm-voters = <&apps_bcm_voter>;
492 mc_virt: interconnect-1 {
493 compatible = "qcom,sm8450-mc-virt";
494 #interconnect-cells = <2>;
495 qcom,bcm-voters = <&apps_bcm_voter>;
505 compatible = "arm,armv8-pmuv3";
510 compatible = "arm,psci-1.0";
513 cpu_pd0: power-domain-cpu0 {
514 #power-domain-cells = <0>;
515 power-domains = <&cluster_pd>;
516 domain-idle-states = <&little_cpu_sleep_0>;
519 cpu_pd1: power-domain-cpu1 {
520 #power-domain-cells = <0>;
521 power-domains = <&cluster_pd>;
522 domain-idle-states = <&little_cpu_sleep_0>;
525 cpu_pd2: power-domain-cpu2 {
526 #power-domain-cells = <0>;
527 power-domains = <&cluster_pd>;
528 domain-idle-states = <&little_cpu_sleep_0>;
531 cpu_pd3: power-domain-cpu3 {
532 #power-domain-cells = <0>;
533 power-domains = <&cluster_pd>;
534 domain-idle-states = <&little_cpu_sleep_0>;
537 cpu_pd4: power-domain-cpu4 {
538 #power-domain-cells = <0>;
539 power-domains = <&cluster_pd>;
540 domain-idle-states = <&big_cpu_sleep_0>;
543 cpu_pd5: power-domain-cpu5 {
544 #power-domain-cells = <0>;
545 power-domains = <&cluster_pd>;
546 domain-idle-states = <&big_cpu_sleep_0>;
549 cpu_pd6: power-domain-cpu6 {
550 #power-domain-cells = <0>;
551 power-domains = <&cluster_pd>;
552 domain-idle-states = <&big_cpu_sleep_0>;
555 cpu_pd7: power-domain-cpu7 {
556 #power-domain-cells = <0>;
557 power-domains = <&cluster_pd>;
558 domain-idle-states = <&big_cpu_sleep_0>;
561 cluster_pd: power-domain-cpu-cluster0 {
562 #power-domain-cells = <0>;
563 domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>;
567 qup_opp_table_100mhz: opp-table-qup {
568 compatible = "operating-points-v2";
570 opp-50000000 {
571 opp-hz = /bits/ 64 <50000000>;
572 required-opps = <&rpmhpd_opp_min_svs>;
575 opp-75000000 {
576 opp-hz = /bits/ 64 <75000000>;
577 required-opps = <&rpmhpd_opp_low_svs>;
580 opp-100000000 {
581 opp-hz = /bits/ 64 <100000000>;
582 required-opps = <&rpmhpd_opp_svs>;
586 reserved_memory: reserved-memory {
587 #address-cells = <2>;
588 #size-cells = <2>;
593 no-map;
598 no-map;
603 no-map;
608 no-map;
613 no-map;
617 compatible = "qcom,cmd-db";
619 no-map;
624 no-map;
629 no-map;
634 no-map;
639 no-map;
647 no-map;
652 no-map;
657 no-map;
662 no-map;
667 no-map;
672 no-map;
677 no-map;
682 no-map;
687 no-map;
692 no-map;
697 no-map;
703 no-map;
709 no-map;
714 no-map;
719 no-map;
724 no-map;
728 compatible = "qcom,rmtfs-mem";
730 no-map;
732 qcom,client-id = <1>;
738 no-map;
743 no-map;
752 no-map;
757 no-map;
762 no-map;
767 no-map;
772 no-map;
777 no-map;
782 no-map;
787 no-map;
792 no-map;
797 no-map;
802 no-map;
807 no-map;
812 no-map;
817 no-map;
821 smp2p-adsp {
824 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
830 qcom,local-pid = <0>;
831 qcom,remote-pid = <2>;
833 smp2p_adsp_out: master-kernel {
834 qcom,entry-name = "master-kernel";
835 #qcom,smem-state-cells = <1>;
838 smp2p_adsp_in: slave-kernel {
839 qcom,entry-name = "slave-kernel";
840 interrupt-controller;
841 #interrupt-cells = <2>;
845 smp2p-cdsp {
848 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
854 qcom,local-pid = <0>;
855 qcom,remote-pid = <5>;
857 smp2p_cdsp_out: master-kernel {
858 qcom,entry-name = "master-kernel";
859 #qcom,smem-state-cells = <1>;
862 smp2p_cdsp_in: slave-kernel {
863 qcom,entry-name = "slave-kernel";
864 interrupt-controller;
865 #interrupt-cells = <2>;
869 smp2p-modem {
872 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
878 qcom,local-pid = <0>;
879 qcom,remote-pid = <1>;
881 smp2p_modem_out: master-kernel {
882 qcom,entry-name = "master-kernel";
883 #qcom,smem-state-cells = <1>;
886 smp2p_modem_in: slave-kernel {
887 qcom,entry-name = "slave-kernel";
888 interrupt-controller;
889 #interrupt-cells = <2>;
892 ipa_smp2p_out: ipa-ap-to-modem {
893 qcom,entry-name = "ipa";
894 #qcom,smem-state-cells = <1>;
897 ipa_smp2p_in: ipa-modem-to-ap {
898 qcom,entry-name = "ipa";
899 interrupt-controller;
900 #interrupt-cells = <2>;
904 smp2p-slpi {
907 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
913 qcom,local-pid = <0>;
914 qcom,remote-pid = <3>;
916 smp2p_slpi_out: master-kernel {
917 qcom,entry-name = "master-kernel";
918 #qcom,smem-state-cells = <1>;
921 smp2p_slpi_in: slave-kernel {
922 qcom,entry-name = "slave-kernel";
923 interrupt-controller;
924 #interrupt-cells = <2>;
929 #address-cells = <2>;
930 #size-cells = <2>;
932 dma-ranges = <0 0 0 0 0x10 0>;
933 compatible = "simple-bus";
935 gcc: clock-controller@100000 {
936 compatible = "qcom,gcc-sm8450";
938 #clock-cells = <1>;
939 #reset-cells = <1>;
940 #power-domain-cells = <1>;
950 clock-names = "bi_tcxo",
961 gpi_dma2: dma-controller@800000 {
962 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
963 #dma-cells = <3>;
977 dma-channels = <12>;
978 dma-channel-mask = <0x7e>;
984 compatible = "qcom,geni-se-qup";
986 clock-names = "m-ahb", "s-ahb";
990 #address-cells = <2>;
991 #size-cells = <2>;
996 compatible = "qcom,geni-i2c";
998 clock-names = "se";
1000 pinctrl-names = "default";
1001 pinctrl-0 = <&qup_i2c15_data_clk>;
1003 #address-cells = <1>;
1004 #size-cells = <0>;
1008 interconnect-names = "qup-core", "qup-config", "qup-memory";
1011 dma-names = "tx", "rx";
1016 compatible = "qcom,geni-spi";
1018 clock-names = "se";
1021 pinctrl-names = "default";
1022 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1025 interconnect-names = "qup-core", "qup-config";
1028 dma-names = "tx", "rx";
1029 #address-cells = <1>;
1030 #size-cells = <0>;
1035 compatible = "qcom,geni-i2c";
1037 clock-names = "se";
1039 pinctrl-names = "default";
1040 pinctrl-0 = <&qup_i2c16_data_clk>;
1042 #address-cells = <1>;
1043 #size-cells = <0>;
1047 interconnect-names = "qup-core", "qup-config", "qup-memory";
1050 dma-names = "tx", "rx";
1055 compatible = "qcom,geni-spi";
1057 clock-names = "se";
1060 pinctrl-names = "default";
1061 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
1064 interconnect-names = "qup-core", "qup-config";
1067 dma-names = "tx", "rx";
1068 #address-cells = <1>;
1069 #size-cells = <0>;
1074 compatible = "qcom,geni-i2c";
1076 clock-names = "se";
1078 pinctrl-names = "default";
1079 pinctrl-0 = <&qup_i2c17_data_clk>;
1081 #address-cells = <1>;
1082 #size-cells = <0>;
1086 interconnect-names = "qup-core", "qup-config", "qup-memory";
1089 dma-names = "tx", "rx";
1094 compatible = "qcom,geni-spi";
1096 clock-names = "se";
1099 pinctrl-names = "default";
1100 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
1103 interconnect-names = "qup-core", "qup-config";
1106 dma-names = "tx", "rx";
1107 #address-cells = <1>;
1108 #size-cells = <0>;
1113 compatible = "qcom,geni-i2c";
1115 clock-names = "se";
1117 pinctrl-names = "default";
1118 pinctrl-0 = <&qup_i2c18_data_clk>;
1120 #address-cells = <1>;
1121 #size-cells = <0>;
1125 interconnect-names = "qup-core", "qup-config", "qup-memory";
1128 dma-names = "tx", "rx";
1133 compatible = "qcom,geni-spi";
1135 clock-names = "se";
1138 pinctrl-names = "default";
1139 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
1142 interconnect-names = "qup-core", "qup-config";
1145 dma-names = "tx", "rx";
1146 #address-cells = <1>;
1147 #size-cells = <0>;
1152 compatible = "qcom,geni-i2c";
1154 clock-names = "se";
1156 pinctrl-names = "default";
1157 pinctrl-0 = <&qup_i2c19_data_clk>;
1159 #address-cells = <1>;
1160 #size-cells = <0>;
1164 interconnect-names = "qup-core", "qup-config", "qup-memory";
1167 dma-names = "tx", "rx";
1172 compatible = "qcom,geni-spi";
1174 clock-names = "se";
1177 pinctrl-names = "default";
1178 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
1181 interconnect-names = "qup-core", "qup-config";
1184 dma-names = "tx", "rx";
1185 #address-cells = <1>;
1186 #size-cells = <0>;
1191 compatible = "qcom,geni-i2c";
1193 clock-names = "se";
1195 pinctrl-names = "default";
1196 pinctrl-0 = <&qup_i2c20_data_clk>;
1198 #address-cells = <1>;
1199 #size-cells = <0>;
1203 interconnect-names = "qup-core", "qup-config", "qup-memory";
1206 dma-names = "tx", "rx";
1211 compatible = "qcom,geni-uart";
1213 clock-names = "se";
1215 pinctrl-names = "default";
1216 pinctrl-0 = <&qup_uart20_default>;
1222 interconnect-names = "qup-core",
1223 "qup-config";
1228 compatible = "qcom,geni-spi";
1230 clock-names = "se";
1233 pinctrl-names = "default";
1234 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1237 interconnect-names = "qup-core", "qup-config";
1240 dma-names = "tx", "rx";
1241 #address-cells = <1>;
1242 #size-cells = <0>;
1247 compatible = "qcom,geni-i2c";
1249 clock-names = "se";
1251 pinctrl-names = "default";
1252 pinctrl-0 = <&qup_i2c21_data_clk>;
1254 #address-cells = <1>;
1255 #size-cells = <0>;
1259 interconnect-names = "qup-core", "qup-config", "qup-memory";
1262 dma-names = "tx", "rx";
1267 compatible = "qcom,geni-spi";
1269 clock-names = "se";
1272 pinctrl-names = "default";
1273 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1276 interconnect-names = "qup-core", "qup-config";
1279 dma-names = "tx", "rx";
1280 #address-cells = <1>;
1281 #size-cells = <0>;
1286 gpi_dma0: dma-controller@900000 {
1287 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1288 #dma-cells = <3>;
1302 dma-channels = <12>;
1303 dma-channel-mask = <0x7e>;
1309 compatible = "qcom,geni-se-qup";
1311 clock-names = "m-ahb", "s-ahb";
1316 interconnect-names = "qup-core";
1317 #address-cells = <2>;
1318 #size-cells = <2>;
1323 compatible = "qcom,geni-i2c";
1325 clock-names = "se";
1327 pinctrl-names = "default";
1328 pinctrl-0 = <&qup_i2c0_data_clk>;
1330 #address-cells = <1>;
1331 #size-cells = <0>;
1335 interconnect-names = "qup-core", "qup-config", "qup-memory";
1338 dma-names = "tx", "rx";
1343 compatible = "qcom,geni-spi";
1345 clock-names = "se";
1348 pinctrl-names = "default";
1349 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1350 power-domains = <&rpmhpd RPMHPD_CX>;
1351 operating-points-v2 = <&qup_opp_table_100mhz>;
1355 interconnect-names = "qup-core", "qup-config", "qup-memory";
1358 dma-names = "tx", "rx";
1359 #address-cells = <1>;
1360 #size-cells = <0>;
1365 compatible = "qcom,geni-i2c";
1367 clock-names = "se";
1369 pinctrl-names = "default";
1370 pinctrl-0 = <&qup_i2c1_data_clk>;
1372 #address-cells = <1>;
1373 #size-cells = <0>;
1377 interconnect-names = "qup-core", "qup-config", "qup-memory";
1380 dma-names = "tx", "rx";
1385 compatible = "qcom,geni-spi";
1387 clock-names = "se";
1390 pinctrl-names = "default";
1391 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1395 interconnect-names = "qup-core", "qup-config", "qup-memory";
1398 dma-names = "tx", "rx";
1399 #address-cells = <1>;
1400 #size-cells = <0>;
1405 compatible = "qcom,geni-i2c";
1407 clock-names = "se";
1409 pinctrl-names = "default";
1410 pinctrl-0 = <&qup_i2c2_data_clk>;
1412 #address-cells = <1>;
1413 #size-cells = <0>;
1417 interconnect-names = "qup-core", "qup-config", "qup-memory";
1420 dma-names = "tx", "rx";
1425 compatible = "qcom,geni-spi";
1427 clock-names = "se";
1430 pinctrl-names = "default";
1431 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1435 interconnect-names = "qup-core", "qup-config", "qup-memory";
1438 dma-names = "tx", "rx";
1439 #address-cells = <1>;
1440 #size-cells = <0>;
1446 compatible = "qcom,geni-i2c";
1448 clock-names = "se";
1450 pinctrl-names = "default";
1451 pinctrl-0 = <&qup_i2c3_data_clk>;
1453 #address-cells = <1>;
1454 #size-cells = <0>;
1458 interconnect-names = "qup-core", "qup-config", "qup-memory";
1461 dma-names = "tx", "rx";
1466 compatible = "qcom,geni-spi";
1468 clock-names = "se";
1471 pinctrl-names = "default";
1472 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1476 interconnect-names = "qup-core", "qup-config", "qup-memory";
1479 dma-names = "tx", "rx";
1480 #address-cells = <1>;
1481 #size-cells = <0>;
1486 compatible = "qcom,geni-i2c";
1488 clock-names = "se";
1490 pinctrl-names = "default";
1491 pinctrl-0 = <&qup_i2c4_data_clk>;
1493 #address-cells = <1>;
1494 #size-cells = <0>;
1498 interconnect-names = "qup-core", "qup-config", "qup-memory";
1501 dma-names = "tx", "rx";
1506 compatible = "qcom,geni-spi";
1508 clock-names = "se";
1511 pinctrl-names = "default";
1512 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1513 power-domains = <&rpmhpd RPMHPD_CX>;
1514 operating-points-v2 = <&qup_opp_table_100mhz>;
1518 interconnect-names = "qup-core", "qup-config", "qup-memory";
1521 dma-names = "tx", "rx";
1522 #address-cells = <1>;
1523 #size-cells = <0>;
1528 compatible = "qcom,geni-i2c";
1530 clock-names = "se";
1532 pinctrl-names = "default";
1533 pinctrl-0 = <&qup_i2c5_data_clk>;
1535 #address-cells = <1>;
1536 #size-cells = <0>;
1540 interconnect-names = "qup-core", "qup-config", "qup-memory";
1543 dma-names = "tx", "rx";
1548 compatible = "qcom,geni-spi";
1550 clock-names = "se";
1553 pinctrl-names = "default";
1554 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1558 interconnect-names = "qup-core", "qup-config", "qup-memory";
1561 dma-names = "tx", "rx";
1562 #address-cells = <1>;
1563 #size-cells = <0>;
1569 compatible = "qcom,geni-i2c";
1571 clock-names = "se";
1573 pinctrl-names = "default";
1574 pinctrl-0 = <&qup_i2c6_data_clk>;
1576 #address-cells = <1>;
1577 #size-cells = <0>;
1581 interconnect-names = "qup-core", "qup-config", "qup-memory";
1584 dma-names = "tx", "rx";
1589 compatible = "qcom,geni-spi";
1591 clock-names = "se";
1594 pinctrl-names = "default";
1595 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1599 interconnect-names = "qup-core", "qup-config", "qup-memory";
1602 dma-names = "tx", "rx";
1603 #address-cells = <1>;
1604 #size-cells = <0>;
1609 compatible = "qcom,geni-debug-uart";
1611 clock-names = "se";
1613 pinctrl-names = "default";
1614 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1620 interconnect-names = "qup-core",
1621 "qup-config";
1626 gpi_dma1: dma-controller@a00000 {
1627 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1628 #dma-cells = <3>;
1642 dma-channels = <12>;
1643 dma-channel-mask = <0x7e>;
1649 compatible = "qcom,geni-se-qup";
1651 clock-names = "m-ahb", "s-ahb";
1656 interconnect-names = "qup-core";
1657 #address-cells = <2>;
1658 #size-cells = <2>;
1663 compatible = "qcom,geni-i2c";
1665 clock-names = "se";
1667 pinctrl-names = "default";
1668 pinctrl-0 = <&qup_i2c8_data_clk>;
1670 #address-cells = <1>;
1671 #size-cells = <0>;
1675 interconnect-names = "qup-core", "qup-config", "qup-memory";
1678 dma-names = "tx", "rx";
1683 compatible = "qcom,geni-spi";
1685 clock-names = "se";
1688 pinctrl-names = "default";
1689 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1693 interconnect-names = "qup-core", "qup-config", "qup-memory";
1696 dma-names = "tx", "rx";
1697 #address-cells = <1>;
1698 #size-cells = <0>;
1703 compatible = "qcom,geni-i2c";
1705 clock-names = "se";
1707 pinctrl-names = "default";
1708 pinctrl-0 = <&qup_i2c9_data_clk>;
1710 #address-cells = <1>;
1711 #size-cells = <0>;
1715 interconnect-names = "qup-core", "qup-config", "qup-memory";
1718 dma-names = "tx", "rx";
1723 compatible = "qcom,geni-spi";
1725 clock-names = "se";
1728 pinctrl-names = "default";
1729 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1733 interconnect-names = "qup-core", "qup-config", "qup-memory";
1736 dma-names = "tx", "rx";
1737 #address-cells = <1>;
1738 #size-cells = <0>;
1743 compatible = "qcom,geni-i2c";
1745 clock-names = "se";
1747 pinctrl-names = "default";
1748 pinctrl-0 = <&qup_i2c10_data_clk>;
1750 #address-cells = <1>;
1751 #size-cells = <0>;
1755 interconnect-names = "qup-core", "qup-config", "qup-memory";
1758 dma-names = "tx", "rx";
1763 compatible = "qcom,geni-spi";
1765 clock-names = "se";
1768 pinctrl-names = "default";
1769 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1773 interconnect-names = "qup-core", "qup-config", "qup-memory";
1776 dma-names = "tx", "rx";
1777 #address-cells = <1>;
1778 #size-cells = <0>;
1783 compatible = "qcom,geni-i2c";
1785 clock-names = "se";
1787 pinctrl-names = "default";
1788 pinctrl-0 = <&qup_i2c11_data_clk>;
1790 #address-cells = <1>;
1791 #size-cells = <0>;
1795 interconnect-names = "qup-core", "qup-config", "qup-memory";
1798 dma-names = "tx", "rx";
1803 compatible = "qcom,geni-spi";
1805 clock-names = "se";
1808 pinctrl-names = "default";
1809 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1813 interconnect-names = "qup-core", "qup-config", "qup-memory";
1816 dma-names = "tx", "rx";
1817 #address-cells = <1>;
1818 #size-cells = <0>;
1823 compatible = "qcom,geni-i2c";
1825 clock-names = "se";
1827 pinctrl-names = "default";
1828 pinctrl-0 = <&qup_i2c12_data_clk>;
1830 #address-cells = <1>;
1831 #size-cells = <0>;
1835 interconnect-names = "qup-core", "qup-config", "qup-memory";
1838 dma-names = "tx", "rx";
1843 compatible = "qcom,geni-spi";
1845 clock-names = "se";
1848 pinctrl-names = "default";
1849 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1853 interconnect-names = "qup-core", "qup-config", "qup-memory";
1856 dma-names = "tx", "rx";
1857 #address-cells = <1>;
1858 #size-cells = <0>;
1863 compatible = "qcom,geni-i2c";
1865 clock-names = "se";
1867 pinctrl-names = "default";
1868 pinctrl-0 = <&qup_i2c13_data_clk>;
1873 interconnect-names = "qup-core", "qup-config", "qup-memory";
1876 dma-names = "tx", "rx";
1877 #address-cells = <1>;
1878 #size-cells = <0>;
1883 compatible = "qcom,geni-spi";
1885 clock-names = "se";
1888 pinctrl-names = "default";
1889 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1893 interconnect-names = "qup-core", "qup-config", "qup-memory";
1896 dma-names = "tx", "rx";
1897 #address-cells = <1>;
1898 #size-cells = <0>;
1903 compatible = "qcom,geni-i2c";
1905 clock-names = "se";
1907 pinctrl-names = "default";
1908 pinctrl-0 = <&qup_i2c14_data_clk>;
1913 interconnect-names = "qup-core", "qup-config", "qup-memory";
1916 dma-names = "tx", "rx";
1917 #address-cells = <1>;
1918 #size-cells = <0>;
1923 compatible = "qcom,geni-spi";
1925 clock-names = "se";
1928 pinctrl-names = "default";
1929 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1933 interconnect-names = "qup-core", "qup-config", "qup-memory";
1936 dma-names = "tx", "rx";
1937 #address-cells = <1>;
1938 #size-cells = <0>;
1944 compatible = "qcom,sm8450-trng", "qcom,trng";
1949 compatible = "qcom,pcie-sm8450-pcie0";
1955 reg-names = "parf", "dbi", "elbi", "atu", "config";
1957 linux,pci-domain = <0>;
1958 bus-range = <0x00 0xff>;
1959 num-lanes = <1>;
1961 #address-cells = <3>;
1962 #size-cells = <2>;
1967 msi-map = <0x0 &gic_its 0x5980 0x1>,
1969 msi-map-mask = <0xff00>;
1979 interrupt-names = "msi0",
1988 #interrupt-cells = <1>;
1989 interrupt-map-mask = <0 0 0 0x7>;
1990 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1999 interconnect-names = "pcie-mem", "cpu-pcie";
2013 clock-names = "pipe",
2026 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2030 reset-names = "pci";
2032 power-domains = <&gcc PCIE_0_GDSC>;
2035 phy-names = "pciephy";
2037 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
2038 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
2040 pinctrl-names = "default";
2041 pinctrl-0 = <&pcie0_default_state>;
2043 operating-points-v2 = <&pcie0_opp_table>;
2047 pcie0_opp_table: opp-table {
2048 compatible = "operating-points-v2";
2051 opp-2500000 {
2052 opp-hz = /bits/ 64 <2500000>;
2053 required-opps = <&rpmhpd_opp_low_svs>;
2054 opp-peak-kBps = <250000 1>;
2055 opp-level = <1>;
2059 opp-5000000 {
2060 opp-hz = /bits/ 64 <5000000>;
2061 required-opps = <&rpmhpd_opp_low_svs>;
2062 opp-peak-kBps = <500000 1>;
2063 opp-level = <2>;
2067 opp-8000000 {
2068 opp-hz = /bits/ 64 <8000000>;
2069 required-opps = <&rpmhpd_opp_nom>;
2070 opp-peak-kBps = <984500 1>;
2071 opp-level = <3>;
2078 bus-range = <0x01 0xff>;
2080 #address-cells = <3>;
2081 #size-cells = <2>;
2087 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
2095 clock-names = "aux",
2101 clock-output-names = "pcie_0_pipe_clk";
2102 #clock-cells = <0>;
2104 #phy-cells = <0>;
2107 reset-names = "phy";
2109 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
2110 assigned-clock-rates = <100000000>;
2116 compatible = "qcom,pcie-sm8450-pcie1";
2122 reg-names = "parf", "dbi", "elbi", "atu", "config";
2124 linux,pci-domain = <1>;
2125 bus-range = <0x00 0xff>;
2126 num-lanes = <2>;
2128 #address-cells = <3>;
2129 #size-cells = <2>;
2134 msi-map = <0x0 &gic_its 0x5a00 0x1>,
2136 msi-map-mask = <0xff00>;
2146 interrupt-names = "msi0",
2155 #interrupt-cells = <1>;
2156 interrupt-map-mask = <0 0 0 0x7>;
2157 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2166 interconnect-names = "pcie-mem", "cpu-pcie";
2179 clock-names = "pipe",
2191 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2195 reset-names = "pci";
2197 power-domains = <&gcc PCIE_1_GDSC>;
2200 phy-names = "pciephy";
2202 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
2203 wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
2205 pinctrl-names = "default";
2206 pinctrl-0 = <&pcie1_default_state>;
2208 operating-points-v2 = <&pcie1_opp_table>;
2212 pcie1_opp_table: opp-table {
2213 compatible = "operating-points-v2";
2216 opp-2500000-1 {
2217 opp-hz = /bits/ 64 <2500000>;
2218 required-opps = <&rpmhpd_opp_low_svs>;
2219 opp-peak-kBps = <250000 1>;
2220 opp-level = <1>;
2224 opp-5000000-1 {
2225 opp-hz = /bits/ 64 <5000000>;
2226 required-opps = <&rpmhpd_opp_low_svs>;
2227 opp-peak-kBps = <500000 1>;
2228 opp-level = <1>;
2232 opp-5000000-2 {
2233 opp-hz = /bits/ 64 <5000000>;
2234 required-opps = <&rpmhpd_opp_low_svs>;
2235 opp-peak-kBps = <500000 1>;
2236 opp-level = <2>;
2240 opp-10000000-2 {
2241 opp-hz = /bits/ 64 <10000000>;
2242 required-opps = <&rpmhpd_opp_low_svs>;
2243 opp-peak-kBps = <1000000 1>;
2244 opp-level = <2>;
2248 opp-8000000-3 {
2249 opp-hz = /bits/ 64 <8000000>;
2250 required-opps = <&rpmhpd_opp_nom>;
2251 opp-peak-kBps = <984500 1>;
2252 opp-level = <3>;
2256 opp-16000000-3 {
2257 opp-hz = /bits/ 64 <16000000>;
2258 required-opps = <&rpmhpd_opp_nom>;
2259 opp-peak-kBps = <1969000 1>;
2260 opp-level = <3>;
2264 opp-16000000-4 {
2265 opp-hz = /bits/ 64 <16000000>;
2266 required-opps = <&rpmhpd_opp_nom>;
2267 opp-peak-kBps = <1969000 1>;
2268 opp-level = <4>;
2272 opp-32000000-4 {
2273 opp-hz = /bits/ 64 <32000000>;
2274 required-opps = <&rpmhpd_opp_nom>;
2275 opp-peak-kBps = <3938000 1>;
2276 opp-level = <4>;
2283 bus-range = <0x01 0xff>;
2285 #address-cells = <3>;
2286 #size-cells = <2>;
2291 pcie1_ep: pcie-ep@1c08000 {
2292 compatible = "qcom,sm8450-pcie-ep";
2300 reg-names = "parf",
2316 clock-names = "aux",
2328 interrupt-names = "global",
2336 interconnect-names = "pcie-mem",
2337 "cpu-pcie";
2341 reset-names = "core";
2342 power-domains = <&gcc PCIE_1_GDSC>;
2344 phy-names = "pciephy";
2345 num-lanes = <2>;
2347 pinctrl-names = "default";
2348 pinctrl-0 = <&pcie1_default_state>;
2354 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
2362 clock-names = "aux",
2368 clock-output-names = "pcie_1_pipe_clk";
2369 #clock-cells = <1>;
2371 #phy-cells = <0>;
2374 reset-names = "phy";
2376 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2377 assigned-clock-rates = <100000000>;
2383 compatible = "qcom,sm8450-config-noc";
2385 #interconnect-cells = <2>;
2386 qcom,bcm-voters = <&apps_bcm_voter>;
2390 compatible = "qcom,sm8450-system-noc";
2392 #interconnect-cells = <2>;
2393 qcom,bcm-voters = <&apps_bcm_voter>;
2397 compatible = "qcom,sm8450-pcie-anoc";
2399 #interconnect-cells = <2>;
2400 qcom,bcm-voters = <&apps_bcm_voter>;
2404 compatible = "qcom,sm8450-aggre1-noc";
2406 #interconnect-cells = <2>;
2409 qcom,bcm-voters = <&apps_bcm_voter>;
2413 compatible = "qcom,sm8450-aggre2-noc";
2415 #interconnect-cells = <2>;
2416 qcom,bcm-voters = <&apps_bcm_voter>;
2424 compatible = "qcom,sm8450-mmss-noc";
2426 #interconnect-cells = <2>;
2427 qcom,bcm-voters = <&apps_bcm_voter>;
2431 compatible = "qcom,tcsr-mutex";
2433 #hwlock-cells = <1>;
2437 compatible = "qcom,sm8450-tcsr", "syscon";
2442 compatible = "qcom,adreno-730.1", "qcom,adreno";
2446 reg-names = "kgsl_3d0_reg_memory",
2455 operating-points-v2 = <&gpu_opp_table>;
2458 #cooling-cells = <2>;
2462 gpu_zap_shader: zap-shader {
2463 memory-region = <&gpu_micro_code_mem>;
2466 gpu_opp_table: opp-table {
2467 compatible = "operating-points-v2";
2469 opp-818000000 {
2470 opp-hz = /bits/ 64 <818000000>;
2471 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2474 opp-791000000 {
2475 opp-hz = /bits/ 64 <791000000>;
2476 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2479 opp-734000000 {
2480 opp-hz = /bits/ 64 <734000000>;
2481 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2484 opp-640000000 {
2485 opp-hz = /bits/ 64 <640000000>;
2486 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2489 opp-599000000 {
2490 opp-hz = /bits/ 64 <599000000>;
2491 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2494 opp-545000000 {
2495 opp-hz = /bits/ 64 <545000000>;
2496 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2499 opp-492000000 {
2500 opp-hz = /bits/ 64 <492000000>;
2501 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2504 opp-421000000 {
2505 opp-hz = /bits/ 64 <421000000>;
2506 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
2509 opp-350000000 {
2510 opp-hz = /bits/ 64 <350000000>;
2511 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2514 opp-317000000 {
2515 opp-hz = /bits/ 64 <317000000>;
2516 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2519 opp-285000000 {
2520 opp-hz = /bits/ 64 <285000000>;
2521 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2524 opp-220000000 {
2525 opp-hz = /bits/ 64 <220000000>;
2526 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2532 compatible = "qcom,adreno-gmu-730.1", "qcom,adreno-gmu";
2536 reg-names = "gmu", "rscc", "gmu_pdc";
2540 interrupt-names = "hfi", "gmu";
2549 clock-names = "ahb",
2557 power-domains = <&gpucc GPU_CX_GDSC>,
2559 power-domain-names = "cx",
2566 operating-points-v2 = <&gmu_opp_table>;
2568 gmu_opp_table: opp-table {
2569 compatible = "operating-points-v2";
2571 opp-500000000 {
2572 opp-hz = /bits/ 64 <500000000>;
2573 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2576 opp-200000000 {
2577 opp-hz = /bits/ 64 <200000000>;
2578 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2583 gpucc: clock-controller@3d90000 {
2584 compatible = "qcom,sm8450-gpucc";
2589 #clock-cells = <1>;
2590 #reset-cells = <1>;
2591 #power-domain-cells = <1>;
2595 compatible = "qcom,sm8450-smmu-500", "qcom,adreno-smmu",
2596 "qcom,smmu-500", "arm,mmu-500";
2598 #iommu-cells = <2>;
2599 #global-interrupts = <1>;
2632 clock-names = "gmu",
2638 power-domains = <&gpucc GPU_CX_GDSC>;
2639 dma-coherent;
2643 compatible = "qcom,sm8450-usb-hs-phy",
2644 "qcom,usb-snps-hs-7nm-phy";
2647 #phy-cells = <0>;
2650 clock-names = "ref";
2656 compatible = "qcom,sm8450-qmp-usb3-dp-phy";
2663 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2667 reset-names = "phy", "common";
2669 #clock-cells = <1>;
2670 #phy-cells = <1>;
2672 orientation-switch;
2677 #address-cells = <1>;
2678 #size-cells = <0>;
2691 remote-endpoint = <&usb_1_dwc3_ss>;
2699 remote-endpoint = <&mdss_dp0_out>;
2706 compatible = "qcom,sm8450-slpi-pas";
2709 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2714 interrupt-names = "wdog", "fatal", "ready",
2715 "handover", "stop-ack";
2718 clock-names = "xo";
2720 power-domains = <&rpmhpd RPMHPD_LCX>,
2722 power-domain-names = "lcx", "lmx";
2724 memory-region = <&slpi_mem>;
2728 qcom,smem-states = <&smp2p_slpi_out 0>;
2729 qcom,smem-state-names = "stop";
2733 glink-edge {
2734 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2741 qcom,remote-pid = <3>;
2745 qcom,glink-channels = "fastrpcglink-apps-dsp";
2747 qcom,non-secure-domain;
2748 #address-cells = <1>;
2749 #size-cells = <0>;
2751 compute-cb@1 {
2752 compatible = "qcom,fastrpc-compute-cb";
2757 compute-cb@2 {
2758 compatible = "qcom,fastrpc-compute-cb";
2763 compute-cb@3 {
2764 compatible = "qcom,fastrpc-compute-cb";
2767 /* note: shared-cb = <4> in downstream */
2774 compatible = "qcom,sm8450-adsp-pas";
2777 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2782 interrupt-names = "wdog", "fatal", "ready",
2783 "handover", "stop-ack";
2786 clock-names = "xo";
2788 power-domains = <&rpmhpd RPMHPD_LCX>,
2790 power-domain-names = "lcx", "lmx";
2792 memory-region = <&adsp_mem>;
2796 qcom,smem-states = <&smp2p_adsp_out 0>;
2797 qcom,smem-state-names = "stop";
2801 remoteproc_adsp_glink: glink-edge {
2802 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2809 qcom,remote-pid = <2>;
2813 qcom,glink-channels = "adsp_apps";
2816 #address-cells = <1>;
2817 #size-cells = <0>;
2822 #sound-dai-cells = <0>;
2823 qcom,protection-domain = "avs/audio",
2827 compatible = "qcom,q6apm-dais";
2832 compatible = "qcom,q6apm-lpass-dais";
2833 #sound-dai-cells = <1>;
2840 qcom,protection-domain = "avs/audio",
2843 q6prmcc: clock-controller {
2844 compatible = "qcom,q6prm-lpass-clocks";
2845 #clock-cells = <2>;
2852 qcom,glink-channels = "fastrpcglink-apps-dsp";
2854 qcom,non-secure-domain;
2855 #address-cells = <1>;
2856 #size-cells = <0>;
2858 compute-cb@3 {
2859 compatible = "qcom,fastrpc-compute-cb";
2864 compute-cb@4 {
2865 compatible = "qcom,fastrpc-compute-cb";
2870 compute-cb@5 {
2871 compatible = "qcom,fastrpc-compute-cb";
2880 compatible = "qcom,sm8450-lpass-wsa-macro";
2887 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2889 #clock-cells = <0>;
2890 clock-output-names = "wsa2-mclk";
2891 #sound-dai-cells = <1>;
2895 compatible = "qcom,soundwire-v1.7.0";
2899 clock-names = "iface";
2902 pinctrl-0 = <&wsa2_swr_active>;
2903 pinctrl-names = "default";
2905 qcom,din-ports = <2>;
2906 qcom,dout-ports = <6>;
2908 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2909 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2910 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2911 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2912 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2913 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2914 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2915 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2916 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2918 #address-cells = <2>;
2919 #size-cells = <0>;
2920 #sound-dai-cells = <1>;
2925 compatible = "qcom,sm8450-lpass-rx-macro";
2932 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2934 #clock-cells = <0>;
2935 clock-output-names = "mclk";
2936 #sound-dai-cells = <1>;
2940 compatible = "qcom,soundwire-v1.7.0";
2944 clock-names = "iface";
2946 qcom,din-ports = <0>;
2947 qcom,dout-ports = <5>;
2949 pinctrl-0 = <&rx_swr_active>;
2950 pinctrl-names = "default";
2952 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2953 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2954 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2955 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2956 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2957 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2958 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2959 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2960 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2962 #address-cells = <2>;
2963 #size-cells = <0>;
2964 #sound-dai-cells = <1>;
2969 compatible = "qcom,sm8450-lpass-tx-macro";
2976 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2978 #clock-cells = <0>;
2979 clock-output-names = "mclk";
2980 #sound-dai-cells = <1>;
2984 compatible = "qcom,sm8450-lpass-wsa-macro";
2991 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2993 #clock-cells = <0>;
2994 clock-output-names = "mclk";
2995 #sound-dai-cells = <1>;
2999 compatible = "qcom,soundwire-v1.7.0";
3003 clock-names = "iface";
3006 pinctrl-0 = <&wsa_swr_active>;
3007 pinctrl-names = "default";
3009 qcom,din-ports = <2>;
3010 qcom,dout-ports = <6>;
3012 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
3013 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
3014 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
3015 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3016 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3017 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3018 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
3019 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3020 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3022 #address-cells = <2>;
3023 #size-cells = <0>;
3024 #sound-dai-cells = <1>;
3029 compatible = "qcom,soundwire-v1.7.0";
3033 interrupt-names = "core", "wakeup";
3036 clock-names = "iface";
3039 pinctrl-0 = <&tx_swr_active>;
3040 pinctrl-names = "default";
3042 qcom,din-ports = <4>;
3043 qcom,dout-ports = <0>;
3044 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
3045 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
3046 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
3047 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
3048 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
3049 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
3050 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
3051 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
3052 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
3054 #address-cells = <2>;
3055 #size-cells = <0>;
3056 #sound-dai-cells = <1>;
3061 compatible = "qcom,sm8450-lpass-va-macro";
3067 clock-names = "mclk", "macro", "dcodec", "npl";
3069 #clock-cells = <0>;
3070 clock-output-names = "fsgen";
3071 #sound-dai-cells = <1>;
3076 compatible = "qcom,sm8450-cdsp-pas";
3079 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3084 interrupt-names = "wdog", "fatal", "ready",
3085 "handover", "stop-ack";
3088 clock-names = "xo";
3090 power-domains = <&rpmhpd RPMHPD_CX>,
3092 power-domain-names = "cx", "mxc";
3094 memory-region = <&cdsp_mem>;
3098 qcom,smem-states = <&smp2p_cdsp_out 0>;
3099 qcom,smem-state-names = "stop";
3103 glink-edge {
3104 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3111 qcom,remote-pid = <5>;
3115 qcom,glink-channels = "fastrpcglink-apps-dsp";
3117 qcom,non-secure-domain;
3118 #address-cells = <1>;
3119 #size-cells = <0>;
3121 compute-cb@1 {
3122 compatible = "qcom,fastrpc-compute-cb";
3128 compute-cb@2 {
3129 compatible = "qcom,fastrpc-compute-cb";
3135 compute-cb@3 {
3136 compatible = "qcom,fastrpc-compute-cb";
3142 compute-cb@4 {
3143 compatible = "qcom,fastrpc-compute-cb";
3149 compute-cb@5 {
3150 compatible = "qcom,fastrpc-compute-cb";
3156 compute-cb@6 {
3157 compatible = "qcom,fastrpc-compute-cb";
3163 compute-cb@7 {
3164 compatible = "qcom,fastrpc-compute-cb";
3170 compute-cb@8 {
3171 compatible = "qcom,fastrpc-compute-cb";
3183 compatible = "qcom,sm8450-mpss-pas";
3186 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
3192 interrupt-names = "wdog", "fatal", "ready", "handover",
3193 "stop-ack", "shutdown-ack";
3196 clock-names = "xo";
3198 power-domains = <&rpmhpd RPMHPD_CX>,
3200 power-domain-names = "cx", "mss";
3202 memory-region = <&mpss_mem>;
3206 qcom,smem-states = <&smp2p_modem_out 0>;
3207 qcom,smem-state-names = "stop";
3211 glink-edge {
3212 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
3218 qcom,remote-pid = <1>;
3222 videocc: clock-controller@aaf0000 {
3223 compatible = "qcom,sm8450-videocc";
3227 power-domains = <&rpmhpd RPMHPD_MMCX>,
3229 required-opps = <&rpmhpd_opp_low_svs>,
3231 #clock-cells = <1>;
3232 #reset-cells = <1>;
3233 #power-domain-cells = <1>;
3237 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
3240 power-domains = <&camcc TITAN_TOP_GDSC>;
3247 clock-names = "camnoc_axi",
3252 pinctrl-0 = <&cci0_default &cci1_default>;
3253 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
3254 pinctrl-names = "default", "sleep";
3257 #address-cells = <1>;
3258 #size-cells = <0>;
3260 cci0_i2c0: i2c-bus@0 {
3262 clock-frequency = <1000000>;
3263 #address-cells = <1>;
3264 #size-cells = <0>;
3267 cci0_i2c1: i2c-bus@1 {
3269 clock-frequency = <1000000>;
3270 #address-cells = <1>;
3271 #size-cells = <0>;
3276 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
3279 power-domains = <&camcc TITAN_TOP_GDSC>;
3286 clock-names = "camnoc_axi",
3291 pinctrl-0 = <&cci2_default &cci3_default>;
3292 pinctrl-1 = <&cci2_sleep &cci3_sleep>;
3293 pinctrl-names = "default", "sleep";
3296 #address-cells = <1>;
3297 #size-cells = <0>;
3299 cci1_i2c0: i2c-bus@0 {
3301 clock-frequency = <1000000>;
3302 #address-cells = <1>;
3303 #size-cells = <0>;
3306 cci1_i2c1: i2c-bus@1 {
3308 clock-frequency = <1000000>;
3309 #address-cells = <1>;
3310 #size-cells = <0>;
3314 camcc: clock-controller@ade0000 {
3315 compatible = "qcom,sm8450-camcc";
3321 power-domains = <&rpmhpd RPMHPD_MMCX>,
3323 required-opps = <&rpmhpd_opp_low_svs>,
3325 #clock-cells = <1>;
3326 #reset-cells = <1>;
3327 #power-domain-cells = <1>;
3330 mdss: display-subsystem@ae00000 {
3331 compatible = "qcom,sm8450-mdss";
3333 reg-names = "mdss";
3340 interconnect-names = "mdp0-mem",
3341 "mdp1-mem",
3342 "cpu-cfg";
3346 power-domains = <&dispcc MDSS_GDSC>;
3354 interrupt-controller;
3355 #interrupt-cells = <1>;
3359 #address-cells = <2>;
3360 #size-cells = <2>;
3365 mdss_mdp: display-controller@ae01000 {
3366 compatible = "qcom,sm8450-dpu";
3369 reg-names = "mdp", "vbif";
3377 clock-names = "bus",
3384 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3385 assigned-clock-rates = <19200000>;
3387 operating-points-v2 = <&mdp_opp_table>;
3388 power-domains = <&rpmhpd RPMHPD_MMCX>;
3390 interrupt-parent = <&mdss>;
3394 #address-cells = <1>;
3395 #size-cells = <0>;
3400 remote-endpoint = <&mdss_dsi0_in>;
3407 remote-endpoint = <&mdss_dsi1_in>;
3414 remote-endpoint = <&mdss_dp0_in>;
3419 mdp_opp_table: opp-table {
3420 compatible = "operating-points-v2";
3422 opp-172000000 {
3423 opp-hz = /bits/ 64 <172000000>;
3424 required-opps = <&rpmhpd_opp_low_svs_d1>;
3427 opp-200000000 {
3428 opp-hz = /bits/ 64 <200000000>;
3429 required-opps = <&rpmhpd_opp_low_svs>;
3432 opp-325000000 {
3433 opp-hz = /bits/ 64 <325000000>;
3434 required-opps = <&rpmhpd_opp_svs>;
3437 opp-375000000 {
3438 opp-hz = /bits/ 64 <375000000>;
3439 required-opps = <&rpmhpd_opp_svs_l1>;
3442 opp-500000000 {
3443 opp-hz = /bits/ 64 <500000000>;
3444 required-opps = <&rpmhpd_opp_nom>;
3449 mdss_dp0: displayport-controller@ae90000 {
3450 compatible = "qcom,sm8450-dp", "qcom,sm8350-dp";
3456 interrupt-parent = <&mdss>;
3464 clock-names = "core_iface",
3471 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
3474 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3479 phy-names = "dp";
3481 #sound-dai-cells = <0>;
3483 operating-points-v2 = <&dp_opp_table>;
3484 power-domains = <&rpmhpd RPMHPD_MMCX>;
3489 #address-cells = <1>;
3490 #size-cells = <0>;
3495 remote-endpoint = <&dpu_intf0_out>;
3503 remote-endpoint = <&usb_1_qmpphy_dp_in>;
3508 dp_opp_table: opp-table {
3509 compatible = "operating-points-v2";
3511 opp-160000000 {
3512 opp-hz = /bits/ 64 <160000000>;
3513 required-opps = <&rpmhpd_opp_low_svs>;
3516 opp-270000000 {
3517 opp-hz = /bits/ 64 <270000000>;
3518 required-opps = <&rpmhpd_opp_svs>;
3521 opp-540000000 {
3522 opp-hz = /bits/ 64 <540000000>;
3523 required-opps = <&rpmhpd_opp_svs_l1>;
3526 opp-810000000 {
3527 opp-hz = /bits/ 64 <810000000>;
3528 required-opps = <&rpmhpd_opp_nom>;
3534 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3536 reg-names = "dsi_ctrl";
3538 interrupt-parent = <&mdss>;
3547 clock-names = "byte",
3554 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
3556 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
3559 operating-points-v2 = <&mdss_dsi_opp_table>;
3560 power-domains = <&rpmhpd RPMHPD_MMCX>;
3563 phy-names = "dsi";
3565 #address-cells = <1>;
3566 #size-cells = <0>;
3571 #address-cells = <1>;
3572 #size-cells = <0>;
3577 remote-endpoint = <&dpu_intf1_out>;
3588 mdss_dsi_opp_table: opp-table {
3589 compatible = "operating-points-v2";
3591 opp-187500000 {
3592 opp-hz = /bits/ 64 <187500000>;
3593 required-opps = <&rpmhpd_opp_low_svs>;
3596 opp-300000000 {
3597 opp-hz = /bits/ 64 <300000000>;
3598 required-opps = <&rpmhpd_opp_svs>;
3601 opp-358000000 {
3602 opp-hz = /bits/ 64 <358000000>;
3603 required-opps = <&rpmhpd_opp_svs_l1>;
3609 compatible = "qcom,sm8450-dsi-phy-5nm";
3613 reg-names = "dsi_phy",
3617 #clock-cells = <1>;
3618 #phy-cells = <0>;
3622 clock-names = "iface", "ref";
3628 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3630 reg-names = "dsi_ctrl";
3632 interrupt-parent = <&mdss>;
3641 clock-names = "byte",
3648 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
3650 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
3653 operating-points-v2 = <&mdss_dsi_opp_table>;
3654 power-domains = <&rpmhpd RPMHPD_MMCX>;
3657 phy-names = "dsi";
3659 #address-cells = <1>;
3660 #size-cells = <0>;
3665 #address-cells = <1>;
3666 #size-cells = <0>;
3671 remote-endpoint = <&dpu_intf2_out>;
3684 compatible = "qcom,sm8450-dsi-phy-5nm";
3688 reg-names = "dsi_phy",
3692 #clock-cells = <1>;
3693 #phy-cells = <0>;
3697 clock-names = "iface", "ref";
3703 dispcc: clock-controller@af00000 {
3704 compatible = "qcom,sm8450-dispcc";
3722 power-domains = <&rpmhpd RPMHPD_MMCX>;
3723 required-opps = <&rpmhpd_opp_low_svs>;
3724 #clock-cells = <1>;
3725 #reset-cells = <1>;
3726 #power-domain-cells = <1>;
3729 pdc: interrupt-controller@b220000 {
3730 compatible = "qcom,sm8450-pdc", "qcom,pdc";
3732 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
3734 #interrupt-cells = <2>;
3735 interrupt-parent = <&intc>;
3736 interrupt-controller;
3739 tsens0: thermal-sensor@c263000 {
3740 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3746 interrupt-names = "uplow", "critical";
3747 #thermal-sensor-cells = <1>;
3750 tsens1: thermal-sensor@c265000 {
3751 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3757 interrupt-names = "uplow", "critical";
3758 #thermal-sensor-cells = <1>;
3761 aoss_qmp: power-management@c300000 {
3762 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
3764 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3768 #clock-cells = <0>;
3772 compatible = "qcom,rpmh-stats";
3778 compatible = "qcom,spmi-pmic-arb";
3784 reg-names = "core",
3789 interrupt-names = "periph_irq";
3790 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3793 interrupt-controller;
3794 #interrupt-cells = <4>;
3795 #address-cells = <2>;
3796 #size-cells = <0>;
3800 compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
3803 interrupt-controller;
3804 #interrupt-cells = <3>;
3805 #mbox-cells = <2>;
3809 compatible = "qcom,sm8450-tlmm";
3812 gpio-controller;
3813 #gpio-cells = <2>;
3814 interrupt-controller;
3815 #interrupt-cells = <2>;
3816 gpio-ranges = <&tlmm 0 0 211>;
3817 wakeup-parent = <&pdc>;
3819 sdc2_default_state: sdc2-default-state {
3820 clk-pins {
3822 drive-strength = <16>;
3823 bias-disable;
3826 cmd-pins {
3828 drive-strength = <16>;
3829 bias-pull-up;
3832 data-pins {
3834 drive-strength = <16>;
3835 bias-pull-up;
3839 sdc2_sleep_state: sdc2-sleep-state {
3840 clk-pins {
3842 drive-strength = <2>;
3843 bias-disable;
3846 cmd-pins {
3848 drive-strength = <2>;
3849 bias-pull-up;
3852 data-pins {
3854 drive-strength = <2>;
3855 bias-pull-up;
3859 cci0_default: cci0-default-state {
3863 drive-strength = <2>;
3864 bias-pull-up;
3867 cci0_sleep: cci0-sleep-state {
3871 drive-strength = <2>;
3872 bias-pull-down;
3875 cci1_default: cci1-default-state {
3879 drive-strength = <2>;
3880 bias-pull-up;
3883 cci1_sleep: cci1-sleep-state {
3887 drive-strength = <2>;
3888 bias-pull-down;
3891 cci2_default: cci2-default-state {
3895 drive-strength = <2>;
3896 bias-pull-up;
3899 cci2_sleep: cci2-sleep-state {
3903 drive-strength = <2>;
3904 bias-pull-down;
3907 cci3_default: cci3-default-state {
3911 drive-strength = <2>;
3912 bias-pull-up;
3915 cci3_sleep: cci3-sleep-state {
3919 drive-strength = <2>;
3920 bias-pull-down;
3923 pcie0_default_state: pcie0-default-state {
3924 perst-pins {
3927 drive-strength = <2>;
3928 bias-pull-down;
3931 clkreq-pins {
3934 drive-strength = <2>;
3935 bias-pull-up;
3938 wake-pins {
3941 drive-strength = <2>;
3942 bias-pull-up;
3946 pcie1_default_state: pcie1-default-state {
3947 perst-pins {
3950 drive-strength = <2>;
3951 bias-pull-down;
3954 clkreq-pins {
3957 drive-strength = <2>;
3958 bias-pull-up;
3961 wake-pins {
3964 drive-strength = <2>;
3965 bias-pull-up;
3969 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3974 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3979 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3984 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3989 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3994 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3999 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
4004 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
4009 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
4014 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
4019 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
4024 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
4029 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
4032 drive-strength = <2>;
4033 bias-pull-up;
4036 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
4039 drive-strength = <2>;
4040 bias-pull-up;
4043 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
4048 qup_i2c16_data_clk: qup-i2c16-data-clk-state {
4053 qup_i2c17_data_clk: qup-i2c17-data-clk-state {
4058 qup_i2c18_data_clk: qup-i2c18-data-clk-state {
4063 qup_i2c19_data_clk: qup-i2c19-data-clk-state {
4068 qup_i2c20_data_clk: qup-i2c20-data-clk-state {
4073 qup_i2c21_data_clk: qup-i2c21-data-clk-state {
4078 qup_spi0_cs: qup-spi0-cs-state {
4083 qup_spi0_data_clk: qup-spi0-data-clk-state {
4088 qup_spi1_cs: qup-spi1-cs-state {
4093 qup_spi1_data_clk: qup-spi1-data-clk-state {
4098 qup_spi2_cs: qup-spi2-cs-state {
4103 qup_spi2_data_clk: qup-spi2-data-clk-state {
4108 qup_spi3_cs: qup-spi3-cs-state {
4113 qup_spi3_data_clk: qup-spi3-data-clk-state {
4118 qup_spi4_cs: qup-spi4-cs-state {
4121 drive-strength = <6>;
4122 bias-disable;
4125 qup_spi4_data_clk: qup-spi4-data-clk-state {
4130 qup_spi5_cs: qup-spi5-cs-state {
4135 qup_spi5_data_clk: qup-spi5-data-clk-state {
4140 qup_spi6_cs: qup-spi6-cs-state {
4145 qup_spi6_data_clk: qup-spi6-data-clk-state {
4150 qup_spi8_cs: qup-spi8-cs-state {
4155 qup_spi8_data_clk: qup-spi8-data-clk-state {
4160 qup_spi9_cs: qup-spi9-cs-state {
4165 qup_spi9_data_clk: qup-spi9-data-clk-state {
4170 qup_spi10_cs: qup-spi10-cs-state {
4175 qup_spi10_data_clk: qup-spi10-data-clk-state {
4180 qup_spi11_cs: qup-spi11-cs-state {
4185 qup_spi11_data_clk: qup-spi11-data-clk-state {
4190 qup_spi12_cs: qup-spi12-cs-state {
4195 qup_spi12_data_clk: qup-spi12-data-clk-state {
4200 qup_spi13_cs: qup-spi13-cs-state {
4205 qup_spi13_data_clk: qup-spi13-data-clk-state {
4210 qup_spi14_cs: qup-spi14-cs-state {
4215 qup_spi14_data_clk: qup-spi14-data-clk-state {
4220 qup_spi15_cs: qup-spi15-cs-state {
4225 qup_spi15_data_clk: qup-spi15-data-clk-state {
4230 qup_spi16_cs: qup-spi16-cs-state {
4235 qup_spi16_data_clk: qup-spi16-data-clk-state {
4240 qup_spi17_cs: qup-spi17-cs-state {
4245 qup_spi17_data_clk: qup-spi17-data-clk-state {
4250 qup_spi18_cs: qup-spi18-cs-state {
4253 drive-strength = <6>;
4254 bias-disable;
4257 qup_spi18_data_clk: qup-spi18-data-clk-state {
4260 drive-strength = <6>;
4261 bias-disable;
4264 qup_spi19_cs: qup-spi19-cs-state {
4267 drive-strength = <6>;
4268 bias-disable;
4271 qup_spi19_data_clk: qup-spi19-data-clk-state {
4274 drive-strength = <6>;
4275 bias-disable;
4278 qup_spi20_cs: qup-spi20-cs-state {
4283 qup_spi20_data_clk: qup-spi20-data-clk-state {
4288 qup_spi21_cs: qup-spi21-cs-state {
4293 qup_spi21_data_clk: qup-spi21-data-clk-state {
4298 qup_uart7_rx: qup-uart7-rx-state {
4301 drive-strength = <2>;
4302 bias-disable;
4305 qup_uart7_tx: qup-uart7-tx-state {
4308 drive-strength = <2>;
4309 bias-disable;
4312 qup_uart20_default: qup-uart20-default-state {
4319 compatible = "qcom,sm8450-lpass-lpi-pinctrl";
4322 gpio-controller;
4323 #gpio-cells = <2>;
4324 gpio-ranges = <&lpass_tlmm 0 0 23>;
4328 clock-names = "core", "audio";
4330 tx_swr_active: tx-swr-active-state {
4331 clk-pins {
4334 drive-strength = <2>;
4335 slew-rate = <1>;
4336 bias-disable;
4339 data-pins {
4342 drive-strength = <2>;
4343 slew-rate = <1>;
4344 bias-bus-hold;
4348 rx_swr_active: rx-swr-active-state {
4349 clk-pins {
4352 drive-strength = <2>;
4353 slew-rate = <1>;
4354 bias-disable;
4357 data-pins {
4360 drive-strength = <2>;
4361 slew-rate = <1>;
4362 bias-bus-hold;
4366 dmic01_default: dmic01-default-state {
4367 clk-pins {
4370 drive-strength = <8>;
4371 output-high;
4374 data-pins {
4377 drive-strength = <8>;
4381 dmic23_default: dmic23-default-state {
4382 clk-pins {
4385 drive-strength = <8>;
4386 output-high;
4389 data-pins {
4392 drive-strength = <8>;
4396 wsa_swr_active: wsa-swr-active-state {
4397 clk-pins {
4400 drive-strength = <2>;
4401 slew-rate = <1>;
4402 bias-disable;
4405 data-pins {
4408 drive-strength = <2>;
4409 slew-rate = <1>;
4410 bias-bus-hold;
4414 wsa2_swr_active: wsa2-swr-active-state {
4415 clk-pins {
4418 drive-strength = <2>;
4419 slew-rate = <1>;
4420 bias-disable;
4423 data-pins {
4426 drive-strength = <2>;
4427 slew-rate = <1>;
4428 bias-bus-hold;
4434 compatible = "arm,coresight-stm", "arm,primecell";
4437 reg-names = "stm-base", "stm-stimulus-base";
4440 clock-names = "apb_pclk";
4442 out-ports {
4445 remote-endpoint =
4453 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
4457 clock-names = "apb_pclk";
4459 in-ports {
4460 #address-cells = <1>;
4461 #size-cells = <0>;
4466 remote-endpoint =
4472 out-ports {
4475 remote-endpoint =
4483 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
4488 clock-names = "apb_pclk";
4490 in-ports {
4491 #address-cells = <1>;
4492 #size-cells = <0>;
4497 remote-endpoint =
4505 remote-endpoint =
4511 out-ports {
4514 remote-endpoint =
4522 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
4526 clock-names = "apb_pclk";
4528 in-ports {
4529 #address-cells = <1>;
4530 #size-cells = <0>;
4535 remote-endpoint =
4543 remote-endpoint =
4549 out-ports {
4552 remote-endpoint =
4560 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
4564 clock-names = "apb_pclk";
4566 in-ports {
4569 remote-endpoint =
4575 out-ports {
4579 remote-endpoint =
4587 compatible = "arm,coresight-tmc", "arm,primecell";
4591 arm,buffer-size = <0x10000>;
4593 arm,scatter-gather;
4595 clock-names = "apb_pclk";
4597 in-ports {
4600 remote-endpoint =
4608 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
4612 clock-names = "apb_pclk";
4614 in-ports {
4617 remote-endpoint =
4623 out-ports {
4628 remote-endpoint =
4636 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
4641 clock-names = "apb_pclk";
4643 in-ports {
4644 #address-cells = <1>;
4645 #size-cells = <0>;
4650 remote-endpoint =
4658 remote-endpoint =
4664 out-ports {
4667 remote-endpoint =
4675 compatible = "arm,coresight-tmc", "arm,primecell";
4679 clock-names = "apb_pclk";
4681 in-ports {
4684 remote-endpoint =
4690 out-ports {
4693 remote-endpoint =
4701 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
4704 qcom,replicator-loses-context;
4706 clock-names = "apb_pclk";
4708 in-ports {
4711 remote-endpoint =
4717 out-ports {
4721 remote-endpoint =
4729 compatible = "qcom,coresight-tpda", "arm,primecell";
4734 clock-names = "apb_pclk";
4736 in-ports {
4738 #address-cells = <1>;
4739 #size-cells = <0>;
4744 remote-endpoint =
4752 remote-endpoint =
4758 out-ports {
4762 remote-endpoint =
4770 compatible = "qcom,coresight-tpdm", "arm,primecell";
4775 clock-names = "apb_pclk";
4777 out-ports {
4780 remote-endpoint =
4788 compatible = "qcom,coresight-tpdm", "arm,primecell";
4792 clock-names = "apb_pclk";
4794 out-ports {
4797 remote-endpoint =
4805 compatible = "qcom,coresight-tpdm", "arm,primecell";
4809 clock-names = "apb_pclk";
4811 out-ports {
4814 remote-endpoint =
4822 compatible = "qcom,coresight-tpdm", "arm,primecell";
4826 clock-names = "apb_pclk";
4828 out-ports {
4831 remote-endpoint =
4839 compatible = "arm,coresight-cti", "arm,primecell";
4843 clock-names = "apb_pclk";
4847 compatible = "arm,coresight-cti", "arm,primecell";
4851 clock-names = "apb_pclk";
4855 compatible = "qcom,coresight-tpda", "arm,primecell";
4859 clock-names = "apb_pclk";
4861 in-ports {
4863 #address-cells = <1>;
4864 #size-cells = <0>;
4869 remote-endpoint =
4877 remote-endpoint =
4883 out-ports {
4887 remote-endpoint =
4895 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
4899 clock-names = "apb_pclk";
4901 in-ports {
4905 remote-endpoint =
4911 out-ports {
4914 remote-endpoint =
4922 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
4927 clock-names = "apb_pclk";
4929 in-ports {
4933 remote-endpoint =
4939 out-ports {
4942 remote-endpoint =
4950 compatible = "arm,coresight-cti", "arm,primecell";
4954 clock-names = "apb_pclk";
4958 compatible = "arm,coresight-cti", "arm,primecell";
4962 clock-names = "apb_pclk";
4966 compatible = "arm,coresight-cti", "arm,primecell";
4970 clock-names = "apb_pclk";
4974 compatible = "qcom,sm8450-imem", "syscon", "simple-mfd";
4978 #address-cells = <1>;
4979 #size-cells = <1>;
4981 pil-reloc@94c {
4982 compatible = "qcom,pil-reloc-info";
4988 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
4990 #iommu-cells = <2>;
4991 #global-interrupts = <1>;
5089 dma-coherent;
5092 intc: interrupt-controller@17100000 {
5093 compatible = "arm,gic-v3";
5094 #interrupt-cells = <3>;
5095 interrupt-controller;
5096 #redistributor-regions = <1>;
5097 redistributor-stride = <0x0 0x40000>;
5101 #address-cells = <2>;
5102 #size-cells = <2>;
5105 gic_its: msi-controller@17140000 {
5106 compatible = "arm,gic-v3-its";
5108 msi-controller;
5109 #msi-cells = <1>;
5114 compatible = "arm,armv7-timer-mem";
5115 #address-cells = <1>;
5116 #size-cells = <1>;
5119 clock-frequency = <19200000>;
5122 frame-number = <0>;
5130 frame-number = <1>;
5137 frame-number = <2>;
5144 frame-number = <3>;
5151 frame-number = <4>;
5158 frame-number = <5>;
5165 frame-number = <6>;
5174 compatible = "qcom,rpmh-rsc";
5179 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
5183 qcom,tcs-offset = <0xd00>;
5184 qcom,drv-id = <2>;
5185 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
5187 power-domains = <&cluster_pd>;
5189 apps_bcm_voter: bcm-voter {
5190 compatible = "qcom,bcm-voter";
5193 rpmhcc: clock-controller {
5194 compatible = "qcom,sm8450-rpmh-clk";
5195 #clock-cells = <1>;
5196 clock-names = "xo";
5200 rpmhpd: power-controller {
5201 compatible = "qcom,sm8450-rpmhpd";
5202 #power-domain-cells = <1>;
5203 operating-points-v2 = <&rpmhpd_opp_table>;
5205 rpmhpd_opp_table: opp-table {
5206 compatible = "operating-points-v2";
5209 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5213 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5217 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
5221 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5225 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
5229 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5233 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
5237 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5241 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
5245 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5249 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5253 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5257 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5261 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5268 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
5272 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
5274 clock-names = "xo", "alternate";
5278 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
5279 #freq-domain-cells = <1>;
5280 #clock-cells = <1>;
5284 compatible = "qcom,sm8450-gem-noc";
5286 #interconnect-cells = <2>;
5287 qcom,bcm-voters = <&apps_bcm_voter>;
5290 system-cache-controller@19200000 {
5291 compatible = "qcom,sm8450-llcc";
5295 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
5302 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
5303 "jedec,ufs-2.0";
5307 phy-names = "ufsphy";
5308 lanes-per-direction = <2>;
5309 #reset-cells = <1>;
5311 reset-names = "rst";
5313 power-domains = <&gcc UFS_PHY_GDSC>;
5316 dma-coherent;
5320 interconnect-names = "ufs-ddr", "cpu-ufs";
5321 clock-names =
5339 freq-table-hz =
5354 compatible = "qcom,sm8450-qmp-ufs-phy";
5357 clock-names = "ref", "ref_aux", "qref";
5362 power-domains = <&gcc UFS_PHY_GDSC>;
5365 reset-names = "ufsphy";
5367 #clock-cells = <1>;
5368 #phy-cells = <0>;
5374 compatible = "qcom,sm8450-inline-crypto-engine",
5375 "qcom,inline-crypto-engine";
5380 cryptobam: dma-controller@1dc4000 {
5381 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
5384 #dma-cells = <1>;
5386 qcom,num-ees = <4>;
5387 num-channels = <16>;
5388 qcom,controlled-remotely;
5397 compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce";
5400 dma-names = "rx", "tx";
5407 interconnect-names = "memory";
5411 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5";
5416 interrupt-names = "hc_irq", "pwr_irq";
5421 clock-names = "iface", "core", "xo";
5425 interconnect-names = "sdhc-ddr","cpu-sdhc";
5427 power-domains = <&rpmhpd RPMHPD_CX>;
5428 operating-points-v2 = <&sdhc2_opp_table>;
5429 bus-width = <4>;
5430 dma-coherent;
5432 /* Forbid SDR104/SDR50 - broken hw! */
5433 sdhci-caps-mask = <0x3 0x0>;
5437 sdhc2_opp_table: opp-table {
5438 compatible = "operating-points-v2";
5440 opp-100000000 {
5441 opp-hz = /bits/ 64 <100000000>;
5442 required-opps = <&rpmhpd_opp_low_svs>;
5445 opp-202000000 {
5446 opp-hz = /bits/ 64 <202000000>;
5447 required-opps = <&rpmhpd_opp_svs_l1>;
5453 compatible = "qcom,sm8450-dwc3", "qcom,snps-dwc3";
5463 clock-names = "cfg_noc",
5470 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
5472 assigned-clock-rates = <19200000>, <200000000>;
5474 interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
5480 interrupt-names = "dwc_usb3",
5487 power-domains = <&gcc USB30_PRIM_GDSC>;
5493 interconnect-names = "usb-ddr", "apps-usb";
5499 snps,dis-u1-entry-quirk;
5500 snps,dis-u2-entry-quirk;
5502 phy-names = "usb2-phy", "usb3-phy";
5503 usb-role-switch;
5506 #address-cells = <1>;
5507 #size-cells = <0>;
5520 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
5527 compatible = "qcom,sm8450-nsp-noc";
5529 #interconnect-cells = <2>;
5530 qcom,bcm-voters = <&apps_bcm_voter>;
5534 compatible = "qcom,sm8450-lpass-ag-noc";
5536 #interconnect-cells = <2>;
5537 qcom,bcm-voters = <&apps_bcm_voter>;
5544 thermal-zones {
5545 aoss0-thermal {
5546 thermal-sensors = <&tsens0 0>;
5549 thermal-engine-config {
5555 reset-mon-cfg {
5563 cpuss0-thermal {
5564 thermal-sensors = <&tsens0 1>;
5567 thermal-engine-config {
5573 reset-mon-cfg {
5581 cpuss1-thermal {
5582 thermal-sensors = <&tsens0 2>;
5585 thermal-engine-config {
5591 reset-mon-cfg {
5599 cpuss3-thermal {
5600 thermal-sensors = <&tsens0 3>;
5603 thermal-engine-config {
5609 reset-mon-cfg {
5617 cpuss4-thermal {
5618 thermal-sensors = <&tsens0 4>;
5621 thermal-engine-config {
5627 reset-mon-cfg {
5635 cpu4-top-thermal {
5636 thermal-sensors = <&tsens0 5>;
5639 cpu4_top_alert0: trip-point0 {
5645 cpu4_top_alert1: trip-point1 {
5651 cpu4_top_crit: cpu-crit {
5659 cpu4-bottom-thermal {
5660 thermal-sensors = <&tsens0 6>;
5663 cpu4_bottom_alert0: trip-point0 {
5669 cpu4_bottom_alert1: trip-point1 {
5675 cpu4_bottom_crit: cpu-crit {
5683 cpu5-top-thermal {
5684 thermal-sensors = <&tsens0 7>;
5687 cpu5_top_alert0: trip-point0 {
5693 cpu5_top_alert1: trip-point1 {
5699 cpu5_top_crit: cpu-crit {
5707 cpu5-bottom-thermal {
5708 thermal-sensors = <&tsens0 8>;
5711 cpu5_bottom_alert0: trip-point0 {
5717 cpu5_bottom_alert1: trip-point1 {
5723 cpu5_bottom_crit: cpu-crit {
5731 cpu6-top-thermal {
5732 thermal-sensors = <&tsens0 9>;
5735 cpu6_top_alert0: trip-point0 {
5741 cpu6_top_alert1: trip-point1 {
5747 cpu6_top_crit: cpu-crit {
5755 cpu6-bottom-thermal {
5756 thermal-sensors = <&tsens0 10>;
5759 cpu6_bottom_alert0: trip-point0 {
5765 cpu6_bottom_alert1: trip-point1 {
5771 cpu6_bottom_crit: cpu-crit {
5779 cpu7-top-thermal {
5780 thermal-sensors = <&tsens0 11>;
5783 cpu7_top_alert0: trip-point0 {
5789 cpu7_top_alert1: trip-point1 {
5795 cpu7_top_crit: cpu-crit {
5803 cpu7-middle-thermal {
5804 thermal-sensors = <&tsens0 12>;
5807 cpu7_middle_alert0: trip-point0 {
5813 cpu7_middle_alert1: trip-point1 {
5819 cpu7_middle_crit: cpu-crit {
5827 cpu7-bottom-thermal {
5828 thermal-sensors = <&tsens0 13>;
5831 cpu7_bottom_alert0: trip-point0 {
5837 cpu7_bottom_alert1: trip-point1 {
5843 cpu7_bottom_crit: cpu-crit {
5851 gpu-top-thermal {
5852 polling-delay-passive = <10>;
5854 thermal-sensors = <&tsens0 14>;
5856 cooling-maps {
5859 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5864 gpu_top_alert0: trip-point0 {
5870 trip-point1 {
5876 trip-point2 {
5884 gpu-bottom-thermal {
5885 polling-delay-passive = <10>;
5887 thermal-sensors = <&tsens0 15>;
5889 cooling-maps {
5892 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5897 gpu_bottom_alert0: trip-point0 {
5903 trip-point1 {
5909 trip-point2 {
5917 aoss1-thermal {
5918 thermal-sensors = <&tsens1 0>;
5921 thermal-engine-config {
5927 reset-mon-cfg {
5935 cpu0-thermal {
5936 thermal-sensors = <&tsens1 1>;
5939 cpu0_alert0: trip-point0 {
5945 cpu0_alert1: trip-point1 {
5951 cpu0_crit: cpu-crit {
5959 cpu1-thermal {
5960 thermal-sensors = <&tsens1 2>;
5963 cpu1_alert0: trip-point0 {
5969 cpu1_alert1: trip-point1 {
5975 cpu1_crit: cpu-crit {
5983 cpu2-thermal {
5984 thermal-sensors = <&tsens1 3>;
5987 cpu2_alert0: trip-point0 {
5993 cpu2_alert1: trip-point1 {
5999 cpu2_crit: cpu-crit {
6007 cpu3-thermal {
6008 thermal-sensors = <&tsens1 4>;
6011 cpu3_alert0: trip-point0 {
6017 cpu3_alert1: trip-point1 {
6023 cpu3_crit: cpu-crit {
6031 cdsp0-thermal {
6032 polling-delay-passive = <10>;
6034 thermal-sensors = <&tsens1 5>;
6037 thermal-engine-config {
6043 thermal-hal-config {
6049 reset-mon-cfg {
6055 cdsp_0_config: junction-config {
6063 cdsp1-thermal {
6064 polling-delay-passive = <10>;
6066 thermal-sensors = <&tsens1 6>;
6069 thermal-engine-config {
6075 thermal-hal-config {
6081 reset-mon-cfg {
6087 cdsp_1_config: junction-config {
6095 cdsp2-thermal {
6096 polling-delay-passive = <10>;
6098 thermal-sensors = <&tsens1 7>;
6101 thermal-engine-config {
6107 thermal-hal-config {
6113 reset-mon-cfg {
6119 cdsp_2_config: junction-config {
6127 video-thermal {
6128 thermal-sensors = <&tsens1 8>;
6131 thermal-engine-config {
6137 reset-mon-cfg {
6145 mem-thermal {
6146 polling-delay-passive = <10>;
6148 thermal-sensors = <&tsens1 9>;
6151 thermal-engine-config {
6157 ddr_config0: ddr0-config {
6163 reset-mon-cfg {
6171 modem0-thermal {
6172 thermal-sensors = <&tsens1 10>;
6175 thermal-engine-config {
6181 mdmss0_config0: mdmss0-config0 {
6187 mdmss0_config1: mdmss0-config1 {
6193 reset-mon-cfg {
6201 modem1-thermal {
6202 thermal-sensors = <&tsens1 11>;
6205 thermal-engine-config {
6211 mdmss1_config0: mdmss1-config0 {
6217 mdmss1_config1: mdmss1-config1 {
6223 reset-mon-cfg {
6231 modem2-thermal {
6232 thermal-sensors = <&tsens1 12>;
6235 thermal-engine-config {
6241 mdmss2_config0: mdmss2-config0 {
6247 mdmss2_config1: mdmss2-config1 {
6253 reset-mon-cfg {
6261 modem3-thermal {
6262 thermal-sensors = <&tsens1 13>;
6265 thermal-engine-config {
6271 mdmss3_config0: mdmss3-config0 {
6277 mdmss3_config1: mdmss3-config1 {
6283 reset-mon-cfg {
6291 camera0-thermal {
6292 thermal-sensors = <&tsens1 14>;
6295 thermal-engine-config {
6301 reset-mon-cfg {
6309 camera1-thermal {
6310 thermal-sensors = <&tsens1 15>;
6313 thermal-engine-config {
6319 reset-mon-cfg {
6329 compatible = "arm,armv8-timer";
6334 clock-frequency = <19200000>;