Lines Matching +full:0 +full:xae91000
39 #clock-cells = <0>;
45 #clock-cells = <0>;
52 #size-cells = <0>;
54 CPU0: cpu@0 {
57 reg = <0x0 0x0>;
62 qcom,freq-domain = <&cpufreq_hw 0>;
64 clocks = <&cpufreq_hw 0>;
81 reg = <0x0 0x100>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
88 clocks = <&cpufreq_hw 0>;
100 reg = <0x0 0x200>;
105 qcom,freq-domain = <&cpufreq_hw 0>;
107 clocks = <&cpufreq_hw 0>;
119 reg = <0x0 0x300>;
124 qcom,freq-domain = <&cpufreq_hw 0>;
126 clocks = <&cpufreq_hw 0>;
138 reg = <0x0 0x400>;
157 reg = <0x0 0x500>;
176 reg = <0x0 0x600>;
195 reg = <0x0 0x700>;
250 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
253 arm,psci-suspend-param = <0x40000004>;
260 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
263 arm,psci-suspend-param = <0x40000004>;
272 CLUSTER_SLEEP_0: cluster-sleep-0 {
274 arm,psci-suspend-param = <0x41000044>;
282 arm,psci-suspend-param = <0x4100c344>;
293 qcom,dload-mode = <&tcsr 0x13000>;
294 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
299 clk_virt: interconnect-0 {
314 reg = <0x0 0xa0000000 0x0 0x0>;
327 #power-domain-cells = <0>;
333 #power-domain-cells = <0>;
339 #power-domain-cells = <0>;
345 #power-domain-cells = <0>;
351 #power-domain-cells = <0>;
357 #power-domain-cells = <0>;
363 #power-domain-cells = <0>;
369 #power-domain-cells = <0>;
375 #power-domain-cells = <0>;
405 reg = <0x0 0x80000000 0x0 0x600000>;
410 reg = <0x0 0x80600000 0x0 0x40000>;
415 reg = <0x0 0x80640000 0x0 0x180000>;
420 reg = <0x0 0x807c0000 0x0 0x40000>;
425 reg = <0x0 0x80800000 0x0 0x60000>;
431 reg = <0x0 0x80860000 0x0 0x20000>;
436 reg = <0x0 0x80880000 0x0 0x20000>;
441 reg = <0x0 0x808a0000 0x0 0x40000>;
446 reg = <0x0 0x808e0000 0x0 0x4000>;
451 reg = <0x0 0x808e4000 0x0 0x10000>;
458 reg = <0x0 0x80900000 0x0 0x200000>;
464 reg = <0x0 0x80b00000 0x0 0x100000>;
469 reg = <0x0 0x80c00000 0x0 0x4600000>;
474 reg = <0x0 0x85700000 0x0 0x700000>;
479 reg = <0x0 0x85e00000 0x0 0x2100000>;
484 reg = <0x0 0x88000000 0x0 0x1900000>;
489 reg = <0x0 0x89900000 0x0 0x2000000>;
494 reg = <0x0 0x8b900000 0x0 0x10000>;
499 reg = <0x0 0x8b910000 0x0 0xa000>;
504 reg = <0x0 0x8b91a000 0x0 0x2000>;
509 reg = <0x0 0x8ba00000 0x0 0x180000>;
515 reg = <0x0 0x8bb80000 0x0 0x60000>;
521 reg = <0x0 0x8bbe0000 0x0 0x20000>;
526 reg = <0x0 0x8bc00000 0x0 0x13200000>;
531 reg = <0x0 0x9ee00000 0x0 0x700000>;
536 reg = <0x0 0x9f500000 0x0 0x800000>;
542 reg = <0x0 0x9fd00000 0x0 0x280000>;
550 reg = <0x0 0xa6e00000 0x0 0x40000>;
555 reg = <0x0 0xa6f00000 0x0 0x100000>;
561 /* Linux kernel image is loaded at 0xa0000000 */
564 reg = <0x0 0xbb000000 0x0 0x5000000>;
569 reg = <0x0 0xc0000000 0x0 0x20000000>;
574 reg = <0x0 0xe0000000 0x0 0x600000>;
579 reg = <0x0 0xe0600000 0x0 0x400000>;
584 reg = <0x0 0xe0a00000 0x0 0x100000>;
589 reg = <0x0 0xe0b00000 0x0 0x4af3000>;
594 reg = <0x0 0xe55f3000 0x0 0x9000>;
599 reg = <0x0 0xe55fc000 0x0 0x4000>;
604 reg = <0x0 0xe5600000 0x0 0x100000>;
609 reg = <0x0 0xe8800000 0x0 0x100000>;
614 reg = <0x0 0xe8900000 0x0 0x1200000>;
619 reg = <0x0 0xe9b00000 0x0 0x500000>;
624 reg = <0x0 0xea000000 0x0 0x3900000>;
629 reg = <0x0 0xed900000 0x0 0x3b00000>;
643 qcom,local-pid = <0>;
667 qcom,local-pid = <0>;
691 qcom,local-pid = <0>;
726 qcom,local-pid = <0>;
741 soc: soc@0 {
744 ranges = <0 0 0 0 0x10 0>;
745 dma-ranges = <0 0 0 0 0x10 0>;
750 reg = <0x0 0x00100000 0x0 0x1f4200>;
759 <&ufs_mem_phy 0>,
777 reg = <0 0x00800000 0 0x60000>;
791 dma-channel-mask = <0x7e>;
792 iommus = <&apps_smmu 0x496 0x0>;
798 reg = <0x0 0x008c0000 0x0 0x2000>;
802 iommus = <&apps_smmu 0x483 0x0>;
810 reg = <0x0 0x00880000 0x0 0x4000>;
814 pinctrl-0 = <&qup_i2c15_data_clk>;
817 #size-cells = <0>;
818 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
819 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
820 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
822 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
823 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
830 reg = <0x0 0x00880000 0x0 0x4000>;
835 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
836 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
837 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
839 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
840 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
843 #size-cells = <0>;
849 reg = <0x0 0x00884000 0x0 0x4000>;
853 pinctrl-0 = <&qup_i2c16_data_clk>;
856 #size-cells = <0>;
857 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
858 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
859 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
861 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
869 reg = <0x0 0x00884000 0x0 0x4000>;
874 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
875 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
876 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
878 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
882 #size-cells = <0>;
888 reg = <0x0 0x00888000 0x0 0x4000>;
892 pinctrl-0 = <&qup_i2c17_data_clk>;
895 #size-cells = <0>;
896 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
897 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
898 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
900 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
908 reg = <0x0 0x00888000 0x0 0x4000>;
913 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
914 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
915 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
917 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
921 #size-cells = <0>;
927 reg = <0x0 0x0088c000 0x0 0x4000>;
931 pinctrl-0 = <&qup_i2c18_data_clk>;
934 #size-cells = <0>;
935 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
936 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
937 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
939 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
947 reg = <0 0x0088c000 0 0x4000>;
952 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
953 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
954 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
956 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
960 #size-cells = <0>;
966 reg = <0x0 0x00890000 0x0 0x4000>;
970 pinctrl-0 = <&qup_i2c19_data_clk>;
973 #size-cells = <0>;
974 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
975 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
976 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
978 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
986 reg = <0 0x00890000 0 0x4000>;
991 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
992 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
993 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
995 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
999 #size-cells = <0>;
1005 reg = <0x0 0x00894000 0x0 0x4000>;
1009 pinctrl-0 = <&qup_i2c20_data_clk>;
1012 #size-cells = <0>;
1013 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1014 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1015 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1017 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1025 reg = <0 0x00894000 0 0x4000>;
1029 pinctrl-0 = <&qup_uart20_default>;
1042 reg = <0 0x00894000 0 0x4000>;
1047 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1048 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1049 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1051 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1055 #size-cells = <0>;
1061 reg = <0x0 0x00898000 0x0 0x4000>;
1065 pinctrl-0 = <&qup_i2c21_data_clk>;
1068 #size-cells = <0>;
1069 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1070 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1071 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1073 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1081 reg = <0 0x00898000 0 0x4000>;
1086 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1087 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1088 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1090 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1094 #size-cells = <0>;
1102 reg = <0 0x00900000 0 0x60000>;
1116 dma-channel-mask = <0x7e>;
1117 iommus = <&apps_smmu 0x5b6 0x0>;
1123 reg = <0x0 0x009c0000 0x0 0x2000>;
1127 iommus = <&apps_smmu 0x5a3 0x0>;
1128 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
1137 reg = <0x0 0x00980000 0x0 0x4000>;
1141 pinctrl-0 = <&qup_i2c0_data_clk>;
1144 #size-cells = <0>;
1145 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1146 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1147 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1149 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1150 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1157 reg = <0x0 0x00980000 0x0 0x4000>;
1162 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1165 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1166 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1167 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1169 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1170 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1173 #size-cells = <0>;
1179 reg = <0x0 0x00984000 0x0 0x4000>;
1183 pinctrl-0 = <&qup_i2c1_data_clk>;
1186 #size-cells = <0>;
1187 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1188 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1189 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1191 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1199 reg = <0x0 0x00984000 0x0 0x4000>;
1204 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1205 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1206 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1207 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1209 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1213 #size-cells = <0>;
1219 reg = <0x0 0x00988000 0x0 0x4000>;
1223 pinctrl-0 = <&qup_i2c2_data_clk>;
1226 #size-cells = <0>;
1227 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1228 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1229 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1231 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1239 reg = <0x0 0x00988000 0x0 0x4000>;
1244 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1245 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1246 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1247 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1249 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1253 #size-cells = <0>;
1260 reg = <0x0 0x0098c000 0x0 0x4000>;
1264 pinctrl-0 = <&qup_i2c3_data_clk>;
1267 #size-cells = <0>;
1268 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1269 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1270 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1272 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1280 reg = <0x0 0x0098c000 0x0 0x4000>;
1285 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1286 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1287 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1288 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1290 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1294 #size-cells = <0>;
1300 reg = <0x0 0x00990000 0x0 0x4000>;
1304 pinctrl-0 = <&qup_i2c4_data_clk>;
1307 #size-cells = <0>;
1308 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1309 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1310 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1312 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1320 reg = <0x0 0x00990000 0x0 0x4000>;
1325 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1328 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1329 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1330 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1332 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1336 #size-cells = <0>;
1342 reg = <0x0 0x00994000 0x0 0x4000>;
1346 pinctrl-0 = <&qup_i2c5_data_clk>;
1349 #size-cells = <0>;
1350 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1351 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1352 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1354 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1362 reg = <0x0 0x00994000 0x0 0x4000>;
1367 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1368 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1369 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1370 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1372 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1376 #size-cells = <0>;
1383 reg = <0x0 0x00998000 0x0 0x4000>;
1387 pinctrl-0 = <&qup_i2c6_data_clk>;
1390 #size-cells = <0>;
1391 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1392 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1393 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1395 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1403 reg = <0x0 0x00998000 0x0 0x4000>;
1408 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1409 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1410 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1411 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1413 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1417 #size-cells = <0>;
1423 reg = <0 0x0099c000 0 0x4000>;
1427 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1442 reg = <0 0x00a00000 0 0x60000>;
1456 dma-channel-mask = <0x7e>;
1457 iommus = <&apps_smmu 0x56 0x0>;
1463 reg = <0x0 0x00ac0000 0x0 0x6000>;
1467 iommus = <&apps_smmu 0x43 0x0>;
1468 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1477 reg = <0x0 0x00a80000 0x0 0x4000>;
1481 pinctrl-0 = <&qup_i2c8_data_clk>;
1484 #size-cells = <0>;
1485 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1486 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1487 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1489 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1490 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1497 reg = <0x0 0x00a80000 0x0 0x4000>;
1502 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1503 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1504 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1505 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1507 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1508 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1511 #size-cells = <0>;
1517 reg = <0x0 0x00a84000 0x0 0x4000>;
1521 pinctrl-0 = <&qup_i2c9_data_clk>;
1524 #size-cells = <0>;
1525 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1526 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1527 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1529 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1537 reg = <0x0 0x00a84000 0x0 0x4000>;
1542 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1543 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1544 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1545 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1547 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1551 #size-cells = <0>;
1557 reg = <0x0 0x00a88000 0x0 0x4000>;
1561 pinctrl-0 = <&qup_i2c10_data_clk>;
1564 #size-cells = <0>;
1565 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1566 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1567 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1569 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1577 reg = <0x0 0x00a88000 0x0 0x4000>;
1582 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1583 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1584 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1585 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1587 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1591 #size-cells = <0>;
1597 reg = <0x0 0x00a8c000 0x0 0x4000>;
1601 pinctrl-0 = <&qup_i2c11_data_clk>;
1604 #size-cells = <0>;
1605 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1606 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1607 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1609 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1617 reg = <0x0 0x00a8c000 0x0 0x4000>;
1622 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1623 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1624 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1625 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1627 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1631 #size-cells = <0>;
1637 reg = <0x0 0x00a90000 0x0 0x4000>;
1641 pinctrl-0 = <&qup_i2c12_data_clk>;
1644 #size-cells = <0>;
1645 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1646 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1647 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1649 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1657 reg = <0x0 0x00a90000 0x0 0x4000>;
1662 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1663 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1664 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1665 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1667 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1671 #size-cells = <0>;
1677 reg = <0 0x00a94000 0 0x4000>;
1681 pinctrl-0 = <&qup_i2c13_data_clk>;
1683 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1684 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1685 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1687 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1691 #size-cells = <0>;
1697 reg = <0x0 0x00a94000 0x0 0x4000>;
1702 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1703 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1704 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1705 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1707 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1711 #size-cells = <0>;
1717 reg = <0 0x00a98000 0 0x4000>;
1721 pinctrl-0 = <&qup_i2c14_data_clk>;
1723 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1724 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1725 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1727 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1731 #size-cells = <0>;
1737 reg = <0x0 0x00a98000 0x0 0x4000>;
1742 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1743 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1744 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1745 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1747 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1751 #size-cells = <0>;
1758 reg = <0 0x010c3000 0 0x1000>;
1763 reg = <0 0x01c00000 0 0x3000>,
1764 <0 0x60000000 0 0xf1d>,
1765 <0 0x60000f20 0 0xa8>,
1766 <0 0x60001000 0 0x1000>,
1767 <0 0x60100000 0 0x100000>;
1770 linux,pci-domain = <0>;
1771 bus-range = <0x00 0xff>;
1777 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1778 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1780 msi-map = <0x0 &gic_its 0x5980 0x1>,
1781 <0x100 &gic_its 0x5981 0x1>;
1782 msi-map-mask = <0xff00>;
1800 interrupt-map-mask = <0 0 0 0x7>;
1801 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1802 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1803 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1804 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1837 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1838 <0x100 &apps_smmu 0x1c01 0x1>;
1852 pinctrl-0 = <&pcie0_default_state>;
1883 pcie@0 {
1885 reg = <0x0 0x0 0x0 0x0 0x0>;
1886 bus-range = <0x01 0xff>;
1896 reg = <0 0x01c06000 0 0x2000>;
1910 #clock-cells = <0>;
1912 #phy-cells = <0>;
1925 reg = <0 0x01c08000 0 0x3000>,
1926 <0 0x40000000 0 0xf1d>,
1927 <0 0x40000f20 0 0xa8>,
1928 <0 0x40001000 0 0x1000>,
1929 <0 0x40100000 0 0x100000>;
1933 bus-range = <0x00 0xff>;
1939 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1940 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1942 msi-map = <0x0 &gic_its 0x5a00 0x1>,
1943 <0x100 &gic_its 0x5a01 0x1>;
1944 msi-map-mask = <0xff00>;
1962 interrupt-map-mask = <0 0 0 0x7>;
1963 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1964 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1965 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1966 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1997 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1998 <0x100 &apps_smmu 0x1c81 0x1>;
2012 pinctrl-0 = <&pcie1_default_state>;
2064 pcie@0 {
2066 reg = <0x0 0x0 0x0 0x0 0x0>;
2067 bus-range = <0x01 0xff>;
2077 reg = <0 0x01c0e000 0 0x2000>;
2093 #phy-cells = <0>;
2106 reg = <0 0x01500000 0 0x1c000>;
2113 reg = <0 0x01680000 0 0x1e200>;
2120 reg = <0 0x016c0000 0 0xe280>;
2127 reg = <0 0x016e0000 0 0x1c080>;
2136 reg = <0 0x01700000 0 0x31080>;
2147 reg = <0 0x01740000 0 0x1f080>;
2154 reg = <0x0 0x01f40000 0x0 0x40000>;
2160 reg = <0x0 0x1fc0000 0x0 0x30000>;
2165 reg = <0x0 0x03d00000 0x0 0x40000>,
2166 <0x0 0x03d9e000 0x0 0x1000>,
2167 <0x0 0x03d61000 0x0 0x800>;
2174 iommus = <&adreno_smmu 0 0x400>,
2175 <&adreno_smmu 1 0x400>;
2255 reg = <0x0 0x03d6a000 0x0 0x35000>,
2256 <0x0 0x03d50000 0x0 0x10000>,
2257 <0x0 0x0b290000 0x0 0x10000>;
2284 iommus = <&adreno_smmu 5 0x400>;
2307 reg = <0x0 0x03d90000 0x0 0xa000>;
2319 reg = <0x0 0x03da0000 0x0 0x40000>;
2367 reg = <0 0x088e3000 0 0x400>;
2369 #phy-cells = <0>;
2379 reg = <0 0x088e8000 0 0x3000>;
2400 #size-cells = <0>;
2402 port@0 {
2403 reg = <0>;
2429 reg = <0 0x02400000 0 0x4000>;
2432 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2450 qcom,smem-states = <&smp2p_slpi_out 0>;
2471 #size-cells = <0>;
2476 iommus = <&apps_smmu 0x0541 0x0>;
2482 iommus = <&apps_smmu 0x0542 0x0>;
2488 iommus = <&apps_smmu 0x0543 0x0>;
2497 reg = <0 0x031e0000 0 0x1000>;
2505 #clock-cells = <0>;
2512 reg = <0 0x031f0000 0 0x2000>;
2518 pinctrl-0 = <&wsa2_swr_active>;
2524 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2525 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2526 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2527 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2528 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2529 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2530 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2531 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2532 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2535 #size-cells = <0>;
2542 reg = <0 0x03200000 0 0x1000>;
2550 #clock-cells = <0>;
2557 reg = <0 0x03210000 0 0x2000>;
2562 qcom,din-ports = <0>;
2565 pinctrl-0 = <&rx_swr_active>;
2568 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2569 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2570 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2571 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2572 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2573 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2574 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2575 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2576 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2579 #size-cells = <0>;
2586 reg = <0 0x03220000 0 0x1000>;
2594 #clock-cells = <0>;
2601 reg = <0 0x03240000 0 0x1000>;
2609 #clock-cells = <0>;
2616 reg = <0 0x03250000 0 0x2000>;
2622 pinctrl-0 = <&wsa_swr_active>;
2628 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2629 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2630 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2631 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2632 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2633 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2634 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2635 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2636 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2639 #size-cells = <0>;
2646 reg = <0 0x033b0000 0 0x2000>;
2655 pinctrl-0 = <&tx_swr_active>;
2659 qcom,dout-ports = <0>;
2660 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2661 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2662 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2663 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2664 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2665 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2666 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2667 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2668 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2671 #size-cells = <0>;
2678 reg = <0 0x033f0000 0 0x1000>;
2685 #clock-cells = <0>;
2693 reg = <0 0x30000000 0 0x100>;
2696 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2714 qcom,smem-states = <&smp2p_adsp_out 0>;
2735 #size-cells = <0>;
2740 #sound-dai-cells = <0>;
2746 iommus = <&apps_smmu 0x1801 0x0>;
2774 #size-cells = <0>;
2779 iommus = <&apps_smmu 0x1803 0x0>;
2785 iommus = <&apps_smmu 0x1804 0x0>;
2791 iommus = <&apps_smmu 0x1805 0x0>;
2799 reg = <0 0x32300000 0 0x1400000>;
2802 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2820 qcom,smem-states = <&smp2p_cdsp_out 0>;
2841 #size-cells = <0>;
2846 iommus = <&apps_smmu 0x2161 0x0400>,
2847 <&apps_smmu 0x1021 0x1420>;
2853 iommus = <&apps_smmu 0x2162 0x0400>,
2854 <&apps_smmu 0x1022 0x1420>;
2860 iommus = <&apps_smmu 0x2163 0x0400>,
2861 <&apps_smmu 0x1023 0x1420>;
2867 iommus = <&apps_smmu 0x2164 0x0400>,
2868 <&apps_smmu 0x1024 0x1420>;
2874 iommus = <&apps_smmu 0x2165 0x0400>,
2875 <&apps_smmu 0x1025 0x1420>;
2881 iommus = <&apps_smmu 0x2166 0x0400>,
2882 <&apps_smmu 0x1026 0x1420>;
2888 iommus = <&apps_smmu 0x2167 0x0400>,
2889 <&apps_smmu 0x1027 0x1420>;
2895 iommus = <&apps_smmu 0x2168 0x0400>,
2896 <&apps_smmu 0x1028 0x1420>;
2906 reg = <0x0 0x04080000 0x0 0x4040>;
2909 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2928 qcom,smem-states = <&smp2p_modem_out 0>;
2946 reg = <0 0x0aaf0000 0 0x10000>;
2958 reg = <0 0x0ac15000 0 0x1000>;
2972 pinctrl-0 = <&cci0_default &cci1_default>;
2978 #size-cells = <0>;
2980 cci0_i2c0: i2c-bus@0 {
2981 reg = <0>;
2984 #size-cells = <0>;
2991 #size-cells = <0>;
2997 reg = <0 0x0ac16000 0 0x1000>;
3011 pinctrl-0 = <&cci2_default &cci3_default>;
3017 #size-cells = <0>;
3019 cci1_i2c0: i2c-bus@0 {
3020 reg = <0>;
3023 #size-cells = <0>;
3030 #size-cells = <0>;
3036 reg = <0 0x0ade0000 0 0x20000>;
3051 reg = <0 0x0ae00000 0 0x1000>;
3055 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
3056 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
3076 iommus = <&apps_smmu 0x2800 0x402>;
3086 reg = <0 0x0ae01000 0 0x8f000>,
3087 <0 0x0aeb0000 0 0x2008>;
3110 interrupts = <0>;
3114 #size-cells = <0>;
3116 port@0 {
3117 reg = <0>;
3170 reg = <0 0xae90000 0 0x200>,
3171 <0 0xae90200 0 0x200>,
3172 <0 0xae90400 0 0xc00>,
3173 <0 0xae91000 0 0x400>,
3174 <0 0xae91400 0 0x400>;
3196 #sound-dai-cells = <0>;
3205 #size-cells = <0>;
3207 port@0 {
3208 reg = <0>;
3250 reg = <0 0x0ae94000 0 0x400>;
3270 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3279 #size-cells = <0>;
3285 #size-cells = <0>;
3287 port@0 {
3288 reg = <0>;
3323 reg = <0 0x0ae94400 0 0x200>,
3324 <0 0x0ae94600 0 0x280>,
3325 <0 0x0ae94900 0 0x260>;
3331 #phy-cells = <0>;
3342 reg = <0 0x0ae96000 0 0x400>;
3362 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
3371 #size-cells = <0>;
3377 #size-cells = <0>;
3379 port@0 {
3380 reg = <0>;
3396 reg = <0 0x0ae96400 0 0x200>,
3397 <0 0x0ae96600 0 0x280>,
3398 <0 0x0ae96900 0 0x260>;
3404 #phy-cells = <0>;
3416 reg = <0 0x0af00000 0 0x20000>;
3421 <&mdss_dsi0_phy 0>,
3423 <&mdss_dsi1_phy 0>,
3427 <0>, /* dp1 */
3428 <0>,
3429 <0>, /* dp2 */
3430 <0>,
3431 <0>, /* dp3 */
3432 <0>;
3443 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
3444 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
3453 reg = <0 0x0c263000 0 0x1000>, /* TM */
3454 <0 0x0c222000 0 0x1000>; /* SROT */
3464 reg = <0 0x0c265000 0 0x1000>, /* TM */
3465 <0 0x0c223000 0 0x1000>; /* SROT */
3475 reg = <0 0x0c300000 0 0x400>;
3480 #clock-cells = <0>;
3485 reg = <0 0x0c3f0000 0 0x400>;
3490 reg = <0 0x0c400000 0 0x00003000>,
3491 <0 0x0c500000 0 0x00400000>,
3492 <0 0x0c440000 0 0x00080000>,
3493 <0 0x0c4c0000 0 0x00010000>,
3494 <0 0x0c42d000 0 0x00010000>;
3502 qcom,ee = <0>;
3503 qcom,channel = <0>;
3507 #size-cells = <0>;
3512 reg = <0 0x0ed18000 0 0x1000>;
3521 reg = <0 0x0f100000 0 0x300000>;
3527 gpio-ranges = <&tlmm 0 0 211>;
4031 reg = <0 0x03440000 0x0 0x20000>,
4032 <0 0x034d0000 0x0 0x10000>;
4035 gpio-ranges = <&lpass_tlmm 0 0 23>;
4146 reg = <0 0x146aa000 0 0x1000>;
4147 ranges = <0 0 0x146aa000 0x1000>;
4154 reg = <0x94c 0xc8>;
4160 reg = <0 0x15000000 0 0x100000>;
4267 redistributor-stride = <0x0 0x40000>;
4268 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */
4269 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */
4277 reg = <0x0 0x17140000 0x0 0x20000>;
4287 ranges = <0 0 0 0x20000000>;
4288 reg = <0x0 0x17420000 0x0 0x1000>;
4292 frame-number = <0>;
4295 reg = <0x17421000 0x1000>,
4296 <0x17422000 0x1000>;
4302 reg = <0x17423000 0x1000>;
4309 reg = <0x17425000 0x1000>;
4316 reg = <0x17427000 0x1000>;
4323 reg = <0x17429000 0x1000>;
4330 reg = <0x1742b000 0x1000>;
4337 reg = <0x1742d000 0x1000>;
4345 reg = <0x0 0x17a00000 0x0 0x10000>,
4346 <0x0 0x17a10000 0x0 0x10000>,
4347 <0x0 0x17a20000 0x0 0x10000>,
4348 <0x0 0x17a30000 0x0 0x10000>;
4349 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4353 qcom,tcs-offset = <0xd00>;
4356 <WAKE_TCS 2>, <CONTROL_TCS 0>;
4439 reg = <0 0x17d91000 0 0x1000>,
4440 <0 0x17d92000 0 0x1000>,
4441 <0 0x17d93000 0 0x1000>;
4448 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4455 reg = <0 0x19100000 0 0xbb800>;
4462 reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>,
4463 <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>,
4464 <0 0x19a00000 0 0x80000>, <0 0x19c00000 0 0x80000>;
4474 reg = <0 0x01d84000 0 0x3000>;
4485 iommus = <&apps_smmu 0xe0 0x0>;
4488 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
4489 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
4511 <0 0>,
4512 <0 0>,
4515 <0 0>,
4516 <0 0>,
4517 <0 0>;
4525 reg = <0 0x01d87000 0 0x1000>;
4534 resets = <&ufs_mem_hc 0>;
4538 #phy-cells = <0>;
4546 reg = <0 0x01d88000 0 0x8000>;
4552 reg = <0 0x01dc4000 0 0x28000>;
4555 qcom,ee = <0>;
4557 iommus = <&apps_smmu 0x584 0x11>,
4558 <&apps_smmu 0x588 0x0>,
4559 <&apps_smmu 0x598 0x5>,
4560 <&apps_smmu 0x59a 0x0>,
4561 <&apps_smmu 0x59f 0x0>;
4566 reg = <0 0x01dfa000 0 0x6000>;
4569 iommus = <&apps_smmu 0x584 0x11>,
4570 <&apps_smmu 0x588 0x0>,
4571 <&apps_smmu 0x598 0x5>,
4572 <&apps_smmu 0x59a 0x0>,
4573 <&apps_smmu 0x59f 0x0>;
4574 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
4580 reg = <0 0x08804000 0 0x1000>;
4591 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
4592 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
4594 iommus = <&apps_smmu 0x4a0 0x0>;
4601 sdhci-caps-mask = <0x3 0x0>;
4622 reg = <0 0x0a6f8800 0 0x400>;
4660 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
4661 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4666 reg = <0 0x0a600000 0 0xcd00>;
4668 iommus = <&apps_smmu 0x0 0x0>;
4676 #size-cells = <0>;
4678 port@0 {
4679 reg = <0>;
4698 reg = <0 0x320c0000 0 0x10000>;
4705 reg = <0 0x03c40000 0 0x17200>;
4716 thermal-sensors = <&tsens0 0>;
5088 thermal-sensors = <&tsens1 0>;