Lines Matching +full:0 +full:x1f4200
40 #clock-cells = <0>;
46 #clock-cells = <0>;
53 #size-cells = <0>;
55 cpu0: cpu@0 {
58 reg = <0x0 0x0>;
63 qcom,freq-domain = <&cpufreq_hw 0>;
65 clocks = <&cpufreq_hw 0>;
82 reg = <0x0 0x100>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
89 clocks = <&cpufreq_hw 0>;
101 reg = <0x0 0x200>;
106 qcom,freq-domain = <&cpufreq_hw 0>;
108 clocks = <&cpufreq_hw 0>;
120 reg = <0x0 0x300>;
125 qcom,freq-domain = <&cpufreq_hw 0>;
127 clocks = <&cpufreq_hw 0>;
139 reg = <0x0 0x400>;
158 reg = <0x0 0x500>;
177 reg = <0x0 0x600>;
196 reg = <0x0 0x700>;
251 little_cpu_sleep_0: cpu-sleep-0-0 {
254 arm,psci-suspend-param = <0x40000004>;
261 big_cpu_sleep_0: cpu-sleep-1-0 {
264 arm,psci-suspend-param = <0x40000004>;
273 cluster_sleep_0: cluster-sleep-0 {
275 arm,psci-suspend-param = <0x41000044>;
283 arm,psci-suspend-param = <0x4100c344>;
291 ete-0 {
409 #size-cells = <0>;
411 port@0 {
412 reg = <0>;
480 qcom,dload-mode = <&tcsr 0x13000>;
481 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
486 clk_virt: interconnect-0 {
501 reg = <0x0 0xa0000000 0x0 0x0>;
514 #power-domain-cells = <0>;
520 #power-domain-cells = <0>;
526 #power-domain-cells = <0>;
532 #power-domain-cells = <0>;
538 #power-domain-cells = <0>;
544 #power-domain-cells = <0>;
550 #power-domain-cells = <0>;
556 #power-domain-cells = <0>;
562 #power-domain-cells = <0>;
592 reg = <0x0 0x80000000 0x0 0x600000>;
597 reg = <0x0 0x80600000 0x0 0x40000>;
602 reg = <0x0 0x80640000 0x0 0x180000>;
607 reg = <0x0 0x807c0000 0x0 0x40000>;
612 reg = <0x0 0x80800000 0x0 0x60000>;
618 reg = <0x0 0x80860000 0x0 0x20000>;
623 reg = <0x0 0x80880000 0x0 0x20000>;
628 reg = <0x0 0x808a0000 0x0 0x40000>;
633 reg = <0x0 0x808e0000 0x0 0x4000>;
638 reg = <0x0 0x808e4000 0x0 0x10000>;
645 reg = <0x0 0x80900000 0x0 0x200000>;
651 reg = <0x0 0x80b00000 0x0 0x100000>;
656 reg = <0x0 0x80c00000 0x0 0x4600000>;
661 reg = <0x0 0x85700000 0x0 0x700000>;
666 reg = <0x0 0x85e00000 0x0 0x2100000>;
671 reg = <0x0 0x88000000 0x0 0x1900000>;
676 reg = <0x0 0x89900000 0x0 0x2000000>;
681 reg = <0x0 0x8b900000 0x0 0x10000>;
686 reg = <0x0 0x8b910000 0x0 0xa000>;
691 reg = <0x0 0x8b91a000 0x0 0x2000>;
696 reg = <0x0 0x8ba00000 0x0 0x180000>;
702 reg = <0x0 0x8bb80000 0x0 0x60000>;
708 reg = <0x0 0x8bbe0000 0x0 0x20000>;
713 reg = <0x0 0x8bc00000 0x0 0x13200000>;
718 reg = <0x0 0x9ee00000 0x0 0x700000>;
723 reg = <0x0 0x9f500000 0x0 0x800000>;
729 reg = <0x0 0x9fd00000 0x0 0x280000>;
737 reg = <0x0 0xa6e00000 0x0 0x40000>;
742 reg = <0x0 0xa6f00000 0x0 0x100000>;
748 /* Linux kernel image is loaded at 0xa0000000 */
751 reg = <0x0 0xbb000000 0x0 0x5000000>;
756 reg = <0x0 0xc0000000 0x0 0x20000000>;
761 reg = <0x0 0xe0000000 0x0 0x600000>;
766 reg = <0x0 0xe0600000 0x0 0x400000>;
771 reg = <0x0 0xe0a00000 0x0 0x100000>;
776 reg = <0x0 0xe0b00000 0x0 0x4af3000>;
781 reg = <0x0 0xe55f3000 0x0 0x9000>;
786 reg = <0x0 0xe55fc000 0x0 0x4000>;
791 reg = <0x0 0xe5600000 0x0 0x100000>;
796 reg = <0x0 0xe8800000 0x0 0x100000>;
801 reg = <0x0 0xe8900000 0x0 0x1200000>;
806 reg = <0x0 0xe9b00000 0x0 0x500000>;
811 reg = <0x0 0xea000000 0x0 0x3900000>;
816 reg = <0x0 0xed900000 0x0 0x3b00000>;
830 qcom,local-pid = <0>;
854 qcom,local-pid = <0>;
878 qcom,local-pid = <0>;
913 qcom,local-pid = <0>;
928 soc: soc@0 {
931 ranges = <0 0 0 0 0x10 0>;
932 dma-ranges = <0 0 0 0 0x10 0>;
937 reg = <0x0 0x00100000 0x0 0x1f4200>;
946 <&ufs_mem_phy 0>,
964 reg = <0 0x00800000 0 0x60000>;
978 dma-channel-mask = <0x7e>;
979 iommus = <&apps_smmu 0x496 0x0>;
985 reg = <0x0 0x008c0000 0x0 0x2000>;
989 iommus = <&apps_smmu 0x483 0x0>;
997 reg = <0x0 0x00880000 0x0 0x4000>;
1001 pinctrl-0 = <&qup_i2c15_data_clk>;
1004 #size-cells = <0>;
1005 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1006 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1007 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1009 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1010 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1017 reg = <0x0 0x00880000 0x0 0x4000>;
1022 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1023 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1024 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1026 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1027 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1030 #size-cells = <0>;
1036 reg = <0x0 0x00884000 0x0 0x4000>;
1040 pinctrl-0 = <&qup_i2c16_data_clk>;
1043 #size-cells = <0>;
1044 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1045 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1046 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1048 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1056 reg = <0x0 0x00884000 0x0 0x4000>;
1061 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
1062 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1063 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1065 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1069 #size-cells = <0>;
1075 reg = <0x0 0x00888000 0x0 0x4000>;
1079 pinctrl-0 = <&qup_i2c17_data_clk>;
1082 #size-cells = <0>;
1083 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1084 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1085 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1087 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1095 reg = <0x0 0x00888000 0x0 0x4000>;
1100 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
1101 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1102 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1104 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1108 #size-cells = <0>;
1114 reg = <0x0 0x0088c000 0x0 0x4000>;
1118 pinctrl-0 = <&qup_i2c18_data_clk>;
1121 #size-cells = <0>;
1122 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1123 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1124 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1126 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1134 reg = <0 0x0088c000 0 0x4000>;
1139 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
1140 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1141 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1143 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1147 #size-cells = <0>;
1153 reg = <0x0 0x00890000 0x0 0x4000>;
1157 pinctrl-0 = <&qup_i2c19_data_clk>;
1160 #size-cells = <0>;
1161 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1162 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1163 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1165 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1173 reg = <0 0x00890000 0 0x4000>;
1178 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
1179 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1180 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1182 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1186 #size-cells = <0>;
1192 reg = <0x0 0x00894000 0x0 0x4000>;
1196 pinctrl-0 = <&qup_i2c20_data_clk>;
1199 #size-cells = <0>;
1200 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1201 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1202 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1204 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1212 reg = <0 0x00894000 0 0x4000>;
1216 pinctrl-0 = <&qup_uart20_default>;
1229 reg = <0 0x00894000 0 0x4000>;
1234 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1235 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1236 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1238 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1242 #size-cells = <0>;
1248 reg = <0x0 0x00898000 0x0 0x4000>;
1252 pinctrl-0 = <&qup_i2c21_data_clk>;
1255 #size-cells = <0>;
1256 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1257 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1258 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1260 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1268 reg = <0 0x00898000 0 0x4000>;
1273 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1274 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1275 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1277 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1281 #size-cells = <0>;
1289 reg = <0 0x00900000 0 0x60000>;
1303 dma-channel-mask = <0x7e>;
1304 iommus = <&apps_smmu 0x5b6 0x0>;
1310 reg = <0x0 0x009c0000 0x0 0x2000>;
1314 iommus = <&apps_smmu 0x5a3 0x0>;
1315 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
1324 reg = <0x0 0x00980000 0x0 0x4000>;
1328 pinctrl-0 = <&qup_i2c0_data_clk>;
1331 #size-cells = <0>;
1332 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1333 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1334 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1336 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1337 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1344 reg = <0x0 0x00980000 0x0 0x4000>;
1349 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1352 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1353 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1354 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1356 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1357 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1360 #size-cells = <0>;
1366 reg = <0x0 0x00984000 0x0 0x4000>;
1370 pinctrl-0 = <&qup_i2c1_data_clk>;
1373 #size-cells = <0>;
1374 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1375 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1376 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1378 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1386 reg = <0x0 0x00984000 0x0 0x4000>;
1391 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1392 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1393 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1394 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1396 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1400 #size-cells = <0>;
1406 reg = <0x0 0x00988000 0x0 0x4000>;
1410 pinctrl-0 = <&qup_i2c2_data_clk>;
1413 #size-cells = <0>;
1414 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1415 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1416 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1418 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1426 reg = <0x0 0x00988000 0x0 0x4000>;
1431 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1432 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1433 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1434 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1436 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1440 #size-cells = <0>;
1447 reg = <0x0 0x0098c000 0x0 0x4000>;
1451 pinctrl-0 = <&qup_i2c3_data_clk>;
1454 #size-cells = <0>;
1455 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1456 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1457 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1459 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1467 reg = <0x0 0x0098c000 0x0 0x4000>;
1472 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1473 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1474 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1475 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1477 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1481 #size-cells = <0>;
1487 reg = <0x0 0x00990000 0x0 0x4000>;
1491 pinctrl-0 = <&qup_i2c4_data_clk>;
1494 #size-cells = <0>;
1495 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1496 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1497 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1499 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1507 reg = <0x0 0x00990000 0x0 0x4000>;
1512 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1515 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1516 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1517 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1519 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1523 #size-cells = <0>;
1529 reg = <0x0 0x00994000 0x0 0x4000>;
1533 pinctrl-0 = <&qup_i2c5_data_clk>;
1536 #size-cells = <0>;
1537 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1538 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1539 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1541 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1549 reg = <0x0 0x00994000 0x0 0x4000>;
1554 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1555 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1556 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1557 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1559 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1563 #size-cells = <0>;
1570 reg = <0x0 0x00998000 0x0 0x4000>;
1574 pinctrl-0 = <&qup_i2c6_data_clk>;
1577 #size-cells = <0>;
1578 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1579 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1580 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1582 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1590 reg = <0x0 0x00998000 0x0 0x4000>;
1595 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1596 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1597 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1598 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1600 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1604 #size-cells = <0>;
1610 reg = <0 0x0099c000 0 0x4000>;
1614 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1629 reg = <0 0x00a00000 0 0x60000>;
1643 dma-channel-mask = <0x7e>;
1644 iommus = <&apps_smmu 0x56 0x0>;
1650 reg = <0x0 0x00ac0000 0x0 0x6000>;
1654 iommus = <&apps_smmu 0x43 0x0>;
1655 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1664 reg = <0x0 0x00a80000 0x0 0x4000>;
1668 pinctrl-0 = <&qup_i2c8_data_clk>;
1671 #size-cells = <0>;
1672 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1673 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1674 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1676 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1677 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1684 reg = <0x0 0x00a80000 0x0 0x4000>;
1689 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1690 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1691 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1692 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1694 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1695 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1698 #size-cells = <0>;
1704 reg = <0x0 0x00a84000 0x0 0x4000>;
1708 pinctrl-0 = <&qup_i2c9_data_clk>;
1711 #size-cells = <0>;
1712 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1713 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1714 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1716 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1724 reg = <0x0 0x00a84000 0x0 0x4000>;
1729 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1730 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1731 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1732 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1734 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1738 #size-cells = <0>;
1744 reg = <0x0 0x00a88000 0x0 0x4000>;
1748 pinctrl-0 = <&qup_i2c10_data_clk>;
1751 #size-cells = <0>;
1752 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1753 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1754 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1756 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1764 reg = <0x0 0x00a88000 0x0 0x4000>;
1769 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1770 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1771 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1772 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1774 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1778 #size-cells = <0>;
1784 reg = <0x0 0x00a8c000 0x0 0x4000>;
1788 pinctrl-0 = <&qup_i2c11_data_clk>;
1791 #size-cells = <0>;
1792 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1793 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1794 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1796 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1804 reg = <0x0 0x00a8c000 0x0 0x4000>;
1809 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1810 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1811 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1812 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1814 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1818 #size-cells = <0>;
1824 reg = <0x0 0x00a90000 0x0 0x4000>;
1828 pinctrl-0 = <&qup_i2c12_data_clk>;
1831 #size-cells = <0>;
1832 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1833 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1834 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1836 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1844 reg = <0x0 0x00a90000 0x0 0x4000>;
1849 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1850 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1851 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1852 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1854 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1858 #size-cells = <0>;
1864 reg = <0 0x00a94000 0 0x4000>;
1868 pinctrl-0 = <&qup_i2c13_data_clk>;
1870 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1871 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1872 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1874 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1878 #size-cells = <0>;
1884 reg = <0x0 0x00a94000 0x0 0x4000>;
1889 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1890 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1891 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1892 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1894 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1898 #size-cells = <0>;
1904 reg = <0 0x00a98000 0 0x4000>;
1908 pinctrl-0 = <&qup_i2c14_data_clk>;
1910 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1911 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1912 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1914 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1918 #size-cells = <0>;
1924 reg = <0x0 0x00a98000 0x0 0x4000>;
1929 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1930 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1931 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1932 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1934 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1938 #size-cells = <0>;
1945 reg = <0 0x010c3000 0 0x1000>;
1950 reg = <0 0x01c00000 0 0x3000>,
1951 <0 0x60000000 0 0xf1d>,
1952 <0 0x60000f20 0 0xa8>,
1953 <0 0x60001000 0 0x1000>,
1954 <0 0x60100000 0 0x100000>;
1957 linux,pci-domain = <0>;
1958 bus-range = <0x00 0xff>;
1964 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1965 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1967 msi-map = <0x0 &gic_its 0x5980 0x1>,
1968 <0x100 &gic_its 0x5981 0x1>;
1969 msi-map-mask = <0xff00>;
1989 interrupt-map-mask = <0 0 0 0x7>;
1990 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1991 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1992 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1993 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2026 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2027 <0x100 &apps_smmu 0x1c01 0x1>;
2041 pinctrl-0 = <&pcie0_default_state>;
2072 pcieport0: pcie@0 {
2074 reg = <0x0 0x0 0x0 0x0 0x0>;
2075 bus-range = <0x01 0xff>;
2085 reg = <0 0x01c06000 0 0x2000>;
2099 #clock-cells = <0>;
2101 #phy-cells = <0>;
2114 reg = <0 0x01c08000 0 0x3000>,
2115 <0 0x40000000 0 0xf1d>,
2116 <0 0x40000f20 0 0xa8>,
2117 <0 0x40001000 0 0x1000>,
2118 <0 0x40100000 0 0x100000>;
2122 bus-range = <0x00 0xff>;
2128 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2129 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2131 msi-map = <0x0 &gic_its 0x5a00 0x1>,
2132 <0x100 &gic_its 0x5a01 0x1>;
2133 msi-map-mask = <0xff00>;
2153 interrupt-map-mask = <0 0 0 0x7>;
2154 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2155 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2156 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2157 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2188 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2189 <0x100 &apps_smmu 0x1c81 0x1>;
2203 pinctrl-0 = <&pcie1_default_state>;
2255 pcie@0 {
2257 reg = <0x0 0x0 0x0 0x0 0x0>;
2258 bus-range = <0x01 0xff>;
2268 reg = <0x0 0x01c08000 0x0 0x3000>,
2269 <0x0 0x40000000 0x0 0xf1d>,
2270 <0x0 0x40000f20 0x0 0xa8>,
2271 <0x0 0x40001000 0x0 0x1000>,
2272 <0x0 0x40200000 0x0 0x1000000>,
2273 <0x0 0x01c0b000 0x0 0x1000>,
2274 <0x0 0x40002000 0x0 0x1000>;
2314 iommus = <&apps_smmu 0x1c80 0x7f>;
2323 pinctrl-0 = <&pcie1_default_state>;
2330 reg = <0 0x01c0e000 0 0x2000>;
2346 #phy-cells = <0>;
2359 reg = <0 0x01500000 0 0x1c000>;
2366 reg = <0 0x01680000 0 0x1e200>;
2373 reg = <0 0x016c0000 0 0xe280>;
2380 reg = <0 0x016e0000 0 0x1c080>;
2389 reg = <0 0x01700000 0 0x31080>;
2400 reg = <0 0x01740000 0 0x1f080>;
2407 reg = <0x0 0x01f40000 0x0 0x40000>;
2413 reg = <0x0 0x1fc0000 0x0 0x30000>;
2418 reg = <0x0 0x03d00000 0x0 0x40000>,
2419 <0x0 0x03d9e000 0x0 0x1000>,
2420 <0x0 0x03d61000 0x0 0x800>;
2427 iommus = <&adreno_smmu 0 0x400>,
2428 <&adreno_smmu 1 0x400>;
2508 reg = <0x0 0x03d6a000 0x0 0x35000>,
2509 <0x0 0x03d50000 0x0 0x10000>,
2510 <0x0 0x0b290000 0x0 0x10000>;
2537 iommus = <&adreno_smmu 5 0x400>;
2560 reg = <0x0 0x03d90000 0x0 0xa000>;
2572 reg = <0x0 0x03da0000 0x0 0x40000>;
2620 reg = <0 0x088e3000 0 0x400>;
2622 #phy-cells = <0>;
2632 reg = <0 0x088e8000 0 0x3000>;
2653 #size-cells = <0>;
2655 port@0 {
2656 reg = <0>;
2682 reg = <0 0x02400000 0 0x4000>;
2685 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2703 qcom,smem-states = <&smp2p_slpi_out 0>;
2724 #size-cells = <0>;
2729 iommus = <&apps_smmu 0x0541 0x0>;
2735 iommus = <&apps_smmu 0x0542 0x0>;
2741 iommus = <&apps_smmu 0x0543 0x0>;
2750 reg = <0x0 0x03000000 0x0 0x10000>;
2753 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2771 qcom,smem-states = <&smp2p_adsp_out 0>;
2792 #size-cells = <0>;
2797 #sound-dai-cells = <0>;
2803 iommus = <&apps_smmu 0x1801 0x0>;
2831 #size-cells = <0>;
2836 iommus = <&apps_smmu 0x1803 0x0>;
2842 iommus = <&apps_smmu 0x1804 0x0>;
2848 iommus = <&apps_smmu 0x1805 0x0>;
2856 reg = <0 0x031e0000 0 0x1000>;
2864 #clock-cells = <0>;
2871 reg = <0 0x031f0000 0 0x2000>;
2877 pinctrl-0 = <&wsa2_swr_active>;
2883 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2884 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2885 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2886 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2887 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2888 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2889 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2890 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2891 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2894 #size-cells = <0>;
2901 reg = <0 0x03200000 0 0x1000>;
2909 #clock-cells = <0>;
2916 reg = <0 0x03210000 0 0x2000>;
2921 qcom,din-ports = <0>;
2924 pinctrl-0 = <&rx_swr_active>;
2927 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2928 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2929 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2930 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2931 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2932 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2933 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2934 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2935 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2938 #size-cells = <0>;
2945 reg = <0 0x03220000 0 0x1000>;
2953 #clock-cells = <0>;
2960 reg = <0 0x03240000 0 0x1000>;
2968 #clock-cells = <0>;
2975 reg = <0 0x03250000 0 0x2000>;
2981 pinctrl-0 = <&wsa_swr_active>;
2987 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2988 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2989 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2990 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2991 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2992 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2993 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2994 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2995 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2998 #size-cells = <0>;
3005 reg = <0 0x033b0000 0 0x2000>;
3014 pinctrl-0 = <&tx_swr_active>;
3018 qcom,dout-ports = <0>;
3019 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
3020 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
3021 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
3022 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
3023 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
3024 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
3025 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
3026 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
3027 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
3030 #size-cells = <0>;
3037 reg = <0 0x033f0000 0 0x1000>;
3044 #clock-cells = <0>;
3052 reg = <0 0x32300000 0 0x10000>;
3055 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3073 qcom,smem-states = <&smp2p_cdsp_out 0>;
3094 #size-cells = <0>;
3099 iommus = <&apps_smmu 0x2161 0x0400>,
3100 <&apps_smmu 0x1021 0x1420>;
3106 iommus = <&apps_smmu 0x2162 0x0400>,
3107 <&apps_smmu 0x1022 0x1420>;
3113 iommus = <&apps_smmu 0x2163 0x0400>,
3114 <&apps_smmu 0x1023 0x1420>;
3120 iommus = <&apps_smmu 0x2164 0x0400>,
3121 <&apps_smmu 0x1024 0x1420>;
3127 iommus = <&apps_smmu 0x2165 0x0400>,
3128 <&apps_smmu 0x1025 0x1420>;
3134 iommus = <&apps_smmu 0x2166 0x0400>,
3135 <&apps_smmu 0x1026 0x1420>;
3141 iommus = <&apps_smmu 0x2167 0x0400>,
3142 <&apps_smmu 0x1027 0x1420>;
3148 iommus = <&apps_smmu 0x2168 0x0400>,
3149 <&apps_smmu 0x1028 0x1420>;
3159 reg = <0x0 0x04080000 0x0 0x10000>;
3162 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
3181 qcom,smem-states = <&smp2p_modem_out 0>;
3199 reg = <0 0x0aaf0000 0 0x10000>;
3211 reg = <0 0x0ac15000 0 0x1000>;
3225 pinctrl-0 = <&cci0_default &cci1_default>;
3231 #size-cells = <0>;
3233 cci0_i2c0: i2c-bus@0 {
3234 reg = <0>;
3237 #size-cells = <0>;
3244 #size-cells = <0>;
3250 reg = <0 0x0ac16000 0 0x1000>;
3264 pinctrl-0 = <&cci2_default &cci3_default>;
3270 #size-cells = <0>;
3272 cci1_i2c0: i2c-bus@0 {
3273 reg = <0>;
3276 #size-cells = <0>;
3283 #size-cells = <0>;
3289 reg = <0 0x0ade0000 0 0x20000>;
3304 reg = <0 0x0ae00000 0 0x1000>;
3308 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
3309 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
3329 iommus = <&apps_smmu 0x2800 0x402>;
3339 reg = <0 0x0ae01000 0 0x8f000>,
3340 <0 0x0aeb0000 0 0x3000>;
3363 interrupts = <0>;
3367 #size-cells = <0>;
3369 port@0 {
3370 reg = <0>;
3423 reg = <0 0xae90000 0 0x200>,
3424 <0 0xae90200 0 0x200>,
3425 <0 0xae90400 0 0xc00>,
3426 <0 0xae91000 0 0x400>,
3427 <0 0xae91400 0 0x400>;
3449 #sound-dai-cells = <0>;
3458 #size-cells = <0>;
3460 port@0 {
3461 reg = <0>;
3503 reg = <0 0x0ae94000 0 0x400>;
3534 #size-cells = <0>;
3540 #size-cells = <0>;
3542 port@0 {
3543 reg = <0>;
3578 reg = <0 0x0ae94400 0 0x200>,
3579 <0 0x0ae94600 0 0x280>,
3580 <0 0x0ae94900 0 0x260>;
3586 #phy-cells = <0>;
3597 reg = <0 0x0ae96000 0 0x400>;
3628 #size-cells = <0>;
3634 #size-cells = <0>;
3636 port@0 {
3637 reg = <0>;
3653 reg = <0 0x0ae96400 0 0x200>,
3654 <0 0x0ae96600 0 0x280>,
3655 <0 0x0ae96900 0 0x260>;
3661 #phy-cells = <0>;
3673 reg = <0 0x0af00000 0 0x20000>;
3684 <0>, /* dp1 */
3685 <0>,
3686 <0>, /* dp2 */
3687 <0>,
3688 <0>, /* dp3 */
3689 <0>;
3699 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
3700 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
3709 reg = <0 0x0c263000 0 0x1000>, /* TM */
3710 <0 0x0c222000 0 0x1000>; /* SROT */
3720 reg = <0 0x0c265000 0 0x1000>, /* TM */
3721 <0 0x0c223000 0 0x1000>; /* SROT */
3731 reg = <0 0x0c300000 0 0x400>;
3736 #clock-cells = <0>;
3741 reg = <0 0x0c3f0000 0 0x400>;
3747 reg = <0 0x0c400000 0 0x00003000>,
3748 <0 0x0c500000 0 0x00400000>,
3749 <0 0x0c440000 0 0x00080000>,
3750 <0 0x0c4c0000 0 0x00010000>,
3751 <0 0x0c42d000 0 0x00010000>;
3759 qcom,ee = <0>;
3760 qcom,channel = <0>;
3764 #size-cells = <0>;
3769 reg = <0 0x0ed18000 0 0x1000>;
3778 reg = <0 0x0f100000 0 0x300000>;
3784 gpio-ranges = <&tlmm 0 0 211>;
4288 reg = <0 0x03440000 0x0 0x20000>,
4289 <0 0x034d0000 0x0 0x10000>;
4292 gpio-ranges = <&lpass_tlmm 0 0 23>;
4403 reg = <0x0 0x10002000 0x0 0x1000>,
4404 <0x0 0x16280000 0x0 0x180000>;
4422 reg = <0x0 0x10041000 0x0 0x1000>;
4429 #size-cells = <0>;
4453 reg = <0x0 0x10042000 0x0 0x1000>;
4460 #size-cells = <0>;
4491 reg = <0x0 0x10045000 0x0 0x1000>;
4498 #size-cells = <0>;
4500 port@0 {
4501 reg = <0>;
4529 reg = <0x0 0x10046000 0x0 0x1000>;
4556 reg = <0x0 0x10048000 0x0 0x1000>;
4558 iommus = <&apps_smmu 0x0600 0>;
4559 arm,buffer-size = <0x10000>;
4577 reg = <0x0 0x1004e000 0x0 0x1000>;
4606 reg = <0x0 0x10b04000 0x0 0x1000>;
4613 #size-cells = <0>;
4644 reg = <0x0 0x10b05000 0x0 0x1000>;
4670 reg = <0x0 0x10b06000 0x0 0x1000>;
4699 reg = <0x0 0x10b08000 0x0 0x1000>;
4707 #size-cells = <0>;
4709 port@0 {
4710 reg = <0>;
4739 reg = <0x0 0x10b09000 0x0 0x1000>;
4757 reg = <0x0 0x10b0d000 0x0 0x1000>;
4774 reg = <0x0 0x10c28000 0x0 0x1000>;
4791 reg = <0x0 0x10c29000 0x0 0x1000>;
4808 reg = <0x0 0x10c2a000 0x0 0x1000>;
4816 reg = <0x0 0x10c2b000 0x0 0x1000>;
4824 reg = <0x0 0x10c2e000 0x0 0x1000>;
4832 #size-cells = <0>;
4864 reg = <0x0 0x10c2f000 0x0 0x1000>;
4892 reg = <0x0 0x13810000 0x0 0x1000>;
4919 reg = <0x0 0x138e0000 0x0 0x1000>;
4927 reg = <0x0 0x138f0000 0x0 0x1000>;
4935 reg = <0x0 0x13900000 0x0 0x1000>;
4943 reg = <0 0x146aa000 0 0x1000>;
4944 ranges = <0 0 0x146aa000 0x1000>;
4951 reg = <0x94c 0xc8>;
4957 reg = <0 0x15000000 0 0x100000>;
5065 redistributor-stride = <0x0 0x40000>;
5066 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */
5067 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */
5075 reg = <0x0 0x17140000 0x0 0x20000>;
5085 ranges = <0 0 0 0x20000000>;
5086 reg = <0x0 0x17420000 0x0 0x1000>;
5090 frame-number = <0>;
5093 reg = <0x17421000 0x1000>,
5094 <0x17422000 0x1000>;
5100 reg = <0x17423000 0x1000>;
5107 reg = <0x17425000 0x1000>;
5114 reg = <0x17427000 0x1000>;
5121 reg = <0x17429000 0x1000>;
5128 reg = <0x1742b000 0x1000>;
5135 reg = <0x1742d000 0x1000>;
5143 reg = <0x0 0x17a00000 0x0 0x10000>,
5144 <0x0 0x17a10000 0x0 0x10000>,
5145 <0x0 0x17a20000 0x0 0x10000>,
5146 <0x0 0x17a30000 0x0 0x10000>;
5147 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
5151 qcom,tcs-offset = <0xd00>;
5154 <WAKE_TCS 2>, <CONTROL_TCS 0>;
5237 reg = <0 0x17d91000 0 0x1000>,
5238 <0 0x17d92000 0 0x1000>,
5239 <0 0x17d93000 0 0x1000>;
5246 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
5253 reg = <0 0x19100000 0 0xbb800>;
5260 reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>,
5261 <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>,
5262 <0 0x19a00000 0 0x80000>, <0 0x19c00000 0 0x80000>;
5272 reg = <0 0x01d84000 0 0x3000>;
5283 iommus = <&apps_smmu 0xe0 0x0>;
5286 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
5287 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
5309 <0 0>,
5310 <0 0>,
5313 <0 0>,
5314 <0 0>,
5315 <0 0>;
5323 reg = <0 0x01d87000 0 0x1000>;
5332 resets = <&ufs_mem_hc 0>;
5336 #phy-cells = <0>;
5344 reg = <0 0x01d88000 0 0x8000>;
5350 reg = <0 0x01dc4000 0 0x28000>;
5353 qcom,ee = <0>;
5357 iommus = <&apps_smmu 0x584 0x11>,
5358 <&apps_smmu 0x588 0x0>,
5359 <&apps_smmu 0x598 0x5>,
5360 <&apps_smmu 0x59a 0x0>,
5361 <&apps_smmu 0x59f 0x0>;
5366 reg = <0 0x01dfa000 0 0x6000>;
5369 iommus = <&apps_smmu 0x584 0x11>,
5370 <&apps_smmu 0x588 0x0>,
5371 <&apps_smmu 0x598 0x5>,
5372 <&apps_smmu 0x59a 0x0>,
5373 <&apps_smmu 0x59f 0x0>;
5374 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
5380 reg = <0 0x08804000 0 0x1000>;
5391 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
5392 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
5394 iommus = <&apps_smmu 0x4a0 0x0>;
5401 sdhci-caps-mask = <0x3 0x0>;
5422 reg = <0 0x0a6f8800 0 0x400>;
5460 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
5461 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
5466 reg = <0 0x0a600000 0 0xcd00>;
5468 iommus = <&apps_smmu 0x0 0x0>;
5479 #size-cells = <0>;
5481 port@0 {
5482 reg = <0>;
5501 reg = <0 0x320c0000 0 0x10000>;
5508 reg = <0 0x03c40000 0 0x17200>;
5519 thermal-sensors = <&tsens0 0>;
5891 thermal-sensors = <&tsens1 0>;