Lines Matching refs:gcc
10 #include <dt-bindings/clock/qcom,gcc-sm8350.h>
669 gcc: clock-controller@100000 { label
670 compatible = "qcom,gcc-sm8350";
736 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
737 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
748 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
764 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
780 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
796 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
812 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
828 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
844 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
860 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
878 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
894 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
907 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
923 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
962 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
963 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
974 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
990 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1006 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1022 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1038 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1054 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1070 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1085 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1101 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1117 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1133 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1149 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1165 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1181 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1197 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1210 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1226 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1265 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1266 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1277 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1293 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1309 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1325 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1341 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1357 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1373 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1389 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1405 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1421 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1437 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1453 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1559 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1560 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1561 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1562 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1563 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1564 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1565 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1566 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
1567 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>;
1581 resets = <&gcc GCC_PCIE_0_BCR>;
1584 power-domains = <&gcc PCIE_0_GDSC>;
1605 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1606 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1607 <&gcc GCC_PCIE_0_CLKREF_EN>,
1608 <&gcc GCC_PCIE0_PHY_RCHNG_CLK>,
1609 <&gcc GCC_PCIE_0_PIPE_CLK>;
1612 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1615 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>;
1670 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
1671 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1672 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1673 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1674 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1675 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1676 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1677 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1690 resets = <&gcc GCC_PCIE_1_BCR>;
1693 power-domains = <&gcc PCIE_1_GDSC>;
1714 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
1715 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1716 <&gcc GCC_PCIE_1_CLKREF_EN>,
1717 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>,
1718 <&gcc GCC_PCIE_1_PIPE_CLK>;
1721 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1724 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
1744 resets = <&gcc GCC_UFS_PHY_BCR>;
1747 power-domains = <&gcc UFS_PHY_GDSC>;
1762 <&gcc GCC_UFS_PHY_AXI_CLK>,
1763 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1764 <&gcc GCC_UFS_PHY_AHB_CLK>,
1765 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1767 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1768 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1769 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1792 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
1793 <&gcc GCC_UFS_1_CLKREF_EN>;
1798 power-domains = <&gcc UFS_PHY_GDSC>;
2128 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2129 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2164 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2165 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2193 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2194 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
2337 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2338 <&gcc GCC_SDCC2_APPS_CLK>,
2341 resets = <&gcc GCC_SDCC2_BCR>;
2378 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2391 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2404 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2406 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2407 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2410 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2411 <&gcc GCC_USB3_PHY_PRIM_BCR>;
2455 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2456 <&gcc GCC_USB3_SEC_CLKREF_EN>,
2457 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
2458 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2467 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
2468 <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
2620 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2621 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2622 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2623 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2624 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
2631 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2632 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2646 power-domains = <&gcc USB30_PRIM_GDSC>;
2648 resets = <&gcc GCC_USB30_PRIM_BCR>;
2697 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2698 <&gcc GCC_USB30_SEC_MASTER_CLK>,
2699 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2700 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
2701 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2702 <&gcc GCC_USB3_SEC_CLKREF_EN>;
2710 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2711 <&gcc GCC_USB30_SEC_MASTER_CLK>;
2725 power-domains = <&gcc USB30_SEC_GDSC>;
2727 resets = <&gcc GCC_USB30_SEC_BCR>;
2765 <&gcc GCC_DISP_HF_AXI_CLK>,
2766 <&gcc GCC_DISP_SF_AXI_CLK>,
2788 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
2789 <&gcc GCC_DISP_SF_AXI_CLK>,
2963 <&gcc GCC_DISP_HF_AXI_CLK>;
3062 <&gcc GCC_DISP_HF_AXI_CLK>;
3712 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;