Lines Matching +full:ufs +full:- +full:ddr
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interconnect/qcom,sm8350.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
9 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
10 #include <dt-bindings/clock/qcom,gcc-sm8350.h>
11 #include <dt-bindings/clock/qcom,gpucc-sm8350.h>
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/interconnect/qcom,icc.h>
17 #include <dt-bindings/interconnect/qcom,sm8350.h>
18 #include <dt-bindings/mailbox/qcom-ipcc.h>
19 #include <dt-bindings/phy/phy-qcom-qmp.h>
20 #include <dt-bindings/power/qcom-rpmpd.h>
21 #include <dt-bindings/power/qcom,rpmhpd.h>
22 #include <dt-bindings/soc/qcom,apr.h>
23 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
24 #include <dt-bindings/sound/qcom,q6afe.h>
25 #include <dt-bindings/sound/qcom,q6asm.h>
26 #include <dt-bindings/thermal/thermal.h>
27 #include <dt-bindings/interconnect/qcom,sm8350.h>
30 interrupt-parent = <&intc>;
32 #address-cells = <2>;
33 #size-cells = <2>;
38 xo_board: xo-board {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 clock-frequency = <38400000>;
42 clock-output-names = "xo_board";
45 sleep_clk: sleep-clk {
46 compatible = "fixed-clock";
47 clock-frequency = <32764>;
48 #clock-cells = <0>;
53 #address-cells = <2>;
54 #size-cells = <0>;
58 compatible = "arm,cortex-a55";
61 enable-method = "psci";
62 next-level-cache = <&l2_0>;
63 qcom,freq-domain = <&cpufreq_hw 0>;
64 power-domains = <&cpu_pd0>;
65 power-domain-names = "psci";
66 #cooling-cells = <2>;
67 l2_0: l2-cache {
69 cache-level = <2>;
70 cache-unified;
71 next-level-cache = <&l3_0>;
72 l3_0: l3-cache {
74 cache-level = <3>;
75 cache-unified;
82 compatible = "arm,cortex-a55";
85 enable-method = "psci";
86 next-level-cache = <&l2_100>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
88 power-domains = <&cpu_pd1>;
89 power-domain-names = "psci";
90 #cooling-cells = <2>;
91 l2_100: l2-cache {
93 cache-level = <2>;
94 cache-unified;
95 next-level-cache = <&l3_0>;
101 compatible = "arm,cortex-a55";
104 enable-method = "psci";
105 next-level-cache = <&l2_200>;
106 qcom,freq-domain = <&cpufreq_hw 0>;
107 power-domains = <&cpu_pd2>;
108 power-domain-names = "psci";
109 #cooling-cells = <2>;
110 l2_200: l2-cache {
112 cache-level = <2>;
113 cache-unified;
114 next-level-cache = <&l3_0>;
120 compatible = "arm,cortex-a55";
123 enable-method = "psci";
124 next-level-cache = <&l2_300>;
125 qcom,freq-domain = <&cpufreq_hw 0>;
126 power-domains = <&cpu_pd3>;
127 power-domain-names = "psci";
128 #cooling-cells = <2>;
129 l2_300: l2-cache {
131 cache-level = <2>;
132 cache-unified;
133 next-level-cache = <&l3_0>;
139 compatible = "arm,cortex-a78";
142 enable-method = "psci";
143 next-level-cache = <&l2_400>;
144 qcom,freq-domain = <&cpufreq_hw 1>;
145 power-domains = <&cpu_pd4>;
146 power-domain-names = "psci";
147 #cooling-cells = <2>;
148 l2_400: l2-cache {
150 cache-level = <2>;
151 cache-unified;
152 next-level-cache = <&l3_0>;
158 compatible = "arm,cortex-a78";
161 enable-method = "psci";
162 next-level-cache = <&l2_500>;
163 qcom,freq-domain = <&cpufreq_hw 1>;
164 power-domains = <&cpu_pd5>;
165 power-domain-names = "psci";
166 #cooling-cells = <2>;
167 l2_500: l2-cache {
169 cache-level = <2>;
170 cache-unified;
171 next-level-cache = <&l3_0>;
177 compatible = "arm,cortex-a78";
180 enable-method = "psci";
181 next-level-cache = <&l2_600>;
182 qcom,freq-domain = <&cpufreq_hw 1>;
183 power-domains = <&cpu_pd6>;
184 power-domain-names = "psci";
185 #cooling-cells = <2>;
186 l2_600: l2-cache {
188 cache-level = <2>;
189 cache-unified;
190 next-level-cache = <&l3_0>;
196 compatible = "arm,cortex-x1";
199 enable-method = "psci";
200 next-level-cache = <&l2_700>;
201 qcom,freq-domain = <&cpufreq_hw 2>;
202 power-domains = <&cpu_pd7>;
203 power-domain-names = "psci";
204 #cooling-cells = <2>;
205 l2_700: l2-cache {
207 cache-level = <2>;
208 cache-unified;
209 next-level-cache = <&l3_0>;
213 cpu-map {
249 idle-states {
250 entry-method = "psci";
252 little_cpu_sleep_0: cpu-sleep-0-0 {
253 compatible = "arm,idle-state";
254 idle-state-name = "silver-rail-power-collapse";
255 arm,psci-suspend-param = <0x40000004>;
256 entry-latency-us = <360>;
257 exit-latency-us = <531>;
258 min-residency-us = <3934>;
259 local-timer-stop;
262 big_cpu_sleep_0: cpu-sleep-1-0 {
263 compatible = "arm,idle-state";
264 idle-state-name = "gold-rail-power-collapse";
265 arm,psci-suspend-param = <0x40000004>;
266 entry-latency-us = <702>;
267 exit-latency-us = <1061>;
268 min-residency-us = <4488>;
269 local-timer-stop;
273 domain-idle-states {
274 cluster_sleep_apss_off: cluster-sleep-0 {
275 compatible = "domain-idle-state";
276 arm,psci-suspend-param = <0x41000044>;
277 entry-latency-us = <2752>;
278 exit-latency-us = <3048>;
279 min-residency-us = <6118>;
282 cluster_sleep_aoss_sleep: cluster-sleep-1 {
283 compatible = "domain-idle-state";
284 arm,psci-suspend-param = <0x4100c344>;
285 entry-latency-us = <3263>;
286 exit-latency-us = <6562>;
287 min-residency-us = <9987>;
294 compatible = "qcom,scm-sm8350", "qcom,scm";
295 qcom,dload-mode = <&tcsr 0x13000>;
296 #reset-cells = <1>;
306 pmu-a55 {
307 compatible = "arm,cortex-a55-pmu";
311 pmu-a78 {
312 compatible = "arm,cortex-a78-pmu";
316 pmu-x1 {
317 compatible = "arm,cortex-x1-pmu";
322 compatible = "arm,psci-1.0";
325 cpu_pd0: power-domain-cpu0 {
326 #power-domain-cells = <0>;
327 power-domains = <&cluster_pd>;
328 domain-idle-states = <&little_cpu_sleep_0>;
331 cpu_pd1: power-domain-cpu1 {
332 #power-domain-cells = <0>;
333 power-domains = <&cluster_pd>;
334 domain-idle-states = <&little_cpu_sleep_0>;
337 cpu_pd2: power-domain-cpu2 {
338 #power-domain-cells = <0>;
339 power-domains = <&cluster_pd>;
340 domain-idle-states = <&little_cpu_sleep_0>;
343 cpu_pd3: power-domain-cpu3 {
344 #power-domain-cells = <0>;
345 power-domains = <&cluster_pd>;
346 domain-idle-states = <&little_cpu_sleep_0>;
349 cpu_pd4: power-domain-cpu4 {
350 #power-domain-cells = <0>;
351 power-domains = <&cluster_pd>;
352 domain-idle-states = <&big_cpu_sleep_0>;
355 cpu_pd5: power-domain-cpu5 {
356 #power-domain-cells = <0>;
357 power-domains = <&cluster_pd>;
358 domain-idle-states = <&big_cpu_sleep_0>;
361 cpu_pd6: power-domain-cpu6 {
362 #power-domain-cells = <0>;
363 power-domains = <&cluster_pd>;
364 domain-idle-states = <&big_cpu_sleep_0>;
367 cpu_pd7: power-domain-cpu7 {
368 #power-domain-cells = <0>;
369 power-domains = <&cluster_pd>;
370 domain-idle-states = <&big_cpu_sleep_0>;
373 cluster_pd: power-domain-cpu-cluster0 {
374 #power-domain-cells = <0>;
375 domain-idle-states = <&cluster_sleep_apss_off &cluster_sleep_aoss_sleep>;
379 qup_opp_table_100mhz: opp-table-qup100mhz {
380 compatible = "operating-points-v2";
382 opp-50000000 {
383 opp-hz = /bits/ 64 <50000000>;
384 required-opps = <&rpmhpd_opp_min_svs>;
387 opp-75000000 {
388 opp-hz = /bits/ 64 <75000000>;
389 required-opps = <&rpmhpd_opp_low_svs>;
392 opp-100000000 {
393 opp-hz = /bits/ 64 <100000000>;
394 required-opps = <&rpmhpd_opp_svs>;
398 qup_opp_table_120mhz: opp-table-qup120mhz {
399 compatible = "operating-points-v2";
401 opp-50000000 {
402 opp-hz = /bits/ 64 <50000000>;
403 required-opps = <&rpmhpd_opp_min_svs>;
406 opp-75000000 {
407 opp-hz = /bits/ 64 <75000000>;
408 required-opps = <&rpmhpd_opp_low_svs>;
411 opp-120000000 {
412 opp-hz = /bits/ 64 <120000000>;
413 required-opps = <&rpmhpd_opp_svs>;
417 reserved_memory: reserved-memory {
418 #address-cells = <2>;
419 #size-cells = <2>;
424 no-map;
428 no-map;
433 compatible = "qcom,cmd-db";
435 no-map;
440 no-map;
447 no-map;
452 no-map;
457 no-map;
462 no-map;
467 no-map;
472 no-map;
477 no-map;
482 no-map;
487 no-map;
492 no-map;
497 no-map;
502 no-map;
507 no-map;
512 no-map;
516 compatible = "qcom,rmtfs-mem";
518 no-map;
520 qcom,client-id = <1>;
526 no-map;
531 no-map;
536 no-map;
541 no-map;
546 no-map;
551 no-map;
555 smp2p-adsp {
558 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
564 qcom,local-pid = <0>;
565 qcom,remote-pid = <2>;
567 smp2p_adsp_out: master-kernel {
568 qcom,entry-name = "master-kernel";
569 #qcom,smem-state-cells = <1>;
572 smp2p_adsp_in: slave-kernel {
573 qcom,entry-name = "slave-kernel";
574 interrupt-controller;
575 #interrupt-cells = <2>;
579 smp2p-cdsp {
582 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
588 qcom,local-pid = <0>;
589 qcom,remote-pid = <5>;
591 smp2p_cdsp_out: master-kernel {
592 qcom,entry-name = "master-kernel";
593 #qcom,smem-state-cells = <1>;
596 smp2p_cdsp_in: slave-kernel {
597 qcom,entry-name = "slave-kernel";
598 interrupt-controller;
599 #interrupt-cells = <2>;
603 smp2p-modem {
606 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
612 qcom,local-pid = <0>;
613 qcom,remote-pid = <1>;
615 smp2p_modem_out: master-kernel {
616 qcom,entry-name = "master-kernel";
617 #qcom,smem-state-cells = <1>;
620 smp2p_modem_in: slave-kernel {
621 qcom,entry-name = "slave-kernel";
622 interrupt-controller;
623 #interrupt-cells = <2>;
626 ipa_smp2p_out: ipa-ap-to-modem {
627 qcom,entry-name = "ipa";
628 #qcom,smem-state-cells = <1>;
631 ipa_smp2p_in: ipa-modem-to-ap {
632 qcom,entry-name = "ipa";
633 interrupt-controller;
634 #interrupt-cells = <2>;
638 smp2p-slpi {
641 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
647 qcom,local-pid = <0>;
648 qcom,remote-pid = <3>;
650 smp2p_slpi_out: master-kernel {
651 qcom,entry-name = "master-kernel";
652 #qcom,smem-state-cells = <1>;
655 smp2p_slpi_in: slave-kernel {
656 qcom,entry-name = "slave-kernel";
657 interrupt-controller;
658 #interrupt-cells = <2>;
663 #address-cells = <2>;
664 #size-cells = <2>;
666 dma-ranges = <0 0 0 0 0x10 0>;
667 compatible = "simple-bus";
669 gcc: clock-controller@100000 {
670 compatible = "qcom,gcc-sm8350";
672 #clock-cells = <1>;
673 #reset-cells = <1>;
674 #power-domain-cells = <1>;
675 clock-names = "bi_tcxo",
702 compatible = "qcom,sm8350-ipcc", "qcom,ipcc";
705 interrupt-controller;
706 #interrupt-cells = <3>;
707 #mbox-cells = <2>;
710 gpi_dma2: dma-controller@800000 {
711 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
725 dma-channels = <12>;
726 dma-channel-mask = <0xff>;
728 #dma-cells = <3>;
733 compatible = "qcom,geni-se-qup";
735 clock-names = "m-ahb", "s-ahb";
739 #address-cells = <2>;
740 #size-cells = <2>;
745 compatible = "qcom,geni-i2c";
747 clock-names = "se";
749 pinctrl-names = "default";
750 pinctrl-0 = <&qup_i2c14_default>;
754 dma-names = "tx", "rx";
755 #address-cells = <1>;
756 #size-cells = <0>;
761 compatible = "qcom,geni-spi";
763 clock-names = "se";
766 power-domains = <&rpmhpd RPMHPD_CX>;
767 operating-points-v2 = <&qup_opp_table_120mhz>;
770 dma-names = "tx", "rx";
771 #address-cells = <1>;
772 #size-cells = <0>;
777 compatible = "qcom,geni-i2c";
779 clock-names = "se";
781 pinctrl-names = "default";
782 pinctrl-0 = <&qup_i2c15_default>;
786 dma-names = "tx", "rx";
787 #address-cells = <1>;
788 #size-cells = <0>;
793 compatible = "qcom,geni-spi";
795 clock-names = "se";
798 power-domains = <&rpmhpd RPMHPD_CX>;
799 operating-points-v2 = <&qup_opp_table_120mhz>;
802 dma-names = "tx", "rx";
803 #address-cells = <1>;
804 #size-cells = <0>;
809 compatible = "qcom,geni-i2c";
811 clock-names = "se";
813 pinctrl-names = "default";
814 pinctrl-0 = <&qup_i2c16_default>;
818 dma-names = "tx", "rx";
819 #address-cells = <1>;
820 #size-cells = <0>;
825 compatible = "qcom,geni-spi";
827 clock-names = "se";
830 power-domains = <&rpmhpd RPMHPD_CX>;
831 operating-points-v2 = <&qup_opp_table_100mhz>;
834 dma-names = "tx", "rx";
835 #address-cells = <1>;
836 #size-cells = <0>;
841 compatible = "qcom,geni-i2c";
843 clock-names = "se";
845 pinctrl-names = "default";
846 pinctrl-0 = <&qup_i2c17_default>;
850 dma-names = "tx", "rx";
851 #address-cells = <1>;
852 #size-cells = <0>;
857 compatible = "qcom,geni-spi";
859 clock-names = "se";
862 power-domains = <&rpmhpd RPMHPD_CX>;
863 operating-points-v2 = <&qup_opp_table_100mhz>;
866 dma-names = "tx", "rx";
867 #address-cells = <1>;
868 #size-cells = <0>;
872 /* QUP no. 18 seems to be strictly SPI/UART-only */
875 compatible = "qcom,geni-spi";
877 clock-names = "se";
880 power-domains = <&rpmhpd RPMHPD_CX>;
881 operating-points-v2 = <&qup_opp_table_100mhz>;
884 dma-names = "tx", "rx";
885 #address-cells = <1>;
886 #size-cells = <0>;
891 compatible = "qcom,geni-uart";
893 clock-names = "se";
895 pinctrl-names = "default";
896 pinctrl-0 = <&qup_uart18_default>;
898 power-domains = <&rpmhpd RPMHPD_CX>;
899 operating-points-v2 = <&qup_opp_table_100mhz>;
904 compatible = "qcom,geni-i2c";
906 clock-names = "se";
908 pinctrl-names = "default";
909 pinctrl-0 = <&qup_i2c19_default>;
913 dma-names = "tx", "rx";
914 #address-cells = <1>;
915 #size-cells = <0>;
920 compatible = "qcom,geni-spi";
922 clock-names = "se";
925 power-domains = <&rpmhpd RPMHPD_CX>;
926 operating-points-v2 = <&qup_opp_table_100mhz>;
929 dma-names = "tx", "rx";
930 #address-cells = <1>;
931 #size-cells = <0>;
936 gpi_dma0: dma-controller@900000 {
937 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
951 dma-channels = <12>;
952 dma-channel-mask = <0x7e>;
954 #dma-cells = <3>;
959 compatible = "qcom,geni-se-qup";
961 clock-names = "m-ahb", "s-ahb";
965 #address-cells = <2>;
966 #size-cells = <2>;
971 compatible = "qcom,geni-i2c";
973 clock-names = "se";
975 pinctrl-names = "default";
976 pinctrl-0 = <&qup_i2c0_default>;
980 dma-names = "tx", "rx";
981 #address-cells = <1>;
982 #size-cells = <0>;
987 compatible = "qcom,geni-spi";
989 clock-names = "se";
992 power-domains = <&rpmhpd RPMHPD_CX>;
993 operating-points-v2 = <&qup_opp_table_100mhz>;
996 dma-names = "tx", "rx";
997 #address-cells = <1>;
998 #size-cells = <0>;
1003 compatible = "qcom,geni-i2c";
1005 clock-names = "se";
1007 pinctrl-names = "default";
1008 pinctrl-0 = <&qup_i2c1_default>;
1012 dma-names = "tx", "rx";
1013 #address-cells = <1>;
1014 #size-cells = <0>;
1019 compatible = "qcom,geni-spi";
1021 clock-names = "se";
1024 power-domains = <&rpmhpd RPMHPD_CX>;
1025 operating-points-v2 = <&qup_opp_table_100mhz>;
1028 dma-names = "tx", "rx";
1029 #address-cells = <1>;
1030 #size-cells = <0>;
1035 compatible = "qcom,geni-i2c";
1037 clock-names = "se";
1039 pinctrl-names = "default";
1040 pinctrl-0 = <&qup_i2c2_default>;
1044 dma-names = "tx", "rx";
1045 #address-cells = <1>;
1046 #size-cells = <0>;
1051 compatible = "qcom,geni-spi";
1053 clock-names = "se";
1056 power-domains = <&rpmhpd RPMHPD_CX>;
1057 operating-points-v2 = <&qup_opp_table_100mhz>;
1060 dma-names = "tx", "rx";
1061 #address-cells = <1>;
1062 #size-cells = <0>;
1067 compatible = "qcom,geni-debug-uart";
1069 clock-names = "se";
1071 pinctrl-names = "default";
1072 pinctrl-0 = <&qup_uart3_default_state>;
1074 power-domains = <&rpmhpd RPMHPD_CX>;
1075 operating-points-v2 = <&qup_opp_table_100mhz>;
1079 /* QUP no. 3 seems to be strictly SPI-only */
1082 compatible = "qcom,geni-spi";
1084 clock-names = "se";
1087 power-domains = <&rpmhpd RPMHPD_CX>;
1088 operating-points-v2 = <&qup_opp_table_100mhz>;
1091 dma-names = "tx", "rx";
1092 #address-cells = <1>;
1093 #size-cells = <0>;
1098 compatible = "qcom,geni-i2c";
1100 clock-names = "se";
1102 pinctrl-names = "default";
1103 pinctrl-0 = <&qup_i2c4_default>;
1107 dma-names = "tx", "rx";
1108 #address-cells = <1>;
1109 #size-cells = <0>;
1114 compatible = "qcom,geni-spi";
1116 clock-names = "se";
1119 power-domains = <&rpmhpd RPMHPD_CX>;
1120 operating-points-v2 = <&qup_opp_table_100mhz>;
1123 dma-names = "tx", "rx";
1124 #address-cells = <1>;
1125 #size-cells = <0>;
1130 compatible = "qcom,geni-i2c";
1132 clock-names = "se";
1134 pinctrl-names = "default";
1135 pinctrl-0 = <&qup_i2c5_default>;
1139 dma-names = "tx", "rx";
1140 #address-cells = <1>;
1141 #size-cells = <0>;
1146 compatible = "qcom,geni-spi";
1148 clock-names = "se";
1151 power-domains = <&rpmhpd RPMHPD_CX>;
1152 operating-points-v2 = <&qup_opp_table_100mhz>;
1155 dma-names = "tx", "rx";
1156 #address-cells = <1>;
1157 #size-cells = <0>;
1162 compatible = "qcom,geni-i2c";
1164 clock-names = "se";
1166 pinctrl-names = "default";
1167 pinctrl-0 = <&qup_i2c6_default>;
1171 dma-names = "tx", "rx";
1172 #address-cells = <1>;
1173 #size-cells = <0>;
1178 compatible = "qcom,geni-spi";
1180 clock-names = "se";
1183 power-domains = <&rpmhpd RPMHPD_CX>;
1184 operating-points-v2 = <&qup_opp_table_100mhz>;
1187 dma-names = "tx", "rx";
1188 #address-cells = <1>;
1189 #size-cells = <0>;
1194 compatible = "qcom,geni-uart";
1196 clock-names = "se";
1198 pinctrl-names = "default";
1199 pinctrl-0 = <&qup_uart6_default>;
1201 power-domains = <&rpmhpd RPMHPD_CX>;
1202 operating-points-v2 = <&qup_opp_table_100mhz>;
1207 compatible = "qcom,geni-i2c";
1209 clock-names = "se";
1211 pinctrl-names = "default";
1212 pinctrl-0 = <&qup_i2c7_default>;
1216 dma-names = "tx", "rx";
1217 #address-cells = <1>;
1218 #size-cells = <0>;
1223 compatible = "qcom,geni-spi";
1225 clock-names = "se";
1228 power-domains = <&rpmhpd RPMHPD_CX>;
1229 operating-points-v2 = <&qup_opp_table_100mhz>;
1232 dma-names = "tx", "rx";
1233 #address-cells = <1>;
1234 #size-cells = <0>;
1239 gpi_dma1: dma-controller@a00000 {
1240 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
1254 dma-channels = <12>;
1255 dma-channel-mask = <0xff>;
1257 #dma-cells = <3>;
1262 compatible = "qcom,geni-se-qup";
1264 clock-names = "m-ahb", "s-ahb";
1268 #address-cells = <2>;
1269 #size-cells = <2>;
1274 compatible = "qcom,geni-i2c";
1276 clock-names = "se";
1278 pinctrl-names = "default";
1279 pinctrl-0 = <&qup_i2c8_default>;
1283 dma-names = "tx", "rx";
1284 #address-cells = <1>;
1285 #size-cells = <0>;
1290 compatible = "qcom,geni-spi";
1292 clock-names = "se";
1295 power-domains = <&rpmhpd RPMHPD_CX>;
1296 operating-points-v2 = <&qup_opp_table_120mhz>;
1299 dma-names = "tx", "rx";
1300 #address-cells = <1>;
1301 #size-cells = <0>;
1306 compatible = "qcom,geni-i2c";
1308 clock-names = "se";
1310 pinctrl-names = "default";
1311 pinctrl-0 = <&qup_i2c9_default>;
1315 dma-names = "tx", "rx";
1316 #address-cells = <1>;
1317 #size-cells = <0>;
1322 compatible = "qcom,geni-spi";
1324 clock-names = "se";
1327 power-domains = <&rpmhpd RPMHPD_CX>;
1328 operating-points-v2 = <&qup_opp_table_100mhz>;
1331 dma-names = "tx", "rx";
1332 #address-cells = <1>;
1333 #size-cells = <0>;
1338 compatible = "qcom,geni-i2c";
1340 clock-names = "se";
1342 pinctrl-names = "default";
1343 pinctrl-0 = <&qup_i2c10_default>;
1347 dma-names = "tx", "rx";
1348 #address-cells = <1>;
1349 #size-cells = <0>;
1354 compatible = "qcom,geni-spi";
1356 clock-names = "se";
1359 power-domains = <&rpmhpd RPMHPD_CX>;
1360 operating-points-v2 = <&qup_opp_table_100mhz>;
1363 dma-names = "tx", "rx";
1364 #address-cells = <1>;
1365 #size-cells = <0>;
1370 compatible = "qcom,geni-i2c";
1372 clock-names = "se";
1374 pinctrl-names = "default";
1375 pinctrl-0 = <&qup_i2c11_default>;
1379 dma-names = "tx", "rx";
1380 #address-cells = <1>;
1381 #size-cells = <0>;
1386 compatible = "qcom,geni-spi";
1388 clock-names = "se";
1391 power-domains = <&rpmhpd RPMHPD_CX>;
1392 operating-points-v2 = <&qup_opp_table_100mhz>;
1395 dma-names = "tx", "rx";
1396 #address-cells = <1>;
1397 #size-cells = <0>;
1402 compatible = "qcom,geni-i2c";
1404 clock-names = "se";
1406 pinctrl-names = "default";
1407 pinctrl-0 = <&qup_i2c12_default>;
1411 dma-names = "tx", "rx";
1412 #address-cells = <1>;
1413 #size-cells = <0>;
1418 compatible = "qcom,geni-spi";
1420 clock-names = "se";
1423 power-domains = <&rpmhpd RPMHPD_CX>;
1424 operating-points-v2 = <&qup_opp_table_100mhz>;
1427 dma-names = "tx", "rx";
1428 #address-cells = <1>;
1429 #size-cells = <0>;
1434 compatible = "qcom,geni-i2c";
1436 clock-names = "se";
1438 pinctrl-names = "default";
1439 pinctrl-0 = <&qup_i2c13_default>;
1443 dma-names = "tx", "rx";
1444 #address-cells = <1>;
1445 #size-cells = <0>;
1450 compatible = "qcom,geni-spi";
1452 clock-names = "se";
1455 power-domains = <&rpmhpd RPMHPD_CX>;
1456 operating-points-v2 = <&qup_opp_table_100mhz>;
1459 dma-names = "tx", "rx";
1460 #address-cells = <1>;
1461 #size-cells = <0>;
1467 compatible = "qcom,prng-ee";
1470 clock-names = "core";
1474 compatible = "qcom,sm8350-config-noc";
1476 #interconnect-cells = <2>;
1477 qcom,bcm-voters = <&apps_bcm_voter>;
1481 compatible = "qcom,sm8350-mc-virt";
1483 #interconnect-cells = <2>;
1484 qcom,bcm-voters = <&apps_bcm_voter>;
1488 compatible = "qcom,sm8350-system-noc";
1490 #interconnect-cells = <2>;
1491 qcom,bcm-voters = <&apps_bcm_voter>;
1495 compatible = "qcom,sm8350-aggre1-noc";
1497 #interconnect-cells = <2>;
1498 qcom,bcm-voters = <&apps_bcm_voter>;
1502 compatible = "qcom,sm8350-aggre2-noc";
1504 #interconnect-cells = <2>;
1505 qcom,bcm-voters = <&apps_bcm_voter>;
1509 compatible = "qcom,sm8350-mmss-noc";
1511 #interconnect-cells = <2>;
1512 qcom,bcm-voters = <&apps_bcm_voter>;
1516 compatible = "qcom,pcie-sm8350";
1522 reg-names = "parf", "dbi", "elbi", "atu", "config";
1524 linux,pci-domain = <0>;
1525 bus-range = <0x00 0xff>;
1526 num-lanes = <1>;
1528 #address-cells = <3>;
1529 #size-cells = <2>;
1542 interrupt-names = "msi0",
1550 #interrupt-cells = <1>;
1551 interrupt-map-mask = <0 0 0 0x7>;
1552 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1566 clock-names = "aux",
1576 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1580 reset-names = "pci";
1582 power-domains = <&gcc PCIE_0_GDSC>;
1585 phy-names = "pciephy";
1592 bus-range = <0x01 0xff>;
1594 #address-cells = <3>;
1595 #size-cells = <2>;
1601 compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy";
1608 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
1611 reset-names = "phy";
1613 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>;
1614 assigned-clock-rates = <100000000>;
1616 #clock-cells = <0>;
1617 clock-output-names = "pcie_0_pipe_clk";
1619 #phy-cells = <0>;
1625 compatible = "qcom,pcie-sm8350";
1631 reg-names = "parf", "dbi", "elbi", "atu", "config";
1633 linux,pci-domain = <1>;
1634 bus-range = <0x00 0xff>;
1635 num-lanes = <2>;
1637 #address-cells = <3>;
1638 #size-cells = <2>;
1651 interrupt-names = "msi0",
1659 #interrupt-cells = <1>;
1660 interrupt-map-mask = <0 0 0 0x7>;
1661 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1674 clock-names = "aux",
1683 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1687 reset-names = "pci";
1689 power-domains = <&gcc PCIE_1_GDSC>;
1692 phy-names = "pciephy";
1699 bus-range = <0x01 0xff>;
1701 #address-cells = <3>;
1702 #size-cells = <2>;
1708 compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy";
1715 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
1718 reset-names = "phy";
1720 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
1721 assigned-clock-rates = <100000000>;
1723 #clock-cells = <0>;
1724 clock-output-names = "pcie_1_pipe_clk";
1726 #phy-cells = <0>;
1732 compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
1733 "jedec,ufs-2.0";
1737 phy-names = "ufsphy";
1738 lanes-per-direction = <2>;
1739 #reset-cells = <1>;
1741 reset-names = "rst";
1743 power-domains = <&gcc UFS_PHY_GDSC>;
1746 dma-coherent;
1748 clock-names =
1770 interconnect-names = "ufs-ddr", "cpu-ufs";
1771 freq-table-hz =
1784 compatible = "qcom,sm8350-qmp-ufs-phy";
1790 clock-names = "ref",
1794 power-domains = <&gcc UFS_PHY_GDSC>;
1797 reset-names = "ufsphy";
1799 #clock-cells = <1>;
1800 #phy-cells = <0>;
1805 cryptobam: dma-controller@1dc4000 {
1806 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
1809 #dma-cells = <1>;
1811 qcom,num-ees = <4>;
1812 num-channels = <16>;
1813 qcom,controlled-remotely;
1819 compatible = "qcom,sm8350-qce", "qcom,sm8150-qce", "qcom,qce";
1822 dma-names = "rx", "tx";
1826 interconnect-names = "memory";
1830 compatible = "qcom,sm8350-ipa";
1837 reg-names = "ipa-reg",
1838 "ipa-shared",
1841 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>,
1845 interrupt-names = "ipa",
1847 "ipa-clock-query",
1848 "ipa-setup-ready";
1851 clock-names = "core";
1855 interconnect-names = "memory",
1860 qcom,smem-states = <&ipa_smp2p_out 0>,
1862 qcom,smem-state-names = "ipa-clock-enabled-valid",
1863 "ipa-clock-enabled";
1869 compatible = "qcom,tcsr-mutex";
1871 #hwlock-cells = <1>;
1875 compatible = "qcom,sm8350-tcsr", "syscon";
1880 compatible = "qcom,sm8350-adsp-pas";
1883 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
1888 interrupt-names = "wdog", "fatal", "ready",
1889 "handover", "stop-ack";
1892 clock-names = "xo";
1894 power-domains = <&rpmhpd RPMHPD_LCX>,
1896 power-domain-names = "lcx", "lmx";
1898 memory-region = <&pil_adsp_mem>;
1902 qcom,smem-states = <&smp2p_adsp_out 0>;
1903 qcom,smem-state-names = "stop";
1907 glink-edge {
1908 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
1915 qcom,remote-pid = <2>;
1918 compatible = "qcom,apr-v2";
1919 qcom,glink-channels = "apr_audio_svc";
1921 #address-cells = <1>;
1922 #size-cells = <0>;
1927 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
1933 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
1936 compatible = "qcom,q6afe-dais";
1937 #address-cells = <1>;
1938 #size-cells = <0>;
1939 #sound-dai-cells = <1>;
1942 q6afecc: clock-controller {
1943 compatible = "qcom,q6afe-clocks";
1944 #clock-cells = <2>;
1951 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
1954 compatible = "qcom,q6asm-dais";
1955 #address-cells = <1>;
1956 #size-cells = <0>;
1957 #sound-dai-cells = <1>;
1977 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
1980 compatible = "qcom,q6adm-routing";
1981 #sound-dai-cells = <0>;
1988 qcom,glink-channels = "fastrpcglink-apps-dsp";
1990 qcom,non-secure-domain;
1991 #address-cells = <1>;
1992 #size-cells = <0>;
1994 compute-cb@3 {
1995 compatible = "qcom,fastrpc-compute-cb";
2000 compute-cb@4 {
2001 compatible = "qcom,fastrpc-compute-cb";
2006 compute-cb@5 {
2007 compatible = "qcom,fastrpc-compute-cb";
2016 compatible = "qcom,sm8350-lpass-lpi-pinctrl";
2022 clock-names = "core", "audio";
2024 gpio-controller;
2025 #gpio-cells = <2>;
2026 gpio-ranges = <&lpass_tlmm 0 0 15>;
2030 compatible = "qcom,adreno-660.1", "qcom,adreno";
2035 reg-names = "kgsl_3d0_reg_memory",
2043 operating-points-v2 = <&gpu_opp_table>;
2046 #cooling-cells = <2>;
2050 zap-shader {
2051 memory-region = <&pil_gpu_mem>;
2055 gpu_opp_table: opp-table {
2056 compatible = "operating-points-v2";
2058 opp-840000000 {
2059 opp-hz = /bits/ 64 <840000000>;
2060 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2063 opp-778000000 {
2064 opp-hz = /bits/ 64 <778000000>;
2065 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2068 opp-738000000 {
2069 opp-hz = /bits/ 64 <738000000>;
2070 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2073 opp-676000000 {
2074 opp-hz = /bits/ 64 <676000000>;
2075 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2078 opp-608000000 {
2079 opp-hz = /bits/ 64 <608000000>;
2080 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2083 opp-540000000 {
2084 opp-hz = /bits/ 64 <540000000>;
2085 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2088 opp-491000000 {
2089 opp-hz = /bits/ 64 <491000000>;
2090 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2093 opp-443000000 {
2094 opp-hz = /bits/ 64 <443000000>;
2095 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2098 opp-379000000 {
2099 opp-hz = /bits/ 64 <379000000>;
2100 opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>;
2103 opp-315000000 {
2104 opp-hz = /bits/ 64 <315000000>;
2105 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2111 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu";
2116 reg-names = "gmu", "rscc", "gmu_pdc";
2120 interrupt-names = "hfi", "gmu";
2129 clock-names = "gmu",
2137 power-domains = <&gpucc GPU_CX_GDSC>,
2139 power-domain-names = "cx",
2144 operating-points-v2 = <&gmu_opp_table>;
2146 gmu_opp_table: opp-table {
2147 compatible = "operating-points-v2";
2149 opp-200000000 {
2150 opp-hz = /bits/ 64 <200000000>;
2151 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2156 gpucc: clock-controller@3d90000 {
2157 compatible = "qcom,sm8350-gpucc";
2162 clock-names = "bi_tcxo",
2165 #clock-cells = <1>;
2166 #reset-cells = <1>;
2167 #power-domain-cells = <1>;
2171 compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu",
2172 "qcom,smmu-500", "arm,mmu-500";
2174 #iommu-cells = <2>;
2175 #global-interrupts = <2>;
2196 clock-names = "bus",
2204 power-domains = <&gpucc GPU_CX_GDSC>;
2205 dma-coherent;
2209 compatible = "qcom,sm8350-lpass-ag-noc";
2211 #interconnect-cells = <2>;
2212 qcom,bcm-voters = <&apps_bcm_voter>;
2216 compatible = "qcom,sm8350-mpss-pas";
2219 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2225 interrupt-names = "wdog", "fatal", "ready", "handover",
2226 "stop-ack", "shutdown-ack";
2229 clock-names = "xo";
2231 power-domains = <&rpmhpd RPMHPD_CX>,
2233 power-domain-names = "cx", "mss";
2237 memory-region = <&pil_modem_mem>;
2241 qcom,smem-states = <&smp2p_modem_out 0>;
2242 qcom,smem-state-names = "stop";
2246 glink-edge {
2247 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2253 qcom,remote-pid = <1>;
2258 compatible = "qcom,sm8350-slpi-pas";
2261 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2266 interrupt-names = "wdog", "fatal", "ready",
2267 "handover", "stop-ack";
2270 clock-names = "xo";
2272 power-domains = <&rpmhpd RPMHPD_LCX>,
2274 power-domain-names = "lcx", "lmx";
2276 memory-region = <&pil_slpi_mem>;
2280 qcom,smem-states = <&smp2p_slpi_out 0>;
2281 qcom,smem-state-names = "stop";
2285 glink-edge {
2286 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2293 qcom,remote-pid = <3>;
2297 qcom,glink-channels = "fastrpcglink-apps-dsp";
2299 qcom,non-secure-domain;
2300 #address-cells = <1>;
2301 #size-cells = <0>;
2303 compute-cb@1 {
2304 compatible = "qcom,fastrpc-compute-cb";
2309 compute-cb@2 {
2310 compatible = "qcom,fastrpc-compute-cb";
2315 compute-cb@3 {
2316 compatible = "qcom,fastrpc-compute-cb";
2319 /* note: shared-cb = <4> in downstream */
2326 compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5";
2331 interrupt-names = "hc_irq", "pwr_irq";
2336 clock-names = "iface", "core", "xo";
2340 interconnect-names = "sdhc-ddr","cpu-sdhc";
2342 power-domains = <&rpmhpd RPMHPD_CX>;
2343 operating-points-v2 = <&sdhc2_opp_table>;
2344 bus-width = <4>;
2345 dma-coherent;
2349 sdhc2_opp_table: opp-table {
2350 compatible = "operating-points-v2";
2352 opp-100000000 {
2353 opp-hz = /bits/ 64 <100000000>;
2354 required-opps = <&rpmhpd_opp_low_svs>;
2357 opp-202000000 {
2358 opp-hz = /bits/ 64 <202000000>;
2359 required-opps = <&rpmhpd_opp_svs_l1>;
2365 compatible = "qcom,sm8350-usb-hs-phy",
2366 "qcom,usb-snps-hs-7nm-phy";
2369 #phy-cells = <0>;
2372 clock-names = "ref";
2378 compatible = "qcom,sm8250-usb-hs-phy",
2379 "qcom,usb-snps-hs-7nm-phy";
2382 #phy-cells = <0>;
2385 clock-names = "ref";
2391 compatible = "qcom,sm8350-refgen-regulator",
2392 "qcom,sm8250-refgen-regulator";
2397 compatible = "qcom,sm8350-qmp-usb3-dp-phy";
2404 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2408 reset-names = "phy", "common";
2410 #clock-cells = <1>;
2411 #phy-cells = <1>;
2413 orientation-switch;
2418 #address-cells = <1>;
2419 #size-cells = <0>;
2432 remote-endpoint = <&usb_1_dwc3_ss>;
2440 remote-endpoint = <&mdss_dp_out>;
2447 compatible = "qcom,sm8350-qmp-usb3-uni-phy";
2455 clock-names = "aux",
2459 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2460 #clock-cells = <0>;
2461 #phy-cells = <0>;
2465 reset-names = "phy",
2470 compatible = "qcom,sm8350-dc-noc";
2472 #interconnect-cells = <2>;
2473 qcom,bcm-voters = <&apps_bcm_voter>;
2477 compatible = "qcom,sm8350-gem-noc";
2479 #interconnect-cells = <2>;
2480 qcom,bcm-voters = <&apps_bcm_voter>;
2483 system-cache-controller@9200000 {
2484 compatible = "qcom,sm8350-llcc";
2488 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2493 compatible = "qcom,sm8350-compute-noc";
2495 #interconnect-cells = <2>;
2496 qcom,bcm-voters = <&apps_bcm_voter>;
2500 compatible = "qcom,sm8350-cdsp-pas";
2503 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2508 interrupt-names = "wdog", "fatal", "ready",
2509 "handover", "stop-ack";
2512 clock-names = "xo";
2514 power-domains = <&rpmhpd RPMHPD_CX>,
2516 power-domain-names = "cx", "mxc";
2520 memory-region = <&pil_cdsp_mem>;
2524 qcom,smem-states = <&smp2p_cdsp_out 0>;
2525 qcom,smem-state-names = "stop";
2529 glink-edge {
2530 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2537 qcom,remote-pid = <5>;
2541 qcom,glink-channels = "fastrpcglink-apps-dsp";
2543 qcom,non-secure-domain;
2544 #address-cells = <1>;
2545 #size-cells = <0>;
2547 compute-cb@1 {
2548 compatible = "qcom,fastrpc-compute-cb";
2554 compute-cb@2 {
2555 compatible = "qcom,fastrpc-compute-cb";
2561 compute-cb@3 {
2562 compatible = "qcom,fastrpc-compute-cb";
2568 compute-cb@4 {
2569 compatible = "qcom,fastrpc-compute-cb";
2575 compute-cb@5 {
2576 compatible = "qcom,fastrpc-compute-cb";
2582 compute-cb@6 {
2583 compatible = "qcom,fastrpc-compute-cb";
2589 compute-cb@7 {
2590 compatible = "qcom,fastrpc-compute-cb";
2596 compute-cb@8 {
2597 compatible = "qcom,fastrpc-compute-cb";
2609 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2612 #address-cells = <2>;
2613 #size-cells = <2>;
2621 clock-names = "cfg_noc",
2627 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2629 assigned-clock-rates = <19200000>, <200000000>;
2631 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
2636 interrupt-names = "pwr_event",
2642 power-domains = <&gcc USB30_PRIM_GDSC>;
2648 interconnect-names = "usb-ddr", "apps-usb";
2658 snps,dis-u1-entry-quirk;
2659 snps,dis-u2-entry-quirk;
2661 phy-names = "usb2-phy", "usb3-phy";
2664 #address-cells = <1>;
2665 #size-cells = <0>;
2678 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
2686 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2689 #address-cells = <2>;
2690 #size-cells = <2>;
2699 clock-names = "cfg_noc",
2706 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2708 assigned-clock-rates = <19200000>, <200000000>;
2710 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
2715 interrupt-names = "pwr_event",
2721 power-domains = <&gcc USB30_SEC_GDSC>;
2727 interconnect-names = "usb-ddr", "apps-usb";
2737 snps,dis-u1-entry-quirk;
2738 snps,dis-u2-entry-quirk;
2740 phy-names = "usb2-phy", "usb3-phy";
2744 mdss: display-subsystem@ae00000 {
2745 compatible = "qcom,sm8350-mdss";
2747 reg-names = "mdss";
2753 interconnect-names = "mdp0-mem",
2754 "mdp1-mem",
2755 "cpu-cfg";
2757 power-domains = <&dispcc MDSS_GDSC>;
2764 clock-names = "iface", "bus", "nrt_bus", "core";
2767 interrupt-controller;
2768 #interrupt-cells = <1>;
2774 #address-cells = <2>;
2775 #size-cells = <2>;
2778 mdss_mdp: display-controller@ae01000 {
2779 compatible = "qcom,sm8350-dpu";
2782 reg-names = "mdp", "vbif";
2790 clock-names = "bus",
2797 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2798 assigned-clock-rates = <19200000>;
2800 operating-points-v2 = <&dpu_opp_table>;
2801 power-domains = <&rpmhpd RPMHPD_MMCX>;
2803 interrupt-parent = <&mdss>;
2806 dpu_opp_table: opp-table {
2807 compatible = "operating-points-v2";
2809 /* TODO: opp-200000000 should work with
2814 opp-200000000 {
2815 opp-hz = /bits/ 64 <200000000>;
2816 required-opps = <&rpmhpd_opp_svs>;
2819 opp-300000000 {
2820 opp-hz = /bits/ 64 <300000000>;
2821 required-opps = <&rpmhpd_opp_svs>;
2824 opp-345000000 {
2825 opp-hz = /bits/ 64 <345000000>;
2826 required-opps = <&rpmhpd_opp_svs_l1>;
2829 opp-460000000 {
2830 opp-hz = /bits/ 64 <460000000>;
2831 required-opps = <&rpmhpd_opp_nom>;
2836 #address-cells = <1>;
2837 #size-cells = <0>;
2842 remote-endpoint = <&mdss_dsi0_in>;
2849 remote-endpoint = <&mdss_dsi1_in>;
2856 remote-endpoint = <&mdss_dp_in>;
2862 mdss_dp: displayport-controller@ae90000 {
2863 compatible = "qcom,sm8350-dp";
2869 interrupt-parent = <&mdss>;
2876 clock-names = "core_iface",
2882 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
2884 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2888 phy-names = "dp";
2890 #sound-dai-cells = <0>;
2892 operating-points-v2 = <&dp_opp_table>;
2893 power-domains = <&rpmhpd RPMHPD_MMCX>;
2898 #address-cells = <1>;
2899 #size-cells = <0>;
2904 remote-endpoint = <&dpu_intf0_out>;
2912 remote-endpoint = <&usb_1_qmpphy_dp_in>;
2917 dp_opp_table: opp-table {
2918 compatible = "operating-points-v2";
2920 opp-160000000 {
2921 opp-hz = /bits/ 64 <160000000>;
2922 required-opps = <&rpmhpd_opp_low_svs>;
2925 opp-270000000 {
2926 opp-hz = /bits/ 64 <270000000>;
2927 required-opps = <&rpmhpd_opp_svs>;
2930 opp-540000000 {
2931 opp-hz = /bits/ 64 <540000000>;
2932 required-opps = <&rpmhpd_opp_svs_l1>;
2935 opp-810000000 {
2936 opp-hz = /bits/ 64 <810000000>;
2937 required-opps = <&rpmhpd_opp_nom>;
2943 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2945 reg-names = "dsi_ctrl";
2947 interrupt-parent = <&mdss>;
2956 clock-names = "byte",
2963 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2965 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
2968 operating-points-v2 = <&dsi0_opp_table>;
2969 power-domains = <&rpmhpd RPMHPD_MMCX>;
2970 refgen-supply = <&refgen>;
2974 #address-cells = <1>;
2975 #size-cells = <0>;
2979 dsi0_opp_table: opp-table {
2980 compatible = "operating-points-v2";
2982 /* TODO: opp-187500000 should work with
2987 opp-187500000 {
2988 opp-hz = /bits/ 64 <187500000>;
2989 required-opps = <&rpmhpd_opp_svs>;
2992 opp-300000000 {
2993 opp-hz = /bits/ 64 <300000000>;
2994 required-opps = <&rpmhpd_opp_svs>;
2997 opp-358000000 {
2998 opp-hz = /bits/ 64 <358000000>;
2999 required-opps = <&rpmhpd_opp_svs_l1>;
3004 #address-cells = <1>;
3005 #size-cells = <0>;
3010 remote-endpoint = <&dpu_intf1_out>;
3023 compatible = "qcom,sm8350-dsi-phy-5nm";
3027 reg-names = "dsi_phy",
3031 #clock-cells = <1>;
3032 #phy-cells = <0>;
3036 clock-names = "iface", "ref";
3042 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3044 reg-names = "dsi_ctrl";
3046 interrupt-parent = <&mdss>;
3055 clock-names = "byte",
3062 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
3064 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
3067 operating-points-v2 = <&dsi1_opp_table>;
3068 power-domains = <&rpmhpd RPMHPD_MMCX>;
3069 refgen-supply = <&refgen>;
3073 #address-cells = <1>;
3074 #size-cells = <0>;
3078 dsi1_opp_table: opp-table {
3079 compatible = "operating-points-v2";
3081 /* TODO: opp-187500000 should work with
3086 opp-187500000 {
3087 opp-hz = /bits/ 64 <187500000>;
3088 required-opps = <&rpmhpd_opp_svs>;
3091 opp-300000000 {
3092 opp-hz = /bits/ 64 <300000000>;
3093 required-opps = <&rpmhpd_opp_svs>;
3096 opp-358000000 {
3097 opp-hz = /bits/ 64 <358000000>;
3098 required-opps = <&rpmhpd_opp_svs_l1>;
3103 #address-cells = <1>;
3104 #size-cells = <0>;
3109 remote-endpoint = <&dpu_intf2_out>;
3122 compatible = "qcom,sm8350-dsi-phy-5nm";
3126 reg-names = "dsi_phy",
3130 #clock-cells = <1>;
3131 #phy-cells = <0>;
3135 clock-names = "iface", "ref";
3141 dispcc: clock-controller@af00000 {
3142 compatible = "qcom,sm8350-dispcc";
3151 clock-names = "bi_tcxo",
3158 #clock-cells = <1>;
3159 #reset-cells = <1>;
3160 #power-domain-cells = <1>;
3162 power-domains = <&rpmhpd RPMHPD_MMCX>;
3165 pdc: interrupt-controller@b220000 {
3166 compatible = "qcom,sm8350-pdc", "qcom,pdc";
3168 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
3172 #interrupt-cells = <2>;
3173 interrupt-parent = <&intc>;
3174 interrupt-controller;
3177 tsens0: thermal-sensor@c263000 {
3178 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
3182 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
3184 interrupt-names = "uplow", "critical";
3185 #thermal-sensor-cells = <1>;
3188 tsens1: thermal-sensor@c265000 {
3189 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
3193 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
3195 interrupt-names = "uplow", "critical";
3196 #thermal-sensor-cells = <1>;
3199 aoss_qmp: power-management@c300000 {
3200 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp";
3202 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3206 #clock-cells = <0>;
3210 compatible = "qcom,rpmh-stats";
3215 compatible = "qcom,spmi-pmic-arb";
3221 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3222 interrupt-names = "periph_irq";
3223 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3226 #address-cells = <2>;
3227 #size-cells = <0>;
3228 interrupt-controller;
3229 #interrupt-cells = <4>;
3233 compatible = "qcom,sm8350-tlmm";
3236 gpio-controller;
3237 #gpio-cells = <2>;
3238 interrupt-controller;
3239 #interrupt-cells = <2>;
3240 gpio-ranges = <&tlmm 0 0 204>;
3241 wakeup-parent = <&pdc>;
3243 sdc2_default_state: sdc2-default-state {
3244 clk-pins {
3246 drive-strength = <16>;
3247 bias-disable;
3250 cmd-pins {
3252 drive-strength = <16>;
3253 bias-pull-up;
3256 data-pins {
3258 drive-strength = <16>;
3259 bias-pull-up;
3263 sdc2_sleep_state: sdc2-sleep-state {
3264 clk-pins {
3266 drive-strength = <2>;
3267 bias-disable;
3270 cmd-pins {
3272 drive-strength = <2>;
3273 bias-pull-up;
3276 data-pins {
3278 drive-strength = <2>;
3279 bias-pull-up;
3283 qup_uart3_default_state: qup-uart3-default-state {
3284 rx-pins {
3288 tx-pins {
3294 qup_uart6_default: qup-uart6-default-state {
3297 drive-strength = <2>;
3298 bias-disable;
3301 qup_uart18_default: qup-uart18-default-state {
3304 drive-strength = <2>;
3305 bias-disable;
3308 qup_i2c0_default: qup-i2c0-default-state {
3311 drive-strength = <2>;
3312 bias-pull-up;
3315 qup_i2c1_default: qup-i2c1-default-state {
3318 drive-strength = <2>;
3319 bias-pull-up;
3322 qup_i2c2_default: qup-i2c2-default-state {
3325 drive-strength = <2>;
3326 bias-pull-up;
3329 qup_i2c4_default: qup-i2c4-default-state {
3332 drive-strength = <2>;
3333 bias-pull-up;
3336 qup_i2c5_default: qup-i2c5-default-state {
3339 drive-strength = <2>;
3340 bias-pull-up;
3343 qup_i2c6_default: qup-i2c6-default-state {
3346 drive-strength = <2>;
3347 bias-pull-up;
3350 qup_i2c7_default: qup-i2c7-default-state {
3353 drive-strength = <2>;
3354 bias-disable;
3357 qup_i2c8_default: qup-i2c8-default-state {
3360 drive-strength = <2>;
3361 bias-pull-up;
3364 qup_i2c9_default: qup-i2c9-default-state {
3367 drive-strength = <2>;
3368 bias-pull-up;
3371 qup_i2c10_default: qup-i2c10-default-state {
3374 drive-strength = <2>;
3375 bias-pull-up;
3378 qup_i2c11_default: qup-i2c11-default-state {
3381 drive-strength = <2>;
3382 bias-pull-up;
3385 qup_i2c12_default: qup-i2c12-default-state {
3388 drive-strength = <2>;
3389 bias-pull-up;
3392 qup_i2c13_default: qup-i2c13-default-state {
3395 drive-strength = <2>;
3396 bias-pull-up;
3399 qup_i2c14_default: qup-i2c14-default-state {
3402 drive-strength = <2>;
3403 bias-disable;
3406 qup_i2c15_default: qup-i2c15-default-state {
3409 drive-strength = <2>;
3410 bias-disable;
3413 qup_i2c16_default: qup-i2c16-default-state {
3416 drive-strength = <2>;
3417 bias-disable;
3420 qup_i2c17_default: qup-i2c17-default-state {
3423 drive-strength = <2>;
3424 bias-disable;
3427 qup_i2c19_default: qup-i2c19-default-state {
3430 drive-strength = <2>;
3431 bias-disable;
3436 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500";
3438 #iommu-cells = <2>;
3439 #global-interrupts = <2>;
3538 dma-coherent;
3541 intc: interrupt-controller@17a00000 {
3542 compatible = "arm,gic-v3";
3543 #interrupt-cells = <3>;
3544 interrupt-controller;
3545 #redistributor-regions = <1>;
3546 redistributor-stride = <0 0x20000>;
3553 compatible = "arm,armv7-timer-mem";
3554 #address-cells = <1>;
3555 #size-cells = <1>;
3558 clock-frequency = <19200000>;
3561 frame-number = <0>;
3569 frame-number = <1>;
3576 frame-number = <2>;
3583 frame-number = <3>;
3590 frame-number = <4>;
3597 frame-number = <5>;
3604 frame-number = <6>;
3613 compatible = "qcom,rpmh-rsc";
3617 reg-names = "drv-0", "drv-1", "drv-2";
3621 qcom,tcs-offset = <0xd00>;
3622 qcom,drv-id = <2>;
3623 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
3625 power-domains = <&cluster_pd>;
3627 rpmhcc: clock-controller {
3628 compatible = "qcom,sm8350-rpmh-clk";
3629 #clock-cells = <1>;
3630 clock-names = "xo";
3634 rpmhpd: power-controller {
3635 compatible = "qcom,sm8350-rpmhpd";
3636 #power-domain-cells = <1>;
3637 operating-points-v2 = <&rpmhpd_opp_table>;
3639 rpmhpd_opp_table: opp-table {
3640 compatible = "operating-points-v2";
3643 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3647 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3651 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3655 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3659 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3663 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3667 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3671 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3675 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3679 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3684 apps_bcm_voter: bcm-voter {
3685 compatible = "qcom,bcm-voter";
3690 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
3694 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
3699 interrupt-names = "dcvsh-irq-0",
3700 "dcvsh-irq-1",
3701 "dcvsh-irq-2";
3704 clock-names = "xo", "alternate";
3706 #freq-domain-cells = <1>;
3707 #clock-cells = <1>;
3711 thermal_zones: thermal-zones {
3712 cpu0-thermal {
3713 polling-delay-passive = <250>;
3715 thermal-sensors = <&tsens0 1>;
3718 cpu0_alert0: trip-point0 {
3724 cpu0_alert1: trip-point1 {
3730 cpu0_crit: cpu-crit {
3737 cooling-maps {
3740 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3747 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3755 cpu1-thermal {
3756 polling-delay-passive = <250>;
3758 thermal-sensors = <&tsens0 2>;
3761 cpu1_alert0: trip-point0 {
3767 cpu1_alert1: trip-point1 {
3773 cpu1_crit: cpu-crit {
3780 cooling-maps {
3783 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3790 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3798 cpu2-thermal {
3799 polling-delay-passive = <250>;
3801 thermal-sensors = <&tsens0 3>;
3804 cpu2_alert0: trip-point0 {
3810 cpu2_alert1: trip-point1 {
3816 cpu2_crit: cpu-crit {
3823 cooling-maps {
3826 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3833 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3841 cpu3-thermal {
3842 polling-delay-passive = <250>;
3844 thermal-sensors = <&tsens0 4>;
3847 cpu3_alert0: trip-point0 {
3853 cpu3_alert1: trip-point1 {
3859 cpu3_crit: cpu-crit {
3866 cooling-maps {
3869 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3876 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3884 cpu4-top-thermal {
3885 polling-delay-passive = <250>;
3887 thermal-sensors = <&tsens0 7>;
3890 cpu4_top_alert0: trip-point0 {
3896 cpu4_top_alert1: trip-point1 {
3902 cpu4_top_crit: cpu-crit {
3909 cooling-maps {
3912 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3919 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3927 cpu5-top-thermal {
3928 polling-delay-passive = <250>;
3930 thermal-sensors = <&tsens0 8>;
3933 cpu5_top_alert0: trip-point0 {
3939 cpu5_top_alert1: trip-point1 {
3945 cpu5_top_crit: cpu-crit {
3952 cooling-maps {
3955 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3962 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3970 cpu6-top-thermal {
3971 polling-delay-passive = <250>;
3973 thermal-sensors = <&tsens0 9>;
3976 cpu6_top_alert0: trip-point0 {
3982 cpu6_top_alert1: trip-point1 {
3988 cpu6_top_crit: cpu-crit {
3995 cooling-maps {
3998 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4005 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4013 cpu7-top-thermal {
4014 polling-delay-passive = <250>;
4016 thermal-sensors = <&tsens0 10>;
4019 cpu7_top_alert0: trip-point0 {
4025 cpu7_top_alert1: trip-point1 {
4031 cpu7_top_crit: cpu-crit {
4038 cooling-maps {
4041 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4048 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4056 cpu4-bottom-thermal {
4057 polling-delay-passive = <250>;
4059 thermal-sensors = <&tsens0 11>;
4062 cpu4_bottom_alert0: trip-point0 {
4068 cpu4_bottom_alert1: trip-point1 {
4074 cpu4_bottom_crit: cpu-crit {
4081 cooling-maps {
4084 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4091 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4099 cpu5-bottom-thermal {
4100 polling-delay-passive = <250>;
4102 thermal-sensors = <&tsens0 12>;
4105 cpu5_bottom_alert0: trip-point0 {
4111 cpu5_bottom_alert1: trip-point1 {
4117 cpu5_bottom_crit: cpu-crit {
4124 cooling-maps {
4127 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4134 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4142 cpu6-bottom-thermal {
4143 polling-delay-passive = <250>;
4145 thermal-sensors = <&tsens0 13>;
4148 cpu6_bottom_alert0: trip-point0 {
4154 cpu6_bottom_alert1: trip-point1 {
4160 cpu6_bottom_crit: cpu-crit {
4167 cooling-maps {
4170 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4177 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4185 cpu7-bottom-thermal {
4186 polling-delay-passive = <250>;
4188 thermal-sensors = <&tsens0 14>;
4191 cpu7_bottom_alert0: trip-point0 {
4197 cpu7_bottom_alert1: trip-point1 {
4203 cpu7_bottom_crit: cpu-crit {
4210 cooling-maps {
4213 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4220 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4228 aoss0-thermal {
4229 polling-delay-passive = <250>;
4231 thermal-sensors = <&tsens0 0>;
4234 aoss0_alert0: trip-point0 {
4242 cluster0-thermal {
4243 polling-delay-passive = <250>;
4245 thermal-sensors = <&tsens0 5>;
4248 cluster0_alert0: trip-point0 {
4253 cluster0_crit: cluster0-crit {
4261 cluster1-thermal {
4262 polling-delay-passive = <250>;
4264 thermal-sensors = <&tsens0 6>;
4267 cluster1_alert0: trip-point0 {
4272 cluster1_crit: cluster1-crit {
4280 aoss1-thermal {
4281 polling-delay-passive = <250>;
4283 thermal-sensors = <&tsens1 0>;
4286 aoss1_alert0: trip-point0 {
4294 gpu-top-thermal {
4295 polling-delay-passive = <250>;
4297 thermal-sensors = <&tsens1 1>;
4299 cooling-maps {
4302 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4307 gpu_top_alert0: trip-point0 {
4313 trip-point1 {
4319 trip-point2 {
4327 gpu-bottom-thermal {
4328 polling-delay-passive = <250>;
4330 thermal-sensors = <&tsens1 2>;
4332 cooling-maps {
4335 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4340 gpu_bottom_alert0: trip-point0 {
4346 trip-point1 {
4352 trip-point2 {
4360 nspss1-thermal {
4361 polling-delay-passive = <250>;
4363 thermal-sensors = <&tsens1 3>;
4366 nspss1_alert0: trip-point0 {
4374 nspss2-thermal {
4375 polling-delay-passive = <250>;
4377 thermal-sensors = <&tsens1 4>;
4380 nspss2_alert0: trip-point0 {
4388 nspss3-thermal {
4389 polling-delay-passive = <250>;
4391 thermal-sensors = <&tsens1 5>;
4394 nspss3_alert0: trip-point0 {
4402 video-thermal {
4403 polling-delay-passive = <250>;
4405 thermal-sensors = <&tsens1 6>;
4408 video_alert0: trip-point0 {
4416 mem-thermal {
4417 polling-delay-passive = <250>;
4419 thermal-sensors = <&tsens1 7>;
4422 mem_alert0: trip-point0 {
4430 modem1-top-thermal {
4431 polling-delay-passive = <250>;
4433 thermal-sensors = <&tsens1 8>;
4436 modem1_alert0: trip-point0 {
4444 modem2-top-thermal {
4445 polling-delay-passive = <250>;
4447 thermal-sensors = <&tsens1 9>;
4450 modem2_alert0: trip-point0 {
4458 modem3-top-thermal {
4459 polling-delay-passive = <250>;
4461 thermal-sensors = <&tsens1 10>;
4464 modem3_alert0: trip-point0 {
4472 modem4-top-thermal {
4473 polling-delay-passive = <250>;
4475 thermal-sensors = <&tsens1 11>;
4478 modem4_alert0: trip-point0 {
4486 camera-top-thermal {
4487 polling-delay-passive = <250>;
4489 thermal-sensors = <&tsens1 12>;
4492 camera1_alert0: trip-point0 {
4500 cam-bottom-thermal {
4501 polling-delay-passive = <250>;
4503 thermal-sensors = <&tsens1 13>;
4506 camera2_alert0: trip-point0 {
4516 compatible = "arm,armv8-timer";