Lines Matching +full:q6afe +full:- +full:clocks
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interconnect/qcom,sm8350.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
9 #include <dt-bindings/clock/qcom,gcc-sm8350.h>
10 #include <dt-bindings/clock/qcom,gpucc-sm8350.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/firmware/qcom,scm.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interconnect/qcom,icc.h>
16 #include <dt-bindings/interconnect/qcom,sm8350.h>
17 #include <dt-bindings/mailbox/qcom-ipcc.h>
18 #include <dt-bindings/phy/phy-qcom-qmp.h>
19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/power/qcom,rpmhpd.h>
21 #include <dt-bindings/soc/qcom,apr.h>
22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
23 #include <dt-bindings/sound/qcom,q6afe.h>
24 #include <dt-bindings/thermal/thermal.h>
25 #include <dt-bindings/interconnect/qcom,sm8350.h>
28 interrupt-parent = <&intc>;
30 #address-cells = <2>;
31 #size-cells = <2>;
35 clocks {
36 xo_board: xo-board {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-frequency = <38400000>;
40 clock-output-names = "xo_board";
43 sleep_clk: sleep-clk {
44 compatible = "fixed-clock";
45 clock-frequency = <32000>;
46 #clock-cells = <0>;
51 #address-cells = <2>;
52 #size-cells = <0>;
56 compatible = "arm,cortex-a55";
58 clocks = <&cpufreq_hw 0>;
59 enable-method = "psci";
60 next-level-cache = <&L2_0>;
61 qcom,freq-domain = <&cpufreq_hw 0>;
62 power-domains = <&CPU_PD0>;
63 power-domain-names = "psci";
64 #cooling-cells = <2>;
65 L2_0: l2-cache {
67 cache-level = <2>;
68 cache-unified;
69 next-level-cache = <&L3_0>;
70 L3_0: l3-cache {
72 cache-level = <3>;
73 cache-unified;
80 compatible = "arm,cortex-a55";
82 clocks = <&cpufreq_hw 0>;
83 enable-method = "psci";
84 next-level-cache = <&L2_100>;
85 qcom,freq-domain = <&cpufreq_hw 0>;
86 power-domains = <&CPU_PD1>;
87 power-domain-names = "psci";
88 #cooling-cells = <2>;
89 L2_100: l2-cache {
91 cache-level = <2>;
92 cache-unified;
93 next-level-cache = <&L3_0>;
99 compatible = "arm,cortex-a55";
101 clocks = <&cpufreq_hw 0>;
102 enable-method = "psci";
103 next-level-cache = <&L2_200>;
104 qcom,freq-domain = <&cpufreq_hw 0>;
105 power-domains = <&CPU_PD2>;
106 power-domain-names = "psci";
107 #cooling-cells = <2>;
108 L2_200: l2-cache {
110 cache-level = <2>;
111 cache-unified;
112 next-level-cache = <&L3_0>;
118 compatible = "arm,cortex-a55";
120 clocks = <&cpufreq_hw 0>;
121 enable-method = "psci";
122 next-level-cache = <&L2_300>;
123 qcom,freq-domain = <&cpufreq_hw 0>;
124 power-domains = <&CPU_PD3>;
125 power-domain-names = "psci";
126 #cooling-cells = <2>;
127 L2_300: l2-cache {
129 cache-level = <2>;
130 cache-unified;
131 next-level-cache = <&L3_0>;
137 compatible = "arm,cortex-a78";
139 clocks = <&cpufreq_hw 1>;
140 enable-method = "psci";
141 next-level-cache = <&L2_400>;
142 qcom,freq-domain = <&cpufreq_hw 1>;
143 power-domains = <&CPU_PD4>;
144 power-domain-names = "psci";
145 #cooling-cells = <2>;
146 L2_400: l2-cache {
148 cache-level = <2>;
149 cache-unified;
150 next-level-cache = <&L3_0>;
156 compatible = "arm,cortex-a78";
158 clocks = <&cpufreq_hw 1>;
159 enable-method = "psci";
160 next-level-cache = <&L2_500>;
161 qcom,freq-domain = <&cpufreq_hw 1>;
162 power-domains = <&CPU_PD5>;
163 power-domain-names = "psci";
164 #cooling-cells = <2>;
165 L2_500: l2-cache {
167 cache-level = <2>;
168 cache-unified;
169 next-level-cache = <&L3_0>;
175 compatible = "arm,cortex-a78";
177 clocks = <&cpufreq_hw 1>;
178 enable-method = "psci";
179 next-level-cache = <&L2_600>;
180 qcom,freq-domain = <&cpufreq_hw 1>;
181 power-domains = <&CPU_PD6>;
182 power-domain-names = "psci";
183 #cooling-cells = <2>;
184 L2_600: l2-cache {
186 cache-level = <2>;
187 cache-unified;
188 next-level-cache = <&L3_0>;
194 compatible = "arm,cortex-x1";
196 clocks = <&cpufreq_hw 2>;
197 enable-method = "psci";
198 next-level-cache = <&L2_700>;
199 qcom,freq-domain = <&cpufreq_hw 2>;
200 power-domains = <&CPU_PD7>;
201 power-domain-names = "psci";
202 #cooling-cells = <2>;
203 L2_700: l2-cache {
205 cache-level = <2>;
206 cache-unified;
207 next-level-cache = <&L3_0>;
211 cpu-map {
247 idle-states {
248 entry-method = "psci";
250 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
251 compatible = "arm,idle-state";
252 idle-state-name = "silver-rail-power-collapse";
253 arm,psci-suspend-param = <0x40000004>;
254 entry-latency-us = <360>;
255 exit-latency-us = <531>;
256 min-residency-us = <3934>;
257 local-timer-stop;
260 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
261 compatible = "arm,idle-state";
262 idle-state-name = "gold-rail-power-collapse";
263 arm,psci-suspend-param = <0x40000004>;
264 entry-latency-us = <702>;
265 exit-latency-us = <1061>;
266 min-residency-us = <4488>;
267 local-timer-stop;
271 domain-idle-states {
272 CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 {
273 compatible = "domain-idle-state";
274 arm,psci-suspend-param = <0x41000044>;
275 entry-latency-us = <2752>;
276 exit-latency-us = <3048>;
277 min-residency-us = <6118>;
280 CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 {
281 compatible = "domain-idle-state";
282 arm,psci-suspend-param = <0x4100c344>;
283 entry-latency-us = <3263>;
284 exit-latency-us = <6562>;
285 min-residency-us = <9987>;
292 compatible = "qcom,scm-sm8350", "qcom,scm";
293 qcom,dload-mode = <&tcsr 0x13000>;
294 #reset-cells = <1>;
304 pmu-a55 {
305 compatible = "arm,cortex-a55-pmu";
309 pmu-a78 {
310 compatible = "arm,cortex-a78-pmu";
314 pmu-x1 {
315 compatible = "arm,cortex-x1-pmu";
320 compatible = "arm,psci-1.0";
323 CPU_PD0: power-domain-cpu0 {
324 #power-domain-cells = <0>;
325 power-domains = <&CLUSTER_PD>;
326 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
329 CPU_PD1: power-domain-cpu1 {
330 #power-domain-cells = <0>;
331 power-domains = <&CLUSTER_PD>;
332 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
335 CPU_PD2: power-domain-cpu2 {
336 #power-domain-cells = <0>;
337 power-domains = <&CLUSTER_PD>;
338 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
341 CPU_PD3: power-domain-cpu3 {
342 #power-domain-cells = <0>;
343 power-domains = <&CLUSTER_PD>;
344 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
347 CPU_PD4: power-domain-cpu4 {
348 #power-domain-cells = <0>;
349 power-domains = <&CLUSTER_PD>;
350 domain-idle-states = <&BIG_CPU_SLEEP_0>;
353 CPU_PD5: power-domain-cpu5 {
354 #power-domain-cells = <0>;
355 power-domains = <&CLUSTER_PD>;
356 domain-idle-states = <&BIG_CPU_SLEEP_0>;
359 CPU_PD6: power-domain-cpu6 {
360 #power-domain-cells = <0>;
361 power-domains = <&CLUSTER_PD>;
362 domain-idle-states = <&BIG_CPU_SLEEP_0>;
365 CPU_PD7: power-domain-cpu7 {
366 #power-domain-cells = <0>;
367 power-domains = <&CLUSTER_PD>;
368 domain-idle-states = <&BIG_CPU_SLEEP_0>;
371 CLUSTER_PD: power-domain-cpu-cluster0 {
372 #power-domain-cells = <0>;
373 domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLEEP>;
377 qup_opp_table_100mhz: opp-table-qup100mhz {
378 compatible = "operating-points-v2";
380 opp-50000000 {
381 opp-hz = /bits/ 64 <50000000>;
382 required-opps = <&rpmhpd_opp_min_svs>;
385 opp-75000000 {
386 opp-hz = /bits/ 64 <75000000>;
387 required-opps = <&rpmhpd_opp_low_svs>;
390 opp-100000000 {
391 opp-hz = /bits/ 64 <100000000>;
392 required-opps = <&rpmhpd_opp_svs>;
396 qup_opp_table_120mhz: opp-table-qup120mhz {
397 compatible = "operating-points-v2";
399 opp-50000000 {
400 opp-hz = /bits/ 64 <50000000>;
401 required-opps = <&rpmhpd_opp_min_svs>;
404 opp-75000000 {
405 opp-hz = /bits/ 64 <75000000>;
406 required-opps = <&rpmhpd_opp_low_svs>;
409 opp-120000000 {
410 opp-hz = /bits/ 64 <120000000>;
411 required-opps = <&rpmhpd_opp_svs>;
415 reserved_memory: reserved-memory {
416 #address-cells = <2>;
417 #size-cells = <2>;
422 no-map;
426 no-map;
431 compatible = "qcom,cmd-db";
433 no-map;
438 no-map;
445 no-map;
450 no-map;
455 no-map;
460 no-map;
465 no-map;
470 no-map;
475 no-map;
480 no-map;
485 no-map;
490 no-map;
495 no-map;
500 no-map;
505 no-map;
510 no-map;
514 compatible = "qcom,rmtfs-mem";
516 no-map;
518 qcom,client-id = <1>;
524 no-map;
529 no-map;
534 no-map;
539 no-map;
544 no-map;
549 no-map;
553 smp2p-adsp {
556 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
562 qcom,local-pid = <0>;
563 qcom,remote-pid = <2>;
565 smp2p_adsp_out: master-kernel {
566 qcom,entry-name = "master-kernel";
567 #qcom,smem-state-cells = <1>;
570 smp2p_adsp_in: slave-kernel {
571 qcom,entry-name = "slave-kernel";
572 interrupt-controller;
573 #interrupt-cells = <2>;
577 smp2p-cdsp {
580 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
586 qcom,local-pid = <0>;
587 qcom,remote-pid = <5>;
589 smp2p_cdsp_out: master-kernel {
590 qcom,entry-name = "master-kernel";
591 #qcom,smem-state-cells = <1>;
594 smp2p_cdsp_in: slave-kernel {
595 qcom,entry-name = "slave-kernel";
596 interrupt-controller;
597 #interrupt-cells = <2>;
601 smp2p-modem {
604 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
610 qcom,local-pid = <0>;
611 qcom,remote-pid = <1>;
613 smp2p_modem_out: master-kernel {
614 qcom,entry-name = "master-kernel";
615 #qcom,smem-state-cells = <1>;
618 smp2p_modem_in: slave-kernel {
619 qcom,entry-name = "slave-kernel";
620 interrupt-controller;
621 #interrupt-cells = <2>;
624 ipa_smp2p_out: ipa-ap-to-modem {
625 qcom,entry-name = "ipa";
626 #qcom,smem-state-cells = <1>;
629 ipa_smp2p_in: ipa-modem-to-ap {
630 qcom,entry-name = "ipa";
631 interrupt-controller;
632 #interrupt-cells = <2>;
636 smp2p-slpi {
639 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
645 qcom,local-pid = <0>;
646 qcom,remote-pid = <3>;
648 smp2p_slpi_out: master-kernel {
649 qcom,entry-name = "master-kernel";
650 #qcom,smem-state-cells = <1>;
653 smp2p_slpi_in: slave-kernel {
654 qcom,entry-name = "slave-kernel";
655 interrupt-controller;
656 #interrupt-cells = <2>;
661 #address-cells = <2>;
662 #size-cells = <2>;
664 dma-ranges = <0 0 0 0 0x10 0>;
665 compatible = "simple-bus";
667 gcc: clock-controller@100000 {
668 compatible = "qcom,gcc-sm8350";
670 #clock-cells = <1>;
671 #reset-cells = <1>;
672 #power-domain-cells = <1>;
673 clock-names = "bi_tcxo",
685 clocks = <&rpmhcc RPMH_CXO_CLK>,
700 compatible = "qcom,sm8350-ipcc", "qcom,ipcc";
703 interrupt-controller;
704 #interrupt-cells = <3>;
705 #mbox-cells = <2>;
708 gpi_dma2: dma-controller@800000 {
709 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
723 dma-channels = <12>;
724 dma-channel-mask = <0xff>;
726 #dma-cells = <3>;
731 compatible = "qcom,geni-se-qup";
733 clock-names = "m-ahb", "s-ahb";
734 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
737 #address-cells = <2>;
738 #size-cells = <2>;
743 compatible = "qcom,geni-i2c";
745 clock-names = "se";
746 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
747 pinctrl-names = "default";
748 pinctrl-0 = <&qup_i2c14_default>;
752 dma-names = "tx", "rx";
753 #address-cells = <1>;
754 #size-cells = <0>;
759 compatible = "qcom,geni-spi";
761 clock-names = "se";
762 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
764 power-domains = <&rpmhpd RPMHPD_CX>;
765 operating-points-v2 = <&qup_opp_table_120mhz>;
768 dma-names = "tx", "rx";
769 #address-cells = <1>;
770 #size-cells = <0>;
775 compatible = "qcom,geni-i2c";
777 clock-names = "se";
778 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
779 pinctrl-names = "default";
780 pinctrl-0 = <&qup_i2c15_default>;
784 dma-names = "tx", "rx";
785 #address-cells = <1>;
786 #size-cells = <0>;
791 compatible = "qcom,geni-spi";
793 clock-names = "se";
794 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
796 power-domains = <&rpmhpd RPMHPD_CX>;
797 operating-points-v2 = <&qup_opp_table_120mhz>;
800 dma-names = "tx", "rx";
801 #address-cells = <1>;
802 #size-cells = <0>;
807 compatible = "qcom,geni-i2c";
809 clock-names = "se";
810 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
811 pinctrl-names = "default";
812 pinctrl-0 = <&qup_i2c16_default>;
816 dma-names = "tx", "rx";
817 #address-cells = <1>;
818 #size-cells = <0>;
823 compatible = "qcom,geni-spi";
825 clock-names = "se";
826 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
828 power-domains = <&rpmhpd RPMHPD_CX>;
829 operating-points-v2 = <&qup_opp_table_100mhz>;
832 dma-names = "tx", "rx";
833 #address-cells = <1>;
834 #size-cells = <0>;
839 compatible = "qcom,geni-i2c";
841 clock-names = "se";
842 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
843 pinctrl-names = "default";
844 pinctrl-0 = <&qup_i2c17_default>;
848 dma-names = "tx", "rx";
849 #address-cells = <1>;
850 #size-cells = <0>;
855 compatible = "qcom,geni-spi";
857 clock-names = "se";
858 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
860 power-domains = <&rpmhpd RPMHPD_CX>;
861 operating-points-v2 = <&qup_opp_table_100mhz>;
864 dma-names = "tx", "rx";
865 #address-cells = <1>;
866 #size-cells = <0>;
870 /* QUP no. 18 seems to be strictly SPI/UART-only */
873 compatible = "qcom,geni-spi";
875 clock-names = "se";
876 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
878 power-domains = <&rpmhpd RPMHPD_CX>;
879 operating-points-v2 = <&qup_opp_table_100mhz>;
882 dma-names = "tx", "rx";
883 #address-cells = <1>;
884 #size-cells = <0>;
889 compatible = "qcom,geni-uart";
891 clock-names = "se";
892 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
893 pinctrl-names = "default";
894 pinctrl-0 = <&qup_uart18_default>;
896 power-domains = <&rpmhpd RPMHPD_CX>;
897 operating-points-v2 = <&qup_opp_table_100mhz>;
902 compatible = "qcom,geni-i2c";
904 clock-names = "se";
905 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
906 pinctrl-names = "default";
907 pinctrl-0 = <&qup_i2c19_default>;
911 dma-names = "tx", "rx";
912 #address-cells = <1>;
913 #size-cells = <0>;
918 compatible = "qcom,geni-spi";
920 clock-names = "se";
921 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
923 power-domains = <&rpmhpd RPMHPD_CX>;
924 operating-points-v2 = <&qup_opp_table_100mhz>;
927 dma-names = "tx", "rx";
928 #address-cells = <1>;
929 #size-cells = <0>;
934 gpi_dma0: dma-controller@900000 {
935 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
949 dma-channels = <12>;
950 dma-channel-mask = <0x7e>;
952 #dma-cells = <3>;
957 compatible = "qcom,geni-se-qup";
959 clock-names = "m-ahb", "s-ahb";
960 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
963 #address-cells = <2>;
964 #size-cells = <2>;
969 compatible = "qcom,geni-i2c";
971 clock-names = "se";
972 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
973 pinctrl-names = "default";
974 pinctrl-0 = <&qup_i2c0_default>;
978 dma-names = "tx", "rx";
979 #address-cells = <1>;
980 #size-cells = <0>;
985 compatible = "qcom,geni-spi";
987 clock-names = "se";
988 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
990 power-domains = <&rpmhpd RPMHPD_CX>;
991 operating-points-v2 = <&qup_opp_table_100mhz>;
994 dma-names = "tx", "rx";
995 #address-cells = <1>;
996 #size-cells = <0>;
1001 compatible = "qcom,geni-i2c";
1003 clock-names = "se";
1004 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1005 pinctrl-names = "default";
1006 pinctrl-0 = <&qup_i2c1_default>;
1010 dma-names = "tx", "rx";
1011 #address-cells = <1>;
1012 #size-cells = <0>;
1017 compatible = "qcom,geni-spi";
1019 clock-names = "se";
1020 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1022 power-domains = <&rpmhpd RPMHPD_CX>;
1023 operating-points-v2 = <&qup_opp_table_100mhz>;
1026 dma-names = "tx", "rx";
1027 #address-cells = <1>;
1028 #size-cells = <0>;
1033 compatible = "qcom,geni-i2c";
1035 clock-names = "se";
1036 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1037 pinctrl-names = "default";
1038 pinctrl-0 = <&qup_i2c2_default>;
1042 dma-names = "tx", "rx";
1043 #address-cells = <1>;
1044 #size-cells = <0>;
1049 compatible = "qcom,geni-spi";
1051 clock-names = "se";
1052 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1054 power-domains = <&rpmhpd RPMHPD_CX>;
1055 operating-points-v2 = <&qup_opp_table_100mhz>;
1058 dma-names = "tx", "rx";
1059 #address-cells = <1>;
1060 #size-cells = <0>;
1065 compatible = "qcom,geni-debug-uart";
1067 clock-names = "se";
1068 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1069 pinctrl-names = "default";
1070 pinctrl-0 = <&qup_uart3_default_state>;
1072 power-domains = <&rpmhpd RPMHPD_CX>;
1073 operating-points-v2 = <&qup_opp_table_100mhz>;
1077 /* QUP no. 3 seems to be strictly SPI-only */
1080 compatible = "qcom,geni-spi";
1082 clock-names = "se";
1083 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1085 power-domains = <&rpmhpd RPMHPD_CX>;
1086 operating-points-v2 = <&qup_opp_table_100mhz>;
1089 dma-names = "tx", "rx";
1090 #address-cells = <1>;
1091 #size-cells = <0>;
1096 compatible = "qcom,geni-i2c";
1098 clock-names = "se";
1099 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1100 pinctrl-names = "default";
1101 pinctrl-0 = <&qup_i2c4_default>;
1105 dma-names = "tx", "rx";
1106 #address-cells = <1>;
1107 #size-cells = <0>;
1112 compatible = "qcom,geni-spi";
1114 clock-names = "se";
1115 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1117 power-domains = <&rpmhpd RPMHPD_CX>;
1118 operating-points-v2 = <&qup_opp_table_100mhz>;
1121 dma-names = "tx", "rx";
1122 #address-cells = <1>;
1123 #size-cells = <0>;
1128 compatible = "qcom,geni-i2c";
1130 clock-names = "se";
1131 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1132 pinctrl-names = "default";
1133 pinctrl-0 = <&qup_i2c5_default>;
1137 dma-names = "tx", "rx";
1138 #address-cells = <1>;
1139 #size-cells = <0>;
1144 compatible = "qcom,geni-spi";
1146 clock-names = "se";
1147 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1149 power-domains = <&rpmhpd RPMHPD_CX>;
1150 operating-points-v2 = <&qup_opp_table_100mhz>;
1153 dma-names = "tx", "rx";
1154 #address-cells = <1>;
1155 #size-cells = <0>;
1160 compatible = "qcom,geni-i2c";
1162 clock-names = "se";
1163 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1164 pinctrl-names = "default";
1165 pinctrl-0 = <&qup_i2c6_default>;
1169 dma-names = "tx", "rx";
1170 #address-cells = <1>;
1171 #size-cells = <0>;
1176 compatible = "qcom,geni-spi";
1178 clock-names = "se";
1179 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1181 power-domains = <&rpmhpd RPMHPD_CX>;
1182 operating-points-v2 = <&qup_opp_table_100mhz>;
1185 dma-names = "tx", "rx";
1186 #address-cells = <1>;
1187 #size-cells = <0>;
1192 compatible = "qcom,geni-uart";
1194 clock-names = "se";
1195 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1196 pinctrl-names = "default";
1197 pinctrl-0 = <&qup_uart6_default>;
1199 power-domains = <&rpmhpd RPMHPD_CX>;
1200 operating-points-v2 = <&qup_opp_table_100mhz>;
1205 compatible = "qcom,geni-i2c";
1207 clock-names = "se";
1208 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1209 pinctrl-names = "default";
1210 pinctrl-0 = <&qup_i2c7_default>;
1214 dma-names = "tx", "rx";
1215 #address-cells = <1>;
1216 #size-cells = <0>;
1221 compatible = "qcom,geni-spi";
1223 clock-names = "se";
1224 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1226 power-domains = <&rpmhpd RPMHPD_CX>;
1227 operating-points-v2 = <&qup_opp_table_100mhz>;
1230 dma-names = "tx", "rx";
1231 #address-cells = <1>;
1232 #size-cells = <0>;
1237 gpi_dma1: dma-controller@a00000 {
1238 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
1252 dma-channels = <12>;
1253 dma-channel-mask = <0xff>;
1255 #dma-cells = <3>;
1260 compatible = "qcom,geni-se-qup";
1262 clock-names = "m-ahb", "s-ahb";
1263 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1266 #address-cells = <2>;
1267 #size-cells = <2>;
1272 compatible = "qcom,geni-i2c";
1274 clock-names = "se";
1275 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1276 pinctrl-names = "default";
1277 pinctrl-0 = <&qup_i2c8_default>;
1281 dma-names = "tx", "rx";
1282 #address-cells = <1>;
1283 #size-cells = <0>;
1288 compatible = "qcom,geni-spi";
1290 clock-names = "se";
1291 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1293 power-domains = <&rpmhpd RPMHPD_CX>;
1294 operating-points-v2 = <&qup_opp_table_120mhz>;
1297 dma-names = "tx", "rx";
1298 #address-cells = <1>;
1299 #size-cells = <0>;
1304 compatible = "qcom,geni-i2c";
1306 clock-names = "se";
1307 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1308 pinctrl-names = "default";
1309 pinctrl-0 = <&qup_i2c9_default>;
1313 dma-names = "tx", "rx";
1314 #address-cells = <1>;
1315 #size-cells = <0>;
1320 compatible = "qcom,geni-spi";
1322 clock-names = "se";
1323 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1325 power-domains = <&rpmhpd RPMHPD_CX>;
1326 operating-points-v2 = <&qup_opp_table_100mhz>;
1329 dma-names = "tx", "rx";
1330 #address-cells = <1>;
1331 #size-cells = <0>;
1336 compatible = "qcom,geni-i2c";
1338 clock-names = "se";
1339 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1340 pinctrl-names = "default";
1341 pinctrl-0 = <&qup_i2c10_default>;
1345 dma-names = "tx", "rx";
1346 #address-cells = <1>;
1347 #size-cells = <0>;
1352 compatible = "qcom,geni-spi";
1354 clock-names = "se";
1355 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1357 power-domains = <&rpmhpd RPMHPD_CX>;
1358 operating-points-v2 = <&qup_opp_table_100mhz>;
1361 dma-names = "tx", "rx";
1362 #address-cells = <1>;
1363 #size-cells = <0>;
1368 compatible = "qcom,geni-i2c";
1370 clock-names = "se";
1371 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1372 pinctrl-names = "default";
1373 pinctrl-0 = <&qup_i2c11_default>;
1377 dma-names = "tx", "rx";
1378 #address-cells = <1>;
1379 #size-cells = <0>;
1384 compatible = "qcom,geni-spi";
1386 clock-names = "se";
1387 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1389 power-domains = <&rpmhpd RPMHPD_CX>;
1390 operating-points-v2 = <&qup_opp_table_100mhz>;
1393 dma-names = "tx", "rx";
1394 #address-cells = <1>;
1395 #size-cells = <0>;
1400 compatible = "qcom,geni-i2c";
1402 clock-names = "se";
1403 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1404 pinctrl-names = "default";
1405 pinctrl-0 = <&qup_i2c12_default>;
1409 dma-names = "tx", "rx";
1410 #address-cells = <1>;
1411 #size-cells = <0>;
1416 compatible = "qcom,geni-spi";
1418 clock-names = "se";
1419 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1421 power-domains = <&rpmhpd RPMHPD_CX>;
1422 operating-points-v2 = <&qup_opp_table_100mhz>;
1425 dma-names = "tx", "rx";
1426 #address-cells = <1>;
1427 #size-cells = <0>;
1432 compatible = "qcom,geni-i2c";
1434 clock-names = "se";
1435 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1436 pinctrl-names = "default";
1437 pinctrl-0 = <&qup_i2c13_default>;
1441 dma-names = "tx", "rx";
1442 #address-cells = <1>;
1443 #size-cells = <0>;
1448 compatible = "qcom,geni-spi";
1450 clock-names = "se";
1451 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1453 power-domains = <&rpmhpd RPMHPD_CX>;
1454 operating-points-v2 = <&qup_opp_table_100mhz>;
1457 dma-names = "tx", "rx";
1458 #address-cells = <1>;
1459 #size-cells = <0>;
1465 compatible = "qcom,prng-ee";
1467 clocks = <&rpmhcc RPMH_HWKM_CLK>;
1468 clock-names = "core";
1472 compatible = "qcom,sm8350-config-noc";
1474 #interconnect-cells = <2>;
1475 qcom,bcm-voters = <&apps_bcm_voter>;
1479 compatible = "qcom,sm8350-mc-virt";
1481 #interconnect-cells = <2>;
1482 qcom,bcm-voters = <&apps_bcm_voter>;
1486 compatible = "qcom,sm8350-system-noc";
1488 #interconnect-cells = <2>;
1489 qcom,bcm-voters = <&apps_bcm_voter>;
1493 compatible = "qcom,sm8350-aggre1-noc";
1495 #interconnect-cells = <2>;
1496 qcom,bcm-voters = <&apps_bcm_voter>;
1500 compatible = "qcom,sm8350-aggre2-noc";
1502 #interconnect-cells = <2>;
1503 qcom,bcm-voters = <&apps_bcm_voter>;
1507 compatible = "qcom,sm8350-mmss-noc";
1509 #interconnect-cells = <2>;
1510 qcom,bcm-voters = <&apps_bcm_voter>;
1514 compatible = "qcom,pcie-sm8350";
1520 reg-names = "parf", "dbi", "elbi", "atu", "config";
1522 linux,pci-domain = <0>;
1523 bus-range = <0x00 0xff>;
1524 num-lanes = <1>;
1526 #address-cells = <3>;
1527 #size-cells = <2>;
1540 interrupt-names = "msi0",
1548 #interrupt-cells = <1>;
1549 interrupt-map-mask = <0 0 0 0x7>;
1550 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1555 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1564 clock-names = "aux",
1574 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1578 reset-names = "pci";
1580 power-domains = <&gcc PCIE_0_GDSC>;
1583 phy-names = "pciephy";
1590 bus-range = <0x01 0xff>;
1592 #address-cells = <3>;
1593 #size-cells = <2>;
1599 compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy";
1601 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1606 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
1609 reset-names = "phy";
1611 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>;
1612 assigned-clock-rates = <100000000>;
1614 #clock-cells = <0>;
1615 clock-output-names = "pcie_0_pipe_clk";
1617 #phy-cells = <0>;
1623 compatible = "qcom,pcie-sm8350";
1629 reg-names = "parf", "dbi", "elbi", "atu", "config";
1631 linux,pci-domain = <1>;
1632 bus-range = <0x00 0xff>;
1633 num-lanes = <2>;
1635 #address-cells = <3>;
1636 #size-cells = <2>;
1649 interrupt-names = "msi0",
1657 #interrupt-cells = <1>;
1658 interrupt-map-mask = <0 0 0 0x7>;
1659 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1664 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
1672 clock-names = "aux",
1681 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1685 reset-names = "pci";
1687 power-domains = <&gcc PCIE_1_GDSC>;
1690 phy-names = "pciephy";
1697 bus-range = <0x01 0xff>;
1699 #address-cells = <3>;
1700 #size-cells = <2>;
1706 compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy";
1708 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
1713 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
1716 reset-names = "phy";
1718 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
1719 assigned-clock-rates = <100000000>;
1721 #clock-cells = <0>;
1722 clock-output-names = "pcie_1_pipe_clk";
1724 #phy-cells = <0>;
1730 compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
1731 "jedec,ufs-2.0";
1735 phy-names = "ufsphy";
1736 lanes-per-direction = <2>;
1737 #reset-cells = <1>;
1739 reset-names = "rst";
1741 power-domains = <&gcc UFS_PHY_GDSC>;
1744 dma-coherent;
1746 clock-names =
1755 clocks =
1768 interconnect-names = "ufs-ddr", "cpu-ufs";
1769 freq-table-hz =
1782 compatible = "qcom,sm8350-qmp-ufs-phy";
1785 clocks = <&rpmhcc RPMH_CXO_CLK>,
1788 clock-names = "ref",
1792 power-domains = <&gcc UFS_PHY_GDSC>;
1795 reset-names = "ufsphy";
1797 #clock-cells = <1>;
1798 #phy-cells = <0>;
1803 cryptobam: dma-controller@1dc4000 {
1804 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
1807 #dma-cells = <1>;
1809 qcom,controlled-remotely;
1817 compatible = "qcom,sm8350-qce", "qcom,sm8150-qce", "qcom,qce";
1820 dma-names = "rx", "tx";
1824 interconnect-names = "memory";
1830 compatible = "qcom,sm8350-ipa";
1837 reg-names = "ipa-reg",
1838 "ipa-shared",
1841 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>,
1845 interrupt-names = "ipa",
1847 "ipa-clock-query",
1848 "ipa-setup-ready";
1850 clocks = <&rpmhcc RPMH_IPA_CLK>;
1851 clock-names = "core";
1855 interconnect-names = "memory",
1860 qcom,smem-states = <&ipa_smp2p_out 0>,
1862 qcom,smem-state-names = "ipa-clock-enabled-valid",
1863 "ipa-clock-enabled";
1869 compatible = "qcom,tcsr-mutex";
1871 #hwlock-cells = <1>;
1875 compatible = "qcom,sm8350-tcsr", "syscon";
1880 compatible = "qcom,sm8350-lpass-lpi-pinctrl";
1884 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1886 clock-names = "core", "audio";
1888 gpio-controller;
1889 #gpio-cells = <2>;
1890 gpio-ranges = <&lpass_tlmm 0 0 15>;
1894 compatible = "qcom,adreno-660.1", "qcom,adreno";
1899 reg-names = "kgsl_3d0_reg_memory",
1907 operating-points-v2 = <&gpu_opp_table>;
1910 #cooling-cells = <2>;
1914 zap-shader {
1915 memory-region = <&pil_gpu_mem>;
1919 gpu_opp_table: opp-table {
1920 compatible = "operating-points-v2";
1922 opp-840000000 {
1923 opp-hz = /bits/ 64 <840000000>;
1924 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1927 opp-778000000 {
1928 opp-hz = /bits/ 64 <778000000>;
1929 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1932 opp-738000000 {
1933 opp-hz = /bits/ 64 <738000000>;
1934 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1937 opp-676000000 {
1938 opp-hz = /bits/ 64 <676000000>;
1939 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1942 opp-608000000 {
1943 opp-hz = /bits/ 64 <608000000>;
1944 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1947 opp-540000000 {
1948 opp-hz = /bits/ 64 <540000000>;
1949 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1952 opp-491000000 {
1953 opp-hz = /bits/ 64 <491000000>;
1954 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
1957 opp-443000000 {
1958 opp-hz = /bits/ 64 <443000000>;
1959 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1962 opp-379000000 {
1963 opp-hz = /bits/ 64 <379000000>;
1964 opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>;
1967 opp-315000000 {
1968 opp-hz = /bits/ 64 <315000000>;
1969 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1975 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu";
1980 reg-names = "gmu", "rscc", "gmu_pdc";
1984 interrupt-names = "hfi", "gmu";
1986 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
1993 clock-names = "gmu",
2001 power-domains = <&gpucc GPU_CX_GDSC>,
2003 power-domain-names = "cx",
2008 operating-points-v2 = <&gmu_opp_table>;
2010 gmu_opp_table: opp-table {
2011 compatible = "operating-points-v2";
2013 opp-200000000 {
2014 opp-hz = /bits/ 64 <200000000>;
2015 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2020 gpucc: clock-controller@3d90000 {
2021 compatible = "qcom,sm8350-gpucc";
2023 clocks = <&rpmhcc RPMH_CXO_CLK>,
2026 clock-names = "bi_tcxo",
2029 #clock-cells = <1>;
2030 #reset-cells = <1>;
2031 #power-domain-cells = <1>;
2035 compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu",
2036 "qcom,smmu-500", "arm,mmu-500";
2038 #iommu-cells = <2>;
2039 #global-interrupts = <2>;
2053 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2060 clock-names = "bus",
2068 power-domains = <&gpucc GPU_CX_GDSC>;
2069 dma-coherent;
2073 compatible = "qcom,sm8350-lpass-ag-noc";
2075 #interconnect-cells = <2>;
2076 qcom,bcm-voters = <&apps_bcm_voter>;
2080 compatible = "qcom,sm8350-mpss-pas";
2083 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2089 interrupt-names = "wdog", "fatal", "ready", "handover",
2090 "stop-ack", "shutdown-ack";
2092 clocks = <&rpmhcc RPMH_CXO_CLK>;
2093 clock-names = "xo";
2095 power-domains = <&rpmhpd RPMHPD_CX>,
2097 power-domain-names = "cx", "mss";
2101 memory-region = <&pil_modem_mem>;
2105 qcom,smem-states = <&smp2p_modem_out 0>;
2106 qcom,smem-state-names = "stop";
2110 glink-edge {
2111 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2117 qcom,remote-pid = <1>;
2122 compatible = "qcom,sm8350-slpi-pas";
2125 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2130 interrupt-names = "wdog", "fatal", "ready",
2131 "handover", "stop-ack";
2133 clocks = <&rpmhcc RPMH_CXO_CLK>;
2134 clock-names = "xo";
2136 power-domains = <&rpmhpd RPMHPD_LCX>,
2138 power-domain-names = "lcx", "lmx";
2140 memory-region = <&pil_slpi_mem>;
2144 qcom,smem-states = <&smp2p_slpi_out 0>;
2145 qcom,smem-state-names = "stop";
2149 glink-edge {
2150 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2157 qcom,remote-pid = <3>;
2161 qcom,glink-channels = "fastrpcglink-apps-dsp";
2163 qcom,non-secure-domain;
2164 #address-cells = <1>;
2165 #size-cells = <0>;
2167 compute-cb@1 {
2168 compatible = "qcom,fastrpc-compute-cb";
2173 compute-cb@2 {
2174 compatible = "qcom,fastrpc-compute-cb";
2179 compute-cb@3 {
2180 compatible = "qcom,fastrpc-compute-cb";
2183 /* note: shared-cb = <4> in downstream */
2190 compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5";
2195 interrupt-names = "hc_irq", "pwr_irq";
2197 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2200 clock-names = "iface", "core", "xo";
2204 interconnect-names = "sdhc-ddr","cpu-sdhc";
2206 power-domains = <&rpmhpd RPMHPD_CX>;
2207 operating-points-v2 = <&sdhc2_opp_table>;
2208 bus-width = <4>;
2209 dma-coherent;
2213 sdhc2_opp_table: opp-table {
2214 compatible = "operating-points-v2";
2216 opp-100000000 {
2217 opp-hz = /bits/ 64 <100000000>;
2218 required-opps = <&rpmhpd_opp_low_svs>;
2221 opp-202000000 {
2222 opp-hz = /bits/ 64 <202000000>;
2223 required-opps = <&rpmhpd_opp_svs_l1>;
2229 compatible = "qcom,sm8350-usb-hs-phy",
2230 "qcom,usb-snps-hs-7nm-phy";
2233 #phy-cells = <0>;
2235 clocks = <&rpmhcc RPMH_CXO_CLK>;
2236 clock-names = "ref";
2242 compatible = "qcom,sm8250-usb-hs-phy",
2243 "qcom,usb-snps-hs-7nm-phy";
2246 #phy-cells = <0>;
2248 clocks = <&rpmhcc RPMH_CXO_CLK>;
2249 clock-names = "ref";
2255 compatible = "qcom,sm8350-refgen-regulator",
2256 "qcom,sm8250-refgen-regulator";
2261 compatible = "qcom,sm8350-qmp-usb3-dp-phy";
2264 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2268 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2272 reset-names = "phy", "common";
2274 #clock-cells = <1>;
2275 #phy-cells = <1>;
2277 orientation-switch;
2282 #address-cells = <1>;
2283 #size-cells = <0>;
2296 remote-endpoint = <&usb_1_dwc3_ss>;
2304 remote-endpoint = <&mdss_dp_out>;
2311 compatible = "qcom,sm8350-qmp-usb3-uni-phy";
2315 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2319 clock-names = "aux",
2323 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2324 #clock-cells = <0>;
2325 #phy-cells = <0>;
2329 reset-names = "phy",
2334 compatible = "qcom,sm8350-dc-noc";
2336 #interconnect-cells = <2>;
2337 qcom,bcm-voters = <&apps_bcm_voter>;
2341 compatible = "qcom,sm8350-gem-noc";
2343 #interconnect-cells = <2>;
2344 qcom,bcm-voters = <&apps_bcm_voter>;
2347 system-cache-controller@9200000 {
2348 compatible = "qcom,sm8350-llcc";
2352 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2357 compatible = "qcom,sm8350-compute-noc";
2359 #interconnect-cells = <2>;
2360 qcom,bcm-voters = <&apps_bcm_voter>;
2364 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2367 #address-cells = <2>;
2368 #size-cells = <2>;
2371 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2376 clock-names = "cfg_noc",
2382 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2384 assigned-clock-rates = <19200000>, <200000000>;
2386 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
2391 interrupt-names = "pwr_event",
2397 power-domains = <&gcc USB30_PRIM_GDSC>;
2403 interconnect-names = "usb-ddr", "apps-usb";
2413 phy-names = "usb2-phy", "usb3-phy";
2416 #address-cells = <1>;
2417 #size-cells = <0>;
2430 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
2438 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2441 #address-cells = <2>;
2442 #size-cells = <2>;
2445 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2451 clock-names = "cfg_noc",
2458 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2460 assigned-clock-rates = <19200000>, <200000000>;
2462 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
2467 interrupt-names = "pwr_event",
2473 power-domains = <&gcc USB30_SEC_GDSC>;
2479 interconnect-names = "usb-ddr", "apps-usb";
2489 phy-names = "usb2-phy", "usb3-phy";
2493 mdss: display-subsystem@ae00000 {
2494 compatible = "qcom,sm8350-mdss";
2496 reg-names = "mdss";
2502 interconnect-names = "mdp0-mem",
2503 "mdp1-mem",
2504 "cpu-cfg";
2506 power-domains = <&dispcc MDSS_GDSC>;
2509 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2513 clock-names = "iface", "bus", "nrt_bus", "core";
2516 interrupt-controller;
2517 #interrupt-cells = <1>;
2523 #address-cells = <2>;
2524 #size-cells = <2>;
2527 mdss_mdp: display-controller@ae01000 {
2528 compatible = "qcom,sm8350-dpu";
2531 reg-names = "mdp", "vbif";
2533 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
2539 clock-names = "bus",
2546 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2547 assigned-clock-rates = <19200000>;
2549 operating-points-v2 = <&dpu_opp_table>;
2550 power-domains = <&rpmhpd RPMHPD_MMCX>;
2552 interrupt-parent = <&mdss>;
2555 dpu_opp_table: opp-table {
2556 compatible = "operating-points-v2";
2558 /* TODO: opp-200000000 should work with
2563 opp-200000000 {
2564 opp-hz = /bits/ 64 <200000000>;
2565 required-opps = <&rpmhpd_opp_svs>;
2568 opp-300000000 {
2569 opp-hz = /bits/ 64 <300000000>;
2570 required-opps = <&rpmhpd_opp_svs>;
2573 opp-345000000 {
2574 opp-hz = /bits/ 64 <345000000>;
2575 required-opps = <&rpmhpd_opp_svs_l1>;
2578 opp-460000000 {
2579 opp-hz = /bits/ 64 <460000000>;
2580 required-opps = <&rpmhpd_opp_nom>;
2585 #address-cells = <1>;
2586 #size-cells = <0>;
2591 remote-endpoint = <&mdss_dsi0_in>;
2598 remote-endpoint = <&mdss_dsi1_in>;
2605 remote-endpoint = <&mdss_dp_in>;
2611 mdss_dp: displayport-controller@ae90000 {
2612 compatible = "qcom,sm8350-dp";
2618 interrupt-parent = <&mdss>;
2620 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2625 clock-names = "core_iface",
2631 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
2633 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2637 phy-names = "dp";
2639 #sound-dai-cells = <0>;
2641 operating-points-v2 = <&dp_opp_table>;
2642 power-domains = <&rpmhpd RPMHPD_MMCX>;
2647 #address-cells = <1>;
2648 #size-cells = <0>;
2653 remote-endpoint = <&dpu_intf0_out>;
2661 remote-endpoint = <&usb_1_qmpphy_dp_in>;
2666 dp_opp_table: opp-table {
2667 compatible = "operating-points-v2";
2669 opp-160000000 {
2670 opp-hz = /bits/ 64 <160000000>;
2671 required-opps = <&rpmhpd_opp_low_svs>;
2674 opp-270000000 {
2675 opp-hz = /bits/ 64 <270000000>;
2676 required-opps = <&rpmhpd_opp_svs>;
2679 opp-540000000 {
2680 opp-hz = /bits/ 64 <540000000>;
2681 required-opps = <&rpmhpd_opp_svs_l1>;
2684 opp-810000000 {
2685 opp-hz = /bits/ 64 <810000000>;
2686 required-opps = <&rpmhpd_opp_nom>;
2692 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2694 reg-names = "dsi_ctrl";
2696 interrupt-parent = <&mdss>;
2699 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2705 clock-names = "byte",
2712 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2714 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2717 operating-points-v2 = <&dsi0_opp_table>;
2718 power-domains = <&rpmhpd RPMHPD_MMCX>;
2719 refgen-supply = <&refgen>;
2723 #address-cells = <1>;
2724 #size-cells = <0>;
2728 dsi0_opp_table: opp-table {
2729 compatible = "operating-points-v2";
2731 /* TODO: opp-187500000 should work with
2736 opp-187500000 {
2737 opp-hz = /bits/ 64 <187500000>;
2738 required-opps = <&rpmhpd_opp_svs>;
2741 opp-300000000 {
2742 opp-hz = /bits/ 64 <300000000>;
2743 required-opps = <&rpmhpd_opp_svs>;
2746 opp-358000000 {
2747 opp-hz = /bits/ 64 <358000000>;
2748 required-opps = <&rpmhpd_opp_svs_l1>;
2753 #address-cells = <1>;
2754 #size-cells = <0>;
2759 remote-endpoint = <&dpu_intf1_out>;
2772 compatible = "qcom,sm8350-dsi-phy-5nm";
2776 reg-names = "dsi_phy",
2780 #clock-cells = <1>;
2781 #phy-cells = <0>;
2783 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2785 clock-names = "iface", "ref";
2791 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2793 reg-names = "dsi_ctrl";
2795 interrupt-parent = <&mdss>;
2798 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
2804 clock-names = "byte",
2811 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
2813 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2816 operating-points-v2 = <&dsi1_opp_table>;
2817 power-domains = <&rpmhpd RPMHPD_MMCX>;
2818 refgen-supply = <&refgen>;
2822 #address-cells = <1>;
2823 #size-cells = <0>;
2827 dsi1_opp_table: opp-table {
2828 compatible = "operating-points-v2";
2830 /* TODO: opp-187500000 should work with
2835 opp-187500000 {
2836 opp-hz = /bits/ 64 <187500000>;
2837 required-opps = <&rpmhpd_opp_svs>;
2840 opp-300000000 {
2841 opp-hz = /bits/ 64 <300000000>;
2842 required-opps = <&rpmhpd_opp_svs>;
2845 opp-358000000 {
2846 opp-hz = /bits/ 64 <358000000>;
2847 required-opps = <&rpmhpd_opp_svs_l1>;
2852 #address-cells = <1>;
2853 #size-cells = <0>;
2858 remote-endpoint = <&dpu_intf2_out>;
2871 compatible = "qcom,sm8350-dsi-phy-5nm";
2875 reg-names = "dsi_phy",
2879 #clock-cells = <1>;
2880 #phy-cells = <0>;
2882 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2884 clock-names = "iface", "ref";
2890 dispcc: clock-controller@af00000 {
2891 compatible = "qcom,sm8350-dispcc";
2893 clocks = <&rpmhcc RPMH_CXO_CLK>,
2898 clock-names = "bi_tcxo",
2905 #clock-cells = <1>;
2906 #reset-cells = <1>;
2907 #power-domain-cells = <1>;
2909 power-domains = <&rpmhpd RPMHPD_MMCX>;
2912 pdc: interrupt-controller@b220000 {
2913 compatible = "qcom,sm8350-pdc", "qcom,pdc";
2915 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
2919 #interrupt-cells = <2>;
2920 interrupt-parent = <&intc>;
2921 interrupt-controller;
2924 tsens0: thermal-sensor@c263000 {
2925 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
2929 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
2931 interrupt-names = "uplow", "critical";
2932 #thermal-sensor-cells = <1>;
2935 tsens1: thermal-sensor@c265000 {
2936 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
2940 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
2942 interrupt-names = "uplow", "critical";
2943 #thermal-sensor-cells = <1>;
2946 aoss_qmp: power-management@c300000 {
2947 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp";
2949 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
2953 #clock-cells = <0>;
2957 compatible = "qcom,rpmh-stats";
2962 compatible = "qcom,spmi-pmic-arb";
2968 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2969 interrupt-names = "periph_irq";
2970 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2973 #address-cells = <2>;
2974 #size-cells = <0>;
2975 interrupt-controller;
2976 #interrupt-cells = <4>;
2980 compatible = "qcom,sm8350-tlmm";
2983 gpio-controller;
2984 #gpio-cells = <2>;
2985 interrupt-controller;
2986 #interrupt-cells = <2>;
2987 gpio-ranges = <&tlmm 0 0 204>;
2988 wakeup-parent = <&pdc>;
2990 sdc2_default_state: sdc2-default-state {
2991 clk-pins {
2993 drive-strength = <16>;
2994 bias-disable;
2997 cmd-pins {
2999 drive-strength = <16>;
3000 bias-pull-up;
3003 data-pins {
3005 drive-strength = <16>;
3006 bias-pull-up;
3010 sdc2_sleep_state: sdc2-sleep-state {
3011 clk-pins {
3013 drive-strength = <2>;
3014 bias-disable;
3017 cmd-pins {
3019 drive-strength = <2>;
3020 bias-pull-up;
3023 data-pins {
3025 drive-strength = <2>;
3026 bias-pull-up;
3030 qup_uart3_default_state: qup-uart3-default-state {
3031 rx-pins {
3035 tx-pins {
3041 qup_uart6_default: qup-uart6-default-state {
3044 drive-strength = <2>;
3045 bias-disable;
3048 qup_uart18_default: qup-uart18-default-state {
3051 drive-strength = <2>;
3052 bias-disable;
3055 qup_i2c0_default: qup-i2c0-default-state {
3058 drive-strength = <2>;
3059 bias-pull-up;
3062 qup_i2c1_default: qup-i2c1-default-state {
3065 drive-strength = <2>;
3066 bias-pull-up;
3069 qup_i2c2_default: qup-i2c2-default-state {
3072 drive-strength = <2>;
3073 bias-pull-up;
3076 qup_i2c4_default: qup-i2c4-default-state {
3079 drive-strength = <2>;
3080 bias-pull-up;
3083 qup_i2c5_default: qup-i2c5-default-state {
3086 drive-strength = <2>;
3087 bias-pull-up;
3090 qup_i2c6_default: qup-i2c6-default-state {
3093 drive-strength = <2>;
3094 bias-pull-up;
3097 qup_i2c7_default: qup-i2c7-default-state {
3100 drive-strength = <2>;
3101 bias-disable;
3104 qup_i2c8_default: qup-i2c8-default-state {
3107 drive-strength = <2>;
3108 bias-pull-up;
3111 qup_i2c9_default: qup-i2c9-default-state {
3114 drive-strength = <2>;
3115 bias-pull-up;
3118 qup_i2c10_default: qup-i2c10-default-state {
3121 drive-strength = <2>;
3122 bias-pull-up;
3125 qup_i2c11_default: qup-i2c11-default-state {
3128 drive-strength = <2>;
3129 bias-pull-up;
3132 qup_i2c12_default: qup-i2c12-default-state {
3135 drive-strength = <2>;
3136 bias-pull-up;
3139 qup_i2c13_default: qup-i2c13-default-state {
3142 drive-strength = <2>;
3143 bias-pull-up;
3146 qup_i2c14_default: qup-i2c14-default-state {
3149 drive-strength = <2>;
3150 bias-disable;
3153 qup_i2c15_default: qup-i2c15-default-state {
3156 drive-strength = <2>;
3157 bias-disable;
3160 qup_i2c16_default: qup-i2c16-default-state {
3163 drive-strength = <2>;
3164 bias-disable;
3167 qup_i2c17_default: qup-i2c17-default-state {
3170 drive-strength = <2>;
3171 bias-disable;
3174 qup_i2c19_default: qup-i2c19-default-state {
3177 drive-strength = <2>;
3178 bias-disable;
3183 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500";
3185 #iommu-cells = <2>;
3186 #global-interrupts = <2>;
3288 compatible = "qcom,sm8350-adsp-pas";
3291 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
3296 interrupt-names = "wdog", "fatal", "ready",
3297 "handover", "stop-ack";
3299 clocks = <&rpmhcc RPMH_CXO_CLK>;
3300 clock-names = "xo";
3302 power-domains = <&rpmhpd RPMHPD_LCX>,
3304 power-domain-names = "lcx", "lmx";
3306 memory-region = <&pil_adsp_mem>;
3310 qcom,smem-states = <&smp2p_adsp_out 0>;
3311 qcom,smem-state-names = "stop";
3315 glink-edge {
3316 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
3323 qcom,remote-pid = <2>;
3326 compatible = "qcom,apr-v2";
3327 qcom,glink-channels = "apr_audio_svc";
3329 #address-cells = <1>;
3330 #size-cells = <0>;
3335 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3338 q6afe: service@4 { label
3339 compatible = "qcom,q6afe";
3341 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3344 compatible = "qcom,q6afe-dais";
3345 #address-cells = <1>;
3346 #size-cells = <0>;
3347 #sound-dai-cells = <1>;
3350 q6afecc: clock-controller {
3351 compatible = "qcom,q6afe-clocks";
3352 #clock-cells = <2>;
3359 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3362 compatible = "qcom,q6asm-dais";
3363 #address-cells = <1>;
3364 #size-cells = <0>;
3365 #sound-dai-cells = <1>;
3385 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3388 compatible = "qcom,q6adm-routing";
3389 #sound-dai-cells = <0>;
3396 qcom,glink-channels = "fastrpcglink-apps-dsp";
3398 qcom,non-secure-domain;
3399 #address-cells = <1>;
3400 #size-cells = <0>;
3402 compute-cb@3 {
3403 compatible = "qcom,fastrpc-compute-cb";
3408 compute-cb@4 {
3409 compatible = "qcom,fastrpc-compute-cb";
3414 compute-cb@5 {
3415 compatible = "qcom,fastrpc-compute-cb";
3423 intc: interrupt-controller@17a00000 {
3424 compatible = "arm,gic-v3";
3425 #interrupt-cells = <3>;
3426 interrupt-controller;
3427 #redistributor-regions = <1>;
3428 redistributor-stride = <0 0x20000>;
3435 compatible = "arm,armv7-timer-mem";
3436 #address-cells = <1>;
3437 #size-cells = <1>;
3440 clock-frequency = <19200000>;
3443 frame-number = <0>;
3451 frame-number = <1>;
3458 frame-number = <2>;
3465 frame-number = <3>;
3472 frame-number = <4>;
3479 frame-number = <5>;
3486 frame-number = <6>;
3495 compatible = "qcom,rpmh-rsc";
3499 reg-names = "drv-0", "drv-1", "drv-2";
3503 qcom,tcs-offset = <0xd00>;
3504 qcom,drv-id = <2>;
3505 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
3507 power-domains = <&CLUSTER_PD>;
3509 rpmhcc: clock-controller {
3510 compatible = "qcom,sm8350-rpmh-clk";
3511 #clock-cells = <1>;
3512 clock-names = "xo";
3513 clocks = <&xo_board>;
3516 rpmhpd: power-controller {
3517 compatible = "qcom,sm8350-rpmhpd";
3518 #power-domain-cells = <1>;
3519 operating-points-v2 = <&rpmhpd_opp_table>;
3521 rpmhpd_opp_table: opp-table {
3522 compatible = "operating-points-v2";
3525 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3529 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3533 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3537 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3541 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3545 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3549 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3553 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3557 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3561 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3566 apps_bcm_voter: bcm-voter {
3567 compatible = "qcom,bcm-voter";
3572 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
3576 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
3581 interrupt-names = "dcvsh-irq-0",
3582 "dcvsh-irq-1",
3583 "dcvsh-irq-2";
3585 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
3586 clock-names = "xo", "alternate";
3588 #freq-domain-cells = <1>;
3589 #clock-cells = <1>;
3593 compatible = "qcom,sm8350-cdsp-pas";
3596 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3601 interrupt-names = "wdog", "fatal", "ready",
3602 "handover", "stop-ack";
3604 clocks = <&rpmhcc RPMH_CXO_CLK>;
3605 clock-names = "xo";
3607 power-domains = <&rpmhpd RPMHPD_CX>,
3609 power-domain-names = "cx", "mxc";
3613 memory-region = <&pil_cdsp_mem>;
3617 qcom,smem-states = <&smp2p_cdsp_out 0>;
3618 qcom,smem-state-names = "stop";
3622 glink-edge {
3623 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3630 qcom,remote-pid = <5>;
3634 qcom,glink-channels = "fastrpcglink-apps-dsp";
3636 qcom,non-secure-domain;
3637 #address-cells = <1>;
3638 #size-cells = <0>;
3640 compute-cb@1 {
3641 compatible = "qcom,fastrpc-compute-cb";
3647 compute-cb@2 {
3648 compatible = "qcom,fastrpc-compute-cb";
3654 compute-cb@3 {
3655 compatible = "qcom,fastrpc-compute-cb";
3661 compute-cb@4 {
3662 compatible = "qcom,fastrpc-compute-cb";
3668 compute-cb@5 {
3669 compatible = "qcom,fastrpc-compute-cb";
3675 compute-cb@6 {
3676 compatible = "qcom,fastrpc-compute-cb";
3682 compute-cb@7 {
3683 compatible = "qcom,fastrpc-compute-cb";
3689 compute-cb@8 {
3690 compatible = "qcom,fastrpc-compute-cb";
3702 thermal_zones: thermal-zones {
3703 cpu0-thermal {
3704 polling-delay-passive = <250>;
3706 thermal-sensors = <&tsens0 1>;
3709 cpu0_alert0: trip-point0 {
3715 cpu0_alert1: trip-point1 {
3721 cpu0_crit: cpu-crit {
3728 cooling-maps {
3731 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3738 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3746 cpu1-thermal {
3747 polling-delay-passive = <250>;
3749 thermal-sensors = <&tsens0 2>;
3752 cpu1_alert0: trip-point0 {
3758 cpu1_alert1: trip-point1 {
3764 cpu1_crit: cpu-crit {
3771 cooling-maps {
3774 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3781 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3789 cpu2-thermal {
3790 polling-delay-passive = <250>;
3792 thermal-sensors = <&tsens0 3>;
3795 cpu2_alert0: trip-point0 {
3801 cpu2_alert1: trip-point1 {
3807 cpu2_crit: cpu-crit {
3814 cooling-maps {
3817 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3824 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3832 cpu3-thermal {
3833 polling-delay-passive = <250>;
3835 thermal-sensors = <&tsens0 4>;
3838 cpu3_alert0: trip-point0 {
3844 cpu3_alert1: trip-point1 {
3850 cpu3_crit: cpu-crit {
3857 cooling-maps {
3860 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3867 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3875 cpu4-top-thermal {
3876 polling-delay-passive = <250>;
3878 thermal-sensors = <&tsens0 7>;
3881 cpu4_top_alert0: trip-point0 {
3887 cpu4_top_alert1: trip-point1 {
3893 cpu4_top_crit: cpu-crit {
3900 cooling-maps {
3903 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3910 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3918 cpu5-top-thermal {
3919 polling-delay-passive = <250>;
3921 thermal-sensors = <&tsens0 8>;
3924 cpu5_top_alert0: trip-point0 {
3930 cpu5_top_alert1: trip-point1 {
3936 cpu5_top_crit: cpu-crit {
3943 cooling-maps {
3946 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3953 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3961 cpu6-top-thermal {
3962 polling-delay-passive = <250>;
3964 thermal-sensors = <&tsens0 9>;
3967 cpu6_top_alert0: trip-point0 {
3973 cpu6_top_alert1: trip-point1 {
3979 cpu6_top_crit: cpu-crit {
3986 cooling-maps {
3989 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3996 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4004 cpu7-top-thermal {
4005 polling-delay-passive = <250>;
4007 thermal-sensors = <&tsens0 10>;
4010 cpu7_top_alert0: trip-point0 {
4016 cpu7_top_alert1: trip-point1 {
4022 cpu7_top_crit: cpu-crit {
4029 cooling-maps {
4032 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4039 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4047 cpu4-bottom-thermal {
4048 polling-delay-passive = <250>;
4050 thermal-sensors = <&tsens0 11>;
4053 cpu4_bottom_alert0: trip-point0 {
4059 cpu4_bottom_alert1: trip-point1 {
4065 cpu4_bottom_crit: cpu-crit {
4072 cooling-maps {
4075 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4082 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4090 cpu5-bottom-thermal {
4091 polling-delay-passive = <250>;
4093 thermal-sensors = <&tsens0 12>;
4096 cpu5_bottom_alert0: trip-point0 {
4102 cpu5_bottom_alert1: trip-point1 {
4108 cpu5_bottom_crit: cpu-crit {
4115 cooling-maps {
4118 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4125 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4133 cpu6-bottom-thermal {
4134 polling-delay-passive = <250>;
4136 thermal-sensors = <&tsens0 13>;
4139 cpu6_bottom_alert0: trip-point0 {
4145 cpu6_bottom_alert1: trip-point1 {
4151 cpu6_bottom_crit: cpu-crit {
4158 cooling-maps {
4161 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4168 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4176 cpu7-bottom-thermal {
4177 polling-delay-passive = <250>;
4179 thermal-sensors = <&tsens0 14>;
4182 cpu7_bottom_alert0: trip-point0 {
4188 cpu7_bottom_alert1: trip-point1 {
4194 cpu7_bottom_crit: cpu-crit {
4201 cooling-maps {
4204 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4211 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4219 aoss0-thermal {
4220 polling-delay-passive = <250>;
4222 thermal-sensors = <&tsens0 0>;
4225 aoss0_alert0: trip-point0 {
4233 cluster0-thermal {
4234 polling-delay-passive = <250>;
4236 thermal-sensors = <&tsens0 5>;
4239 cluster0_alert0: trip-point0 {
4244 cluster0_crit: cluster0-crit {
4252 cluster1-thermal {
4253 polling-delay-passive = <250>;
4255 thermal-sensors = <&tsens0 6>;
4258 cluster1_alert0: trip-point0 {
4263 cluster1_crit: cluster1-crit {
4271 aoss1-thermal {
4272 polling-delay-passive = <250>;
4274 thermal-sensors = <&tsens1 0>;
4277 aoss1_alert0: trip-point0 {
4285 gpu-top-thermal {
4286 polling-delay-passive = <250>;
4288 thermal-sensors = <&tsens1 1>;
4290 cooling-maps {
4293 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4298 gpu_top_alert0: trip-point0 {
4304 trip-point1 {
4310 trip-point2 {
4318 gpu-bottom-thermal {
4319 polling-delay-passive = <250>;
4321 thermal-sensors = <&tsens1 2>;
4323 cooling-maps {
4326 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4331 gpu_bottom_alert0: trip-point0 {
4337 trip-point1 {
4343 trip-point2 {
4351 nspss1-thermal {
4352 polling-delay-passive = <250>;
4354 thermal-sensors = <&tsens1 3>;
4357 nspss1_alert0: trip-point0 {
4365 nspss2-thermal {
4366 polling-delay-passive = <250>;
4368 thermal-sensors = <&tsens1 4>;
4371 nspss2_alert0: trip-point0 {
4379 nspss3-thermal {
4380 polling-delay-passive = <250>;
4382 thermal-sensors = <&tsens1 5>;
4385 nspss3_alert0: trip-point0 {
4393 video-thermal {
4394 polling-delay-passive = <250>;
4396 thermal-sensors = <&tsens1 6>;
4399 video_alert0: trip-point0 {
4407 mem-thermal {
4408 polling-delay-passive = <250>;
4410 thermal-sensors = <&tsens1 7>;
4413 mem_alert0: trip-point0 {
4421 modem1-top-thermal {
4422 polling-delay-passive = <250>;
4424 thermal-sensors = <&tsens1 8>;
4427 modem1_alert0: trip-point0 {
4435 modem2-top-thermal {
4436 polling-delay-passive = <250>;
4438 thermal-sensors = <&tsens1 9>;
4441 modem2_alert0: trip-point0 {
4449 modem3-top-thermal {
4450 polling-delay-passive = <250>;
4452 thermal-sensors = <&tsens1 10>;
4455 modem3_alert0: trip-point0 {
4463 modem4-top-thermal {
4464 polling-delay-passive = <250>;
4466 thermal-sensors = <&tsens1 11>;
4469 modem4_alert0: trip-point0 {
4477 camera-top-thermal {
4478 polling-delay-passive = <250>;
4480 thermal-sensors = <&tsens1 12>;
4483 camera1_alert0: trip-point0 {
4491 cam-bottom-thermal {
4492 polling-delay-passive = <250>;
4494 thermal-sensors = <&tsens1 13>;
4497 camera2_alert0: trip-point0 {
4507 compatible = "arm,armv8-timer";