Lines Matching +full:pdc +full:- +full:intc
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interconnect/qcom,sm8350.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
9 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
10 #include <dt-bindings/clock/qcom,gcc-sm8350.h>
11 #include <dt-bindings/clock/qcom,gpucc-sm8350.h>
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/interconnect/qcom,icc.h>
17 #include <dt-bindings/interconnect/qcom,sm8350.h>
18 #include <dt-bindings/mailbox/qcom-ipcc.h>
19 #include <dt-bindings/phy/phy-qcom-qmp.h>
20 #include <dt-bindings/power/qcom-rpmpd.h>
21 #include <dt-bindings/power/qcom,rpmhpd.h>
22 #include <dt-bindings/soc/qcom,apr.h>
23 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
24 #include <dt-bindings/sound/qcom,q6afe.h>
25 #include <dt-bindings/sound/qcom,q6asm.h>
26 #include <dt-bindings/thermal/thermal.h>
27 #include <dt-bindings/interconnect/qcom,sm8350.h>
30 interrupt-parent = <&intc>;
32 #address-cells = <2>;
33 #size-cells = <2>;
38 xo_board: xo-board {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 clock-frequency = <38400000>;
42 clock-output-names = "xo_board";
45 sleep_clk: sleep-clk {
46 compatible = "fixed-clock";
47 clock-frequency = <32764>;
48 #clock-cells = <0>;
53 #address-cells = <2>;
54 #size-cells = <0>;
58 compatible = "arm,cortex-a55";
61 enable-method = "psci";
62 next-level-cache = <&l2_0>;
63 qcom,freq-domain = <&cpufreq_hw 0>;
64 power-domains = <&cpu_pd0>;
65 power-domain-names = "psci";
66 #cooling-cells = <2>;
67 l2_0: l2-cache {
69 cache-level = <2>;
70 cache-unified;
71 next-level-cache = <&l3_0>;
72 l3_0: l3-cache {
74 cache-level = <3>;
75 cache-unified;
82 compatible = "arm,cortex-a55";
85 enable-method = "psci";
86 next-level-cache = <&l2_100>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
88 power-domains = <&cpu_pd1>;
89 power-domain-names = "psci";
90 #cooling-cells = <2>;
91 l2_100: l2-cache {
93 cache-level = <2>;
94 cache-unified;
95 next-level-cache = <&l3_0>;
101 compatible = "arm,cortex-a55";
104 enable-method = "psci";
105 next-level-cache = <&l2_200>;
106 qcom,freq-domain = <&cpufreq_hw 0>;
107 power-domains = <&cpu_pd2>;
108 power-domain-names = "psci";
109 #cooling-cells = <2>;
110 l2_200: l2-cache {
112 cache-level = <2>;
113 cache-unified;
114 next-level-cache = <&l3_0>;
120 compatible = "arm,cortex-a55";
123 enable-method = "psci";
124 next-level-cache = <&l2_300>;
125 qcom,freq-domain = <&cpufreq_hw 0>;
126 power-domains = <&cpu_pd3>;
127 power-domain-names = "psci";
128 #cooling-cells = <2>;
129 l2_300: l2-cache {
131 cache-level = <2>;
132 cache-unified;
133 next-level-cache = <&l3_0>;
139 compatible = "arm,cortex-a78";
142 enable-method = "psci";
143 next-level-cache = <&l2_400>;
144 qcom,freq-domain = <&cpufreq_hw 1>;
145 power-domains = <&cpu_pd4>;
146 power-domain-names = "psci";
147 #cooling-cells = <2>;
148 l2_400: l2-cache {
150 cache-level = <2>;
151 cache-unified;
152 next-level-cache = <&l3_0>;
158 compatible = "arm,cortex-a78";
161 enable-method = "psci";
162 next-level-cache = <&l2_500>;
163 qcom,freq-domain = <&cpufreq_hw 1>;
164 power-domains = <&cpu_pd5>;
165 power-domain-names = "psci";
166 #cooling-cells = <2>;
167 l2_500: l2-cache {
169 cache-level = <2>;
170 cache-unified;
171 next-level-cache = <&l3_0>;
177 compatible = "arm,cortex-a78";
180 enable-method = "psci";
181 next-level-cache = <&l2_600>;
182 qcom,freq-domain = <&cpufreq_hw 1>;
183 power-domains = <&cpu_pd6>;
184 power-domain-names = "psci";
185 #cooling-cells = <2>;
186 l2_600: l2-cache {
188 cache-level = <2>;
189 cache-unified;
190 next-level-cache = <&l3_0>;
196 compatible = "arm,cortex-x1";
199 enable-method = "psci";
200 next-level-cache = <&l2_700>;
201 qcom,freq-domain = <&cpufreq_hw 2>;
202 power-domains = <&cpu_pd7>;
203 power-domain-names = "psci";
204 #cooling-cells = <2>;
205 l2_700: l2-cache {
207 cache-level = <2>;
208 cache-unified;
209 next-level-cache = <&l3_0>;
213 cpu-map {
249 idle-states {
250 entry-method = "psci";
252 little_cpu_sleep_0: cpu-sleep-0-0 {
253 compatible = "arm,idle-state";
254 idle-state-name = "silver-rail-power-collapse";
255 arm,psci-suspend-param = <0x40000004>;
256 entry-latency-us = <360>;
257 exit-latency-us = <531>;
258 min-residency-us = <3934>;
259 local-timer-stop;
262 big_cpu_sleep_0: cpu-sleep-1-0 {
263 compatible = "arm,idle-state";
264 idle-state-name = "gold-rail-power-collapse";
265 arm,psci-suspend-param = <0x40000004>;
266 entry-latency-us = <702>;
267 exit-latency-us = <1061>;
268 min-residency-us = <4488>;
269 local-timer-stop;
273 domain-idle-states {
274 cluster_sleep_apss_off: cluster-sleep-0 {
275 compatible = "domain-idle-state";
276 arm,psci-suspend-param = <0x41000044>;
277 entry-latency-us = <2752>;
278 exit-latency-us = <3048>;
279 min-residency-us = <6118>;
282 cluster_sleep_aoss_sleep: cluster-sleep-1 {
283 compatible = "domain-idle-state";
284 arm,psci-suspend-param = <0x4100c344>;
285 entry-latency-us = <3263>;
286 exit-latency-us = <6562>;
287 min-residency-us = <9987>;
294 compatible = "qcom,scm-sm8350", "qcom,scm";
295 qcom,dload-mode = <&tcsr 0x13000>;
296 #reset-cells = <1>;
306 pmu-a55 {
307 compatible = "arm,cortex-a55-pmu";
311 pmu-a78 {
312 compatible = "arm,cortex-a78-pmu";
316 pmu-x1 {
317 compatible = "arm,cortex-x1-pmu";
322 compatible = "arm,psci-1.0";
325 cpu_pd0: power-domain-cpu0 {
326 #power-domain-cells = <0>;
327 power-domains = <&cluster_pd>;
328 domain-idle-states = <&little_cpu_sleep_0>;
331 cpu_pd1: power-domain-cpu1 {
332 #power-domain-cells = <0>;
333 power-domains = <&cluster_pd>;
334 domain-idle-states = <&little_cpu_sleep_0>;
337 cpu_pd2: power-domain-cpu2 {
338 #power-domain-cells = <0>;
339 power-domains = <&cluster_pd>;
340 domain-idle-states = <&little_cpu_sleep_0>;
343 cpu_pd3: power-domain-cpu3 {
344 #power-domain-cells = <0>;
345 power-domains = <&cluster_pd>;
346 domain-idle-states = <&little_cpu_sleep_0>;
349 cpu_pd4: power-domain-cpu4 {
350 #power-domain-cells = <0>;
351 power-domains = <&cluster_pd>;
352 domain-idle-states = <&big_cpu_sleep_0>;
355 cpu_pd5: power-domain-cpu5 {
356 #power-domain-cells = <0>;
357 power-domains = <&cluster_pd>;
358 domain-idle-states = <&big_cpu_sleep_0>;
361 cpu_pd6: power-domain-cpu6 {
362 #power-domain-cells = <0>;
363 power-domains = <&cluster_pd>;
364 domain-idle-states = <&big_cpu_sleep_0>;
367 cpu_pd7: power-domain-cpu7 {
368 #power-domain-cells = <0>;
369 power-domains = <&cluster_pd>;
370 domain-idle-states = <&big_cpu_sleep_0>;
373 cluster_pd: power-domain-cpu-cluster0 {
374 #power-domain-cells = <0>;
375 domain-idle-states = <&cluster_sleep_apss_off &cluster_sleep_aoss_sleep>;
379 qup_opp_table_100mhz: opp-table-qup100mhz {
380 compatible = "operating-points-v2";
382 opp-50000000 {
383 opp-hz = /bits/ 64 <50000000>;
384 required-opps = <&rpmhpd_opp_min_svs>;
387 opp-75000000 {
388 opp-hz = /bits/ 64 <75000000>;
389 required-opps = <&rpmhpd_opp_low_svs>;
392 opp-100000000 {
393 opp-hz = /bits/ 64 <100000000>;
394 required-opps = <&rpmhpd_opp_svs>;
398 qup_opp_table_120mhz: opp-table-qup120mhz {
399 compatible = "operating-points-v2";
401 opp-50000000 {
402 opp-hz = /bits/ 64 <50000000>;
403 required-opps = <&rpmhpd_opp_min_svs>;
406 opp-75000000 {
407 opp-hz = /bits/ 64 <75000000>;
408 required-opps = <&rpmhpd_opp_low_svs>;
411 opp-120000000 {
412 opp-hz = /bits/ 64 <120000000>;
413 required-opps = <&rpmhpd_opp_svs>;
417 reserved_memory: reserved-memory {
418 #address-cells = <2>;
419 #size-cells = <2>;
424 no-map;
428 no-map;
433 compatible = "qcom,cmd-db";
435 no-map;
440 no-map;
447 no-map;
452 no-map;
457 no-map;
462 no-map;
467 no-map;
472 no-map;
477 no-map;
482 no-map;
487 no-map;
492 no-map;
497 no-map;
502 no-map;
507 no-map;
512 no-map;
516 compatible = "qcom,rmtfs-mem";
518 no-map;
520 qcom,client-id = <1>;
526 no-map;
531 no-map;
536 no-map;
541 no-map;
546 no-map;
551 no-map;
555 smp2p-adsp {
558 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
564 qcom,local-pid = <0>;
565 qcom,remote-pid = <2>;
567 smp2p_adsp_out: master-kernel {
568 qcom,entry-name = "master-kernel";
569 #qcom,smem-state-cells = <1>;
572 smp2p_adsp_in: slave-kernel {
573 qcom,entry-name = "slave-kernel";
574 interrupt-controller;
575 #interrupt-cells = <2>;
579 smp2p-cdsp {
582 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
588 qcom,local-pid = <0>;
589 qcom,remote-pid = <5>;
591 smp2p_cdsp_out: master-kernel {
592 qcom,entry-name = "master-kernel";
593 #qcom,smem-state-cells = <1>;
596 smp2p_cdsp_in: slave-kernel {
597 qcom,entry-name = "slave-kernel";
598 interrupt-controller;
599 #interrupt-cells = <2>;
603 smp2p-modem {
606 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
612 qcom,local-pid = <0>;
613 qcom,remote-pid = <1>;
615 smp2p_modem_out: master-kernel {
616 qcom,entry-name = "master-kernel";
617 #qcom,smem-state-cells = <1>;
620 smp2p_modem_in: slave-kernel {
621 qcom,entry-name = "slave-kernel";
622 interrupt-controller;
623 #interrupt-cells = <2>;
626 ipa_smp2p_out: ipa-ap-to-modem {
627 qcom,entry-name = "ipa";
628 #qcom,smem-state-cells = <1>;
631 ipa_smp2p_in: ipa-modem-to-ap {
632 qcom,entry-name = "ipa";
633 interrupt-controller;
634 #interrupt-cells = <2>;
638 smp2p-slpi {
641 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
647 qcom,local-pid = <0>;
648 qcom,remote-pid = <3>;
650 smp2p_slpi_out: master-kernel {
651 qcom,entry-name = "master-kernel";
652 #qcom,smem-state-cells = <1>;
655 smp2p_slpi_in: slave-kernel {
656 qcom,entry-name = "slave-kernel";
657 interrupt-controller;
658 #interrupt-cells = <2>;
663 #address-cells = <2>;
664 #size-cells = <2>;
666 dma-ranges = <0 0 0 0 0x10 0>;
667 compatible = "simple-bus";
669 gcc: clock-controller@100000 {
670 compatible = "qcom,gcc-sm8350";
672 #clock-cells = <1>;
673 #reset-cells = <1>;
674 #power-domain-cells = <1>;
675 clock-names = "bi_tcxo",
702 compatible = "qcom,sm8350-ipcc", "qcom,ipcc";
705 interrupt-controller;
706 #interrupt-cells = <3>;
707 #mbox-cells = <2>;
710 gpi_dma2: dma-controller@800000 {
711 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
725 dma-channels = <12>;
726 dma-channel-mask = <0xff>;
728 #dma-cells = <3>;
733 compatible = "qcom,geni-se-qup";
735 clock-names = "m-ahb", "s-ahb";
739 #address-cells = <2>;
740 #size-cells = <2>;
745 compatible = "qcom,geni-i2c";
747 clock-names = "se";
749 pinctrl-names = "default";
750 pinctrl-0 = <&qup_i2c14_default>;
754 dma-names = "tx", "rx";
755 #address-cells = <1>;
756 #size-cells = <0>;
761 compatible = "qcom,geni-spi";
763 clock-names = "se";
766 power-domains = <&rpmhpd RPMHPD_CX>;
767 operating-points-v2 = <&qup_opp_table_120mhz>;
770 dma-names = "tx", "rx";
771 #address-cells = <1>;
772 #size-cells = <0>;
777 compatible = "qcom,geni-i2c";
779 clock-names = "se";
781 pinctrl-names = "default";
782 pinctrl-0 = <&qup_i2c15_default>;
786 dma-names = "tx", "rx";
787 #address-cells = <1>;
788 #size-cells = <0>;
793 compatible = "qcom,geni-spi";
795 clock-names = "se";
798 power-domains = <&rpmhpd RPMHPD_CX>;
799 operating-points-v2 = <&qup_opp_table_120mhz>;
802 dma-names = "tx", "rx";
803 #address-cells = <1>;
804 #size-cells = <0>;
809 compatible = "qcom,geni-i2c";
811 clock-names = "se";
813 pinctrl-names = "default";
814 pinctrl-0 = <&qup_i2c16_default>;
818 dma-names = "tx", "rx";
819 #address-cells = <1>;
820 #size-cells = <0>;
825 compatible = "qcom,geni-spi";
827 clock-names = "se";
830 power-domains = <&rpmhpd RPMHPD_CX>;
831 operating-points-v2 = <&qup_opp_table_100mhz>;
834 dma-names = "tx", "rx";
835 #address-cells = <1>;
836 #size-cells = <0>;
841 compatible = "qcom,geni-i2c";
843 clock-names = "se";
845 pinctrl-names = "default";
846 pinctrl-0 = <&qup_i2c17_default>;
850 dma-names = "tx", "rx";
851 #address-cells = <1>;
852 #size-cells = <0>;
857 compatible = "qcom,geni-spi";
859 clock-names = "se";
862 power-domains = <&rpmhpd RPMHPD_CX>;
863 operating-points-v2 = <&qup_opp_table_100mhz>;
866 dma-names = "tx", "rx";
867 #address-cells = <1>;
868 #size-cells = <0>;
872 /* QUP no. 18 seems to be strictly SPI/UART-only */
875 compatible = "qcom,geni-spi";
877 clock-names = "se";
880 power-domains = <&rpmhpd RPMHPD_CX>;
881 operating-points-v2 = <&qup_opp_table_100mhz>;
884 dma-names = "tx", "rx";
885 #address-cells = <1>;
886 #size-cells = <0>;
891 compatible = "qcom,geni-uart";
893 clock-names = "se";
895 pinctrl-names = "default";
896 pinctrl-0 = <&qup_uart18_default>;
898 power-domains = <&rpmhpd RPMHPD_CX>;
899 operating-points-v2 = <&qup_opp_table_100mhz>;
904 compatible = "qcom,geni-i2c";
906 clock-names = "se";
908 pinctrl-names = "default";
909 pinctrl-0 = <&qup_i2c19_default>;
913 dma-names = "tx", "rx";
914 #address-cells = <1>;
915 #size-cells = <0>;
920 compatible = "qcom,geni-spi";
922 clock-names = "se";
925 power-domains = <&rpmhpd RPMHPD_CX>;
926 operating-points-v2 = <&qup_opp_table_100mhz>;
929 dma-names = "tx", "rx";
930 #address-cells = <1>;
931 #size-cells = <0>;
936 gpi_dma0: dma-controller@900000 {
937 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
951 dma-channels = <12>;
952 dma-channel-mask = <0x7e>;
954 #dma-cells = <3>;
959 compatible = "qcom,geni-se-qup";
961 clock-names = "m-ahb", "s-ahb";
965 #address-cells = <2>;
966 #size-cells = <2>;
971 compatible = "qcom,geni-i2c";
973 clock-names = "se";
975 pinctrl-names = "default";
976 pinctrl-0 = <&qup_i2c0_default>;
980 dma-names = "tx", "rx";
981 #address-cells = <1>;
982 #size-cells = <0>;
987 compatible = "qcom,geni-spi";
989 clock-names = "se";
992 power-domains = <&rpmhpd RPMHPD_CX>;
993 operating-points-v2 = <&qup_opp_table_100mhz>;
996 dma-names = "tx", "rx";
997 #address-cells = <1>;
998 #size-cells = <0>;
1003 compatible = "qcom,geni-i2c";
1005 clock-names = "se";
1007 pinctrl-names = "default";
1008 pinctrl-0 = <&qup_i2c1_default>;
1012 dma-names = "tx", "rx";
1013 #address-cells = <1>;
1014 #size-cells = <0>;
1019 compatible = "qcom,geni-spi";
1021 clock-names = "se";
1024 power-domains = <&rpmhpd RPMHPD_CX>;
1025 operating-points-v2 = <&qup_opp_table_100mhz>;
1028 dma-names = "tx", "rx";
1029 #address-cells = <1>;
1030 #size-cells = <0>;
1035 compatible = "qcom,geni-i2c";
1037 clock-names = "se";
1039 pinctrl-names = "default";
1040 pinctrl-0 = <&qup_i2c2_default>;
1044 dma-names = "tx", "rx";
1045 #address-cells = <1>;
1046 #size-cells = <0>;
1051 compatible = "qcom,geni-spi";
1053 clock-names = "se";
1056 power-domains = <&rpmhpd RPMHPD_CX>;
1057 operating-points-v2 = <&qup_opp_table_100mhz>;
1060 dma-names = "tx", "rx";
1061 #address-cells = <1>;
1062 #size-cells = <0>;
1067 compatible = "qcom,geni-debug-uart";
1069 clock-names = "se";
1071 pinctrl-names = "default";
1072 pinctrl-0 = <&qup_uart3_default_state>;
1074 power-domains = <&rpmhpd RPMHPD_CX>;
1075 operating-points-v2 = <&qup_opp_table_100mhz>;
1079 /* QUP no. 3 seems to be strictly SPI-only */
1082 compatible = "qcom,geni-spi";
1084 clock-names = "se";
1087 power-domains = <&rpmhpd RPMHPD_CX>;
1088 operating-points-v2 = <&qup_opp_table_100mhz>;
1091 dma-names = "tx", "rx";
1092 #address-cells = <1>;
1093 #size-cells = <0>;
1098 compatible = "qcom,geni-i2c";
1100 clock-names = "se";
1102 pinctrl-names = "default";
1103 pinctrl-0 = <&qup_i2c4_default>;
1107 dma-names = "tx", "rx";
1108 #address-cells = <1>;
1109 #size-cells = <0>;
1114 compatible = "qcom,geni-spi";
1116 clock-names = "se";
1119 power-domains = <&rpmhpd RPMHPD_CX>;
1120 operating-points-v2 = <&qup_opp_table_100mhz>;
1123 dma-names = "tx", "rx";
1124 #address-cells = <1>;
1125 #size-cells = <0>;
1130 compatible = "qcom,geni-i2c";
1132 clock-names = "se";
1134 pinctrl-names = "default";
1135 pinctrl-0 = <&qup_i2c5_default>;
1139 dma-names = "tx", "rx";
1140 #address-cells = <1>;
1141 #size-cells = <0>;
1146 compatible = "qcom,geni-spi";
1148 clock-names = "se";
1151 power-domains = <&rpmhpd RPMHPD_CX>;
1152 operating-points-v2 = <&qup_opp_table_100mhz>;
1155 dma-names = "tx", "rx";
1156 #address-cells = <1>;
1157 #size-cells = <0>;
1162 compatible = "qcom,geni-i2c";
1164 clock-names = "se";
1166 pinctrl-names = "default";
1167 pinctrl-0 = <&qup_i2c6_default>;
1171 dma-names = "tx", "rx";
1172 #address-cells = <1>;
1173 #size-cells = <0>;
1178 compatible = "qcom,geni-spi";
1180 clock-names = "se";
1183 power-domains = <&rpmhpd RPMHPD_CX>;
1184 operating-points-v2 = <&qup_opp_table_100mhz>;
1187 dma-names = "tx", "rx";
1188 #address-cells = <1>;
1189 #size-cells = <0>;
1194 compatible = "qcom,geni-uart";
1196 clock-names = "se";
1198 pinctrl-names = "default";
1199 pinctrl-0 = <&qup_uart6_default>;
1201 power-domains = <&rpmhpd RPMHPD_CX>;
1202 operating-points-v2 = <&qup_opp_table_100mhz>;
1207 compatible = "qcom,geni-i2c";
1209 clock-names = "se";
1211 pinctrl-names = "default";
1212 pinctrl-0 = <&qup_i2c7_default>;
1216 dma-names = "tx", "rx";
1217 #address-cells = <1>;
1218 #size-cells = <0>;
1223 compatible = "qcom,geni-spi";
1225 clock-names = "se";
1228 power-domains = <&rpmhpd RPMHPD_CX>;
1229 operating-points-v2 = <&qup_opp_table_100mhz>;
1232 dma-names = "tx", "rx";
1233 #address-cells = <1>;
1234 #size-cells = <0>;
1239 gpi_dma1: dma-controller@a00000 {
1240 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
1254 dma-channels = <12>;
1255 dma-channel-mask = <0xff>;
1257 #dma-cells = <3>;
1262 compatible = "qcom,geni-se-qup";
1264 clock-names = "m-ahb", "s-ahb";
1268 #address-cells = <2>;
1269 #size-cells = <2>;
1274 compatible = "qcom,geni-i2c";
1276 clock-names = "se";
1278 pinctrl-names = "default";
1279 pinctrl-0 = <&qup_i2c8_default>;
1283 dma-names = "tx", "rx";
1284 #address-cells = <1>;
1285 #size-cells = <0>;
1290 compatible = "qcom,geni-spi";
1292 clock-names = "se";
1295 power-domains = <&rpmhpd RPMHPD_CX>;
1296 operating-points-v2 = <&qup_opp_table_120mhz>;
1299 dma-names = "tx", "rx";
1300 #address-cells = <1>;
1301 #size-cells = <0>;
1306 compatible = "qcom,geni-i2c";
1308 clock-names = "se";
1310 pinctrl-names = "default";
1311 pinctrl-0 = <&qup_i2c9_default>;
1315 dma-names = "tx", "rx";
1316 #address-cells = <1>;
1317 #size-cells = <0>;
1322 compatible = "qcom,geni-spi";
1324 clock-names = "se";
1327 power-domains = <&rpmhpd RPMHPD_CX>;
1328 operating-points-v2 = <&qup_opp_table_100mhz>;
1331 dma-names = "tx", "rx";
1332 #address-cells = <1>;
1333 #size-cells = <0>;
1338 compatible = "qcom,geni-i2c";
1340 clock-names = "se";
1342 pinctrl-names = "default";
1343 pinctrl-0 = <&qup_i2c10_default>;
1347 dma-names = "tx", "rx";
1348 #address-cells = <1>;
1349 #size-cells = <0>;
1354 compatible = "qcom,geni-spi";
1356 clock-names = "se";
1359 power-domains = <&rpmhpd RPMHPD_CX>;
1360 operating-points-v2 = <&qup_opp_table_100mhz>;
1363 dma-names = "tx", "rx";
1364 #address-cells = <1>;
1365 #size-cells = <0>;
1370 compatible = "qcom,geni-i2c";
1372 clock-names = "se";
1374 pinctrl-names = "default";
1375 pinctrl-0 = <&qup_i2c11_default>;
1379 dma-names = "tx", "rx";
1380 #address-cells = <1>;
1381 #size-cells = <0>;
1386 compatible = "qcom,geni-spi";
1388 clock-names = "se";
1391 power-domains = <&rpmhpd RPMHPD_CX>;
1392 operating-points-v2 = <&qup_opp_table_100mhz>;
1395 dma-names = "tx", "rx";
1396 #address-cells = <1>;
1397 #size-cells = <0>;
1402 compatible = "qcom,geni-i2c";
1404 clock-names = "se";
1406 pinctrl-names = "default";
1407 pinctrl-0 = <&qup_i2c12_default>;
1411 dma-names = "tx", "rx";
1412 #address-cells = <1>;
1413 #size-cells = <0>;
1418 compatible = "qcom,geni-spi";
1420 clock-names = "se";
1423 power-domains = <&rpmhpd RPMHPD_CX>;
1424 operating-points-v2 = <&qup_opp_table_100mhz>;
1427 dma-names = "tx", "rx";
1428 #address-cells = <1>;
1429 #size-cells = <0>;
1434 compatible = "qcom,geni-i2c";
1436 clock-names = "se";
1438 pinctrl-names = "default";
1439 pinctrl-0 = <&qup_i2c13_default>;
1443 dma-names = "tx", "rx";
1444 #address-cells = <1>;
1445 #size-cells = <0>;
1450 compatible = "qcom,geni-spi";
1452 clock-names = "se";
1455 power-domains = <&rpmhpd RPMHPD_CX>;
1456 operating-points-v2 = <&qup_opp_table_100mhz>;
1459 dma-names = "tx", "rx";
1460 #address-cells = <1>;
1461 #size-cells = <0>;
1467 compatible = "qcom,prng-ee";
1470 clock-names = "core";
1474 compatible = "qcom,sm8350-config-noc";
1476 #interconnect-cells = <2>;
1477 qcom,bcm-voters = <&apps_bcm_voter>;
1481 compatible = "qcom,sm8350-mc-virt";
1483 #interconnect-cells = <2>;
1484 qcom,bcm-voters = <&apps_bcm_voter>;
1488 compatible = "qcom,sm8350-system-noc";
1490 #interconnect-cells = <2>;
1491 qcom,bcm-voters = <&apps_bcm_voter>;
1495 compatible = "qcom,sm8350-aggre1-noc";
1497 #interconnect-cells = <2>;
1498 qcom,bcm-voters = <&apps_bcm_voter>;
1502 compatible = "qcom,sm8350-aggre2-noc";
1504 #interconnect-cells = <2>;
1505 qcom,bcm-voters = <&apps_bcm_voter>;
1509 compatible = "qcom,sm8350-mmss-noc";
1511 #interconnect-cells = <2>;
1512 qcom,bcm-voters = <&apps_bcm_voter>;
1516 compatible = "qcom,pcie-sm8350";
1522 reg-names = "parf", "dbi", "elbi", "atu", "config";
1524 linux,pci-domain = <0>;
1525 bus-range = <0x00 0xff>;
1526 num-lanes = <1>;
1528 #address-cells = <3>;
1529 #size-cells = <2>;
1543 interrupt-names = "msi0",
1552 #interrupt-cells = <1>;
1553 interrupt-map-mask = <0 0 0 0x7>;
1554 interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1555 <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1556 <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1557 <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1568 clock-names = "aux",
1578 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1582 reset-names = "pci";
1584 power-domains = <&gcc PCIE_0_GDSC>;
1587 phy-names = "pciephy";
1594 bus-range = <0x01 0xff>;
1596 #address-cells = <3>;
1597 #size-cells = <2>;
1603 compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy";
1610 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
1613 reset-names = "phy";
1615 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>;
1616 assigned-clock-rates = <100000000>;
1618 #clock-cells = <0>;
1619 clock-output-names = "pcie_0_pipe_clk";
1621 #phy-cells = <0>;
1627 compatible = "qcom,pcie-sm8350";
1633 reg-names = "parf", "dbi", "elbi", "atu", "config";
1635 linux,pci-domain = <1>;
1636 bus-range = <0x00 0xff>;
1637 num-lanes = <2>;
1639 #address-cells = <3>;
1640 #size-cells = <2>;
1654 interrupt-names = "msi0",
1663 #interrupt-cells = <1>;
1664 interrupt-map-mask = <0 0 0 0x7>;
1665 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1666 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1667 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1668 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1678 clock-names = "aux",
1687 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1691 reset-names = "pci";
1693 power-domains = <&gcc PCIE_1_GDSC>;
1696 phy-names = "pciephy";
1703 bus-range = <0x01 0xff>;
1705 #address-cells = <3>;
1706 #size-cells = <2>;
1712 compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy";
1719 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
1722 reset-names = "phy";
1724 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
1725 assigned-clock-rates = <100000000>;
1727 #clock-cells = <0>;
1728 clock-output-names = "pcie_1_pipe_clk";
1730 #phy-cells = <0>;
1736 compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
1737 "jedec,ufs-2.0";
1741 phy-names = "ufsphy";
1742 lanes-per-direction = <2>;
1743 #reset-cells = <1>;
1745 reset-names = "rst";
1747 power-domains = <&gcc UFS_PHY_GDSC>;
1750 dma-coherent;
1752 clock-names =
1774 interconnect-names = "ufs-ddr", "cpu-ufs";
1775 freq-table-hz =
1788 compatible = "qcom,sm8350-qmp-ufs-phy";
1794 clock-names = "ref",
1798 power-domains = <&gcc UFS_PHY_GDSC>;
1801 reset-names = "ufsphy";
1803 #clock-cells = <1>;
1804 #phy-cells = <0>;
1809 cryptobam: dma-controller@1dc4000 {
1810 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
1813 #dma-cells = <1>;
1815 qcom,num-ees = <4>;
1816 num-channels = <16>;
1817 qcom,controlled-remotely;
1823 compatible = "qcom,sm8350-qce", "qcom,sm8150-qce", "qcom,qce";
1826 dma-names = "rx", "tx";
1830 interconnect-names = "memory";
1834 compatible = "qcom,sm8350-ipa";
1841 reg-names = "ipa-reg",
1842 "ipa-shared",
1845 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>,
1846 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1849 interrupt-names = "ipa",
1851 "ipa-clock-query",
1852 "ipa-setup-ready";
1855 clock-names = "core";
1859 interconnect-names = "memory",
1864 qcom,smem-states = <&ipa_smp2p_out 0>,
1866 qcom,smem-state-names = "ipa-clock-enabled-valid",
1867 "ipa-clock-enabled";
1873 compatible = "qcom,tcsr-mutex";
1875 #hwlock-cells = <1>;
1879 compatible = "qcom,sm8350-tcsr", "syscon";
1884 compatible = "qcom,sm8350-adsp-pas";
1887 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
1892 interrupt-names = "wdog", "fatal", "ready",
1893 "handover", "stop-ack";
1896 clock-names = "xo";
1898 power-domains = <&rpmhpd RPMHPD_LCX>,
1900 power-domain-names = "lcx", "lmx";
1902 memory-region = <&pil_adsp_mem>;
1906 qcom,smem-states = <&smp2p_adsp_out 0>;
1907 qcom,smem-state-names = "stop";
1911 glink-edge {
1912 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
1919 qcom,remote-pid = <2>;
1922 compatible = "qcom,apr-v2";
1923 qcom,glink-channels = "apr_audio_svc";
1925 #address-cells = <1>;
1926 #size-cells = <0>;
1931 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
1937 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
1940 compatible = "qcom,q6afe-dais";
1941 #address-cells = <1>;
1942 #size-cells = <0>;
1943 #sound-dai-cells = <1>;
1946 q6afecc: clock-controller {
1947 compatible = "qcom,q6afe-clocks";
1948 #clock-cells = <2>;
1955 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
1958 compatible = "qcom,q6asm-dais";
1959 #address-cells = <1>;
1960 #size-cells = <0>;
1961 #sound-dai-cells = <1>;
1981 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
1984 compatible = "qcom,q6adm-routing";
1985 #sound-dai-cells = <0>;
1992 qcom,glink-channels = "fastrpcglink-apps-dsp";
1994 qcom,non-secure-domain;
1995 #address-cells = <1>;
1996 #size-cells = <0>;
1998 compute-cb@3 {
1999 compatible = "qcom,fastrpc-compute-cb";
2004 compute-cb@4 {
2005 compatible = "qcom,fastrpc-compute-cb";
2010 compute-cb@5 {
2011 compatible = "qcom,fastrpc-compute-cb";
2020 compatible = "qcom,sm8350-lpass-lpi-pinctrl";
2026 clock-names = "core", "audio";
2028 gpio-controller;
2029 #gpio-cells = <2>;
2030 gpio-ranges = <&lpass_tlmm 0 0 15>;
2034 compatible = "qcom,adreno-660.1", "qcom,adreno";
2039 reg-names = "kgsl_3d0_reg_memory",
2047 operating-points-v2 = <&gpu_opp_table>;
2050 #cooling-cells = <2>;
2054 gpu_zap_shader: zap-shader {
2055 memory-region = <&pil_gpu_mem>;
2059 gpu_opp_table: opp-table {
2060 compatible = "operating-points-v2";
2062 opp-840000000 {
2063 opp-hz = /bits/ 64 <840000000>;
2064 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2067 opp-778000000 {
2068 opp-hz = /bits/ 64 <778000000>;
2069 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2072 opp-738000000 {
2073 opp-hz = /bits/ 64 <738000000>;
2074 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2077 opp-676000000 {
2078 opp-hz = /bits/ 64 <676000000>;
2079 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2082 opp-608000000 {
2083 opp-hz = /bits/ 64 <608000000>;
2084 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2087 opp-540000000 {
2088 opp-hz = /bits/ 64 <540000000>;
2089 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2092 opp-491000000 {
2093 opp-hz = /bits/ 64 <491000000>;
2094 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2097 opp-443000000 {
2098 opp-hz = /bits/ 64 <443000000>;
2099 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2102 opp-379000000 {
2103 opp-hz = /bits/ 64 <379000000>;
2104 opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>;
2107 opp-315000000 {
2108 opp-hz = /bits/ 64 <315000000>;
2109 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2115 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu";
2120 reg-names = "gmu", "rscc", "gmu_pdc";
2124 interrupt-names = "hfi", "gmu";
2133 clock-names = "gmu",
2141 power-domains = <&gpucc GPU_CX_GDSC>,
2143 power-domain-names = "cx",
2148 operating-points-v2 = <&gmu_opp_table>;
2150 gmu_opp_table: opp-table {
2151 compatible = "operating-points-v2";
2153 opp-200000000 {
2154 opp-hz = /bits/ 64 <200000000>;
2155 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2160 gpucc: clock-controller@3d90000 {
2161 compatible = "qcom,sm8350-gpucc";
2166 clock-names = "bi_tcxo",
2169 #clock-cells = <1>;
2170 #reset-cells = <1>;
2171 #power-domain-cells = <1>;
2175 compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu",
2176 "qcom,smmu-500", "arm,mmu-500";
2178 #iommu-cells = <2>;
2179 #global-interrupts = <2>;
2200 clock-names = "bus",
2208 power-domains = <&gpucc GPU_CX_GDSC>;
2209 dma-coherent;
2213 compatible = "qcom,sm8350-lpass-ag-noc";
2215 #interconnect-cells = <2>;
2216 qcom,bcm-voters = <&apps_bcm_voter>;
2220 compatible = "qcom,sm8350-mpss-pas";
2223 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2229 interrupt-names = "wdog", "fatal", "ready", "handover",
2230 "stop-ack", "shutdown-ack";
2233 clock-names = "xo";
2235 power-domains = <&rpmhpd RPMHPD_CX>,
2237 power-domain-names = "cx", "mss";
2241 memory-region = <&pil_modem_mem>;
2245 qcom,smem-states = <&smp2p_modem_out 0>;
2246 qcom,smem-state-names = "stop";
2250 glink-edge {
2251 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2257 qcom,remote-pid = <1>;
2262 compatible = "qcom,sm8350-slpi-pas";
2265 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2270 interrupt-names = "wdog", "fatal", "ready",
2271 "handover", "stop-ack";
2274 clock-names = "xo";
2276 power-domains = <&rpmhpd RPMHPD_LCX>,
2278 power-domain-names = "lcx", "lmx";
2280 memory-region = <&pil_slpi_mem>;
2284 qcom,smem-states = <&smp2p_slpi_out 0>;
2285 qcom,smem-state-names = "stop";
2289 glink-edge {
2290 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2297 qcom,remote-pid = <3>;
2301 qcom,glink-channels = "fastrpcglink-apps-dsp";
2303 qcom,non-secure-domain;
2304 #address-cells = <1>;
2305 #size-cells = <0>;
2307 compute-cb@1 {
2308 compatible = "qcom,fastrpc-compute-cb";
2313 compute-cb@2 {
2314 compatible = "qcom,fastrpc-compute-cb";
2319 compute-cb@3 {
2320 compatible = "qcom,fastrpc-compute-cb";
2323 /* note: shared-cb = <4> in downstream */
2330 compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5";
2335 interrupt-names = "hc_irq", "pwr_irq";
2340 clock-names = "iface", "core", "xo";
2344 interconnect-names = "sdhc-ddr","cpu-sdhc";
2346 power-domains = <&rpmhpd RPMHPD_CX>;
2347 operating-points-v2 = <&sdhc2_opp_table>;
2348 bus-width = <4>;
2349 dma-coherent;
2353 sdhc2_opp_table: opp-table {
2354 compatible = "operating-points-v2";
2356 opp-100000000 {
2357 opp-hz = /bits/ 64 <100000000>;
2358 required-opps = <&rpmhpd_opp_low_svs>;
2361 opp-202000000 {
2362 opp-hz = /bits/ 64 <202000000>;
2363 required-opps = <&rpmhpd_opp_svs_l1>;
2369 compatible = "qcom,sm8350-usb-hs-phy",
2370 "qcom,usb-snps-hs-7nm-phy";
2373 #phy-cells = <0>;
2376 clock-names = "ref";
2382 compatible = "qcom,sm8250-usb-hs-phy",
2383 "qcom,usb-snps-hs-7nm-phy";
2386 #phy-cells = <0>;
2389 clock-names = "ref";
2395 compatible = "qcom,sm8350-refgen-regulator",
2396 "qcom,sm8250-refgen-regulator";
2401 compatible = "qcom,sm8350-qmp-usb3-dp-phy";
2408 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2412 reset-names = "phy", "common";
2414 #clock-cells = <1>;
2415 #phy-cells = <1>;
2417 orientation-switch;
2422 #address-cells = <1>;
2423 #size-cells = <0>;
2436 remote-endpoint = <&usb_1_dwc3_ss>;
2444 remote-endpoint = <&mdss_dp_out>;
2451 compatible = "qcom,sm8350-qmp-usb3-uni-phy";
2459 clock-names = "aux",
2463 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2464 #clock-cells = <0>;
2465 #phy-cells = <0>;
2469 reset-names = "phy",
2474 compatible = "qcom,sm8350-dc-noc";
2476 #interconnect-cells = <2>;
2477 qcom,bcm-voters = <&apps_bcm_voter>;
2481 compatible = "qcom,sm8350-gem-noc";
2483 #interconnect-cells = <2>;
2484 qcom,bcm-voters = <&apps_bcm_voter>;
2487 system-cache-controller@9200000 {
2488 compatible = "qcom,sm8350-llcc";
2492 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2497 compatible = "qcom,sm8350-compute-noc";
2499 #interconnect-cells = <2>;
2500 qcom,bcm-voters = <&apps_bcm_voter>;
2504 compatible = "qcom,sm8350-cdsp-pas";
2507 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2512 interrupt-names = "wdog", "fatal", "ready",
2513 "handover", "stop-ack";
2516 clock-names = "xo";
2518 power-domains = <&rpmhpd RPMHPD_CX>,
2520 power-domain-names = "cx", "mxc";
2524 memory-region = <&pil_cdsp_mem>;
2528 qcom,smem-states = <&smp2p_cdsp_out 0>;
2529 qcom,smem-state-names = "stop";
2533 glink-edge {
2534 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2541 qcom,remote-pid = <5>;
2545 qcom,glink-channels = "fastrpcglink-apps-dsp";
2547 qcom,non-secure-domain;
2548 #address-cells = <1>;
2549 #size-cells = <0>;
2551 compute-cb@1 {
2552 compatible = "qcom,fastrpc-compute-cb";
2558 compute-cb@2 {
2559 compatible = "qcom,fastrpc-compute-cb";
2565 compute-cb@3 {
2566 compatible = "qcom,fastrpc-compute-cb";
2572 compute-cb@4 {
2573 compatible = "qcom,fastrpc-compute-cb";
2579 compute-cb@5 {
2580 compatible = "qcom,fastrpc-compute-cb";
2586 compute-cb@6 {
2587 compatible = "qcom,fastrpc-compute-cb";
2593 compute-cb@7 {
2594 compatible = "qcom,fastrpc-compute-cb";
2600 compute-cb@8 {
2601 compatible = "qcom,fastrpc-compute-cb";
2613 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2616 #address-cells = <2>;
2617 #size-cells = <2>;
2625 clock-names = "cfg_noc",
2631 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2633 assigned-clock-rates = <19200000>, <200000000>;
2635 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
2636 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2637 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
2638 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
2639 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
2640 interrupt-names = "pwr_event",
2646 power-domains = <&gcc USB30_PRIM_GDSC>;
2652 interconnect-names = "usb-ddr", "apps-usb";
2662 snps,dis-u1-entry-quirk;
2663 snps,dis-u2-entry-quirk;
2665 phy-names = "usb2-phy", "usb3-phy";
2668 #address-cells = <1>;
2669 #size-cells = <0>;
2682 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
2690 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2693 #address-cells = <2>;
2694 #size-cells = <2>;
2703 clock-names = "cfg_noc",
2710 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2712 assigned-clock-rates = <19200000>, <200000000>;
2714 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
2715 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2716 <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
2717 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
2718 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
2719 interrupt-names = "pwr_event",
2725 power-domains = <&gcc USB30_SEC_GDSC>;
2731 interconnect-names = "usb-ddr", "apps-usb";
2741 snps,dis-u1-entry-quirk;
2742 snps,dis-u2-entry-quirk;
2744 phy-names = "usb2-phy", "usb3-phy";
2748 mdss: display-subsystem@ae00000 {
2749 compatible = "qcom,sm8350-mdss";
2751 reg-names = "mdss";
2757 interconnect-names = "mdp0-mem",
2758 "mdp1-mem",
2759 "cpu-cfg";
2761 power-domains = <&dispcc MDSS_GDSC>;
2768 clock-names = "iface", "bus", "nrt_bus", "core";
2771 interrupt-controller;
2772 #interrupt-cells = <1>;
2778 #address-cells = <2>;
2779 #size-cells = <2>;
2782 mdss_mdp: display-controller@ae01000 {
2783 compatible = "qcom,sm8350-dpu";
2786 reg-names = "mdp", "vbif";
2794 clock-names = "bus",
2801 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2802 assigned-clock-rates = <19200000>;
2804 operating-points-v2 = <&dpu_opp_table>;
2805 power-domains = <&rpmhpd RPMHPD_MMCX>;
2807 interrupt-parent = <&mdss>;
2810 dpu_opp_table: opp-table {
2811 compatible = "operating-points-v2";
2813 /* TODO: opp-200000000 should work with
2818 opp-200000000 {
2819 opp-hz = /bits/ 64 <200000000>;
2820 required-opps = <&rpmhpd_opp_svs>;
2823 opp-300000000 {
2824 opp-hz = /bits/ 64 <300000000>;
2825 required-opps = <&rpmhpd_opp_svs>;
2828 opp-345000000 {
2829 opp-hz = /bits/ 64 <345000000>;
2830 required-opps = <&rpmhpd_opp_svs_l1>;
2833 opp-460000000 {
2834 opp-hz = /bits/ 64 <460000000>;
2835 required-opps = <&rpmhpd_opp_nom>;
2840 #address-cells = <1>;
2841 #size-cells = <0>;
2846 remote-endpoint = <&mdss_dsi0_in>;
2853 remote-endpoint = <&mdss_dsi1_in>;
2860 remote-endpoint = <&mdss_dp_in>;
2866 mdss_dp: displayport-controller@ae90000 {
2867 compatible = "qcom,sm8350-dp";
2873 interrupt-parent = <&mdss>;
2881 clock-names = "core_iface",
2888 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
2891 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2896 phy-names = "dp";
2898 #sound-dai-cells = <0>;
2900 operating-points-v2 = <&dp_opp_table>;
2901 power-domains = <&rpmhpd RPMHPD_MMCX>;
2906 #address-cells = <1>;
2907 #size-cells = <0>;
2912 remote-endpoint = <&dpu_intf0_out>;
2920 remote-endpoint = <&usb_1_qmpphy_dp_in>;
2925 dp_opp_table: opp-table {
2926 compatible = "operating-points-v2";
2928 opp-160000000 {
2929 opp-hz = /bits/ 64 <160000000>;
2930 required-opps = <&rpmhpd_opp_low_svs>;
2933 opp-270000000 {
2934 opp-hz = /bits/ 64 <270000000>;
2935 required-opps = <&rpmhpd_opp_svs>;
2938 opp-540000000 {
2939 opp-hz = /bits/ 64 <540000000>;
2940 required-opps = <&rpmhpd_opp_svs_l1>;
2943 opp-810000000 {
2944 opp-hz = /bits/ 64 <810000000>;
2945 required-opps = <&rpmhpd_opp_nom>;
2951 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2953 reg-names = "dsi_ctrl";
2955 interrupt-parent = <&mdss>;
2964 clock-names = "byte",
2971 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2973 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
2976 operating-points-v2 = <&dsi0_opp_table>;
2977 power-domains = <&rpmhpd RPMHPD_MMCX>;
2978 refgen-supply = <&refgen>;
2982 #address-cells = <1>;
2983 #size-cells = <0>;
2987 dsi0_opp_table: opp-table {
2988 compatible = "operating-points-v2";
2990 /* TODO: opp-187500000 should work with
2995 opp-187500000 {
2996 opp-hz = /bits/ 64 <187500000>;
2997 required-opps = <&rpmhpd_opp_svs>;
3000 opp-300000000 {
3001 opp-hz = /bits/ 64 <300000000>;
3002 required-opps = <&rpmhpd_opp_svs>;
3005 opp-358000000 {
3006 opp-hz = /bits/ 64 <358000000>;
3007 required-opps = <&rpmhpd_opp_svs_l1>;
3012 #address-cells = <1>;
3013 #size-cells = <0>;
3018 remote-endpoint = <&dpu_intf1_out>;
3031 compatible = "qcom,sm8350-dsi-phy-5nm";
3035 reg-names = "dsi_phy",
3039 #clock-cells = <1>;
3040 #phy-cells = <0>;
3044 clock-names = "iface", "ref";
3050 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3052 reg-names = "dsi_ctrl";
3054 interrupt-parent = <&mdss>;
3063 clock-names = "byte",
3070 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
3072 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
3075 operating-points-v2 = <&dsi1_opp_table>;
3076 power-domains = <&rpmhpd RPMHPD_MMCX>;
3077 refgen-supply = <&refgen>;
3081 #address-cells = <1>;
3082 #size-cells = <0>;
3086 dsi1_opp_table: opp-table {
3087 compatible = "operating-points-v2";
3089 /* TODO: opp-187500000 should work with
3094 opp-187500000 {
3095 opp-hz = /bits/ 64 <187500000>;
3096 required-opps = <&rpmhpd_opp_svs>;
3099 opp-300000000 {
3100 opp-hz = /bits/ 64 <300000000>;
3101 required-opps = <&rpmhpd_opp_svs>;
3104 opp-358000000 {
3105 opp-hz = /bits/ 64 <358000000>;
3106 required-opps = <&rpmhpd_opp_svs_l1>;
3111 #address-cells = <1>;
3112 #size-cells = <0>;
3117 remote-endpoint = <&dpu_intf2_out>;
3130 compatible = "qcom,sm8350-dsi-phy-5nm";
3134 reg-names = "dsi_phy",
3138 #clock-cells = <1>;
3139 #phy-cells = <0>;
3143 clock-names = "iface", "ref";
3149 dispcc: clock-controller@af00000 {
3150 compatible = "qcom,sm8350-dispcc";
3159 clock-names = "bi_tcxo",
3166 #clock-cells = <1>;
3167 #reset-cells = <1>;
3168 #power-domain-cells = <1>;
3170 power-domains = <&rpmhpd RPMHPD_MMCX>;
3173 pdc: interrupt-controller@b220000 { label
3174 compatible = "qcom,sm8350-pdc", "qcom,pdc";
3176 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
3180 #interrupt-cells = <2>;
3181 interrupt-parent = <&intc>;
3182 interrupt-controller;
3185 tsens0: thermal-sensor@c263000 {
3186 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
3190 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
3191 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
3192 interrupt-names = "uplow", "critical";
3193 #thermal-sensor-cells = <1>;
3196 tsens1: thermal-sensor@c265000 {
3197 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
3201 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
3202 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
3203 interrupt-names = "uplow", "critical";
3204 #thermal-sensor-cells = <1>;
3207 aoss_qmp: power-management@c300000 {
3208 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp";
3210 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3214 #clock-cells = <0>;
3218 compatible = "qcom,rpmh-stats";
3223 compatible = "qcom,spmi-pmic-arb";
3229 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3230 interrupt-names = "periph_irq";
3231 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3234 #address-cells = <2>;
3235 #size-cells = <0>;
3236 interrupt-controller;
3237 #interrupt-cells = <4>;
3241 compatible = "qcom,sm8350-tlmm";
3244 gpio-controller;
3245 #gpio-cells = <2>;
3246 interrupt-controller;
3247 #interrupt-cells = <2>;
3248 gpio-ranges = <&tlmm 0 0 204>;
3249 wakeup-parent = <&pdc>;
3251 sdc2_default_state: sdc2-default-state {
3252 clk-pins {
3254 drive-strength = <16>;
3255 bias-disable;
3258 cmd-pins {
3260 drive-strength = <16>;
3261 bias-pull-up;
3264 data-pins {
3266 drive-strength = <16>;
3267 bias-pull-up;
3271 sdc2_sleep_state: sdc2-sleep-state {
3272 clk-pins {
3274 drive-strength = <2>;
3275 bias-disable;
3278 cmd-pins {
3280 drive-strength = <2>;
3281 bias-pull-up;
3284 data-pins {
3286 drive-strength = <2>;
3287 bias-pull-up;
3291 qup_uart3_default_state: qup-uart3-default-state {
3292 rx-pins {
3296 tx-pins {
3302 qup_uart6_default: qup-uart6-default-state {
3305 drive-strength = <2>;
3306 bias-disable;
3309 qup_uart18_default: qup-uart18-default-state {
3312 drive-strength = <2>;
3313 bias-disable;
3316 qup_i2c0_default: qup-i2c0-default-state {
3319 drive-strength = <2>;
3320 bias-pull-up;
3323 qup_i2c1_default: qup-i2c1-default-state {
3326 drive-strength = <2>;
3327 bias-pull-up;
3330 qup_i2c2_default: qup-i2c2-default-state {
3333 drive-strength = <2>;
3334 bias-pull-up;
3337 qup_i2c4_default: qup-i2c4-default-state {
3340 drive-strength = <2>;
3341 bias-pull-up;
3344 qup_i2c5_default: qup-i2c5-default-state {
3347 drive-strength = <2>;
3348 bias-pull-up;
3351 qup_i2c6_default: qup-i2c6-default-state {
3354 drive-strength = <2>;
3355 bias-pull-up;
3358 qup_i2c7_default: qup-i2c7-default-state {
3361 drive-strength = <2>;
3362 bias-disable;
3365 qup_i2c8_default: qup-i2c8-default-state {
3368 drive-strength = <2>;
3369 bias-pull-up;
3372 qup_i2c9_default: qup-i2c9-default-state {
3375 drive-strength = <2>;
3376 bias-pull-up;
3379 qup_i2c10_default: qup-i2c10-default-state {
3382 drive-strength = <2>;
3383 bias-pull-up;
3386 qup_i2c11_default: qup-i2c11-default-state {
3389 drive-strength = <2>;
3390 bias-pull-up;
3393 qup_i2c12_default: qup-i2c12-default-state {
3396 drive-strength = <2>;
3397 bias-pull-up;
3400 qup_i2c13_default: qup-i2c13-default-state {
3403 drive-strength = <2>;
3404 bias-pull-up;
3407 qup_i2c14_default: qup-i2c14-default-state {
3410 drive-strength = <2>;
3411 bias-disable;
3414 qup_i2c15_default: qup-i2c15-default-state {
3417 drive-strength = <2>;
3418 bias-disable;
3421 qup_i2c16_default: qup-i2c16-default-state {
3424 drive-strength = <2>;
3425 bias-disable;
3428 qup_i2c17_default: qup-i2c17-default-state {
3431 drive-strength = <2>;
3432 bias-disable;
3435 qup_i2c19_default: qup-i2c19-default-state {
3438 drive-strength = <2>;
3439 bias-disable;
3444 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500";
3446 #iommu-cells = <2>;
3447 #global-interrupts = <2>;
3546 dma-coherent;
3549 intc: interrupt-controller@17a00000 { label
3550 compatible = "arm,gic-v3";
3551 #address-cells = <0>;
3552 #interrupt-cells = <3>;
3553 interrupt-controller;
3554 #redistributor-regions = <1>;
3555 redistributor-stride = <0 0x20000>;
3562 compatible = "arm,armv7-timer-mem";
3563 #address-cells = <1>;
3564 #size-cells = <1>;
3567 clock-frequency = <19200000>;
3570 frame-number = <0>;
3578 frame-number = <1>;
3585 frame-number = <2>;
3592 frame-number = <3>;
3599 frame-number = <4>;
3606 frame-number = <5>;
3613 frame-number = <6>;
3622 compatible = "qcom,rpmh-rsc";
3626 reg-names = "drv-0", "drv-1", "drv-2";
3630 qcom,tcs-offset = <0xd00>;
3631 qcom,drv-id = <2>;
3632 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
3634 power-domains = <&cluster_pd>;
3636 rpmhcc: clock-controller {
3637 compatible = "qcom,sm8350-rpmh-clk";
3638 #clock-cells = <1>;
3639 clock-names = "xo";
3643 rpmhpd: power-controller {
3644 compatible = "qcom,sm8350-rpmhpd";
3645 #power-domain-cells = <1>;
3646 operating-points-v2 = <&rpmhpd_opp_table>;
3648 rpmhpd_opp_table: opp-table {
3649 compatible = "operating-points-v2";
3652 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3656 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3660 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3664 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3668 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3672 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3676 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3680 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3684 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3688 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3693 apps_bcm_voter: bcm-voter {
3694 compatible = "qcom,bcm-voter";
3699 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
3703 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
3708 interrupt-names = "dcvsh-irq-0",
3709 "dcvsh-irq-1",
3710 "dcvsh-irq-2";
3713 clock-names = "xo", "alternate";
3715 #freq-domain-cells = <1>;
3716 #clock-cells = <1>;
3720 thermal_zones: thermal-zones {
3721 cpu0-thermal {
3722 polling-delay-passive = <250>;
3724 thermal-sensors = <&tsens0 1>;
3727 cpu0_alert0: trip-point0 {
3733 cpu0_alert1: trip-point1 {
3739 cpu0_crit: cpu-crit {
3746 cooling-maps {
3749 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3756 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3764 cpu1-thermal {
3765 polling-delay-passive = <250>;
3767 thermal-sensors = <&tsens0 2>;
3770 cpu1_alert0: trip-point0 {
3776 cpu1_alert1: trip-point1 {
3782 cpu1_crit: cpu-crit {
3789 cooling-maps {
3792 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3799 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3807 cpu2-thermal {
3808 polling-delay-passive = <250>;
3810 thermal-sensors = <&tsens0 3>;
3813 cpu2_alert0: trip-point0 {
3819 cpu2_alert1: trip-point1 {
3825 cpu2_crit: cpu-crit {
3832 cooling-maps {
3835 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3842 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3850 cpu3-thermal {
3851 polling-delay-passive = <250>;
3853 thermal-sensors = <&tsens0 4>;
3856 cpu3_alert0: trip-point0 {
3862 cpu3_alert1: trip-point1 {
3868 cpu3_crit: cpu-crit {
3875 cooling-maps {
3878 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3885 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3893 cpu4-top-thermal {
3894 polling-delay-passive = <250>;
3896 thermal-sensors = <&tsens0 7>;
3899 cpu4_top_alert0: trip-point0 {
3905 cpu4_top_alert1: trip-point1 {
3911 cpu4_top_crit: cpu-crit {
3918 cooling-maps {
3921 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3928 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3936 cpu5-top-thermal {
3937 polling-delay-passive = <250>;
3939 thermal-sensors = <&tsens0 8>;
3942 cpu5_top_alert0: trip-point0 {
3948 cpu5_top_alert1: trip-point1 {
3954 cpu5_top_crit: cpu-crit {
3961 cooling-maps {
3964 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3971 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3979 cpu6-top-thermal {
3980 polling-delay-passive = <250>;
3982 thermal-sensors = <&tsens0 9>;
3985 cpu6_top_alert0: trip-point0 {
3991 cpu6_top_alert1: trip-point1 {
3997 cpu6_top_crit: cpu-crit {
4004 cooling-maps {
4007 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4014 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4022 cpu7-top-thermal {
4023 polling-delay-passive = <250>;
4025 thermal-sensors = <&tsens0 10>;
4028 cpu7_top_alert0: trip-point0 {
4034 cpu7_top_alert1: trip-point1 {
4040 cpu7_top_crit: cpu-crit {
4047 cooling-maps {
4050 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4057 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4065 cpu4-bottom-thermal {
4066 polling-delay-passive = <250>;
4068 thermal-sensors = <&tsens0 11>;
4071 cpu4_bottom_alert0: trip-point0 {
4077 cpu4_bottom_alert1: trip-point1 {
4083 cpu4_bottom_crit: cpu-crit {
4090 cooling-maps {
4093 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4100 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4108 cpu5-bottom-thermal {
4109 polling-delay-passive = <250>;
4111 thermal-sensors = <&tsens0 12>;
4114 cpu5_bottom_alert0: trip-point0 {
4120 cpu5_bottom_alert1: trip-point1 {
4126 cpu5_bottom_crit: cpu-crit {
4133 cooling-maps {
4136 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4143 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4151 cpu6-bottom-thermal {
4152 polling-delay-passive = <250>;
4154 thermal-sensors = <&tsens0 13>;
4157 cpu6_bottom_alert0: trip-point0 {
4163 cpu6_bottom_alert1: trip-point1 {
4169 cpu6_bottom_crit: cpu-crit {
4176 cooling-maps {
4179 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4186 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4194 cpu7-bottom-thermal {
4195 polling-delay-passive = <250>;
4197 thermal-sensors = <&tsens0 14>;
4200 cpu7_bottom_alert0: trip-point0 {
4206 cpu7_bottom_alert1: trip-point1 {
4212 cpu7_bottom_crit: cpu-crit {
4219 cooling-maps {
4222 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4229 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4237 aoss0-thermal {
4238 polling-delay-passive = <250>;
4240 thermal-sensors = <&tsens0 0>;
4243 aoss0_alert0: trip-point0 {
4251 cluster0-thermal {
4252 polling-delay-passive = <250>;
4254 thermal-sensors = <&tsens0 5>;
4257 cluster0_alert0: trip-point0 {
4262 cluster0_crit: cluster0-crit {
4270 cluster1-thermal {
4271 polling-delay-passive = <250>;
4273 thermal-sensors = <&tsens0 6>;
4276 cluster1_alert0: trip-point0 {
4281 cluster1_crit: cluster1-crit {
4289 aoss1-thermal {
4290 polling-delay-passive = <250>;
4292 thermal-sensors = <&tsens1 0>;
4295 aoss1_alert0: trip-point0 {
4303 gpu-top-thermal {
4304 polling-delay-passive = <250>;
4306 thermal-sensors = <&tsens1 1>;
4308 cooling-maps {
4311 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4316 gpu_top_alert0: trip-point0 {
4322 trip-point1 {
4328 trip-point2 {
4336 gpu-bottom-thermal {
4337 polling-delay-passive = <250>;
4339 thermal-sensors = <&tsens1 2>;
4341 cooling-maps {
4344 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4349 gpu_bottom_alert0: trip-point0 {
4355 trip-point1 {
4361 trip-point2 {
4369 nspss1-thermal {
4370 polling-delay-passive = <250>;
4372 thermal-sensors = <&tsens1 3>;
4375 nspss1_alert0: trip-point0 {
4383 nspss2-thermal {
4384 polling-delay-passive = <250>;
4386 thermal-sensors = <&tsens1 4>;
4389 nspss2_alert0: trip-point0 {
4397 nspss3-thermal {
4398 polling-delay-passive = <250>;
4400 thermal-sensors = <&tsens1 5>;
4403 nspss3_alert0: trip-point0 {
4411 video-thermal {
4412 polling-delay-passive = <250>;
4414 thermal-sensors = <&tsens1 6>;
4417 video_alert0: trip-point0 {
4425 mem-thermal {
4426 polling-delay-passive = <250>;
4428 thermal-sensors = <&tsens1 7>;
4431 mem_alert0: trip-point0 {
4439 modem1-top-thermal {
4440 polling-delay-passive = <250>;
4442 thermal-sensors = <&tsens1 8>;
4445 modem1_alert0: trip-point0 {
4453 modem2-top-thermal {
4454 polling-delay-passive = <250>;
4456 thermal-sensors = <&tsens1 9>;
4459 modem2_alert0: trip-point0 {
4467 modem3-top-thermal {
4468 polling-delay-passive = <250>;
4470 thermal-sensors = <&tsens1 10>;
4473 modem3_alert0: trip-point0 {
4481 modem4-top-thermal {
4482 polling-delay-passive = <250>;
4484 thermal-sensors = <&tsens1 11>;
4487 modem4_alert0: trip-point0 {
4495 camera-top-thermal {
4496 polling-delay-passive = <250>;
4498 thermal-sensors = <&tsens1 12>;
4501 camera1_alert0: trip-point0 {
4509 cam-bottom-thermal {
4510 polling-delay-passive = <250>;
4512 thermal-sensors = <&tsens1 13>;
4515 camera2_alert0: trip-point0 {
4525 compatible = "arm,armv8-timer";