Lines Matching +full:cpu +full:- +full:crit
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interconnect/qcom,sm8350.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
9 #include <dt-bindings/clock/qcom,gcc-sm8350.h>
10 #include <dt-bindings/clock/qcom,gpucc-sm8350.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/firmware/qcom,scm.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interconnect/qcom,icc.h>
16 #include <dt-bindings/interconnect/qcom,sm8350.h>
17 #include <dt-bindings/mailbox/qcom-ipcc.h>
18 #include <dt-bindings/phy/phy-qcom-qmp.h>
19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/power/qcom,rpmhpd.h>
21 #include <dt-bindings/soc/qcom,apr.h>
22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
23 #include <dt-bindings/sound/qcom,q6afe.h>
24 #include <dt-bindings/thermal/thermal.h>
25 #include <dt-bindings/interconnect/qcom,sm8350.h>
28 interrupt-parent = <&intc>;
30 #address-cells = <2>;
31 #size-cells = <2>;
36 xo_board: xo-board {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-frequency = <38400000>;
40 clock-output-names = "xo_board";
43 sleep_clk: sleep-clk {
44 compatible = "fixed-clock";
45 clock-frequency = <32764>;
46 #clock-cells = <0>;
51 #address-cells = <2>;
52 #size-cells = <0>;
54 cpu0: cpu@0 {
55 device_type = "cpu";
56 compatible = "arm,cortex-a55";
59 enable-method = "psci";
60 next-level-cache = <&l2_0>;
61 qcom,freq-domain = <&cpufreq_hw 0>;
62 power-domains = <&cpu_pd0>;
63 power-domain-names = "psci";
64 #cooling-cells = <2>;
65 l2_0: l2-cache {
67 cache-level = <2>;
68 cache-unified;
69 next-level-cache = <&l3_0>;
70 l3_0: l3-cache {
72 cache-level = <3>;
73 cache-unified;
78 cpu1: cpu@100 {
79 device_type = "cpu";
80 compatible = "arm,cortex-a55";
83 enable-method = "psci";
84 next-level-cache = <&l2_100>;
85 qcom,freq-domain = <&cpufreq_hw 0>;
86 power-domains = <&cpu_pd1>;
87 power-domain-names = "psci";
88 #cooling-cells = <2>;
89 l2_100: l2-cache {
91 cache-level = <2>;
92 cache-unified;
93 next-level-cache = <&l3_0>;
97 cpu2: cpu@200 {
98 device_type = "cpu";
99 compatible = "arm,cortex-a55";
102 enable-method = "psci";
103 next-level-cache = <&l2_200>;
104 qcom,freq-domain = <&cpufreq_hw 0>;
105 power-domains = <&cpu_pd2>;
106 power-domain-names = "psci";
107 #cooling-cells = <2>;
108 l2_200: l2-cache {
110 cache-level = <2>;
111 cache-unified;
112 next-level-cache = <&l3_0>;
116 cpu3: cpu@300 {
117 device_type = "cpu";
118 compatible = "arm,cortex-a55";
121 enable-method = "psci";
122 next-level-cache = <&l2_300>;
123 qcom,freq-domain = <&cpufreq_hw 0>;
124 power-domains = <&cpu_pd3>;
125 power-domain-names = "psci";
126 #cooling-cells = <2>;
127 l2_300: l2-cache {
129 cache-level = <2>;
130 cache-unified;
131 next-level-cache = <&l3_0>;
135 cpu4: cpu@400 {
136 device_type = "cpu";
137 compatible = "arm,cortex-a78";
140 enable-method = "psci";
141 next-level-cache = <&l2_400>;
142 qcom,freq-domain = <&cpufreq_hw 1>;
143 power-domains = <&cpu_pd4>;
144 power-domain-names = "psci";
145 #cooling-cells = <2>;
146 l2_400: l2-cache {
148 cache-level = <2>;
149 cache-unified;
150 next-level-cache = <&l3_0>;
154 cpu5: cpu@500 {
155 device_type = "cpu";
156 compatible = "arm,cortex-a78";
159 enable-method = "psci";
160 next-level-cache = <&l2_500>;
161 qcom,freq-domain = <&cpufreq_hw 1>;
162 power-domains = <&cpu_pd5>;
163 power-domain-names = "psci";
164 #cooling-cells = <2>;
165 l2_500: l2-cache {
167 cache-level = <2>;
168 cache-unified;
169 next-level-cache = <&l3_0>;
173 cpu6: cpu@600 {
174 device_type = "cpu";
175 compatible = "arm,cortex-a78";
178 enable-method = "psci";
179 next-level-cache = <&l2_600>;
180 qcom,freq-domain = <&cpufreq_hw 1>;
181 power-domains = <&cpu_pd6>;
182 power-domain-names = "psci";
183 #cooling-cells = <2>;
184 l2_600: l2-cache {
186 cache-level = <2>;
187 cache-unified;
188 next-level-cache = <&l3_0>;
192 cpu7: cpu@700 {
193 device_type = "cpu";
194 compatible = "arm,cortex-x1";
197 enable-method = "psci";
198 next-level-cache = <&l2_700>;
199 qcom,freq-domain = <&cpufreq_hw 2>;
200 power-domains = <&cpu_pd7>;
201 power-domain-names = "psci";
202 #cooling-cells = <2>;
203 l2_700: l2-cache {
205 cache-level = <2>;
206 cache-unified;
207 next-level-cache = <&l3_0>;
211 cpu-map {
214 cpu = <&cpu0>;
218 cpu = <&cpu1>;
222 cpu = <&cpu2>;
226 cpu = <&cpu3>;
230 cpu = <&cpu4>;
234 cpu = <&cpu5>;
238 cpu = <&cpu6>;
242 cpu = <&cpu7>;
247 idle-states {
248 entry-method = "psci";
250 little_cpu_sleep_0: cpu-sleep-0-0 {
251 compatible = "arm,idle-state";
252 idle-state-name = "silver-rail-power-collapse";
253 arm,psci-suspend-param = <0x40000004>;
254 entry-latency-us = <360>;
255 exit-latency-us = <531>;
256 min-residency-us = <3934>;
257 local-timer-stop;
260 big_cpu_sleep_0: cpu-sleep-1-0 {
261 compatible = "arm,idle-state";
262 idle-state-name = "gold-rail-power-collapse";
263 arm,psci-suspend-param = <0x40000004>;
264 entry-latency-us = <702>;
265 exit-latency-us = <1061>;
266 min-residency-us = <4488>;
267 local-timer-stop;
271 domain-idle-states {
272 cluster_sleep_apss_off: cluster-sleep-0 {
273 compatible = "domain-idle-state";
274 arm,psci-suspend-param = <0x41000044>;
275 entry-latency-us = <2752>;
276 exit-latency-us = <3048>;
277 min-residency-us = <6118>;
280 cluster_sleep_aoss_sleep: cluster-sleep-1 {
281 compatible = "domain-idle-state";
282 arm,psci-suspend-param = <0x4100c344>;
283 entry-latency-us = <3263>;
284 exit-latency-us = <6562>;
285 min-residency-us = <9987>;
292 compatible = "qcom,scm-sm8350", "qcom,scm";
293 qcom,dload-mode = <&tcsr 0x13000>;
294 #reset-cells = <1>;
304 pmu-a55 {
305 compatible = "arm,cortex-a55-pmu";
309 pmu-a78 {
310 compatible = "arm,cortex-a78-pmu";
314 pmu-x1 {
315 compatible = "arm,cortex-x1-pmu";
320 compatible = "arm,psci-1.0";
323 cpu_pd0: power-domain-cpu0 {
324 #power-domain-cells = <0>;
325 power-domains = <&cluster_pd>;
326 domain-idle-states = <&little_cpu_sleep_0>;
329 cpu_pd1: power-domain-cpu1 {
330 #power-domain-cells = <0>;
331 power-domains = <&cluster_pd>;
332 domain-idle-states = <&little_cpu_sleep_0>;
335 cpu_pd2: power-domain-cpu2 {
336 #power-domain-cells = <0>;
337 power-domains = <&cluster_pd>;
338 domain-idle-states = <&little_cpu_sleep_0>;
341 cpu_pd3: power-domain-cpu3 {
342 #power-domain-cells = <0>;
343 power-domains = <&cluster_pd>;
344 domain-idle-states = <&little_cpu_sleep_0>;
347 cpu_pd4: power-domain-cpu4 {
348 #power-domain-cells = <0>;
349 power-domains = <&cluster_pd>;
350 domain-idle-states = <&big_cpu_sleep_0>;
353 cpu_pd5: power-domain-cpu5 {
354 #power-domain-cells = <0>;
355 power-domains = <&cluster_pd>;
356 domain-idle-states = <&big_cpu_sleep_0>;
359 cpu_pd6: power-domain-cpu6 {
360 #power-domain-cells = <0>;
361 power-domains = <&cluster_pd>;
362 domain-idle-states = <&big_cpu_sleep_0>;
365 cpu_pd7: power-domain-cpu7 {
366 #power-domain-cells = <0>;
367 power-domains = <&cluster_pd>;
368 domain-idle-states = <&big_cpu_sleep_0>;
371 cluster_pd: power-domain-cpu-cluster0 {
372 #power-domain-cells = <0>;
373 domain-idle-states = <&cluster_sleep_apss_off &cluster_sleep_aoss_sleep>;
377 qup_opp_table_100mhz: opp-table-qup100mhz {
378 compatible = "operating-points-v2";
380 opp-50000000 {
381 opp-hz = /bits/ 64 <50000000>;
382 required-opps = <&rpmhpd_opp_min_svs>;
385 opp-75000000 {
386 opp-hz = /bits/ 64 <75000000>;
387 required-opps = <&rpmhpd_opp_low_svs>;
390 opp-100000000 {
391 opp-hz = /bits/ 64 <100000000>;
392 required-opps = <&rpmhpd_opp_svs>;
396 qup_opp_table_120mhz: opp-table-qup120mhz {
397 compatible = "operating-points-v2";
399 opp-50000000 {
400 opp-hz = /bits/ 64 <50000000>;
401 required-opps = <&rpmhpd_opp_min_svs>;
404 opp-75000000 {
405 opp-hz = /bits/ 64 <75000000>;
406 required-opps = <&rpmhpd_opp_low_svs>;
409 opp-120000000 {
410 opp-hz = /bits/ 64 <120000000>;
411 required-opps = <&rpmhpd_opp_svs>;
415 reserved_memory: reserved-memory {
416 #address-cells = <2>;
417 #size-cells = <2>;
422 no-map;
426 no-map;
431 compatible = "qcom,cmd-db";
433 no-map;
438 no-map;
445 no-map;
450 no-map;
455 no-map;
460 no-map;
465 no-map;
470 no-map;
475 no-map;
480 no-map;
485 no-map;
490 no-map;
495 no-map;
500 no-map;
505 no-map;
510 no-map;
514 compatible = "qcom,rmtfs-mem";
516 no-map;
518 qcom,client-id = <1>;
524 no-map;
529 no-map;
534 no-map;
539 no-map;
544 no-map;
549 no-map;
553 smp2p-adsp {
556 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
562 qcom,local-pid = <0>;
563 qcom,remote-pid = <2>;
565 smp2p_adsp_out: master-kernel {
566 qcom,entry-name = "master-kernel";
567 #qcom,smem-state-cells = <1>;
570 smp2p_adsp_in: slave-kernel {
571 qcom,entry-name = "slave-kernel";
572 interrupt-controller;
573 #interrupt-cells = <2>;
577 smp2p-cdsp {
580 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
586 qcom,local-pid = <0>;
587 qcom,remote-pid = <5>;
589 smp2p_cdsp_out: master-kernel {
590 qcom,entry-name = "master-kernel";
591 #qcom,smem-state-cells = <1>;
594 smp2p_cdsp_in: slave-kernel {
595 qcom,entry-name = "slave-kernel";
596 interrupt-controller;
597 #interrupt-cells = <2>;
601 smp2p-modem {
604 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
610 qcom,local-pid = <0>;
611 qcom,remote-pid = <1>;
613 smp2p_modem_out: master-kernel {
614 qcom,entry-name = "master-kernel";
615 #qcom,smem-state-cells = <1>;
618 smp2p_modem_in: slave-kernel {
619 qcom,entry-name = "slave-kernel";
620 interrupt-controller;
621 #interrupt-cells = <2>;
624 ipa_smp2p_out: ipa-ap-to-modem {
625 qcom,entry-name = "ipa";
626 #qcom,smem-state-cells = <1>;
629 ipa_smp2p_in: ipa-modem-to-ap {
630 qcom,entry-name = "ipa";
631 interrupt-controller;
632 #interrupt-cells = <2>;
636 smp2p-slpi {
639 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
645 qcom,local-pid = <0>;
646 qcom,remote-pid = <3>;
648 smp2p_slpi_out: master-kernel {
649 qcom,entry-name = "master-kernel";
650 #qcom,smem-state-cells = <1>;
653 smp2p_slpi_in: slave-kernel {
654 qcom,entry-name = "slave-kernel";
655 interrupt-controller;
656 #interrupt-cells = <2>;
661 #address-cells = <2>;
662 #size-cells = <2>;
664 dma-ranges = <0 0 0 0 0x10 0>;
665 compatible = "simple-bus";
667 gcc: clock-controller@100000 {
668 compatible = "qcom,gcc-sm8350";
670 #clock-cells = <1>;
671 #reset-cells = <1>;
672 #power-domain-cells = <1>;
673 clock-names = "bi_tcxo",
700 compatible = "qcom,sm8350-ipcc", "qcom,ipcc";
703 interrupt-controller;
704 #interrupt-cells = <3>;
705 #mbox-cells = <2>;
708 gpi_dma2: dma-controller@800000 {
709 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
723 dma-channels = <12>;
724 dma-channel-mask = <0xff>;
726 #dma-cells = <3>;
731 compatible = "qcom,geni-se-qup";
733 clock-names = "m-ahb", "s-ahb";
737 #address-cells = <2>;
738 #size-cells = <2>;
743 compatible = "qcom,geni-i2c";
745 clock-names = "se";
747 pinctrl-names = "default";
748 pinctrl-0 = <&qup_i2c14_default>;
752 dma-names = "tx", "rx";
753 #address-cells = <1>;
754 #size-cells = <0>;
759 compatible = "qcom,geni-spi";
761 clock-names = "se";
764 power-domains = <&rpmhpd RPMHPD_CX>;
765 operating-points-v2 = <&qup_opp_table_120mhz>;
768 dma-names = "tx", "rx";
769 #address-cells = <1>;
770 #size-cells = <0>;
775 compatible = "qcom,geni-i2c";
777 clock-names = "se";
779 pinctrl-names = "default";
780 pinctrl-0 = <&qup_i2c15_default>;
784 dma-names = "tx", "rx";
785 #address-cells = <1>;
786 #size-cells = <0>;
791 compatible = "qcom,geni-spi";
793 clock-names = "se";
796 power-domains = <&rpmhpd RPMHPD_CX>;
797 operating-points-v2 = <&qup_opp_table_120mhz>;
800 dma-names = "tx", "rx";
801 #address-cells = <1>;
802 #size-cells = <0>;
807 compatible = "qcom,geni-i2c";
809 clock-names = "se";
811 pinctrl-names = "default";
812 pinctrl-0 = <&qup_i2c16_default>;
816 dma-names = "tx", "rx";
817 #address-cells = <1>;
818 #size-cells = <0>;
823 compatible = "qcom,geni-spi";
825 clock-names = "se";
828 power-domains = <&rpmhpd RPMHPD_CX>;
829 operating-points-v2 = <&qup_opp_table_100mhz>;
832 dma-names = "tx", "rx";
833 #address-cells = <1>;
834 #size-cells = <0>;
839 compatible = "qcom,geni-i2c";
841 clock-names = "se";
843 pinctrl-names = "default";
844 pinctrl-0 = <&qup_i2c17_default>;
848 dma-names = "tx", "rx";
849 #address-cells = <1>;
850 #size-cells = <0>;
855 compatible = "qcom,geni-spi";
857 clock-names = "se";
860 power-domains = <&rpmhpd RPMHPD_CX>;
861 operating-points-v2 = <&qup_opp_table_100mhz>;
864 dma-names = "tx", "rx";
865 #address-cells = <1>;
866 #size-cells = <0>;
870 /* QUP no. 18 seems to be strictly SPI/UART-only */
873 compatible = "qcom,geni-spi";
875 clock-names = "se";
878 power-domains = <&rpmhpd RPMHPD_CX>;
879 operating-points-v2 = <&qup_opp_table_100mhz>;
882 dma-names = "tx", "rx";
883 #address-cells = <1>;
884 #size-cells = <0>;
889 compatible = "qcom,geni-uart";
891 clock-names = "se";
893 pinctrl-names = "default";
894 pinctrl-0 = <&qup_uart18_default>;
896 power-domains = <&rpmhpd RPMHPD_CX>;
897 operating-points-v2 = <&qup_opp_table_100mhz>;
902 compatible = "qcom,geni-i2c";
904 clock-names = "se";
906 pinctrl-names = "default";
907 pinctrl-0 = <&qup_i2c19_default>;
911 dma-names = "tx", "rx";
912 #address-cells = <1>;
913 #size-cells = <0>;
918 compatible = "qcom,geni-spi";
920 clock-names = "se";
923 power-domains = <&rpmhpd RPMHPD_CX>;
924 operating-points-v2 = <&qup_opp_table_100mhz>;
927 dma-names = "tx", "rx";
928 #address-cells = <1>;
929 #size-cells = <0>;
934 gpi_dma0: dma-controller@900000 {
935 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
949 dma-channels = <12>;
950 dma-channel-mask = <0x7e>;
952 #dma-cells = <3>;
957 compatible = "qcom,geni-se-qup";
959 clock-names = "m-ahb", "s-ahb";
963 #address-cells = <2>;
964 #size-cells = <2>;
969 compatible = "qcom,geni-i2c";
971 clock-names = "se";
973 pinctrl-names = "default";
974 pinctrl-0 = <&qup_i2c0_default>;
978 dma-names = "tx", "rx";
979 #address-cells = <1>;
980 #size-cells = <0>;
985 compatible = "qcom,geni-spi";
987 clock-names = "se";
990 power-domains = <&rpmhpd RPMHPD_CX>;
991 operating-points-v2 = <&qup_opp_table_100mhz>;
994 dma-names = "tx", "rx";
995 #address-cells = <1>;
996 #size-cells = <0>;
1001 compatible = "qcom,geni-i2c";
1003 clock-names = "se";
1005 pinctrl-names = "default";
1006 pinctrl-0 = <&qup_i2c1_default>;
1010 dma-names = "tx", "rx";
1011 #address-cells = <1>;
1012 #size-cells = <0>;
1017 compatible = "qcom,geni-spi";
1019 clock-names = "se";
1022 power-domains = <&rpmhpd RPMHPD_CX>;
1023 operating-points-v2 = <&qup_opp_table_100mhz>;
1026 dma-names = "tx", "rx";
1027 #address-cells = <1>;
1028 #size-cells = <0>;
1033 compatible = "qcom,geni-i2c";
1035 clock-names = "se";
1037 pinctrl-names = "default";
1038 pinctrl-0 = <&qup_i2c2_default>;
1042 dma-names = "tx", "rx";
1043 #address-cells = <1>;
1044 #size-cells = <0>;
1049 compatible = "qcom,geni-spi";
1051 clock-names = "se";
1054 power-domains = <&rpmhpd RPMHPD_CX>;
1055 operating-points-v2 = <&qup_opp_table_100mhz>;
1058 dma-names = "tx", "rx";
1059 #address-cells = <1>;
1060 #size-cells = <0>;
1065 compatible = "qcom,geni-debug-uart";
1067 clock-names = "se";
1069 pinctrl-names = "default";
1070 pinctrl-0 = <&qup_uart3_default_state>;
1072 power-domains = <&rpmhpd RPMHPD_CX>;
1073 operating-points-v2 = <&qup_opp_table_100mhz>;
1077 /* QUP no. 3 seems to be strictly SPI-only */
1080 compatible = "qcom,geni-spi";
1082 clock-names = "se";
1085 power-domains = <&rpmhpd RPMHPD_CX>;
1086 operating-points-v2 = <&qup_opp_table_100mhz>;
1089 dma-names = "tx", "rx";
1090 #address-cells = <1>;
1091 #size-cells = <0>;
1096 compatible = "qcom,geni-i2c";
1098 clock-names = "se";
1100 pinctrl-names = "default";
1101 pinctrl-0 = <&qup_i2c4_default>;
1105 dma-names = "tx", "rx";
1106 #address-cells = <1>;
1107 #size-cells = <0>;
1112 compatible = "qcom,geni-spi";
1114 clock-names = "se";
1117 power-domains = <&rpmhpd RPMHPD_CX>;
1118 operating-points-v2 = <&qup_opp_table_100mhz>;
1121 dma-names = "tx", "rx";
1122 #address-cells = <1>;
1123 #size-cells = <0>;
1128 compatible = "qcom,geni-i2c";
1130 clock-names = "se";
1132 pinctrl-names = "default";
1133 pinctrl-0 = <&qup_i2c5_default>;
1137 dma-names = "tx", "rx";
1138 #address-cells = <1>;
1139 #size-cells = <0>;
1144 compatible = "qcom,geni-spi";
1146 clock-names = "se";
1149 power-domains = <&rpmhpd RPMHPD_CX>;
1150 operating-points-v2 = <&qup_opp_table_100mhz>;
1153 dma-names = "tx", "rx";
1154 #address-cells = <1>;
1155 #size-cells = <0>;
1160 compatible = "qcom,geni-i2c";
1162 clock-names = "se";
1164 pinctrl-names = "default";
1165 pinctrl-0 = <&qup_i2c6_default>;
1169 dma-names = "tx", "rx";
1170 #address-cells = <1>;
1171 #size-cells = <0>;
1176 compatible = "qcom,geni-spi";
1178 clock-names = "se";
1181 power-domains = <&rpmhpd RPMHPD_CX>;
1182 operating-points-v2 = <&qup_opp_table_100mhz>;
1185 dma-names = "tx", "rx";
1186 #address-cells = <1>;
1187 #size-cells = <0>;
1192 compatible = "qcom,geni-uart";
1194 clock-names = "se";
1196 pinctrl-names = "default";
1197 pinctrl-0 = <&qup_uart6_default>;
1199 power-domains = <&rpmhpd RPMHPD_CX>;
1200 operating-points-v2 = <&qup_opp_table_100mhz>;
1205 compatible = "qcom,geni-i2c";
1207 clock-names = "se";
1209 pinctrl-names = "default";
1210 pinctrl-0 = <&qup_i2c7_default>;
1214 dma-names = "tx", "rx";
1215 #address-cells = <1>;
1216 #size-cells = <0>;
1221 compatible = "qcom,geni-spi";
1223 clock-names = "se";
1226 power-domains = <&rpmhpd RPMHPD_CX>;
1227 operating-points-v2 = <&qup_opp_table_100mhz>;
1230 dma-names = "tx", "rx";
1231 #address-cells = <1>;
1232 #size-cells = <0>;
1237 gpi_dma1: dma-controller@a00000 {
1238 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
1252 dma-channels = <12>;
1253 dma-channel-mask = <0xff>;
1255 #dma-cells = <3>;
1260 compatible = "qcom,geni-se-qup";
1262 clock-names = "m-ahb", "s-ahb";
1266 #address-cells = <2>;
1267 #size-cells = <2>;
1272 compatible = "qcom,geni-i2c";
1274 clock-names = "se";
1276 pinctrl-names = "default";
1277 pinctrl-0 = <&qup_i2c8_default>;
1281 dma-names = "tx", "rx";
1282 #address-cells = <1>;
1283 #size-cells = <0>;
1288 compatible = "qcom,geni-spi";
1290 clock-names = "se";
1293 power-domains = <&rpmhpd RPMHPD_CX>;
1294 operating-points-v2 = <&qup_opp_table_120mhz>;
1297 dma-names = "tx", "rx";
1298 #address-cells = <1>;
1299 #size-cells = <0>;
1304 compatible = "qcom,geni-i2c";
1306 clock-names = "se";
1308 pinctrl-names = "default";
1309 pinctrl-0 = <&qup_i2c9_default>;
1313 dma-names = "tx", "rx";
1314 #address-cells = <1>;
1315 #size-cells = <0>;
1320 compatible = "qcom,geni-spi";
1322 clock-names = "se";
1325 power-domains = <&rpmhpd RPMHPD_CX>;
1326 operating-points-v2 = <&qup_opp_table_100mhz>;
1329 dma-names = "tx", "rx";
1330 #address-cells = <1>;
1331 #size-cells = <0>;
1336 compatible = "qcom,geni-i2c";
1338 clock-names = "se";
1340 pinctrl-names = "default";
1341 pinctrl-0 = <&qup_i2c10_default>;
1345 dma-names = "tx", "rx";
1346 #address-cells = <1>;
1347 #size-cells = <0>;
1352 compatible = "qcom,geni-spi";
1354 clock-names = "se";
1357 power-domains = <&rpmhpd RPMHPD_CX>;
1358 operating-points-v2 = <&qup_opp_table_100mhz>;
1361 dma-names = "tx", "rx";
1362 #address-cells = <1>;
1363 #size-cells = <0>;
1368 compatible = "qcom,geni-i2c";
1370 clock-names = "se";
1372 pinctrl-names = "default";
1373 pinctrl-0 = <&qup_i2c11_default>;
1377 dma-names = "tx", "rx";
1378 #address-cells = <1>;
1379 #size-cells = <0>;
1384 compatible = "qcom,geni-spi";
1386 clock-names = "se";
1389 power-domains = <&rpmhpd RPMHPD_CX>;
1390 operating-points-v2 = <&qup_opp_table_100mhz>;
1393 dma-names = "tx", "rx";
1394 #address-cells = <1>;
1395 #size-cells = <0>;
1400 compatible = "qcom,geni-i2c";
1402 clock-names = "se";
1404 pinctrl-names = "default";
1405 pinctrl-0 = <&qup_i2c12_default>;
1409 dma-names = "tx", "rx";
1410 #address-cells = <1>;
1411 #size-cells = <0>;
1416 compatible = "qcom,geni-spi";
1418 clock-names = "se";
1421 power-domains = <&rpmhpd RPMHPD_CX>;
1422 operating-points-v2 = <&qup_opp_table_100mhz>;
1425 dma-names = "tx", "rx";
1426 #address-cells = <1>;
1427 #size-cells = <0>;
1432 compatible = "qcom,geni-i2c";
1434 clock-names = "se";
1436 pinctrl-names = "default";
1437 pinctrl-0 = <&qup_i2c13_default>;
1441 dma-names = "tx", "rx";
1442 #address-cells = <1>;
1443 #size-cells = <0>;
1448 compatible = "qcom,geni-spi";
1450 clock-names = "se";
1453 power-domains = <&rpmhpd RPMHPD_CX>;
1454 operating-points-v2 = <&qup_opp_table_100mhz>;
1457 dma-names = "tx", "rx";
1458 #address-cells = <1>;
1459 #size-cells = <0>;
1465 compatible = "qcom,prng-ee";
1468 clock-names = "core";
1472 compatible = "qcom,sm8350-config-noc";
1474 #interconnect-cells = <2>;
1475 qcom,bcm-voters = <&apps_bcm_voter>;
1479 compatible = "qcom,sm8350-mc-virt";
1481 #interconnect-cells = <2>;
1482 qcom,bcm-voters = <&apps_bcm_voter>;
1486 compatible = "qcom,sm8350-system-noc";
1488 #interconnect-cells = <2>;
1489 qcom,bcm-voters = <&apps_bcm_voter>;
1493 compatible = "qcom,sm8350-aggre1-noc";
1495 #interconnect-cells = <2>;
1496 qcom,bcm-voters = <&apps_bcm_voter>;
1500 compatible = "qcom,sm8350-aggre2-noc";
1502 #interconnect-cells = <2>;
1503 qcom,bcm-voters = <&apps_bcm_voter>;
1507 compatible = "qcom,sm8350-mmss-noc";
1509 #interconnect-cells = <2>;
1510 qcom,bcm-voters = <&apps_bcm_voter>;
1514 compatible = "qcom,pcie-sm8350";
1520 reg-names = "parf", "dbi", "elbi", "atu", "config";
1522 linux,pci-domain = <0>;
1523 bus-range = <0x00 0xff>;
1524 num-lanes = <1>;
1526 #address-cells = <3>;
1527 #size-cells = <2>;
1540 interrupt-names = "msi0",
1548 #interrupt-cells = <1>;
1549 interrupt-map-mask = <0 0 0 0x7>;
1550 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1564 clock-names = "aux",
1574 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1578 reset-names = "pci";
1580 power-domains = <&gcc PCIE_0_GDSC>;
1583 phy-names = "pciephy";
1590 bus-range = <0x01 0xff>;
1592 #address-cells = <3>;
1593 #size-cells = <2>;
1599 compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy";
1606 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
1609 reset-names = "phy";
1611 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>;
1612 assigned-clock-rates = <100000000>;
1614 #clock-cells = <0>;
1615 clock-output-names = "pcie_0_pipe_clk";
1617 #phy-cells = <0>;
1623 compatible = "qcom,pcie-sm8350";
1629 reg-names = "parf", "dbi", "elbi", "atu", "config";
1631 linux,pci-domain = <1>;
1632 bus-range = <0x00 0xff>;
1633 num-lanes = <2>;
1635 #address-cells = <3>;
1636 #size-cells = <2>;
1649 interrupt-names = "msi0",
1657 #interrupt-cells = <1>;
1658 interrupt-map-mask = <0 0 0 0x7>;
1659 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1672 clock-names = "aux",
1681 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1685 reset-names = "pci";
1687 power-domains = <&gcc PCIE_1_GDSC>;
1690 phy-names = "pciephy";
1697 bus-range = <0x01 0xff>;
1699 #address-cells = <3>;
1700 #size-cells = <2>;
1706 compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy";
1713 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
1716 reset-names = "phy";
1718 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
1719 assigned-clock-rates = <100000000>;
1721 #clock-cells = <0>;
1722 clock-output-names = "pcie_1_pipe_clk";
1724 #phy-cells = <0>;
1730 compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
1731 "jedec,ufs-2.0";
1735 phy-names = "ufsphy";
1736 lanes-per-direction = <2>;
1737 #reset-cells = <1>;
1739 reset-names = "rst";
1741 power-domains = <&gcc UFS_PHY_GDSC>;
1744 dma-coherent;
1746 clock-names =
1768 interconnect-names = "ufs-ddr", "cpu-ufs";
1769 freq-table-hz =
1782 compatible = "qcom,sm8350-qmp-ufs-phy";
1788 clock-names = "ref",
1792 power-domains = <&gcc UFS_PHY_GDSC>;
1795 reset-names = "ufsphy";
1797 #clock-cells = <1>;
1798 #phy-cells = <0>;
1803 cryptobam: dma-controller@1dc4000 {
1804 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
1807 #dma-cells = <1>;
1809 qcom,controlled-remotely;
1817 compatible = "qcom,sm8350-qce", "qcom,sm8150-qce", "qcom,qce";
1820 dma-names = "rx", "tx";
1824 interconnect-names = "memory";
1830 compatible = "qcom,sm8350-ipa";
1837 reg-names = "ipa-reg",
1838 "ipa-shared",
1841 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>,
1845 interrupt-names = "ipa",
1847 "ipa-clock-query",
1848 "ipa-setup-ready";
1851 clock-names = "core";
1855 interconnect-names = "memory",
1860 qcom,smem-states = <&ipa_smp2p_out 0>,
1862 qcom,smem-state-names = "ipa-clock-enabled-valid",
1863 "ipa-clock-enabled";
1869 compatible = "qcom,tcsr-mutex";
1871 #hwlock-cells = <1>;
1875 compatible = "qcom,sm8350-tcsr", "syscon";
1880 compatible = "qcom,sm8350-adsp-pas";
1883 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
1888 interrupt-names = "wdog", "fatal", "ready",
1889 "handover", "stop-ack";
1892 clock-names = "xo";
1894 power-domains = <&rpmhpd RPMHPD_LCX>,
1896 power-domain-names = "lcx", "lmx";
1898 memory-region = <&pil_adsp_mem>;
1902 qcom,smem-states = <&smp2p_adsp_out 0>;
1903 qcom,smem-state-names = "stop";
1907 glink-edge {
1908 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
1915 qcom,remote-pid = <2>;
1918 compatible = "qcom,apr-v2";
1919 qcom,glink-channels = "apr_audio_svc";
1921 #address-cells = <1>;
1922 #size-cells = <0>;
1927 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
1933 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
1936 compatible = "qcom,q6afe-dais";
1937 #address-cells = <1>;
1938 #size-cells = <0>;
1939 #sound-dai-cells = <1>;
1942 q6afecc: clock-controller {
1943 compatible = "qcom,q6afe-clocks";
1944 #clock-cells = <2>;
1951 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
1954 compatible = "qcom,q6asm-dais";
1955 #address-cells = <1>;
1956 #size-cells = <0>;
1957 #sound-dai-cells = <1>;
1977 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
1980 compatible = "qcom,q6adm-routing";
1981 #sound-dai-cells = <0>;
1988 qcom,glink-channels = "fastrpcglink-apps-dsp";
1990 qcom,non-secure-domain;
1991 #address-cells = <1>;
1992 #size-cells = <0>;
1994 compute-cb@3 {
1995 compatible = "qcom,fastrpc-compute-cb";
2000 compute-cb@4 {
2001 compatible = "qcom,fastrpc-compute-cb";
2006 compute-cb@5 {
2007 compatible = "qcom,fastrpc-compute-cb";
2016 compatible = "qcom,sm8350-lpass-lpi-pinctrl";
2022 clock-names = "core", "audio";
2024 gpio-controller;
2025 #gpio-cells = <2>;
2026 gpio-ranges = <&lpass_tlmm 0 0 15>;
2030 compatible = "qcom,adreno-660.1", "qcom,adreno";
2035 reg-names = "kgsl_3d0_reg_memory",
2043 operating-points-v2 = <&gpu_opp_table>;
2046 #cooling-cells = <2>;
2050 zap-shader {
2051 memory-region = <&pil_gpu_mem>;
2055 gpu_opp_table: opp-table {
2056 compatible = "operating-points-v2";
2058 opp-840000000 {
2059 opp-hz = /bits/ 64 <840000000>;
2060 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2063 opp-778000000 {
2064 opp-hz = /bits/ 64 <778000000>;
2065 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2068 opp-738000000 {
2069 opp-hz = /bits/ 64 <738000000>;
2070 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2073 opp-676000000 {
2074 opp-hz = /bits/ 64 <676000000>;
2075 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2078 opp-608000000 {
2079 opp-hz = /bits/ 64 <608000000>;
2080 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2083 opp-540000000 {
2084 opp-hz = /bits/ 64 <540000000>;
2085 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2088 opp-491000000 {
2089 opp-hz = /bits/ 64 <491000000>;
2090 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2093 opp-443000000 {
2094 opp-hz = /bits/ 64 <443000000>;
2095 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2098 opp-379000000 {
2099 opp-hz = /bits/ 64 <379000000>;
2100 opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>;
2103 opp-315000000 {
2104 opp-hz = /bits/ 64 <315000000>;
2105 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2111 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu";
2116 reg-names = "gmu", "rscc", "gmu_pdc";
2120 interrupt-names = "hfi", "gmu";
2129 clock-names = "gmu",
2137 power-domains = <&gpucc GPU_CX_GDSC>,
2139 power-domain-names = "cx",
2144 operating-points-v2 = <&gmu_opp_table>;
2146 gmu_opp_table: opp-table {
2147 compatible = "operating-points-v2";
2149 opp-200000000 {
2150 opp-hz = /bits/ 64 <200000000>;
2151 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2156 gpucc: clock-controller@3d90000 {
2157 compatible = "qcom,sm8350-gpucc";
2162 clock-names = "bi_tcxo",
2165 #clock-cells = <1>;
2166 #reset-cells = <1>;
2167 #power-domain-cells = <1>;
2171 compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu",
2172 "qcom,smmu-500", "arm,mmu-500";
2174 #iommu-cells = <2>;
2175 #global-interrupts = <2>;
2196 clock-names = "bus",
2204 power-domains = <&gpucc GPU_CX_GDSC>;
2205 dma-coherent;
2209 compatible = "qcom,sm8350-lpass-ag-noc";
2211 #interconnect-cells = <2>;
2212 qcom,bcm-voters = <&apps_bcm_voter>;
2216 compatible = "qcom,sm8350-mpss-pas";
2219 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2225 interrupt-names = "wdog", "fatal", "ready", "handover",
2226 "stop-ack", "shutdown-ack";
2229 clock-names = "xo";
2231 power-domains = <&rpmhpd RPMHPD_CX>,
2233 power-domain-names = "cx", "mss";
2237 memory-region = <&pil_modem_mem>;
2241 qcom,smem-states = <&smp2p_modem_out 0>;
2242 qcom,smem-state-names = "stop";
2246 glink-edge {
2247 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2253 qcom,remote-pid = <1>;
2258 compatible = "qcom,sm8350-slpi-pas";
2261 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2266 interrupt-names = "wdog", "fatal", "ready",
2267 "handover", "stop-ack";
2270 clock-names = "xo";
2272 power-domains = <&rpmhpd RPMHPD_LCX>,
2274 power-domain-names = "lcx", "lmx";
2276 memory-region = <&pil_slpi_mem>;
2280 qcom,smem-states = <&smp2p_slpi_out 0>;
2281 qcom,smem-state-names = "stop";
2285 glink-edge {
2286 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2293 qcom,remote-pid = <3>;
2297 qcom,glink-channels = "fastrpcglink-apps-dsp";
2299 qcom,non-secure-domain;
2300 #address-cells = <1>;
2301 #size-cells = <0>;
2303 compute-cb@1 {
2304 compatible = "qcom,fastrpc-compute-cb";
2309 compute-cb@2 {
2310 compatible = "qcom,fastrpc-compute-cb";
2315 compute-cb@3 {
2316 compatible = "qcom,fastrpc-compute-cb";
2319 /* note: shared-cb = <4> in downstream */
2326 compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5";
2331 interrupt-names = "hc_irq", "pwr_irq";
2336 clock-names = "iface", "core", "xo";
2340 interconnect-names = "sdhc-ddr","cpu-sdhc";
2342 power-domains = <&rpmhpd RPMHPD_CX>;
2343 operating-points-v2 = <&sdhc2_opp_table>;
2344 bus-width = <4>;
2345 dma-coherent;
2349 sdhc2_opp_table: opp-table {
2350 compatible = "operating-points-v2";
2352 opp-100000000 {
2353 opp-hz = /bits/ 64 <100000000>;
2354 required-opps = <&rpmhpd_opp_low_svs>;
2357 opp-202000000 {
2358 opp-hz = /bits/ 64 <202000000>;
2359 required-opps = <&rpmhpd_opp_svs_l1>;
2365 compatible = "qcom,sm8350-usb-hs-phy",
2366 "qcom,usb-snps-hs-7nm-phy";
2369 #phy-cells = <0>;
2372 clock-names = "ref";
2378 compatible = "qcom,sm8250-usb-hs-phy",
2379 "qcom,usb-snps-hs-7nm-phy";
2382 #phy-cells = <0>;
2385 clock-names = "ref";
2391 compatible = "qcom,sm8350-refgen-regulator",
2392 "qcom,sm8250-refgen-regulator";
2397 compatible = "qcom,sm8350-qmp-usb3-dp-phy";
2404 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2408 reset-names = "phy", "common";
2410 #clock-cells = <1>;
2411 #phy-cells = <1>;
2413 orientation-switch;
2418 #address-cells = <1>;
2419 #size-cells = <0>;
2432 remote-endpoint = <&usb_1_dwc3_ss>;
2440 remote-endpoint = <&mdss_dp_out>;
2447 compatible = "qcom,sm8350-qmp-usb3-uni-phy";
2455 clock-names = "aux",
2459 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2460 #clock-cells = <0>;
2461 #phy-cells = <0>;
2465 reset-names = "phy",
2470 compatible = "qcom,sm8350-dc-noc";
2472 #interconnect-cells = <2>;
2473 qcom,bcm-voters = <&apps_bcm_voter>;
2477 compatible = "qcom,sm8350-gem-noc";
2479 #interconnect-cells = <2>;
2480 qcom,bcm-voters = <&apps_bcm_voter>;
2483 system-cache-controller@9200000 {
2484 compatible = "qcom,sm8350-llcc";
2488 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2493 compatible = "qcom,sm8350-compute-noc";
2495 #interconnect-cells = <2>;
2496 qcom,bcm-voters = <&apps_bcm_voter>;
2500 compatible = "qcom,sm8350-cdsp-pas";
2503 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2508 interrupt-names = "wdog", "fatal", "ready",
2509 "handover", "stop-ack";
2512 clock-names = "xo";
2514 power-domains = <&rpmhpd RPMHPD_CX>,
2516 power-domain-names = "cx", "mxc";
2520 memory-region = <&pil_cdsp_mem>;
2524 qcom,smem-states = <&smp2p_cdsp_out 0>;
2525 qcom,smem-state-names = "stop";
2529 glink-edge {
2530 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2537 qcom,remote-pid = <5>;
2541 qcom,glink-channels = "fastrpcglink-apps-dsp";
2543 qcom,non-secure-domain;
2544 #address-cells = <1>;
2545 #size-cells = <0>;
2547 compute-cb@1 {
2548 compatible = "qcom,fastrpc-compute-cb";
2554 compute-cb@2 {
2555 compatible = "qcom,fastrpc-compute-cb";
2561 compute-cb@3 {
2562 compatible = "qcom,fastrpc-compute-cb";
2568 compute-cb@4 {
2569 compatible = "qcom,fastrpc-compute-cb";
2575 compute-cb@5 {
2576 compatible = "qcom,fastrpc-compute-cb";
2582 compute-cb@6 {
2583 compatible = "qcom,fastrpc-compute-cb";
2589 compute-cb@7 {
2590 compatible = "qcom,fastrpc-compute-cb";
2596 compute-cb@8 {
2597 compatible = "qcom,fastrpc-compute-cb";
2609 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2612 #address-cells = <2>;
2613 #size-cells = <2>;
2621 clock-names = "cfg_noc",
2627 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2629 assigned-clock-rates = <19200000>, <200000000>;
2631 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
2636 interrupt-names = "pwr_event",
2642 power-domains = <&gcc USB30_PRIM_GDSC>;
2648 interconnect-names = "usb-ddr", "apps-usb";
2657 snps,dis-u1-entry-quirk;
2658 snps,dis-u2-entry-quirk;
2660 phy-names = "usb2-phy", "usb3-phy";
2663 #address-cells = <1>;
2664 #size-cells = <0>;
2677 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
2685 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2688 #address-cells = <2>;
2689 #size-cells = <2>;
2698 clock-names = "cfg_noc",
2705 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2707 assigned-clock-rates = <19200000>, <200000000>;
2709 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
2714 interrupt-names = "pwr_event",
2720 power-domains = <&gcc USB30_SEC_GDSC>;
2726 interconnect-names = "usb-ddr", "apps-usb";
2735 snps,dis-u1-entry-quirk;
2736 snps,dis-u2-entry-quirk;
2738 phy-names = "usb2-phy", "usb3-phy";
2742 mdss: display-subsystem@ae00000 {
2743 compatible = "qcom,sm8350-mdss";
2745 reg-names = "mdss";
2751 interconnect-names = "mdp0-mem",
2752 "mdp1-mem",
2753 "cpu-cfg";
2755 power-domains = <&dispcc MDSS_GDSC>;
2762 clock-names = "iface", "bus", "nrt_bus", "core";
2765 interrupt-controller;
2766 #interrupt-cells = <1>;
2772 #address-cells = <2>;
2773 #size-cells = <2>;
2776 mdss_mdp: display-controller@ae01000 {
2777 compatible = "qcom,sm8350-dpu";
2780 reg-names = "mdp", "vbif";
2788 clock-names = "bus",
2795 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2796 assigned-clock-rates = <19200000>;
2798 operating-points-v2 = <&dpu_opp_table>;
2799 power-domains = <&rpmhpd RPMHPD_MMCX>;
2801 interrupt-parent = <&mdss>;
2804 dpu_opp_table: opp-table {
2805 compatible = "operating-points-v2";
2807 /* TODO: opp-200000000 should work with
2812 opp-200000000 {
2813 opp-hz = /bits/ 64 <200000000>;
2814 required-opps = <&rpmhpd_opp_svs>;
2817 opp-300000000 {
2818 opp-hz = /bits/ 64 <300000000>;
2819 required-opps = <&rpmhpd_opp_svs>;
2822 opp-345000000 {
2823 opp-hz = /bits/ 64 <345000000>;
2824 required-opps = <&rpmhpd_opp_svs_l1>;
2827 opp-460000000 {
2828 opp-hz = /bits/ 64 <460000000>;
2829 required-opps = <&rpmhpd_opp_nom>;
2834 #address-cells = <1>;
2835 #size-cells = <0>;
2840 remote-endpoint = <&mdss_dsi0_in>;
2847 remote-endpoint = <&mdss_dsi1_in>;
2854 remote-endpoint = <&mdss_dp_in>;
2860 mdss_dp: displayport-controller@ae90000 {
2861 compatible = "qcom,sm8350-dp";
2867 interrupt-parent = <&mdss>;
2874 clock-names = "core_iface",
2880 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
2882 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2886 phy-names = "dp";
2888 #sound-dai-cells = <0>;
2890 operating-points-v2 = <&dp_opp_table>;
2891 power-domains = <&rpmhpd RPMHPD_MMCX>;
2896 #address-cells = <1>;
2897 #size-cells = <0>;
2902 remote-endpoint = <&dpu_intf0_out>;
2910 remote-endpoint = <&usb_1_qmpphy_dp_in>;
2915 dp_opp_table: opp-table {
2916 compatible = "operating-points-v2";
2918 opp-160000000 {
2919 opp-hz = /bits/ 64 <160000000>;
2920 required-opps = <&rpmhpd_opp_low_svs>;
2923 opp-270000000 {
2924 opp-hz = /bits/ 64 <270000000>;
2925 required-opps = <&rpmhpd_opp_svs>;
2928 opp-540000000 {
2929 opp-hz = /bits/ 64 <540000000>;
2930 required-opps = <&rpmhpd_opp_svs_l1>;
2933 opp-810000000 {
2934 opp-hz = /bits/ 64 <810000000>;
2935 required-opps = <&rpmhpd_opp_nom>;
2941 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2943 reg-names = "dsi_ctrl";
2945 interrupt-parent = <&mdss>;
2954 clock-names = "byte",
2961 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2963 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2966 operating-points-v2 = <&dsi0_opp_table>;
2967 power-domains = <&rpmhpd RPMHPD_MMCX>;
2968 refgen-supply = <&refgen>;
2972 #address-cells = <1>;
2973 #size-cells = <0>;
2977 dsi0_opp_table: opp-table {
2978 compatible = "operating-points-v2";
2980 /* TODO: opp-187500000 should work with
2985 opp-187500000 {
2986 opp-hz = /bits/ 64 <187500000>;
2987 required-opps = <&rpmhpd_opp_svs>;
2990 opp-300000000 {
2991 opp-hz = /bits/ 64 <300000000>;
2992 required-opps = <&rpmhpd_opp_svs>;
2995 opp-358000000 {
2996 opp-hz = /bits/ 64 <358000000>;
2997 required-opps = <&rpmhpd_opp_svs_l1>;
3002 #address-cells = <1>;
3003 #size-cells = <0>;
3008 remote-endpoint = <&dpu_intf1_out>;
3021 compatible = "qcom,sm8350-dsi-phy-5nm";
3025 reg-names = "dsi_phy",
3029 #clock-cells = <1>;
3030 #phy-cells = <0>;
3034 clock-names = "iface", "ref";
3040 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3042 reg-names = "dsi_ctrl";
3044 interrupt-parent = <&mdss>;
3053 clock-names = "byte",
3060 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
3062 assigned-clock-parents = <&mdss_dsi1_phy 0>,
3065 operating-points-v2 = <&dsi1_opp_table>;
3066 power-domains = <&rpmhpd RPMHPD_MMCX>;
3067 refgen-supply = <&refgen>;
3071 #address-cells = <1>;
3072 #size-cells = <0>;
3076 dsi1_opp_table: opp-table {
3077 compatible = "operating-points-v2";
3079 /* TODO: opp-187500000 should work with
3084 opp-187500000 {
3085 opp-hz = /bits/ 64 <187500000>;
3086 required-opps = <&rpmhpd_opp_svs>;
3089 opp-300000000 {
3090 opp-hz = /bits/ 64 <300000000>;
3091 required-opps = <&rpmhpd_opp_svs>;
3094 opp-358000000 {
3095 opp-hz = /bits/ 64 <358000000>;
3096 required-opps = <&rpmhpd_opp_svs_l1>;
3101 #address-cells = <1>;
3102 #size-cells = <0>;
3107 remote-endpoint = <&dpu_intf2_out>;
3120 compatible = "qcom,sm8350-dsi-phy-5nm";
3124 reg-names = "dsi_phy",
3128 #clock-cells = <1>;
3129 #phy-cells = <0>;
3133 clock-names = "iface", "ref";
3139 dispcc: clock-controller@af00000 {
3140 compatible = "qcom,sm8350-dispcc";
3147 clock-names = "bi_tcxo",
3154 #clock-cells = <1>;
3155 #reset-cells = <1>;
3156 #power-domain-cells = <1>;
3158 power-domains = <&rpmhpd RPMHPD_MMCX>;
3161 pdc: interrupt-controller@b220000 {
3162 compatible = "qcom,sm8350-pdc", "qcom,pdc";
3164 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
3168 #interrupt-cells = <2>;
3169 interrupt-parent = <&intc>;
3170 interrupt-controller;
3173 tsens0: thermal-sensor@c263000 {
3174 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
3178 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
3180 interrupt-names = "uplow", "critical";
3181 #thermal-sensor-cells = <1>;
3184 tsens1: thermal-sensor@c265000 {
3185 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
3189 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
3191 interrupt-names = "uplow", "critical";
3192 #thermal-sensor-cells = <1>;
3195 aoss_qmp: power-management@c300000 {
3196 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp";
3198 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3202 #clock-cells = <0>;
3206 compatible = "qcom,rpmh-stats";
3211 compatible = "qcom,spmi-pmic-arb";
3217 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3218 interrupt-names = "periph_irq";
3219 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3222 #address-cells = <2>;
3223 #size-cells = <0>;
3224 interrupt-controller;
3225 #interrupt-cells = <4>;
3229 compatible = "qcom,sm8350-tlmm";
3232 gpio-controller;
3233 #gpio-cells = <2>;
3234 interrupt-controller;
3235 #interrupt-cells = <2>;
3236 gpio-ranges = <&tlmm 0 0 204>;
3237 wakeup-parent = <&pdc>;
3239 sdc2_default_state: sdc2-default-state {
3240 clk-pins {
3242 drive-strength = <16>;
3243 bias-disable;
3246 cmd-pins {
3248 drive-strength = <16>;
3249 bias-pull-up;
3252 data-pins {
3254 drive-strength = <16>;
3255 bias-pull-up;
3259 sdc2_sleep_state: sdc2-sleep-state {
3260 clk-pins {
3262 drive-strength = <2>;
3263 bias-disable;
3266 cmd-pins {
3268 drive-strength = <2>;
3269 bias-pull-up;
3272 data-pins {
3274 drive-strength = <2>;
3275 bias-pull-up;
3279 qup_uart3_default_state: qup-uart3-default-state {
3280 rx-pins {
3284 tx-pins {
3290 qup_uart6_default: qup-uart6-default-state {
3293 drive-strength = <2>;
3294 bias-disable;
3297 qup_uart18_default: qup-uart18-default-state {
3300 drive-strength = <2>;
3301 bias-disable;
3304 qup_i2c0_default: qup-i2c0-default-state {
3307 drive-strength = <2>;
3308 bias-pull-up;
3311 qup_i2c1_default: qup-i2c1-default-state {
3314 drive-strength = <2>;
3315 bias-pull-up;
3318 qup_i2c2_default: qup-i2c2-default-state {
3321 drive-strength = <2>;
3322 bias-pull-up;
3325 qup_i2c4_default: qup-i2c4-default-state {
3328 drive-strength = <2>;
3329 bias-pull-up;
3332 qup_i2c5_default: qup-i2c5-default-state {
3335 drive-strength = <2>;
3336 bias-pull-up;
3339 qup_i2c6_default: qup-i2c6-default-state {
3342 drive-strength = <2>;
3343 bias-pull-up;
3346 qup_i2c7_default: qup-i2c7-default-state {
3349 drive-strength = <2>;
3350 bias-disable;
3353 qup_i2c8_default: qup-i2c8-default-state {
3356 drive-strength = <2>;
3357 bias-pull-up;
3360 qup_i2c9_default: qup-i2c9-default-state {
3363 drive-strength = <2>;
3364 bias-pull-up;
3367 qup_i2c10_default: qup-i2c10-default-state {
3370 drive-strength = <2>;
3371 bias-pull-up;
3374 qup_i2c11_default: qup-i2c11-default-state {
3377 drive-strength = <2>;
3378 bias-pull-up;
3381 qup_i2c12_default: qup-i2c12-default-state {
3384 drive-strength = <2>;
3385 bias-pull-up;
3388 qup_i2c13_default: qup-i2c13-default-state {
3391 drive-strength = <2>;
3392 bias-pull-up;
3395 qup_i2c14_default: qup-i2c14-default-state {
3398 drive-strength = <2>;
3399 bias-disable;
3402 qup_i2c15_default: qup-i2c15-default-state {
3405 drive-strength = <2>;
3406 bias-disable;
3409 qup_i2c16_default: qup-i2c16-default-state {
3412 drive-strength = <2>;
3413 bias-disable;
3416 qup_i2c17_default: qup-i2c17-default-state {
3419 drive-strength = <2>;
3420 bias-disable;
3423 qup_i2c19_default: qup-i2c19-default-state {
3426 drive-strength = <2>;
3427 bias-disable;
3432 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500";
3434 #iommu-cells = <2>;
3435 #global-interrupts = <2>;
3534 dma-coherent;
3537 intc: interrupt-controller@17a00000 {
3538 compatible = "arm,gic-v3";
3539 #interrupt-cells = <3>;
3540 interrupt-controller;
3541 #redistributor-regions = <1>;
3542 redistributor-stride = <0 0x20000>;
3549 compatible = "arm,armv7-timer-mem";
3550 #address-cells = <1>;
3551 #size-cells = <1>;
3554 clock-frequency = <19200000>;
3557 frame-number = <0>;
3565 frame-number = <1>;
3572 frame-number = <2>;
3579 frame-number = <3>;
3586 frame-number = <4>;
3593 frame-number = <5>;
3600 frame-number = <6>;
3609 compatible = "qcom,rpmh-rsc";
3613 reg-names = "drv-0", "drv-1", "drv-2";
3617 qcom,tcs-offset = <0xd00>;
3618 qcom,drv-id = <2>;
3619 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
3621 power-domains = <&cluster_pd>;
3623 rpmhcc: clock-controller {
3624 compatible = "qcom,sm8350-rpmh-clk";
3625 #clock-cells = <1>;
3626 clock-names = "xo";
3630 rpmhpd: power-controller {
3631 compatible = "qcom,sm8350-rpmhpd";
3632 #power-domain-cells = <1>;
3633 operating-points-v2 = <&rpmhpd_opp_table>;
3635 rpmhpd_opp_table: opp-table {
3636 compatible = "operating-points-v2";
3639 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3643 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3647 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3651 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3655 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3659 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3663 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3667 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3671 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3675 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3680 apps_bcm_voter: bcm-voter {
3681 compatible = "qcom,bcm-voter";
3686 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
3690 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
3695 interrupt-names = "dcvsh-irq-0",
3696 "dcvsh-irq-1",
3697 "dcvsh-irq-2";
3700 clock-names = "xo", "alternate";
3702 #freq-domain-cells = <1>;
3703 #clock-cells = <1>;
3707 thermal_zones: thermal-zones {
3708 cpu0-thermal {
3709 polling-delay-passive = <250>;
3711 thermal-sensors = <&tsens0 1>;
3714 cpu0_alert0: trip-point0 {
3720 cpu0_alert1: trip-point1 {
3726 cpu0_crit: cpu-crit {
3733 cooling-maps {
3736 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3743 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3751 cpu1-thermal {
3752 polling-delay-passive = <250>;
3754 thermal-sensors = <&tsens0 2>;
3757 cpu1_alert0: trip-point0 {
3763 cpu1_alert1: trip-point1 {
3769 cpu1_crit: cpu-crit {
3776 cooling-maps {
3779 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3786 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3794 cpu2-thermal {
3795 polling-delay-passive = <250>;
3797 thermal-sensors = <&tsens0 3>;
3800 cpu2_alert0: trip-point0 {
3806 cpu2_alert1: trip-point1 {
3812 cpu2_crit: cpu-crit {
3819 cooling-maps {
3822 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3829 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3837 cpu3-thermal {
3838 polling-delay-passive = <250>;
3840 thermal-sensors = <&tsens0 4>;
3843 cpu3_alert0: trip-point0 {
3849 cpu3_alert1: trip-point1 {
3855 cpu3_crit: cpu-crit {
3862 cooling-maps {
3865 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3872 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3880 cpu4-top-thermal {
3881 polling-delay-passive = <250>;
3883 thermal-sensors = <&tsens0 7>;
3886 cpu4_top_alert0: trip-point0 {
3892 cpu4_top_alert1: trip-point1 {
3898 cpu4_top_crit: cpu-crit {
3905 cooling-maps {
3908 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3915 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3923 cpu5-top-thermal {
3924 polling-delay-passive = <250>;
3926 thermal-sensors = <&tsens0 8>;
3929 cpu5_top_alert0: trip-point0 {
3935 cpu5_top_alert1: trip-point1 {
3941 cpu5_top_crit: cpu-crit {
3948 cooling-maps {
3951 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3958 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3966 cpu6-top-thermal {
3967 polling-delay-passive = <250>;
3969 thermal-sensors = <&tsens0 9>;
3972 cpu6_top_alert0: trip-point0 {
3978 cpu6_top_alert1: trip-point1 {
3984 cpu6_top_crit: cpu-crit {
3991 cooling-maps {
3994 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4001 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4009 cpu7-top-thermal {
4010 polling-delay-passive = <250>;
4012 thermal-sensors = <&tsens0 10>;
4015 cpu7_top_alert0: trip-point0 {
4021 cpu7_top_alert1: trip-point1 {
4027 cpu7_top_crit: cpu-crit {
4034 cooling-maps {
4037 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4044 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4052 cpu4-bottom-thermal {
4053 polling-delay-passive = <250>;
4055 thermal-sensors = <&tsens0 11>;
4058 cpu4_bottom_alert0: trip-point0 {
4064 cpu4_bottom_alert1: trip-point1 {
4070 cpu4_bottom_crit: cpu-crit {
4077 cooling-maps {
4080 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4087 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4095 cpu5-bottom-thermal {
4096 polling-delay-passive = <250>;
4098 thermal-sensors = <&tsens0 12>;
4101 cpu5_bottom_alert0: trip-point0 {
4107 cpu5_bottom_alert1: trip-point1 {
4113 cpu5_bottom_crit: cpu-crit {
4120 cooling-maps {
4123 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4130 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4138 cpu6-bottom-thermal {
4139 polling-delay-passive = <250>;
4141 thermal-sensors = <&tsens0 13>;
4144 cpu6_bottom_alert0: trip-point0 {
4150 cpu6_bottom_alert1: trip-point1 {
4156 cpu6_bottom_crit: cpu-crit {
4163 cooling-maps {
4166 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4173 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4181 cpu7-bottom-thermal {
4182 polling-delay-passive = <250>;
4184 thermal-sensors = <&tsens0 14>;
4187 cpu7_bottom_alert0: trip-point0 {
4193 cpu7_bottom_alert1: trip-point1 {
4199 cpu7_bottom_crit: cpu-crit {
4206 cooling-maps {
4209 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4216 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4224 aoss0-thermal {
4225 polling-delay-passive = <250>;
4227 thermal-sensors = <&tsens0 0>;
4230 aoss0_alert0: trip-point0 {
4238 cluster0-thermal {
4239 polling-delay-passive = <250>;
4241 thermal-sensors = <&tsens0 5>;
4244 cluster0_alert0: trip-point0 {
4249 cluster0_crit: cluster0-crit {
4257 cluster1-thermal {
4258 polling-delay-passive = <250>;
4260 thermal-sensors = <&tsens0 6>;
4263 cluster1_alert0: trip-point0 {
4268 cluster1_crit: cluster1-crit {
4276 aoss1-thermal {
4277 polling-delay-passive = <250>;
4279 thermal-sensors = <&tsens1 0>;
4282 aoss1_alert0: trip-point0 {
4290 gpu-top-thermal {
4291 polling-delay-passive = <250>;
4293 thermal-sensors = <&tsens1 1>;
4295 cooling-maps {
4298 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4303 gpu_top_alert0: trip-point0 {
4309 trip-point1 {
4315 trip-point2 {
4323 gpu-bottom-thermal {
4324 polling-delay-passive = <250>;
4326 thermal-sensors = <&tsens1 2>;
4328 cooling-maps {
4331 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4336 gpu_bottom_alert0: trip-point0 {
4342 trip-point1 {
4348 trip-point2 {
4356 nspss1-thermal {
4357 polling-delay-passive = <250>;
4359 thermal-sensors = <&tsens1 3>;
4362 nspss1_alert0: trip-point0 {
4370 nspss2-thermal {
4371 polling-delay-passive = <250>;
4373 thermal-sensors = <&tsens1 4>;
4376 nspss2_alert0: trip-point0 {
4384 nspss3-thermal {
4385 polling-delay-passive = <250>;
4387 thermal-sensors = <&tsens1 5>;
4390 nspss3_alert0: trip-point0 {
4398 video-thermal {
4399 polling-delay-passive = <250>;
4401 thermal-sensors = <&tsens1 6>;
4404 video_alert0: trip-point0 {
4412 mem-thermal {
4413 polling-delay-passive = <250>;
4415 thermal-sensors = <&tsens1 7>;
4418 mem_alert0: trip-point0 {
4426 modem1-top-thermal {
4427 polling-delay-passive = <250>;
4429 thermal-sensors = <&tsens1 8>;
4432 modem1_alert0: trip-point0 {
4440 modem2-top-thermal {
4441 polling-delay-passive = <250>;
4443 thermal-sensors = <&tsens1 9>;
4446 modem2_alert0: trip-point0 {
4454 modem3-top-thermal {
4455 polling-delay-passive = <250>;
4457 thermal-sensors = <&tsens1 10>;
4460 modem3_alert0: trip-point0 {
4468 modem4-top-thermal {
4469 polling-delay-passive = <250>;
4471 thermal-sensors = <&tsens1 11>;
4474 modem4_alert0: trip-point0 {
4482 camera-top-thermal {
4483 polling-delay-passive = <250>;
4485 thermal-sensors = <&tsens1 12>;
4488 camera1_alert0: trip-point0 {
4496 cam-bottom-thermal {
4497 polling-delay-passive = <250>;
4499 thermal-sensors = <&tsens1 13>;
4502 camera2_alert0: trip-point0 {
4512 compatible = "arm,armv8-timer";