Lines Matching +full:1 +full:d84000
141 clocks = <&cpufreq_hw 1>;
144 qcom,freq-domain = <&cpufreq_hw 1>;
160 clocks = <&cpufreq_hw 1>;
163 qcom,freq-domain = <&cpufreq_hw 1>;
179 clocks = <&cpufreq_hw 1>;
182 qcom,freq-domain = <&cpufreq_hw 1>;
262 big_cpu_sleep_0: cpu-sleep-1-0 {
282 cluster_sleep_aoss_sleep: cluster-sleep-1 {
296 #reset-cells = <1>;
520 qcom,client-id = <1>;
569 #qcom,smem-state-cells = <1>;
593 #qcom,smem-state-cells = <1>;
613 qcom,remote-pid = <1>;
617 #qcom,smem-state-cells = <1>;
628 #qcom,smem-state-cells = <1>;
652 #qcom,smem-state-cells = <1>;
672 #clock-cells = <1>;
673 #reset-cells = <1>;
674 #power-domain-cells = <1>;
695 <&ufs_mem_phy 1>,
753 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
755 #address-cells = <1>;
769 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
771 #address-cells = <1>;
784 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
785 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
787 #address-cells = <1>;
800 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
801 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
803 #address-cells = <1>;
817 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
819 #address-cells = <1>;
833 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
835 #address-cells = <1>;
849 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
851 #address-cells = <1>;
865 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
867 #address-cells = <1>;
883 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
885 #address-cells = <1>;
912 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
914 #address-cells = <1>;
928 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
930 #address-cells = <1>;
979 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
981 #address-cells = <1>;
995 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
997 #address-cells = <1>;
1010 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1011 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1013 #address-cells = <1>;
1026 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1027 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1029 #address-cells = <1>;
1043 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1045 #address-cells = <1>;
1059 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1061 #address-cells = <1>;
1090 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1092 #address-cells = <1>;
1106 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1108 #address-cells = <1>;
1122 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1124 #address-cells = <1>;
1138 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1140 #address-cells = <1>;
1154 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1156 #address-cells = <1>;
1170 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1172 #address-cells = <1>;
1186 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1188 #address-cells = <1>;
1215 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1217 #address-cells = <1>;
1231 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1233 #address-cells = <1>;
1282 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1284 #address-cells = <1>;
1298 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1300 #address-cells = <1>;
1313 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1314 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1316 #address-cells = <1>;
1329 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1330 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1332 #address-cells = <1>;
1346 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1348 #address-cells = <1>;
1362 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1364 #address-cells = <1>;
1378 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1380 #address-cells = <1>;
1394 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1396 #address-cells = <1>;
1410 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1412 #address-cells = <1>;
1426 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1428 #address-cells = <1>;
1442 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1444 #address-cells = <1>;
1458 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1460 #address-cells = <1>;
1515 pcie0: pcie@1c00000 {
1526 num-lanes = <1>;
1552 #interrupt-cells = <1>;
1554 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1602 pcie0_phy: phy@1c06000 {
1626 pcie1: pcie@1c08000 {
1635 linux,pci-domain = <1>;
1663 #interrupt-cells = <1>;
1665 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1711 pcie1_phy: phy@1c0e000 {
1735 ufs_mem_hc: ufshc@1d84000 {
1743 #reset-cells = <1>;
1787 ufs_mem_phy: phy@1d87000 {
1803 #clock-cells = <1>;
1809 cryptobam: dma-controller@1dc4000 {
1813 #dma-cells = <1>;
1822 crypto: crypto@1dfa000 {
1833 ipa: ipa@1e40000 {
1848 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1865 <&ipa_smp2p_out 1>;
1872 tcsr_mutex: hwlock@1f40000 {
1875 #hwlock-cells = <1>;
1878 tcsr: syscon@1fc0000 {
1889 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
1925 #address-cells = <1>;
1941 #address-cells = <1>;
1943 #sound-dai-cells = <1>;
1959 #address-cells = <1>;
1961 #sound-dai-cells = <1>;
1968 dai@1 {
1995 #address-cells = <1>;
2045 iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>;
2169 #clock-cells = <1>;
2170 #reset-cells = <1>;
2171 #power-domain-cells = <1>;
2225 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2257 qcom,remote-pid = <1>;
2267 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2304 #address-cells = <1>;
2307 compute-cb@1 {
2309 reg = <1>;
2414 #clock-cells = <1>;
2415 #phy-cells = <1>;
2422 #address-cells = <1>;
2432 port@1 {
2433 reg = <1>;
2509 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2548 #address-cells = <1>;
2551 compute-cb@1 {
2553 reg = <1>;
2668 #address-cells = <1>;
2678 port@1 {
2679 reg = <1>;
2772 #interrupt-cells = <1>;
2840 #address-cells = <1>;
2850 port@1 {
2851 reg = <1>;
2902 #address-cells = <1>;
2912 port@1 {
2913 reg = <1>;
2978 #address-cells = <1>;
3008 #address-cells = <1>;
3018 port@1 {
3019 reg = <1>;
3035 #clock-cells = <1>;
3077 #address-cells = <1>;
3107 #address-cells = <1>;
3117 port@1 {
3118 reg = <1>;
3134 #clock-cells = <1>;
3162 #clock-cells = <1>;
3163 #reset-cells = <1>;
3164 #power-domain-cells = <1>;
3172 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
3174 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>,
3189 #thermal-sensor-cells = <1>;
3200 #thermal-sensor-cells = <1>;
3227 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3549 #redistributor-regions = <1>;
3558 #address-cells = <1>;
3559 #size-cells = <1>;
3573 frame-number = <1>;
3621 reg-names = "drv-0", "drv-1", "drv-2";
3633 #clock-cells = <1>;
3640 #power-domain-cells = <1>;
3704 "dcvsh-irq-1",
3710 #freq-domain-cells = <1>;
3711 #clock-cells = <1>;
3719 thermal-sensors = <&tsens0 1>;
4301 thermal-sensors = <&tsens1 1>;