Lines Matching +full:0 +full:xae90400
38 #clock-cells = <0>;
46 #clock-cells = <0>;
52 #size-cells = <0>;
54 CPU0: cpu@0 {
57 reg = <0x0 0x0>;
58 clocks = <&cpufreq_hw 0>;
61 qcom,freq-domain = <&cpufreq_hw 0>;
81 reg = <0x0 0x100>;
82 clocks = <&cpufreq_hw 0>;
85 qcom,freq-domain = <&cpufreq_hw 0>;
100 reg = <0x0 0x200>;
101 clocks = <&cpufreq_hw 0>;
104 qcom,freq-domain = <&cpufreq_hw 0>;
119 reg = <0x0 0x300>;
120 clocks = <&cpufreq_hw 0>;
123 qcom,freq-domain = <&cpufreq_hw 0>;
138 reg = <0x0 0x400>;
157 reg = <0x0 0x500>;
176 reg = <0x0 0x600>;
195 reg = <0x0 0x700>;
250 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
253 arm,psci-suspend-param = <0x40000004>;
260 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
263 arm,psci-suspend-param = <0x40000004>;
272 CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 {
274 arm,psci-suspend-param = <0x41000044>;
282 arm,psci-suspend-param = <0x4100c344>;
293 qcom,dload-mode = <&tcsr 0x13000>;
301 reg = <0x0 0x80000000 0x0 0x0>;
324 #power-domain-cells = <0>;
330 #power-domain-cells = <0>;
336 #power-domain-cells = <0>;
342 #power-domain-cells = <0>;
348 #power-domain-cells = <0>;
354 #power-domain-cells = <0>;
360 #power-domain-cells = <0>;
366 #power-domain-cells = <0>;
372 #power-domain-cells = <0>;
421 reg = <0x0 0x80000000 0x0 0x600000>;
427 reg = <0x0 0x80700000 0x0 0x160000>;
432 reg = <0x0 0x80860000 0x0 0x20000>;
437 reg = <0x0 0x80880000 0x0 0x14000>;
443 reg = <0x0 0x80900000 0x0 0x200000>;
449 reg = <0x0 0x80b00000 0x0 0x100000>;
454 reg = <0x0 0x80c00000 0x0 0x4600000>;
459 reg = <0x0 0x85200000 0x0 0x500000>;
464 reg = <0x0 0x85700000 0x0 0x500000>;
469 reg = <0x0 0x85c00000 0x0 0x500000>;
474 reg = <0x0 0x86100000 0x0 0x2100000>;
479 reg = <0x0 0x88200000 0x0 0x1500000>;
484 reg = <0x0 0x89700000 0x0 0x1e00000>;
489 reg = <0x0 0x8b500000 0x0 0x10000>;
494 reg = <0x0 0x8b510000 0x0 0xa000>;
499 reg = <0x0 0x8b51a000 0x0 0x2000>;
504 reg = <0x0 0x8b600000 0x0 0x100000>;
509 reg = <0x0 0x8b800000 0x0 0x10000000>;
515 reg = <0x0 0x9b800000 0x0 0x280000>;
523 reg = <0x0 0xd0000000 0x0 0x800000>;
528 reg = <0x0 0xd0800000 0x0 0x76f7000>;
533 reg = <0x0 0xd7ef7000 0x0 0x9000>;
538 reg = <0x0 0xd7f00000 0x0 0x80000>;
543 reg = <0x0 0xd7f80000 0x0 0x80000>;
548 reg = <0x0 0xd8800000 0x0 0x6800000>;
562 qcom,local-pid = <0>;
586 qcom,local-pid = <0>;
610 qcom,local-pid = <0>;
645 qcom,local-pid = <0>;
660 soc: soc@0 {
663 ranges = <0 0 0 0 0x10 0>;
664 dma-ranges = <0 0 0 0 0x10 0>;
669 reg = <0x0 0x00100000 0x0 0x1f0000>;
689 <0>,
690 <0>,
691 <0>,
692 <&ufs_mem_phy 0>,
696 <0>;
701 reg = <0 0x00408000 0 0x1000>;
710 reg = <0 0x00800000 0 0x60000>;
724 dma-channel-mask = <0xff>;
725 iommus = <&apps_smmu 0x5f6 0x0>;
732 reg = <0x0 0x008c0000 0x0 0x6000>;
736 iommus = <&apps_smmu 0x5e3 0x0>;
744 reg = <0 0x00880000 0 0x4000>;
748 pinctrl-0 = <&qup_i2c14_default>;
750 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
751 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
754 #size-cells = <0>;
760 reg = <0 0x00880000 0 0x4000>;
766 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
767 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
770 #size-cells = <0>;
776 reg = <0 0x00884000 0 0x4000>;
780 pinctrl-0 = <&qup_i2c15_default>;
782 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
786 #size-cells = <0>;
792 reg = <0 0x00884000 0 0x4000>;
798 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
802 #size-cells = <0>;
808 reg = <0 0x00888000 0 0x4000>;
812 pinctrl-0 = <&qup_i2c16_default>;
814 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
818 #size-cells = <0>;
824 reg = <0 0x00888000 0 0x4000>;
830 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
834 #size-cells = <0>;
840 reg = <0 0x0088c000 0 0x4000>;
844 pinctrl-0 = <&qup_i2c17_default>;
846 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
850 #size-cells = <0>;
856 reg = <0 0x0088c000 0 0x4000>;
862 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
866 #size-cells = <0>;
874 reg = <0 0x00890000 0 0x4000>;
880 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
884 #size-cells = <0>;
890 reg = <0 0x00890000 0 0x4000>;
894 pinctrl-0 = <&qup_uart18_default>;
903 reg = <0 0x00894000 0 0x4000>;
907 pinctrl-0 = <&qup_i2c19_default>;
909 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
913 #size-cells = <0>;
919 reg = <0 0x00894000 0 0x4000>;
925 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
929 #size-cells = <0>;
936 reg = <0 0x00900000 0 0x60000>;
950 dma-channel-mask = <0x7e>;
951 iommus = <&apps_smmu 0x5b6 0x0>;
958 reg = <0x0 0x009c0000 0x0 0x6000>;
962 iommus = <&apps_smmu 0x5a3 0>;
970 reg = <0 0x00980000 0 0x4000>;
974 pinctrl-0 = <&qup_i2c0_default>;
976 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
977 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
980 #size-cells = <0>;
986 reg = <0 0x00980000 0 0x4000>;
992 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
993 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
996 #size-cells = <0>;
1002 reg = <0 0x00984000 0 0x4000>;
1006 pinctrl-0 = <&qup_i2c1_default>;
1008 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1012 #size-cells = <0>;
1018 reg = <0 0x00984000 0 0x4000>;
1024 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1028 #size-cells = <0>;
1034 reg = <0 0x00988000 0 0x4000>;
1038 pinctrl-0 = <&qup_i2c2_default>;
1040 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1044 #size-cells = <0>;
1050 reg = <0 0x00988000 0 0x4000>;
1056 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1060 #size-cells = <0>;
1066 reg = <0 0x0098c000 0 0x4000>;
1070 pinctrl-0 = <&qup_uart3_default_state>;
1081 reg = <0 0x0098c000 0 0x4000>;
1087 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1091 #size-cells = <0>;
1097 reg = <0 0x00990000 0 0x4000>;
1101 pinctrl-0 = <&qup_i2c4_default>;
1103 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1107 #size-cells = <0>;
1113 reg = <0 0x00990000 0 0x4000>;
1119 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1123 #size-cells = <0>;
1129 reg = <0 0x00994000 0 0x4000>;
1133 pinctrl-0 = <&qup_i2c5_default>;
1135 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1139 #size-cells = <0>;
1145 reg = <0 0x00994000 0 0x4000>;
1151 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1155 #size-cells = <0>;
1161 reg = <0 0x00998000 0 0x4000>;
1165 pinctrl-0 = <&qup_i2c6_default>;
1167 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1171 #size-cells = <0>;
1177 reg = <0 0x00998000 0 0x4000>;
1183 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1187 #size-cells = <0>;
1193 reg = <0 0x00998000 0 0x4000>;
1197 pinctrl-0 = <&qup_uart6_default>;
1206 reg = <0 0x0099c000 0 0x4000>;
1210 pinctrl-0 = <&qup_i2c7_default>;
1212 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1216 #size-cells = <0>;
1222 reg = <0 0x0099c000 0 0x4000>;
1228 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1232 #size-cells = <0>;
1239 reg = <0 0x00a00000 0 0x60000>;
1253 dma-channel-mask = <0xff>;
1254 iommus = <&apps_smmu 0x56 0x0>;
1261 reg = <0x0 0x00ac0000 0x0 0x6000>;
1265 iommus = <&apps_smmu 0x43 0>;
1273 reg = <0 0x00a80000 0 0x4000>;
1277 pinctrl-0 = <&qup_i2c8_default>;
1279 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1280 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1283 #size-cells = <0>;
1289 reg = <0 0x00a80000 0 0x4000>;
1295 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1296 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1299 #size-cells = <0>;
1305 reg = <0 0x00a84000 0 0x4000>;
1309 pinctrl-0 = <&qup_i2c9_default>;
1311 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1315 #size-cells = <0>;
1321 reg = <0 0x00a84000 0 0x4000>;
1327 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1331 #size-cells = <0>;
1337 reg = <0 0x00a88000 0 0x4000>;
1341 pinctrl-0 = <&qup_i2c10_default>;
1343 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1347 #size-cells = <0>;
1353 reg = <0 0x00a88000 0 0x4000>;
1359 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1363 #size-cells = <0>;
1369 reg = <0 0x00a8c000 0 0x4000>;
1373 pinctrl-0 = <&qup_i2c11_default>;
1375 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1379 #size-cells = <0>;
1385 reg = <0 0x00a8c000 0 0x4000>;
1391 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1395 #size-cells = <0>;
1401 reg = <0 0x00a90000 0 0x4000>;
1405 pinctrl-0 = <&qup_i2c12_default>;
1407 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1411 #size-cells = <0>;
1417 reg = <0 0x00a90000 0 0x4000>;
1423 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1427 #size-cells = <0>;
1433 reg = <0 0x00a94000 0 0x4000>;
1437 pinctrl-0 = <&qup_i2c13_default>;
1439 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1443 #size-cells = <0>;
1449 reg = <0 0x00a94000 0 0x4000>;
1455 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1459 #size-cells = <0>;
1466 reg = <0 0x010d3000 0 0x1000>;
1473 reg = <0 0x01500000 0 0xa580>;
1480 reg = <0 0x01580000 0 0x1000>;
1487 reg = <0 0x01680000 0 0x1c200>;
1494 reg = <0 0x016e0000 0 0x1f180>;
1501 reg = <0 0x01700000 0 0x33000>;
1508 reg = <0 0x01740000 0 0x1f080>;
1515 reg = <0 0x01c00000 0 0x3000>,
1516 <0 0x60000000 0 0xf1d>,
1517 <0 0x60000f20 0 0xa8>,
1518 <0 0x60001000 0 0x1000>,
1519 <0 0x60100000 0 0x100000>;
1522 linux,pci-domain = <0>;
1523 bus-range = <0x00 0xff>;
1529 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1530 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1549 interrupt-map-mask = <0 0 0 0x7>;
1550 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1551 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1552 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1553 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1574 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1575 <0x100 &apps_smmu 0x1c01 0x1>;
1587 pcie@0 {
1589 reg = <0x0 0x0 0x0 0x0 0x0>;
1590 bus-range = <0x01 0xff>;
1600 reg = <0 0x01c06000 0 0x2000>;
1614 #clock-cells = <0>;
1617 #phy-cells = <0>;
1624 reg = <0 0x01c08000 0 0x3000>,
1625 <0 0x40000000 0 0xf1d>,
1626 <0 0x40000f20 0 0xa8>,
1627 <0 0x40001000 0 0x1000>,
1628 <0 0x40100000 0 0x100000>;
1632 bus-range = <0x00 0xff>;
1638 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1639 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1658 interrupt-map-mask = <0 0 0 0x7>;
1659 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1660 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1661 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1662 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1681 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1682 <0x100 &apps_smmu 0x1c81 0x1>;
1694 pcie@0 {
1696 reg = <0x0 0x0 0x0 0x0 0x0>;
1697 bus-range = <0x01 0xff>;
1707 reg = <0 0x01c0e000 0 0x2000>;
1721 #clock-cells = <0>;
1724 #phy-cells = <0>;
1732 reg = <0 0x01d84000 0 0x3000>;
1743 iommus = <&apps_smmu 0xe0 0x0>;
1771 <0 0>,
1772 <0 0>,
1774 <0 0>,
1775 <0 0>,
1776 <0 0>,
1777 <0 0>;
1783 reg = <0 0x01d87000 0 0x1000>;
1794 resets = <&ufs_mem_hc 0>;
1798 #phy-cells = <0>;
1805 reg = <0 0x01dc4000 0 0x24000>;
1808 qcom,ee = <0>;
1810 iommus = <&apps_smmu 0x594 0x0011>,
1811 <&apps_smmu 0x596 0x0011>;
1818 reg = <0 0x01dfa000 0 0x6000>;
1821 iommus = <&apps_smmu 0x594 0x0011>,
1822 <&apps_smmu 0x596 0x0011>;
1823 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
1832 iommus = <&apps_smmu 0x5c0 0x0>,
1833 <&apps_smmu 0x5c2 0x0>;
1834 reg = <0 0x01e40000 0 0x8000>,
1835 <0 0x01e50000 0 0x4b20>,
1836 <0 0x01e04000 0 0x23000>;
1843 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1853 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1854 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1860 qcom,smem-states = <&ipa_smp2p_out 0>,
1870 reg = <0x0 0x01f40000 0x0 0x40000>;
1876 reg = <0x0 0x1fc0000 0x0 0x30000>;
1881 reg = <0 0x033c0000 0 0x20000>,
1882 <0 0x03550000 0 0x10000>;
1890 gpio-ranges = <&lpass_tlmm 0 0 15>;
1896 reg = <0 0x03d00000 0 0x40000>,
1897 <0 0x03d9e000 0 0x1000>,
1898 <0 0x03d61000 0 0x800>;
1905 iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>;
1977 reg = <0 0x03d6a000 0 0x34000>,
1978 <0 0x03de0000 0 0x10000>,
1979 <0 0x0b290000 0 0x10000>;
2006 iommus = <&adreno_smmu 5 0x400>;
2022 reg = <0 0x03d90000 0 0x9000>;
2037 reg = <0 0x03da0000 0 0x20000>;
2074 reg = <0 0x03c40000 0 0xf080>;
2081 reg = <0x0 0x04080000 0x0 0x4040>;
2084 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2099 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
2105 qcom,smem-states = <&smp2p_modem_out 0>;
2123 reg = <0 0x05c00000 0 0x4000>;
2126 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2144 qcom,smem-states = <&smp2p_slpi_out 0>;
2165 #size-cells = <0>;
2170 iommus = <&apps_smmu 0x0541 0x0>;
2176 iommus = <&apps_smmu 0x0542 0x0>;
2182 iommus = <&apps_smmu 0x0543 0x0>;
2191 reg = <0 0x08804000 0 0x1000>;
2202 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2203 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2205 iommus = <&apps_smmu 0x4a0 0x0>;
2231 reg = <0 0x088e3000 0 0x400>;
2233 #phy-cells = <0>;
2244 reg = <0 0x088e4000 0 0x400>;
2246 #phy-cells = <0>;
2257 reg = <0x0 0x088e7000 0x0 0x84>;
2262 reg = <0 0x088e8000 0 0x3000>;
2283 #size-cells = <0>;
2285 port@0 {
2286 reg = <0>;
2312 reg = <0 0x088eb000 0 0x2000>;
2324 #clock-cells = <0>;
2325 #phy-cells = <0>;
2335 reg = <0 0x090c0000 0 0x4200>;
2342 reg = <0 0x09100000 0 0xb4000>;
2349 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
2350 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
2351 <0 0x09600000 0 0x58000>;
2358 reg = <0 0x0a0c0000 0 0xa180>;
2365 reg = <0 0x0a6f8800 0 0x400>;
2401 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
2402 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
2407 reg = <0 0x0a600000 0 0xcd00>;
2409 iommus = <&apps_smmu 0x0 0x0>;
2417 #size-cells = <0>;
2419 port@0 {
2420 reg = <0>;
2439 reg = <0 0x0a8f8800 0 0x400>;
2477 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
2478 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
2483 reg = <0 0x0a800000 0 0xcd00>;
2485 iommus = <&apps_smmu 0x20 0x0>;
2495 reg = <0 0x0ae00000 0 0x1000>;
2498 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
2499 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>,
2519 iommus = <&apps_smmu 0x820 0x402>;
2529 reg = <0 0x0ae01000 0 0x8f000>,
2530 <0 0x0aeb0000 0 0x2008>;
2553 interrupts = <0>;
2586 #size-cells = <0>;
2588 port@0 {
2589 reg = <0>;
2613 reg = <0 0xae90000 0 0x200>,
2614 <0 0xae90200 0 0x200>,
2615 <0 0xae90400 0 0x600>,
2616 <0 0xae91000 0 0x400>,
2617 <0 0xae91400 0 0x400>;
2639 #sound-dai-cells = <0>;
2648 #size-cells = <0>;
2650 port@0 {
2651 reg = <0>;
2693 reg = <0 0x0ae94000 0 0x400>;
2714 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2724 #size-cells = <0>;
2754 #size-cells = <0>;
2756 port@0 {
2757 reg = <0>;
2773 reg = <0 0x0ae94400 0 0x200>,
2774 <0 0x0ae94600 0 0x280>,
2775 <0 0x0ae94900 0 0x27c>;
2781 #phy-cells = <0>;
2792 reg = <0 0x0ae96000 0 0x400>;
2813 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2823 #size-cells = <0>;
2853 #size-cells = <0>;
2855 port@0 {
2856 reg = <0>;
2872 reg = <0 0x0ae96400 0 0x200>,
2873 <0 0x0ae96600 0 0x280>,
2874 <0 0x0ae96900 0 0x27c>;
2880 #phy-cells = <0>;
2892 reg = <0 0x0af00000 0 0x10000>;
2894 <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>,
2895 <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>,
2914 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
2915 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
2926 reg = <0 0x0c263000 0 0x1ff>, /* TM */
2927 <0 0x0c222000 0 0x8>; /* SROT */
2937 reg = <0 0x0c265000 0 0x1ff>, /* TM */
2938 <0 0x0c223000 0 0x8>; /* SROT */
2948 reg = <0 0x0c300000 0 0x400>;
2953 #clock-cells = <0>;
2958 reg = <0 0x0c3f0000 0 0x400>;
2963 reg = <0x0 0x0c440000 0x0 0x1100>,
2964 <0x0 0x0c600000 0x0 0x2000000>,
2965 <0x0 0x0e600000 0x0 0x100000>,
2966 <0x0 0x0e700000 0x0 0xa0000>,
2967 <0x0 0x0c40a000 0x0 0x26000>;
2971 qcom,ee = <0>;
2972 qcom,channel = <0>;
2974 #size-cells = <0>;
2981 reg = <0 0x0f100000 0 0x300000>;
2987 gpio-ranges = <&tlmm 0 0 204>;
3184 reg = <0 0x15000000 0 0x100000>;
3289 reg = <0 0x17300000 0 0x100>;
3292 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
3310 qcom,smem-states = <&smp2p_adsp_out 0>;
3330 #size-cells = <0>;
3346 #size-cells = <0>;
3364 #size-cells = <0>;
3366 iommus = <&apps_smmu 0x1801 0x0>;
3368 dai@0 {
3369 reg = <0>;
3389 #sound-dai-cells = <0>;
3400 #size-cells = <0>;
3405 iommus = <&apps_smmu 0x1803 0x0>;
3411 iommus = <&apps_smmu 0x1804 0x0>;
3417 iommus = <&apps_smmu 0x1805 0x0>;
3428 redistributor-stride = <0 0x20000>;
3429 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
3430 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
3438 ranges = <0 0 0 0x20000000>;
3439 reg = <0x0 0x17c20000 0x0 0x1000>;
3443 frame-number = <0>;
3446 reg = <0x17c21000 0x1000>,
3447 <0x17c22000 0x1000>;
3453 reg = <0x17c23000 0x1000>;
3460 reg = <0x17c25000 0x1000>;
3467 reg = <0x17c27000 0x1000>;
3474 reg = <0x17c29000 0x1000>;
3481 reg = <0x17c2b000 0x1000>;
3488 reg = <0x17c2d000 0x1000>;
3496 reg = <0x0 0x18200000 0x0 0x10000>,
3497 <0x0 0x18210000 0x0 0x10000>,
3498 <0x0 0x18220000 0x0 0x10000>;
3499 reg-names = "drv-0", "drv-1", "drv-2";
3503 qcom,tcs-offset = <0xd00>;
3506 <WAKE_TCS 3>, <CONTROL_TCS 0>;
3573 reg = <0 0x18591000 0 0x1000>,
3574 <0 0x18592000 0 0x1000>,
3575 <0 0x18593000 0 0x1000>;
3581 interrupt-names = "dcvsh-irq-0",
3594 reg = <0 0x98900000 0 0x1400000>;
3597 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3611 interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
3617 qcom,smem-states = <&smp2p_cdsp_out 0>;
3638 #size-cells = <0>;
3643 iommus = <&apps_smmu 0x2161 0x0400>,
3644 <&apps_smmu 0x1181 0x0420>;
3650 iommus = <&apps_smmu 0x2162 0x0400>,
3651 <&apps_smmu 0x1182 0x0420>;
3657 iommus = <&apps_smmu 0x2163 0x0400>,
3658 <&apps_smmu 0x1183 0x0420>;
3664 iommus = <&apps_smmu 0x2164 0x0400>,
3665 <&apps_smmu 0x1184 0x0420>;
3671 iommus = <&apps_smmu 0x2165 0x0400>,
3672 <&apps_smmu 0x1185 0x0420>;
3678 iommus = <&apps_smmu 0x2166 0x0400>,
3679 <&apps_smmu 0x1186 0x0420>;
3685 iommus = <&apps_smmu 0x2167 0x0400>,
3686 <&apps_smmu 0x1187 0x0420>;
3692 iommus = <&apps_smmu 0x2168 0x0400>,
3693 <&apps_smmu 0x1188 0x0420>;
4222 thermal-sensors = <&tsens0 0>;
4274 thermal-sensors = <&tsens1 0>;