Lines Matching +full:ufs +full:- +full:ddr
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
9 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
10 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
15 #include <dt-bindings/interconnect/qcom,sm8250.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom-rpmpd.h>
19 #include <dt-bindings/power/qcom,rpmhpd.h>
20 #include <dt-bindings/soc/qcom,apr.h>
21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
22 #include <dt-bindings/sound/qcom,q6afe.h>
23 #include <dt-bindings/thermal/thermal.h>
24 #include <dt-bindings/clock/qcom,camcc-sm8250.h>
25 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
28 interrupt-parent = <&intc>;
30 #address-cells = <2>;
31 #size-cells = <2>;
79 xo_board: xo-board {
80 compatible = "fixed-clock";
81 #clock-cells = <0>;
82 clock-frequency = <38400000>;
83 clock-output-names = "xo_board";
86 sleep_clk: sleep-clk {
87 compatible = "fixed-clock";
88 clock-frequency = <32764>;
89 #clock-cells = <0>;
94 #address-cells = <2>;
95 #size-cells = <0>;
102 enable-method = "psci";
103 capacity-dmips-mhz = <448>;
104 dynamic-power-coefficient = <105>;
105 next-level-cache = <&l2_0>;
106 power-domains = <&cpu_pd0>;
107 power-domain-names = "psci";
108 qcom,freq-domain = <&cpufreq_hw 0>;
109 operating-points-v2 = <&cpu0_opp_table>;
112 #cooling-cells = <2>;
113 l2_0: l2-cache {
115 cache-level = <2>;
116 cache-size = <0x20000>;
117 cache-unified;
118 next-level-cache = <&l3_0>;
119 l3_0: l3-cache {
121 cache-level = <3>;
122 cache-size = <0x400000>;
123 cache-unified;
133 enable-method = "psci";
134 capacity-dmips-mhz = <448>;
135 dynamic-power-coefficient = <105>;
136 next-level-cache = <&l2_100>;
137 power-domains = <&cpu_pd1>;
138 power-domain-names = "psci";
139 qcom,freq-domain = <&cpufreq_hw 0>;
140 operating-points-v2 = <&cpu0_opp_table>;
143 #cooling-cells = <2>;
144 l2_100: l2-cache {
146 cache-level = <2>;
147 cache-size = <0x20000>;
148 cache-unified;
149 next-level-cache = <&l3_0>;
158 enable-method = "psci";
159 capacity-dmips-mhz = <448>;
160 dynamic-power-coefficient = <105>;
161 next-level-cache = <&l2_200>;
162 power-domains = <&cpu_pd2>;
163 power-domain-names = "psci";
164 qcom,freq-domain = <&cpufreq_hw 0>;
165 operating-points-v2 = <&cpu0_opp_table>;
168 #cooling-cells = <2>;
169 l2_200: l2-cache {
171 cache-level = <2>;
172 cache-size = <0x20000>;
173 cache-unified;
174 next-level-cache = <&l3_0>;
183 enable-method = "psci";
184 capacity-dmips-mhz = <448>;
185 dynamic-power-coefficient = <105>;
186 next-level-cache = <&l2_300>;
187 power-domains = <&cpu_pd3>;
188 power-domain-names = "psci";
189 qcom,freq-domain = <&cpufreq_hw 0>;
190 operating-points-v2 = <&cpu0_opp_table>;
193 #cooling-cells = <2>;
194 l2_300: l2-cache {
196 cache-level = <2>;
197 cache-size = <0x20000>;
198 cache-unified;
199 next-level-cache = <&l3_0>;
208 enable-method = "psci";
209 capacity-dmips-mhz = <1024>;
210 dynamic-power-coefficient = <379>;
211 next-level-cache = <&l2_400>;
212 power-domains = <&cpu_pd4>;
213 power-domain-names = "psci";
214 qcom,freq-domain = <&cpufreq_hw 1>;
215 operating-points-v2 = <&cpu4_opp_table>;
218 #cooling-cells = <2>;
219 l2_400: l2-cache {
221 cache-level = <2>;
222 cache-size = <0x40000>;
223 cache-unified;
224 next-level-cache = <&l3_0>;
233 enable-method = "psci";
234 capacity-dmips-mhz = <1024>;
235 dynamic-power-coefficient = <379>;
236 next-level-cache = <&l2_500>;
237 power-domains = <&cpu_pd5>;
238 power-domain-names = "psci";
239 qcom,freq-domain = <&cpufreq_hw 1>;
240 operating-points-v2 = <&cpu4_opp_table>;
243 #cooling-cells = <2>;
244 l2_500: l2-cache {
246 cache-level = <2>;
247 cache-size = <0x40000>;
248 cache-unified;
249 next-level-cache = <&l3_0>;
258 enable-method = "psci";
259 capacity-dmips-mhz = <1024>;
260 dynamic-power-coefficient = <379>;
261 next-level-cache = <&l2_600>;
262 power-domains = <&cpu_pd6>;
263 power-domain-names = "psci";
264 qcom,freq-domain = <&cpufreq_hw 1>;
265 operating-points-v2 = <&cpu4_opp_table>;
268 #cooling-cells = <2>;
269 l2_600: l2-cache {
271 cache-level = <2>;
272 cache-size = <0x40000>;
273 cache-unified;
274 next-level-cache = <&l3_0>;
283 enable-method = "psci";
284 capacity-dmips-mhz = <1024>;
285 dynamic-power-coefficient = <444>;
286 next-level-cache = <&l2_700>;
287 power-domains = <&cpu_pd7>;
288 power-domain-names = "psci";
289 qcom,freq-domain = <&cpufreq_hw 2>;
290 operating-points-v2 = <&cpu7_opp_table>;
293 #cooling-cells = <2>;
294 l2_700: l2-cache {
296 cache-level = <2>;
297 cache-size = <0x80000>;
298 cache-unified;
299 next-level-cache = <&l3_0>;
303 cpu-map {
339 idle-states {
340 entry-method = "psci";
342 little_cpu_sleep_0: cpu-sleep-0-0 {
343 compatible = "arm,idle-state";
344 idle-state-name = "silver-rail-power-collapse";
345 arm,psci-suspend-param = <0x40000004>;
346 entry-latency-us = <360>;
347 exit-latency-us = <531>;
348 min-residency-us = <3934>;
349 local-timer-stop;
352 big_cpu_sleep_0: cpu-sleep-1-0 {
353 compatible = "arm,idle-state";
354 idle-state-name = "gold-rail-power-collapse";
355 arm,psci-suspend-param = <0x40000004>;
356 entry-latency-us = <702>;
357 exit-latency-us = <1061>;
358 min-residency-us = <4488>;
359 local-timer-stop;
363 domain-idle-states {
364 cluster_sleep_0: cluster-sleep-0 {
365 compatible = "domain-idle-state";
366 arm,psci-suspend-param = <0x4100c244>;
367 entry-latency-us = <3264>;
368 exit-latency-us = <6562>;
369 min-residency-us = <9987>;
374 qup_virt: interconnect-qup-virt {
375 compatible = "qcom,sm8250-qup-virt";
376 #interconnect-cells = <2>;
377 qcom,bcm-voters = <&apps_bcm_voter>;
380 cpu0_opp_table: opp-table-cpu0 {
381 compatible = "operating-points-v2";
382 opp-shared;
384 cpu0_opp1: opp-300000000 {
385 opp-hz = /bits/ 64 <300000000>;
386 opp-peak-kBps = <800000 9600000>;
389 cpu0_opp2: opp-403200000 {
390 opp-hz = /bits/ 64 <403200000>;
391 opp-peak-kBps = <800000 9600000>;
394 cpu0_opp3: opp-518400000 {
395 opp-hz = /bits/ 64 <518400000>;
396 opp-peak-kBps = <800000 16588800>;
399 cpu0_opp4: opp-614400000 {
400 opp-hz = /bits/ 64 <614400000>;
401 opp-peak-kBps = <800000 16588800>;
404 cpu0_opp5: opp-691200000 {
405 opp-hz = /bits/ 64 <691200000>;
406 opp-peak-kBps = <800000 19660800>;
409 cpu0_opp6: opp-787200000 {
410 opp-hz = /bits/ 64 <787200000>;
411 opp-peak-kBps = <1804000 19660800>;
414 cpu0_opp7: opp-883200000 {
415 opp-hz = /bits/ 64 <883200000>;
416 opp-peak-kBps = <1804000 23347200>;
419 cpu0_opp8: opp-979200000 {
420 opp-hz = /bits/ 64 <979200000>;
421 opp-peak-kBps = <1804000 26419200>;
424 cpu0_opp9: opp-1075200000 {
425 opp-hz = /bits/ 64 <1075200000>;
426 opp-peak-kBps = <1804000 29491200>;
429 cpu0_opp10: opp-1171200000 {
430 opp-hz = /bits/ 64 <1171200000>;
431 opp-peak-kBps = <1804000 32563200>;
434 cpu0_opp11: opp-1248000000 {
435 opp-hz = /bits/ 64 <1248000000>;
436 opp-peak-kBps = <1804000 36249600>;
439 cpu0_opp12: opp-1344000000 {
440 opp-hz = /bits/ 64 <1344000000>;
441 opp-peak-kBps = <2188000 36249600>;
444 cpu0_opp13: opp-1420800000 {
445 opp-hz = /bits/ 64 <1420800000>;
446 opp-peak-kBps = <2188000 39321600>;
449 cpu0_opp14: opp-1516800000 {
450 opp-hz = /bits/ 64 <1516800000>;
451 opp-peak-kBps = <3072000 42393600>;
454 cpu0_opp15: opp-1612800000 {
455 opp-hz = /bits/ 64 <1612800000>;
456 opp-peak-kBps = <3072000 42393600>;
459 cpu0_opp16: opp-1708800000 {
460 opp-hz = /bits/ 64 <1708800000>;
461 opp-peak-kBps = <4068000 42393600>;
464 cpu0_opp17: opp-1804800000 {
465 opp-hz = /bits/ 64 <1804800000>;
466 opp-peak-kBps = <4068000 42393600>;
470 cpu4_opp_table: opp-table-cpu4 {
471 compatible = "operating-points-v2";
472 opp-shared;
474 cpu4_opp1: opp-710400000 {
475 opp-hz = /bits/ 64 <710400000>;
476 opp-peak-kBps = <1804000 19660800>;
479 cpu4_opp2: opp-825600000 {
480 opp-hz = /bits/ 64 <825600000>;
481 opp-peak-kBps = <2188000 23347200>;
484 cpu4_opp3: opp-940800000 {
485 opp-hz = /bits/ 64 <940800000>;
486 opp-peak-kBps = <2188000 26419200>;
489 cpu4_opp4: opp-1056000000 {
490 opp-hz = /bits/ 64 <1056000000>;
491 opp-peak-kBps = <3072000 26419200>;
494 cpu4_opp5: opp-1171200000 {
495 opp-hz = /bits/ 64 <1171200000>;
496 opp-peak-kBps = <3072000 29491200>;
499 cpu4_opp6: opp-1286400000 {
500 opp-hz = /bits/ 64 <1286400000>;
501 opp-peak-kBps = <4068000 29491200>;
504 cpu4_opp7: opp-1382400000 {
505 opp-hz = /bits/ 64 <1382400000>;
506 opp-peak-kBps = <4068000 32563200>;
509 cpu4_opp8: opp-1478400000 {
510 opp-hz = /bits/ 64 <1478400000>;
511 opp-peak-kBps = <4068000 32563200>;
514 cpu4_opp9: opp-1574400000 {
515 opp-hz = /bits/ 64 <1574400000>;
516 opp-peak-kBps = <5412000 39321600>;
519 cpu4_opp10: opp-1670400000 {
520 opp-hz = /bits/ 64 <1670400000>;
521 opp-peak-kBps = <5412000 42393600>;
524 cpu4_opp11: opp-1766400000 {
525 opp-hz = /bits/ 64 <1766400000>;
526 opp-peak-kBps = <5412000 45465600>;
529 cpu4_opp12: opp-1862400000 {
530 opp-hz = /bits/ 64 <1862400000>;
531 opp-peak-kBps = <6220000 45465600>;
534 cpu4_opp13: opp-1958400000 {
535 opp-hz = /bits/ 64 <1958400000>;
536 opp-peak-kBps = <6220000 48537600>;
539 cpu4_opp14: opp-2054400000 {
540 opp-hz = /bits/ 64 <2054400000>;
541 opp-peak-kBps = <7216000 48537600>;
544 cpu4_opp15: opp-2150400000 {
545 opp-hz = /bits/ 64 <2150400000>;
546 opp-peak-kBps = <7216000 51609600>;
549 cpu4_opp16: opp-2246400000 {
550 opp-hz = /bits/ 64 <2246400000>;
551 opp-peak-kBps = <7216000 51609600>;
554 cpu4_opp17: opp-2342400000 {
555 opp-hz = /bits/ 64 <2342400000>;
556 opp-peak-kBps = <8368000 51609600>;
559 cpu4_opp18: opp-2419200000 {
560 opp-hz = /bits/ 64 <2419200000>;
561 opp-peak-kBps = <8368000 51609600>;
565 cpu7_opp_table: opp-table-cpu7 {
566 compatible = "operating-points-v2";
567 opp-shared;
569 cpu7_opp1: opp-844800000 {
570 opp-hz = /bits/ 64 <844800000>;
571 opp-peak-kBps = <2188000 19660800>;
574 cpu7_opp2: opp-960000000 {
575 opp-hz = /bits/ 64 <960000000>;
576 opp-peak-kBps = <2188000 26419200>;
579 cpu7_opp3: opp-1075200000 {
580 opp-hz = /bits/ 64 <1075200000>;
581 opp-peak-kBps = <3072000 26419200>;
584 cpu7_opp4: opp-1190400000 {
585 opp-hz = /bits/ 64 <1190400000>;
586 opp-peak-kBps = <3072000 29491200>;
589 cpu7_opp5: opp-1305600000 {
590 opp-hz = /bits/ 64 <1305600000>;
591 opp-peak-kBps = <4068000 32563200>;
594 cpu7_opp6: opp-1401600000 {
595 opp-hz = /bits/ 64 <1401600000>;
596 opp-peak-kBps = <4068000 32563200>;
599 cpu7_opp7: opp-1516800000 {
600 opp-hz = /bits/ 64 <1516800000>;
601 opp-peak-kBps = <4068000 36249600>;
604 cpu7_opp8: opp-1632000000 {
605 opp-hz = /bits/ 64 <1632000000>;
606 opp-peak-kBps = <5412000 39321600>;
609 cpu7_opp9: opp-1747200000 {
610 opp-hz = /bits/ 64 <1747200000>;
611 opp-peak-kBps = <5412000 42393600>;
614 cpu7_opp10: opp-1862400000 {
615 opp-hz = /bits/ 64 <1862400000>;
616 opp-peak-kBps = <6220000 45465600>;
619 cpu7_opp11: opp-1977600000 {
620 opp-hz = /bits/ 64 <1977600000>;
621 opp-peak-kBps = <6220000 48537600>;
624 cpu7_opp12: opp-2073600000 {
625 opp-hz = /bits/ 64 <2073600000>;
626 opp-peak-kBps = <7216000 48537600>;
629 cpu7_opp13: opp-2169600000 {
630 opp-hz = /bits/ 64 <2169600000>;
631 opp-peak-kBps = <7216000 51609600>;
634 cpu7_opp14: opp-2265600000 {
635 opp-hz = /bits/ 64 <2265600000>;
636 opp-peak-kBps = <7216000 51609600>;
639 cpu7_opp15: opp-2361600000 {
640 opp-hz = /bits/ 64 <2361600000>;
641 opp-peak-kBps = <8368000 51609600>;
644 cpu7_opp16: opp-2457600000 {
645 opp-hz = /bits/ 64 <2457600000>;
646 opp-peak-kBps = <8368000 51609600>;
649 cpu7_opp17: opp-2553600000 {
650 opp-hz = /bits/ 64 <2553600000>;
651 opp-peak-kBps = <8368000 51609600>;
654 cpu7_opp18: opp-2649600000 {
655 opp-hz = /bits/ 64 <2649600000>;
656 opp-peak-kBps = <8368000 51609600>;
659 cpu7_opp19: opp-2745600000 {
660 opp-hz = /bits/ 64 <2745600000>;
661 opp-peak-kBps = <8368000 51609600>;
664 cpu7_opp20: opp-2841600000 {
665 opp-hz = /bits/ 64 <2841600000>;
666 opp-peak-kBps = <8368000 51609600>;
672 compatible = "qcom,scm-sm8250", "qcom,scm";
673 qcom,dload-mode = <&tcsr 0x13000>;
674 #reset-cells = <1>;
685 compatible = "arm,armv8-pmuv3";
690 compatible = "arm,psci-1.0";
693 cpu_pd0: power-domain-cpu0 {
694 #power-domain-cells = <0>;
695 power-domains = <&cluster_pd>;
696 domain-idle-states = <&little_cpu_sleep_0>;
699 cpu_pd1: power-domain-cpu1 {
700 #power-domain-cells = <0>;
701 power-domains = <&cluster_pd>;
702 domain-idle-states = <&little_cpu_sleep_0>;
705 cpu_pd2: power-domain-cpu2 {
706 #power-domain-cells = <0>;
707 power-domains = <&cluster_pd>;
708 domain-idle-states = <&little_cpu_sleep_0>;
711 cpu_pd3: power-domain-cpu3 {
712 #power-domain-cells = <0>;
713 power-domains = <&cluster_pd>;
714 domain-idle-states = <&little_cpu_sleep_0>;
717 cpu_pd4: power-domain-cpu4 {
718 #power-domain-cells = <0>;
719 power-domains = <&cluster_pd>;
720 domain-idle-states = <&big_cpu_sleep_0>;
723 cpu_pd5: power-domain-cpu5 {
724 #power-domain-cells = <0>;
725 power-domains = <&cluster_pd>;
726 domain-idle-states = <&big_cpu_sleep_0>;
729 cpu_pd6: power-domain-cpu6 {
730 #power-domain-cells = <0>;
731 power-domains = <&cluster_pd>;
732 domain-idle-states = <&big_cpu_sleep_0>;
735 cpu_pd7: power-domain-cpu7 {
736 #power-domain-cells = <0>;
737 power-domains = <&cluster_pd>;
738 domain-idle-states = <&big_cpu_sleep_0>;
741 cluster_pd: power-domain-cpu-cluster0 {
742 #power-domain-cells = <0>;
743 domain-idle-states = <&cluster_sleep_0>;
747 qup_opp_table: opp-table-qup {
748 compatible = "operating-points-v2";
750 opp-50000000 {
751 opp-hz = /bits/ 64 <50000000>;
752 required-opps = <&rpmhpd_opp_min_svs>;
755 opp-75000000 {
756 opp-hz = /bits/ 64 <75000000>;
757 required-opps = <&rpmhpd_opp_low_svs>;
760 opp-120000000 {
761 opp-hz = /bits/ 64 <120000000>;
762 required-opps = <&rpmhpd_opp_svs>;
766 reserved-memory {
767 #address-cells = <2>;
768 #size-cells = <2>;
773 no-map;
778 no-map;
782 compatible = "qcom,cmd-db";
784 no-map;
789 no-map;
794 no-map;
799 no-map;
804 no-map;
809 no-map;
814 no-map;
819 no-map;
824 no-map;
829 no-map;
834 no-map;
839 no-map;
844 no-map;
849 no-map;
854 no-map;
859 no-map;
865 memory-region = <&smem_mem>;
869 smp2p-adsp {
872 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
878 qcom,local-pid = <0>;
879 qcom,remote-pid = <2>;
881 smp2p_adsp_out: master-kernel {
882 qcom,entry-name = "master-kernel";
883 #qcom,smem-state-cells = <1>;
886 smp2p_adsp_in: slave-kernel {
887 qcom,entry-name = "slave-kernel";
888 interrupt-controller;
889 #interrupt-cells = <2>;
893 smp2p-cdsp {
896 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
902 qcom,local-pid = <0>;
903 qcom,remote-pid = <5>;
905 smp2p_cdsp_out: master-kernel {
906 qcom,entry-name = "master-kernel";
907 #qcom,smem-state-cells = <1>;
910 smp2p_cdsp_in: slave-kernel {
911 qcom,entry-name = "slave-kernel";
912 interrupt-controller;
913 #interrupt-cells = <2>;
917 smp2p-slpi {
920 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
926 qcom,local-pid = <0>;
927 qcom,remote-pid = <3>;
929 smp2p_slpi_out: master-kernel {
930 qcom,entry-name = "master-kernel";
931 #qcom,smem-state-cells = <1>;
934 smp2p_slpi_in: slave-kernel {
935 qcom,entry-name = "slave-kernel";
936 interrupt-controller;
937 #interrupt-cells = <2>;
942 #address-cells = <2>;
943 #size-cells = <2>;
945 dma-ranges = <0 0 0 0 0x10 0>;
946 compatible = "simple-bus";
948 gcc: clock-controller@100000 {
949 compatible = "qcom,gcc-sm8250";
951 #clock-cells = <1>;
952 #reset-cells = <1>;
953 #power-domain-cells = <1>;
954 clock-names = "bi_tcxo",
963 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
966 interrupt-controller;
967 #interrupt-cells = <3>;
968 #mbox-cells = <2>;
972 compatible = "qcom,sm8250-qfprom", "qcom,qfprom";
974 #address-cells = <1>;
975 #size-cells = <1>;
977 gpu_speed_bin: gpu-speed-bin@19b {
984 compatible = "qcom,prng-ee";
987 clock-names = "core";
990 gpi_dma2: dma-controller@800000 {
991 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1003 dma-channels = <10>;
1004 dma-channel-mask = <0x3f>;
1006 #dma-cells = <3>;
1011 compatible = "qcom,geni-se-qup";
1013 clock-names = "m-ahb", "s-ahb";
1016 #address-cells = <2>;
1017 #size-cells = <2>;
1023 compatible = "qcom,geni-i2c";
1025 clock-names = "se";
1027 pinctrl-names = "default";
1028 pinctrl-0 = <&qup_i2c14_default>;
1032 dma-names = "tx", "rx";
1033 power-domains = <&rpmhpd SM8250_CX>;
1037 interconnect-names = "qup-core",
1038 "qup-config",
1039 "qup-memory";
1040 #address-cells = <1>;
1041 #size-cells = <0>;
1046 compatible = "qcom,geni-spi";
1048 clock-names = "se";
1053 dma-names = "tx", "rx";
1054 power-domains = <&rpmhpd RPMHPD_CX>;
1055 operating-points-v2 = <&qup_opp_table>;
1059 interconnect-names = "qup-core",
1060 "qup-config",
1061 "qup-memory";
1062 #address-cells = <1>;
1063 #size-cells = <0>;
1068 compatible = "qcom,geni-i2c";
1070 clock-names = "se";
1072 pinctrl-names = "default";
1073 pinctrl-0 = <&qup_i2c15_default>;
1077 dma-names = "tx", "rx";
1078 power-domains = <&rpmhpd SM8250_CX>;
1082 interconnect-names = "qup-core",
1083 "qup-config",
1084 "qup-memory";
1085 #address-cells = <1>;
1086 #size-cells = <0>;
1091 compatible = "qcom,geni-spi";
1093 clock-names = "se";
1098 dma-names = "tx", "rx";
1099 power-domains = <&rpmhpd RPMHPD_CX>;
1100 operating-points-v2 = <&qup_opp_table>;
1104 interconnect-names = "qup-core",
1105 "qup-config",
1106 "qup-memory";
1107 #address-cells = <1>;
1108 #size-cells = <0>;
1113 compatible = "qcom,geni-i2c";
1115 clock-names = "se";
1117 pinctrl-names = "default";
1118 pinctrl-0 = <&qup_i2c16_default>;
1122 dma-names = "tx", "rx";
1123 power-domains = <&rpmhpd SM8250_CX>;
1127 interconnect-names = "qup-core",
1128 "qup-config",
1129 "qup-memory";
1130 #address-cells = <1>;
1131 #size-cells = <0>;
1136 compatible = "qcom,geni-spi";
1138 clock-names = "se";
1143 dma-names = "tx", "rx";
1144 power-domains = <&rpmhpd RPMHPD_CX>;
1145 operating-points-v2 = <&qup_opp_table>;
1149 interconnect-names = "qup-core",
1150 "qup-config",
1151 "qup-memory";
1152 #address-cells = <1>;
1153 #size-cells = <0>;
1158 compatible = "qcom,geni-i2c";
1160 clock-names = "se";
1162 pinctrl-names = "default";
1163 pinctrl-0 = <&qup_i2c17_default>;
1167 dma-names = "tx", "rx";
1168 power-domains = <&rpmhpd SM8250_CX>;
1172 interconnect-names = "qup-core",
1173 "qup-config",
1174 "qup-memory";
1175 #address-cells = <1>;
1176 #size-cells = <0>;
1181 compatible = "qcom,geni-spi";
1183 clock-names = "se";
1188 dma-names = "tx", "rx";
1189 power-domains = <&rpmhpd RPMHPD_CX>;
1190 operating-points-v2 = <&qup_opp_table>;
1194 interconnect-names = "qup-core",
1195 "qup-config",
1196 "qup-memory";
1197 #address-cells = <1>;
1198 #size-cells = <0>;
1203 compatible = "qcom,geni-uart";
1205 clock-names = "se";
1207 pinctrl-names = "default";
1208 pinctrl-0 = <&qup_uart17_default>;
1210 power-domains = <&rpmhpd RPMHPD_CX>;
1211 operating-points-v2 = <&qup_opp_table>;
1214 interconnect-names = "qup-core",
1215 "qup-config";
1220 compatible = "qcom,geni-i2c";
1222 clock-names = "se";
1224 pinctrl-names = "default";
1225 pinctrl-0 = <&qup_i2c18_default>;
1229 dma-names = "tx", "rx";
1230 power-domains = <&rpmhpd SM8250_CX>;
1234 interconnect-names = "qup-core",
1235 "qup-config",
1236 "qup-memory";
1237 #address-cells = <1>;
1238 #size-cells = <0>;
1243 compatible = "qcom,geni-spi";
1245 clock-names = "se";
1250 dma-names = "tx", "rx";
1251 power-domains = <&rpmhpd RPMHPD_CX>;
1252 operating-points-v2 = <&qup_opp_table>;
1256 interconnect-names = "qup-core",
1257 "qup-config",
1258 "qup-memory";
1259 #address-cells = <1>;
1260 #size-cells = <0>;
1265 compatible = "qcom,geni-uart";
1267 clock-names = "se";
1269 pinctrl-names = "default";
1270 pinctrl-0 = <&qup_uart18_default>;
1272 power-domains = <&rpmhpd RPMHPD_CX>;
1273 operating-points-v2 = <&qup_opp_table>;
1276 interconnect-names = "qup-core",
1277 "qup-config";
1282 compatible = "qcom,geni-i2c";
1284 clock-names = "se";
1286 pinctrl-names = "default";
1287 pinctrl-0 = <&qup_i2c19_default>;
1291 dma-names = "tx", "rx";
1292 power-domains = <&rpmhpd SM8250_CX>;
1296 interconnect-names = "qup-core",
1297 "qup-config",
1298 "qup-memory";
1299 #address-cells = <1>;
1300 #size-cells = <0>;
1305 compatible = "qcom,geni-spi";
1307 clock-names = "se";
1312 dma-names = "tx", "rx";
1313 power-domains = <&rpmhpd RPMHPD_CX>;
1314 operating-points-v2 = <&qup_opp_table>;
1318 interconnect-names = "qup-core",
1319 "qup-config",
1320 "qup-memory";
1321 #address-cells = <1>;
1322 #size-cells = <0>;
1327 gpi_dma0: dma-controller@900000 {
1328 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1343 dma-channels = <15>;
1344 dma-channel-mask = <0x7ff>;
1346 #dma-cells = <3>;
1351 compatible = "qcom,geni-se-qup";
1353 clock-names = "m-ahb", "s-ahb";
1356 #address-cells = <2>;
1357 #size-cells = <2>;
1363 compatible = "qcom,geni-i2c";
1365 clock-names = "se";
1367 pinctrl-names = "default";
1368 pinctrl-0 = <&qup_i2c0_default>;
1372 dma-names = "tx", "rx";
1373 power-domains = <&rpmhpd SM8250_CX>;
1377 interconnect-names = "qup-core",
1378 "qup-config",
1379 "qup-memory";
1380 #address-cells = <1>;
1381 #size-cells = <0>;
1386 compatible = "qcom,geni-spi";
1388 clock-names = "se";
1393 dma-names = "tx", "rx";
1394 power-domains = <&rpmhpd RPMHPD_CX>;
1395 operating-points-v2 = <&qup_opp_table>;
1399 interconnect-names = "qup-core",
1400 "qup-config",
1401 "qup-memory";
1402 #address-cells = <1>;
1403 #size-cells = <0>;
1408 compatible = "qcom,geni-i2c";
1410 clock-names = "se";
1412 pinctrl-names = "default";
1413 pinctrl-0 = <&qup_i2c1_default>;
1417 dma-names = "tx", "rx";
1418 power-domains = <&rpmhpd SM8250_CX>;
1422 interconnect-names = "qup-core",
1423 "qup-config",
1424 "qup-memory";
1425 #address-cells = <1>;
1426 #size-cells = <0>;
1431 compatible = "qcom,geni-spi";
1433 clock-names = "se";
1438 dma-names = "tx", "rx";
1439 power-domains = <&rpmhpd RPMHPD_CX>;
1440 operating-points-v2 = <&qup_opp_table>;
1444 interconnect-names = "qup-core",
1445 "qup-config",
1446 "qup-memory";
1447 #address-cells = <1>;
1448 #size-cells = <0>;
1453 compatible = "qcom,geni-i2c";
1455 clock-names = "se";
1457 pinctrl-names = "default";
1458 pinctrl-0 = <&qup_i2c2_default>;
1462 dma-names = "tx", "rx";
1463 power-domains = <&rpmhpd SM8250_CX>;
1467 interconnect-names = "qup-core",
1468 "qup-config",
1469 "qup-memory";
1470 #address-cells = <1>;
1471 #size-cells = <0>;
1476 compatible = "qcom,geni-spi";
1478 clock-names = "se";
1483 dma-names = "tx", "rx";
1484 power-domains = <&rpmhpd RPMHPD_CX>;
1485 operating-points-v2 = <&qup_opp_table>;
1489 interconnect-names = "qup-core",
1490 "qup-config",
1491 "qup-memory";
1492 #address-cells = <1>;
1493 #size-cells = <0>;
1498 compatible = "qcom,geni-debug-uart";
1500 clock-names = "se";
1502 pinctrl-names = "default";
1503 pinctrl-0 = <&qup_uart2_default>;
1505 power-domains = <&rpmhpd RPMHPD_CX>;
1506 operating-points-v2 = <&qup_opp_table>;
1509 interconnect-names = "qup-core",
1510 "qup-config";
1515 compatible = "qcom,geni-i2c";
1517 clock-names = "se";
1519 pinctrl-names = "default";
1520 pinctrl-0 = <&qup_i2c3_default>;
1524 dma-names = "tx", "rx";
1525 power-domains = <&rpmhpd SM8250_CX>;
1529 interconnect-names = "qup-core",
1530 "qup-config",
1531 "qup-memory";
1532 #address-cells = <1>;
1533 #size-cells = <0>;
1538 compatible = "qcom,geni-spi";
1540 clock-names = "se";
1545 dma-names = "tx", "rx";
1546 power-domains = <&rpmhpd RPMHPD_CX>;
1547 operating-points-v2 = <&qup_opp_table>;
1551 interconnect-names = "qup-core",
1552 "qup-config",
1553 "qup-memory";
1554 #address-cells = <1>;
1555 #size-cells = <0>;
1560 compatible = "qcom,geni-i2c";
1562 clock-names = "se";
1564 pinctrl-names = "default";
1565 pinctrl-0 = <&qup_i2c4_default>;
1569 dma-names = "tx", "rx";
1570 power-domains = <&rpmhpd SM8250_CX>;
1574 interconnect-names = "qup-core",
1575 "qup-config",
1576 "qup-memory";
1577 #address-cells = <1>;
1578 #size-cells = <0>;
1583 compatible = "qcom,geni-spi";
1585 clock-names = "se";
1590 dma-names = "tx", "rx";
1591 power-domains = <&rpmhpd RPMHPD_CX>;
1592 operating-points-v2 = <&qup_opp_table>;
1596 interconnect-names = "qup-core",
1597 "qup-config",
1598 "qup-memory";
1599 #address-cells = <1>;
1600 #size-cells = <0>;
1605 compatible = "qcom,geni-i2c";
1607 clock-names = "se";
1609 pinctrl-names = "default";
1610 pinctrl-0 = <&qup_i2c5_default>;
1614 dma-names = "tx", "rx";
1615 power-domains = <&rpmhpd SM8250_CX>;
1619 interconnect-names = "qup-core",
1620 "qup-config",
1621 "qup-memory";
1622 #address-cells = <1>;
1623 #size-cells = <0>;
1628 compatible = "qcom,geni-spi";
1630 clock-names = "se";
1635 dma-names = "tx", "rx";
1636 power-domains = <&rpmhpd RPMHPD_CX>;
1637 operating-points-v2 = <&qup_opp_table>;
1641 interconnect-names = "qup-core",
1642 "qup-config",
1643 "qup-memory";
1644 #address-cells = <1>;
1645 #size-cells = <0>;
1650 compatible = "qcom,geni-i2c";
1652 clock-names = "se";
1654 pinctrl-names = "default";
1655 pinctrl-0 = <&qup_i2c6_default>;
1659 dma-names = "tx", "rx";
1660 power-domains = <&rpmhpd SM8250_CX>;
1664 interconnect-names = "qup-core",
1665 "qup-config",
1666 "qup-memory";
1667 #address-cells = <1>;
1668 #size-cells = <0>;
1673 compatible = "qcom,geni-spi";
1675 clock-names = "se";
1680 dma-names = "tx", "rx";
1681 power-domains = <&rpmhpd RPMHPD_CX>;
1682 operating-points-v2 = <&qup_opp_table>;
1686 interconnect-names = "qup-core",
1687 "qup-config",
1688 "qup-memory";
1689 #address-cells = <1>;
1690 #size-cells = <0>;
1695 compatible = "qcom,geni-uart";
1697 clock-names = "se";
1699 pinctrl-names = "default";
1700 pinctrl-0 = <&qup_uart6_default>;
1702 power-domains = <&rpmhpd RPMHPD_CX>;
1703 operating-points-v2 = <&qup_opp_table>;
1706 interconnect-names = "qup-core",
1707 "qup-config";
1712 compatible = "qcom,geni-i2c";
1714 clock-names = "se";
1716 pinctrl-names = "default";
1717 pinctrl-0 = <&qup_i2c7_default>;
1721 dma-names = "tx", "rx";
1722 power-domains = <&rpmhpd SM8250_CX>;
1726 interconnect-names = "qup-core",
1727 "qup-config",
1728 "qup-memory";
1729 #address-cells = <1>;
1730 #size-cells = <0>;
1735 compatible = "qcom,geni-spi";
1737 clock-names = "se";
1742 dma-names = "tx", "rx";
1743 power-domains = <&rpmhpd RPMHPD_CX>;
1744 operating-points-v2 = <&qup_opp_table>;
1748 interconnect-names = "qup-core",
1749 "qup-config",
1750 "qup-memory";
1751 #address-cells = <1>;
1752 #size-cells = <0>;
1757 gpi_dma1: dma-controller@a00000 {
1758 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1770 dma-channels = <10>;
1771 dma-channel-mask = <0x3f>;
1773 #dma-cells = <3>;
1778 compatible = "qcom,geni-se-qup";
1780 clock-names = "m-ahb", "s-ahb";
1783 #address-cells = <2>;
1784 #size-cells = <2>;
1790 compatible = "qcom,geni-i2c";
1792 clock-names = "se";
1794 pinctrl-names = "default";
1795 pinctrl-0 = <&qup_i2c8_default>;
1799 dma-names = "tx", "rx";
1800 power-domains = <&rpmhpd SM8250_CX>;
1804 interconnect-names = "qup-core",
1805 "qup-config",
1806 "qup-memory";
1807 #address-cells = <1>;
1808 #size-cells = <0>;
1813 compatible = "qcom,geni-spi";
1815 clock-names = "se";
1820 dma-names = "tx", "rx";
1821 power-domains = <&rpmhpd RPMHPD_CX>;
1822 operating-points-v2 = <&qup_opp_table>;
1826 interconnect-names = "qup-core",
1827 "qup-config",
1828 "qup-memory";
1829 #address-cells = <1>;
1830 #size-cells = <0>;
1835 compatible = "qcom,geni-i2c";
1837 clock-names = "se";
1839 pinctrl-names = "default";
1840 pinctrl-0 = <&qup_i2c9_default>;
1844 dma-names = "tx", "rx";
1845 power-domains = <&rpmhpd SM8250_CX>;
1849 interconnect-names = "qup-core",
1850 "qup-config",
1851 "qup-memory";
1852 #address-cells = <1>;
1853 #size-cells = <0>;
1858 compatible = "qcom,geni-spi";
1860 clock-names = "se";
1865 dma-names = "tx", "rx";
1866 power-domains = <&rpmhpd RPMHPD_CX>;
1867 operating-points-v2 = <&qup_opp_table>;
1871 interconnect-names = "qup-core",
1872 "qup-config",
1873 "qup-memory";
1874 #address-cells = <1>;
1875 #size-cells = <0>;
1880 compatible = "qcom,geni-i2c";
1882 clock-names = "se";
1884 pinctrl-names = "default";
1885 pinctrl-0 = <&qup_i2c10_default>;
1889 dma-names = "tx", "rx";
1890 power-domains = <&rpmhpd SM8250_CX>;
1894 interconnect-names = "qup-core",
1895 "qup-config",
1896 "qup-memory";
1897 #address-cells = <1>;
1898 #size-cells = <0>;
1903 compatible = "qcom,geni-spi";
1905 clock-names = "se";
1910 dma-names = "tx", "rx";
1911 power-domains = <&rpmhpd RPMHPD_CX>;
1912 operating-points-v2 = <&qup_opp_table>;
1916 interconnect-names = "qup-core",
1917 "qup-config",
1918 "qup-memory";
1919 #address-cells = <1>;
1920 #size-cells = <0>;
1925 compatible = "qcom,geni-i2c";
1927 clock-names = "se";
1929 pinctrl-names = "default";
1930 pinctrl-0 = <&qup_i2c11_default>;
1934 dma-names = "tx", "rx";
1935 power-domains = <&rpmhpd SM8250_CX>;
1939 interconnect-names = "qup-core",
1940 "qup-config",
1941 "qup-memory";
1942 #address-cells = <1>;
1943 #size-cells = <0>;
1948 compatible = "qcom,geni-spi";
1950 clock-names = "se";
1955 dma-names = "tx", "rx";
1956 power-domains = <&rpmhpd RPMHPD_CX>;
1957 operating-points-v2 = <&qup_opp_table>;
1961 interconnect-names = "qup-core",
1962 "qup-config",
1963 "qup-memory";
1964 #address-cells = <1>;
1965 #size-cells = <0>;
1970 compatible = "qcom,geni-i2c";
1972 clock-names = "se";
1974 pinctrl-names = "default";
1975 pinctrl-0 = <&qup_i2c12_default>;
1979 dma-names = "tx", "rx";
1980 power-domains = <&rpmhpd SM8250_CX>;
1984 interconnect-names = "qup-core",
1985 "qup-config",
1986 "qup-memory";
1987 #address-cells = <1>;
1988 #size-cells = <0>;
1993 compatible = "qcom,geni-spi";
1995 clock-names = "se";
2000 dma-names = "tx", "rx";
2001 power-domains = <&rpmhpd RPMHPD_CX>;
2002 operating-points-v2 = <&qup_opp_table>;
2006 interconnect-names = "qup-core",
2007 "qup-config",
2008 "qup-memory";
2009 #address-cells = <1>;
2010 #size-cells = <0>;
2015 compatible = "qcom,geni-debug-uart";
2017 clock-names = "se";
2019 pinctrl-names = "default";
2020 pinctrl-0 = <&qup_uart12_default>;
2022 power-domains = <&rpmhpd RPMHPD_CX>;
2023 operating-points-v2 = <&qup_opp_table>;
2026 interconnect-names = "qup-core",
2027 "qup-config";
2032 compatible = "qcom,geni-i2c";
2034 clock-names = "se";
2036 pinctrl-names = "default";
2037 pinctrl-0 = <&qup_i2c13_default>;
2041 dma-names = "tx", "rx";
2042 power-domains = <&rpmhpd SM8250_CX>;
2046 interconnect-names = "qup-core",
2047 "qup-config",
2048 "qup-memory";
2049 #address-cells = <1>;
2050 #size-cells = <0>;
2055 compatible = "qcom,geni-spi";
2057 clock-names = "se";
2062 dma-names = "tx", "rx";
2063 power-domains = <&rpmhpd RPMHPD_CX>;
2064 operating-points-v2 = <&qup_opp_table>;
2068 interconnect-names = "qup-core",
2069 "qup-config",
2070 "qup-memory";
2071 #address-cells = <1>;
2072 #size-cells = <0>;
2078 compatible = "qcom,sm8250-config-noc";
2080 #interconnect-cells = <2>;
2081 qcom,bcm-voters = <&apps_bcm_voter>;
2085 compatible = "qcom,sm8250-system-noc";
2087 #interconnect-cells = <2>;
2088 qcom,bcm-voters = <&apps_bcm_voter>;
2092 compatible = "qcom,sm8250-mc-virt";
2094 #interconnect-cells = <2>;
2095 qcom,bcm-voters = <&apps_bcm_voter>;
2099 compatible = "qcom,sm8250-aggre1-noc";
2101 #interconnect-cells = <2>;
2102 qcom,bcm-voters = <&apps_bcm_voter>;
2106 compatible = "qcom,sm8250-aggre2-noc";
2108 #interconnect-cells = <2>;
2109 qcom,bcm-voters = <&apps_bcm_voter>;
2113 compatible = "qcom,sm8250-compute-noc";
2115 #interconnect-cells = <2>;
2116 qcom,bcm-voters = <&apps_bcm_voter>;
2120 compatible = "qcom,sm8250-mmss-noc";
2122 #interconnect-cells = <2>;
2123 qcom,bcm-voters = <&apps_bcm_voter>;
2127 compatible = "qcom,pcie-sm8250";
2134 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2136 linux,pci-domain = <0>;
2137 bus-range = <0x00 0xff>;
2138 num-lanes = <1>;
2140 #address-cells = <3>;
2141 #size-cells = <2>;
2154 interrupt-names = "msi0",
2162 #interrupt-cells = <1>;
2163 interrupt-map-mask = <0 0 0 0x7>;
2164 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2177 clock-names = "pipe",
2186 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2190 reset-names = "pci";
2192 power-domains = <&gcc PCIE_0_GDSC>;
2195 phy-names = "pciephy";
2197 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
2198 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
2200 pinctrl-names = "default";
2201 pinctrl-0 = <&pcie0_default_state>;
2202 dma-coherent;
2209 bus-range = <0x01 0xff>;
2211 #address-cells = <3>;
2212 #size-cells = <2>;
2218 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
2226 clock-names = "aux",
2232 clock-output-names = "pcie_0_pipe_clk";
2233 #clock-cells = <0>;
2235 #phy-cells = <0>;
2238 reset-names = "phy";
2240 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2241 assigned-clock-rates = <100000000>;
2247 compatible = "qcom,pcie-sm8250";
2254 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2256 linux,pci-domain = <1>;
2257 bus-range = <0x00 0xff>;
2258 num-lanes = <2>;
2260 #address-cells = <3>;
2261 #size-cells = <2>;
2274 interrupt-names = "msi0",
2282 #interrupt-cells = <1>;
2283 interrupt-map-mask = <0 0 0 0x7>;
2284 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2298 clock-names = "pipe",
2308 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2309 assigned-clock-rates = <19200000>;
2311 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2315 reset-names = "pci";
2317 power-domains = <&gcc PCIE_1_GDSC>;
2320 phy-names = "pciephy";
2322 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
2323 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
2325 pinctrl-names = "default";
2326 pinctrl-0 = <&pcie1_default_state>;
2327 dma-coherent;
2334 bus-range = <0x01 0xff>;
2336 #address-cells = <3>;
2337 #size-cells = <2>;
2343 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2351 clock-names = "aux",
2357 clock-output-names = "pcie_1_pipe_clk";
2358 #clock-cells = <0>;
2360 #phy-cells = <0>;
2363 reset-names = "phy";
2365 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2366 assigned-clock-rates = <100000000>;
2372 compatible = "qcom,pcie-sm8250";
2379 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2381 linux,pci-domain = <2>;
2382 bus-range = <0x00 0xff>;
2383 num-lanes = <2>;
2385 #address-cells = <3>;
2386 #size-cells = <2>;
2399 interrupt-names = "msi0",
2407 #interrupt-cells = <1>;
2408 interrupt-map-mask = <0 0 0 0x7>;
2409 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2423 clock-names = "pipe",
2433 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2434 assigned-clock-rates = <19200000>;
2436 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2440 reset-names = "pci";
2442 power-domains = <&gcc PCIE_2_GDSC>;
2445 phy-names = "pciephy";
2447 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
2448 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
2450 pinctrl-names = "default";
2451 pinctrl-0 = <&pcie2_default_state>;
2452 dma-coherent;
2459 bus-range = <0x01 0xff>;
2461 #address-cells = <3>;
2462 #size-cells = <2>;
2468 compatible = "qcom,sm8250-qmp-modem-pcie-phy";
2476 clock-names = "aux",
2482 clock-output-names = "pcie_2_pipe_clk";
2483 #clock-cells = <0>;
2485 #phy-cells = <0>;
2488 reset-names = "phy";
2490 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2491 assigned-clock-rates = <100000000>;
2497 compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
2498 "jedec,ufs-2.0";
2502 phy-names = "ufsphy";
2503 lanes-per-direction = <2>;
2504 #reset-cells = <1>;
2506 reset-names = "rst";
2508 power-domains = <&gcc UFS_PHY_GDSC>;
2512 clock-names =
2531 operating-points-v2 = <&ufs_opp_table>;
2535 interconnect-names = "ufs-ddr", "cpu-ufs";
2539 ufs_opp_table: opp-table {
2540 compatible = "operating-points-v2";
2542 opp-37500000 {
2543 opp-hz = /bits/ 64 <37500000>,
2551 required-opps = <&rpmhpd_opp_low_svs>;
2554 opp-300000000 {
2555 opp-hz = /bits/ 64 <300000000>,
2563 required-opps = <&rpmhpd_opp_nom>;
2569 compatible = "qcom,sm8250-qmp-ufs-phy";
2575 clock-names = "ref",
2580 reset-names = "ufsphy";
2582 power-domains = <&gcc UFS_PHY_GDSC>;
2584 #phy-cells = <0>;
2589 cryptobam: dma-controller@1dc4000 {
2590 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2593 #dma-cells = <1>;
2595 qcom,controlled-remotely;
2596 num-channels = <8>;
2597 qcom,num-ees = <2>;
2607 compatible = "qcom,sm8250-qce", "qcom,sm8150-qce", "qcom,qce";
2610 dma-names = "rx", "tx";
2618 interconnect-names = "memory";
2622 compatible = "qcom,tcsr-mutex";
2624 #hwlock-cells = <1>;
2628 compatible = "qcom,sm8250-tcsr", "syscon";
2633 compatible = "qcom,sm8250-lpass-wsa-macro";
2641 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2643 #clock-cells = <0>;
2644 clock-output-names = "mclk";
2645 #sound-dai-cells = <1>;
2647 pinctrl-names = "default";
2648 pinctrl-0 = <&wsa_swr_active>;
2655 compatible = "qcom,soundwire-v1.5.1";
2658 clock-names = "iface";
2660 qcom,din-ports = <2>;
2661 qcom,dout-ports = <6>;
2663 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2664 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2665 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2666 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2668 #sound-dai-cells = <1>;
2669 #address-cells = <2>;
2670 #size-cells = <0>;
2676 compatible = "qcom,sm8250-lpass-va-macro";
2682 clock-names = "mclk", "macro", "dcodec";
2684 #clock-cells = <0>;
2685 clock-output-names = "fsgen";
2686 #sound-dai-cells = <1>;
2690 pinctrl-names = "default";
2691 pinctrl-0 = <&rx_swr_active>;
2692 compatible = "qcom,sm8250-lpass-rx-macro";
2702 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2704 #clock-cells = <0>;
2705 clock-output-names = "mclk";
2706 #sound-dai-cells = <1>;
2711 compatible = "qcom,soundwire-v1.5.1";
2715 clock-names = "iface";
2717 qcom,din-ports = <0>;
2718 qcom,dout-ports = <5>;
2720 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2721 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2722 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2723 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2724 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2725 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2726 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2727 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2728 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2730 #sound-dai-cells = <1>;
2731 #address-cells = <2>;
2732 #size-cells = <0>;
2736 pinctrl-names = "default";
2737 pinctrl-0 = <&tx_swr_active>;
2738 compatible = "qcom,sm8250-lpass-tx-macro";
2748 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2750 #clock-cells = <0>;
2751 clock-output-names = "mclk";
2752 #sound-dai-cells = <1>;
2758 compatible = "qcom,soundwire-v1.5.1";
2760 interrupt-names = "core";
2764 clock-names = "iface";
2767 qcom,din-ports = <5>;
2768 qcom,dout-ports = <0>;
2769 qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>;
2770 qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>;
2771 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>;
2772 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2773 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2774 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2775 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2776 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2777 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>;
2778 #sound-dai-cells = <1>;
2779 #address-cells = <2>;
2780 #size-cells = <0>;
2784 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
2787 gpio-controller;
2788 #gpio-cells = <2>;
2789 gpio-ranges = <&lpass_tlmm 0 0 14>;
2793 clock-names = "core", "audio";
2795 wsa_swr_active: wsa-swr-active-state {
2796 clk-pins {
2799 drive-strength = <2>;
2800 slew-rate = <1>;
2801 bias-disable;
2804 data-pins {
2807 drive-strength = <2>;
2808 slew-rate = <1>;
2809 bias-bus-hold;
2813 wsa_swr_sleep: wsa-swr-sleep-state {
2814 clk-pins {
2817 drive-strength = <2>;
2818 bias-pull-down;
2821 data-pins {
2824 drive-strength = <2>;
2825 bias-pull-down;
2829 dmic01_active: dmic01-active-state {
2830 clk-pins {
2833 drive-strength = <8>;
2834 output-high;
2836 data-pins {
2839 drive-strength = <8>;
2843 dmic01_sleep: dmic01-sleep-state {
2844 clk-pins {
2847 drive-strength = <2>;
2848 bias-disable;
2849 output-low;
2852 data-pins {
2855 drive-strength = <2>;
2856 bias-pull-down;
2860 rx_swr_active: rx-swr-active-state {
2861 clk-pins {
2864 drive-strength = <2>;
2865 slew-rate = <1>;
2866 bias-disable;
2869 data-pins {
2872 drive-strength = <2>;
2873 slew-rate = <1>;
2874 bias-bus-hold;
2878 tx_swr_active: tx-swr-active-state {
2879 clk-pins {
2882 drive-strength = <2>;
2883 slew-rate = <1>;
2884 bias-disable;
2887 data-pins {
2890 drive-strength = <2>;
2891 slew-rate = <1>;
2892 bias-bus-hold;
2896 tx_swr_sleep: tx-swr-sleep-state {
2897 clk-pins {
2900 drive-strength = <2>;
2901 bias-pull-down;
2904 data1-pins {
2907 drive-strength = <2>;
2908 bias-bus-hold;
2911 data2-pins {
2914 drive-strength = <2>;
2915 bias-pull-down;
2921 compatible = "qcom,adreno-650.2",
2925 reg-names = "kgsl_3d0_reg_memory";
2931 operating-points-v2 = <&gpu_opp_table>;
2935 nvmem-cells = <&gpu_speed_bin>;
2936 nvmem-cell-names = "speed_bin";
2937 #cooling-cells = <2>;
2941 zap-shader {
2942 memory-region = <&gpu_mem>;
2945 gpu_opp_table: opp-table {
2946 compatible = "operating-points-v2";
2948 opp-670000000 {
2949 opp-hz = /bits/ 64 <670000000>;
2950 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2951 opp-supported-hw = <0xa>;
2954 opp-587000000 {
2955 opp-hz = /bits/ 64 <587000000>;
2956 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2957 opp-supported-hw = <0xb>;
2960 opp-525000000 {
2961 opp-hz = /bits/ 64 <525000000>;
2962 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2963 opp-supported-hw = <0xf>;
2966 opp-490000000 {
2967 opp-hz = /bits/ 64 <490000000>;
2968 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2969 opp-supported-hw = <0xf>;
2972 opp-441600000 {
2973 opp-hz = /bits/ 64 <441600000>;
2974 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2975 opp-supported-hw = <0xf>;
2978 opp-400000000 {
2979 opp-hz = /bits/ 64 <400000000>;
2980 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2981 opp-supported-hw = <0xf>;
2984 opp-305000000 {
2985 opp-hz = /bits/ 64 <305000000>;
2986 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2987 opp-supported-hw = <0xf>;
2993 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2999 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
3003 interrupt-names = "hfi", "gmu";
3010 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
3012 power-domains = <&gpucc GPU_CX_GDSC>,
3014 power-domain-names = "cx", "gx";
3018 operating-points-v2 = <&gmu_opp_table>;
3022 gmu_opp_table: opp-table {
3023 compatible = "operating-points-v2";
3025 opp-200000000 {
3026 opp-hz = /bits/ 64 <200000000>;
3027 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3032 gpucc: clock-controller@3d90000 {
3033 compatible = "qcom,sm8250-gpucc";
3038 clock-names = "bi_tcxo",
3041 #clock-cells = <1>;
3042 #reset-cells = <1>;
3043 #power-domain-cells = <1>;
3047 compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu",
3048 "qcom,smmu-500", "arm,mmu-500";
3050 #iommu-cells = <2>;
3051 #global-interrupts = <2>;
3065 clock-names = "ahb", "bus", "iface";
3067 power-domains = <&gpucc GPU_CX_GDSC>;
3068 dma-coherent;
3072 compatible = "qcom,sm8250-slpi-pas";
3075 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
3080 interrupt-names = "wdog", "fatal", "ready",
3081 "handover", "stop-ack";
3084 clock-names = "xo";
3086 power-domains = <&rpmhpd RPMHPD_LCX>,
3088 power-domain-names = "lcx", "lmx";
3090 memory-region = <&slpi_mem>;
3094 qcom,smem-states = <&smp2p_slpi_out 0>;
3095 qcom,smem-state-names = "stop";
3099 glink-edge {
3100 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
3107 qcom,remote-pid = <3>;
3111 qcom,glink-channels = "fastrpcglink-apps-dsp";
3113 qcom,non-secure-domain;
3114 #address-cells = <1>;
3115 #size-cells = <0>;
3117 compute-cb@1 {
3118 compatible = "qcom,fastrpc-compute-cb";
3123 compute-cb@2 {
3124 compatible = "qcom,fastrpc-compute-cb";
3129 compute-cb@3 {
3130 compatible = "qcom,fastrpc-compute-cb";
3133 /* note: shared-cb = <4> in downstream */
3140 compatible = "arm,coresight-stm", "arm,primecell";
3142 reg-names = "stm-base", "stm-stimulus-base";
3145 clock-names = "apb_pclk";
3147 out-ports {
3150 remote-endpoint = <&funnel0_in7>;
3157 compatible = "qcom,coresight-tpda", "arm,primecell";
3161 clock-names = "apb_pclk";
3163 out-ports {
3167 remote-endpoint = <&funnel_qatb_in_tpda>;
3172 in-ports {
3173 #address-cells = <1>;
3174 #size-cells = <0>;
3179 remote-endpoint = <&tpdm_mm_out_tpda9>;
3186 remote-endpoint = <&tpdm_prng_out_tpda_23>;
3193 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3197 clock-names = "apb_pclk";
3199 out-ports {
3202 remote-endpoint = <&funnel_in0_in_funnel_qatb>;
3207 in-ports {
3210 remote-endpoint = <&tpda_out_funnel_qatb>;
3217 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3221 clock-names = "apb_pclk";
3223 out-ports {
3226 remote-endpoint = <&funnel_merg_in_funnel_in0>;
3231 in-ports {
3232 #address-cells = <1>;
3233 #size-cells = <0>;
3238 remote-endpoint = <&funnel_qatb_out_funnel_in0>;
3245 remote-endpoint = <&stm_out>;
3252 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3256 clock-names = "apb_pclk";
3258 out-ports {
3261 remote-endpoint = <&funnel_merg_in_funnel_in1>;
3266 in-ports {
3267 #address-cells = <1>;
3268 #size-cells = <0>;
3273 remote-endpoint = <&funnel_apss_merg_out_funnel_in1>;
3280 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3284 clock-names = "apb_pclk";
3286 out-ports {
3289 remote-endpoint = <&funnel_swao_in_funnel_merg>;
3294 in-ports {
3295 #address-cells = <1>;
3296 #size-cells = <0>;
3301 remote-endpoint = <&funnel_in0_out_funnel_merg>;
3308 remote-endpoint = <&funnel_in1_out_funnel_merg>;
3315 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3319 clock-names = "apb_pclk";
3321 out-ports {
3324 remote-endpoint = <&etr_in>;
3329 in-ports {
3332 remote-endpoint = <&replicator_swao_out_cx_in>;
3339 compatible = "arm,coresight-tmc", "arm,primecell";
3343 clock-names = "apb_pclk";
3344 arm,scatter-gather;
3346 in-ports {
3349 remote-endpoint = <&replicator_out>;
3356 compatible = "qcom,coresight-tpdm", "arm,primecell";
3360 clock-names = "apb_pclk";
3362 out-ports {
3365 remote-endpoint = <&tpda_23_in_tpdm_prng>;
3372 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3373 arm,primecell-periphid = <0x000bb908>;
3378 clock-names = "apb_pclk";
3380 out-ports {
3383 remote-endpoint = <&etf_in_funnel_swao_out>;
3388 in-ports {
3389 #address-cells = <1>;
3390 #size-cells = <0>;
3395 remote-endpoint = <&funnel_merg_out_funnel_swao>;
3402 compatible = "arm,coresight-tmc", "arm,primecell";
3406 clock-names = "apb_pclk";
3408 out-ports {
3411 remote-endpoint = <&replicator_in>;
3416 in-ports {
3420 remote-endpoint = <&funnel_swao_out_etf>;
3427 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3431 clock-names = "apb_pclk";
3433 out-ports {
3436 remote-endpoint = <&replicator_cx_in_swao_out>;
3441 in-ports {
3444 remote-endpoint = <&etf_out>;
3451 compatible = "qcom,coresight-tpdm", "arm,primecell";
3455 clock-names = "apb_pclk";
3457 out-ports {
3460 remote-endpoint = <&funnel_dl_mm_in_tpdm_mm>;
3467 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3471 clock-names = "apb_pclk";
3473 out-ports {
3476 remote-endpoint = <&funnel_dl_center_in_funnel_dl_mm>;
3481 in-ports {
3482 #address-cells = <1>;
3483 #size-cells = <0>;
3488 remote-endpoint = <&tpdm_mm_out_funnel_dl_mm>;
3495 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3499 clock-names = "apb_pclk";
3501 out-ports {
3504 remote-endpoint = <&tpda_9_in_tpdm_mm>;
3509 in-ports {
3510 #address-cells = <1>;
3511 #size-cells = <0>;
3516 remote-endpoint = <&funnel_dl_mm_out_funnel_dl_center>;
3523 compatible = "arm,coresight-etm4x", "arm,primecell";
3529 clock-names = "apb_pclk";
3530 arm,coresight-loses-context-with-cpu;
3532 out-ports {
3535 remote-endpoint = <&apss_funnel_in0>;
3542 compatible = "arm,coresight-etm4x", "arm,primecell";
3548 clock-names = "apb_pclk";
3549 arm,coresight-loses-context-with-cpu;
3551 out-ports {
3554 remote-endpoint = <&apss_funnel_in1>;
3561 compatible = "arm,coresight-etm4x", "arm,primecell";
3567 clock-names = "apb_pclk";
3568 arm,coresight-loses-context-with-cpu;
3570 out-ports {
3573 remote-endpoint = <&apss_funnel_in2>;
3580 compatible = "arm,coresight-etm4x", "arm,primecell";
3586 clock-names = "apb_pclk";
3587 arm,coresight-loses-context-with-cpu;
3589 out-ports {
3592 remote-endpoint = <&apss_funnel_in3>;
3599 compatible = "arm,coresight-etm4x", "arm,primecell";
3605 clock-names = "apb_pclk";
3606 arm,coresight-loses-context-with-cpu;
3608 out-ports {
3611 remote-endpoint = <&apss_funnel_in4>;
3618 compatible = "arm,coresight-etm4x", "arm,primecell";
3624 clock-names = "apb_pclk";
3625 arm,coresight-loses-context-with-cpu;
3627 out-ports {
3630 remote-endpoint = <&apss_funnel_in5>;
3637 compatible = "arm,coresight-etm4x", "arm,primecell";
3643 clock-names = "apb_pclk";
3644 arm,coresight-loses-context-with-cpu;
3646 out-ports {
3649 remote-endpoint = <&apss_funnel_in6>;
3656 compatible = "arm,coresight-etm4x", "arm,primecell";
3662 clock-names = "apb_pclk";
3663 arm,coresight-loses-context-with-cpu;
3665 out-ports {
3668 remote-endpoint = <&apss_funnel_in7>;
3675 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3679 clock-names = "apb_pclk";
3681 out-ports {
3684 remote-endpoint = <&funnel_apss_merg_in_funnel_apss>;
3689 in-ports {
3690 #address-cells = <1>;
3691 #size-cells = <0>;
3696 remote-endpoint = <&etm0_out>;
3703 remote-endpoint = <&etm1_out>;
3710 remote-endpoint = <&etm2_out>;
3717 remote-endpoint = <&etm3_out>;
3724 remote-endpoint = <&etm4_out>;
3731 remote-endpoint = <&etm5_out>;
3738 remote-endpoint = <&etm6_out>;
3745 remote-endpoint = <&etm7_out>;
3752 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3756 clock-names = "apb_pclk";
3758 out-ports {
3761 remote-endpoint = <&funnel_in1_in_funnel_apss_merg>;
3766 in-ports {
3769 remote-endpoint = <&funnel_apss_out_funnel_apss_merg>;
3776 compatible = "qcom,sm8250-cdsp-pas";
3779 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3784 interrupt-names = "wdog", "fatal", "ready",
3785 "handover", "stop-ack";
3788 clock-names = "xo";
3790 power-domains = <&rpmhpd RPMHPD_CX>;
3792 memory-region = <&cdsp_mem>;
3796 qcom,smem-states = <&smp2p_cdsp_out 0>;
3797 qcom,smem-state-names = "stop";
3801 glink-edge {
3802 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3809 qcom,remote-pid = <5>;
3813 qcom,glink-channels = "fastrpcglink-apps-dsp";
3815 qcom,non-secure-domain;
3816 #address-cells = <1>;
3817 #size-cells = <0>;
3819 compute-cb@1 {
3820 compatible = "qcom,fastrpc-compute-cb";
3825 compute-cb@2 {
3826 compatible = "qcom,fastrpc-compute-cb";
3831 compute-cb@3 {
3832 compatible = "qcom,fastrpc-compute-cb";
3837 compute-cb@4 {
3838 compatible = "qcom,fastrpc-compute-cb";
3843 compute-cb@5 {
3844 compatible = "qcom,fastrpc-compute-cb";
3849 compute-cb@6 {
3850 compatible = "qcom,fastrpc-compute-cb";
3855 compute-cb@7 {
3856 compatible = "qcom,fastrpc-compute-cb";
3861 compute-cb@8 {
3862 compatible = "qcom,fastrpc-compute-cb";
3873 compatible = "qcom,sm8250-usb-hs-phy",
3874 "qcom,usb-snps-hs-7nm-phy";
3877 #phy-cells = <0>;
3880 clock-names = "ref";
3886 compatible = "qcom,sm8250-usb-hs-phy",
3887 "qcom,usb-snps-hs-7nm-phy";
3890 #phy-cells = <0>;
3893 clock-names = "ref";
3899 compatible = "qcom,sm8250-qmp-usb3-dp-phy";
3907 clock-names = "aux",
3914 reset-names = "phy", "common";
3916 #clock-cells = <1>;
3917 #phy-cells = <1>;
3919 orientation-switch;
3922 #address-cells = <1>;
3923 #size-cells = <0>;
3934 remote-endpoint = <&usb_1_dwc3_ss_out>;
3947 compatible = "qcom,sm8250-qmp-usb3-uni-phy";
3954 clock-names = "aux",
3958 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3959 #clock-cells = <0>;
3960 #phy-cells = <0>;
3964 reset-names = "phy",
3971 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
3976 interrupt-names = "hc_irq", "pwr_irq";
3981 clock-names = "iface", "core", "xo";
3983 qcom,dll-config = <0x0007642c>;
3984 qcom,ddr-config = <0x80040868>;
3985 power-domains = <&rpmhpd RPMHPD_CX>;
3986 operating-points-v2 = <&sdhc2_opp_table>;
3990 sdhc2_opp_table: opp-table {
3991 compatible = "operating-points-v2";
3993 opp-19200000 {
3994 opp-hz = /bits/ 64 <19200000>;
3995 required-opps = <&rpmhpd_opp_min_svs>;
3998 opp-50000000 {
3999 opp-hz = /bits/ 64 <50000000>;
4000 required-opps = <&rpmhpd_opp_low_svs>;
4003 opp-100000000 {
4004 opp-hz = /bits/ 64 <100000000>;
4005 required-opps = <&rpmhpd_opp_svs>;
4008 opp-202000000 {
4009 opp-hz = /bits/ 64 <202000000>;
4010 required-opps = <&rpmhpd_opp_svs_l1>;
4016 compatible = "qcom,sm8250-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
4023 operating-points-v2 = <&llcc_bwmon_opp_table>;
4025 llcc_bwmon_opp_table: opp-table {
4026 compatible = "operating-points-v2";
4028 opp-800000 {
4029 opp-peak-kBps = <(200 * 4 * 1000)>;
4032 opp-1200000 {
4033 opp-peak-kBps = <(300 * 4 * 1000)>;
4036 opp-1804000 {
4037 opp-peak-kBps = <(451 * 4 * 1000)>;
4040 opp-2188000 {
4041 opp-peak-kBps = <(547 * 4 * 1000)>;
4044 opp-2724000 {
4045 opp-peak-kBps = <(681 * 4 * 1000)>;
4048 opp-3072000 {
4049 opp-peak-kBps = <(768 * 4 * 1000)>;
4052 opp-4068000 {
4053 opp-peak-kBps = <(1017 * 4 * 1000)>;
4058 opp-6220000 {
4059 opp-peak-kBps = <(1555 * 4 * 1000)>;
4062 opp-7216000 {
4063 opp-peak-kBps = <(1804 * 4 * 1000)>;
4066 opp-8368000 {
4067 opp-peak-kBps = <(2092 * 4 * 1000)>;
4071 opp-10944000 {
4072 opp-peak-kBps = <(2736 * 4 * 1000)>;
4078 compatible = "qcom,sm8250-cpu-bwmon", "qcom,sdm845-bwmon";
4084 operating-points-v2 = <&cpu_bwmon_opp_table>;
4086 cpu_bwmon_opp_table: opp-table {
4087 compatible = "operating-points-v2";
4089 opp-800000 {
4090 opp-peak-kBps = <(200 * 4 * 1000)>;
4093 opp-1804000 {
4094 opp-peak-kBps = <(451 * 4 * 1000)>;
4097 opp-2188000 {
4098 opp-peak-kBps = <(547 * 4 * 1000)>;
4101 opp-2724000 {
4102 opp-peak-kBps = <(681 * 4 * 1000)>;
4105 opp-3072000 {
4106 opp-peak-kBps = <(768 * 4 * 1000)>;
4111 opp-6220000 {
4112 opp-peak-kBps = <(1555 * 4 * 1000)>;
4115 opp-6832000 {
4116 opp-peak-kBps = <(1708 * 4 * 1000)>;
4119 opp-8368000 {
4120 opp-peak-kBps = <(2092 * 4 * 1000)>;
4126 opp-10944000 {
4127 opp-peak-kBps = <(2736 * 4 * 1000)>;
4131 opp-12784000 {
4132 opp-peak-kBps = <(3196 * 4 * 1000)>;
4138 compatible = "qcom,sm8250-dc-noc";
4140 #interconnect-cells = <2>;
4141 qcom,bcm-voters = <&apps_bcm_voter>;
4145 compatible = "qcom,sm8250-gem-noc";
4147 #interconnect-cells = <2>;
4148 qcom,bcm-voters = <&apps_bcm_voter>;
4152 compatible = "qcom,sm8250-npu-noc";
4154 #interconnect-cells = <2>;
4155 qcom,bcm-voters = <&apps_bcm_voter>;
4159 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4162 #address-cells = <2>;
4163 #size-cells = <2>;
4165 dma-ranges;
4173 clock-names = "cfg_noc",
4180 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4182 assigned-clock-rates = <19200000>, <200000000>;
4184 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4189 interrupt-names = "pwr_event",
4195 power-domains = <&gcc USB30_PRIM_GDSC>;
4196 wakeup-source;
4202 interconnect-names = "usb-ddr", "apps-usb";
4211 snps,dis-u1-entry-quirk;
4212 snps,dis-u2-entry-quirk;
4214 phy-names = "usb2-phy", "usb3-phy";
4217 #address-cells = <1>;
4218 #size-cells = <0>;
4231 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
4238 system-cache-controller@9200000 {
4239 compatible = "qcom,sm8250-llcc";
4243 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
4248 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4251 #address-cells = <2>;
4252 #size-cells = <2>;
4254 dma-ranges;
4262 clock-names = "cfg_noc",
4269 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4271 assigned-clock-rates = <19200000>, <200000000>;
4273 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
4278 interrupt-names = "pwr_event",
4284 power-domains = <&gcc USB30_SEC_GDSC>;
4285 wakeup-source;
4291 interconnect-names = "usb-ddr", "apps-usb";
4300 snps,dis-u1-entry-quirk;
4301 snps,dis-u2-entry-quirk;
4303 phy-names = "usb2-phy", "usb3-phy";
4307 venus: video-codec@aa00000 {
4308 compatible = "qcom,sm8250-venus";
4311 power-domains = <&videocc MVS0C_GDSC>,
4314 power-domain-names = "venus", "vcodec0", "mx";
4315 operating-points-v2 = <&venus_opp_table>;
4320 clock-names = "iface", "core", "vcodec0_core";
4324 interconnect-names = "cpu-cfg", "video-mem";
4327 memory-region = <&video_mem>;
4331 reset-names = "bus", "core";
4335 video-decoder {
4336 compatible = "venus-decoder";
4339 video-encoder {
4340 compatible = "venus-encoder";
4343 venus_opp_table: opp-table {
4344 compatible = "operating-points-v2";
4346 opp-720000000 {
4347 opp-hz = /bits/ 64 <720000000>;
4348 required-opps = <&rpmhpd_opp_low_svs>;
4351 opp-1014000000 {
4352 opp-hz = /bits/ 64 <1014000000>;
4353 required-opps = <&rpmhpd_opp_svs>;
4356 opp-1098000000 {
4357 opp-hz = /bits/ 64 <1098000000>;
4358 required-opps = <&rpmhpd_opp_svs_l1>;
4361 opp-1332000000 {
4362 opp-hz = /bits/ 64 <1332000000>;
4363 required-opps = <&rpmhpd_opp_nom>;
4368 videocc: clock-controller@abf0000 {
4369 compatible = "qcom,sm8250-videocc";
4374 power-domains = <&rpmhpd RPMHPD_MMCX>;
4375 required-opps = <&rpmhpd_opp_low_svs>;
4376 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
4377 #clock-cells = <1>;
4378 #reset-cells = <1>;
4379 #power-domain-cells = <1>;
4383 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4384 #address-cells = <1>;
4385 #size-cells = <0>;
4389 power-domains = <&camcc TITAN_TOP_GDSC>;
4396 clock-names = "camnoc_axi",
4402 pinctrl-0 = <&cci0_default>;
4403 pinctrl-1 = <&cci0_sleep>;
4404 pinctrl-names = "default", "sleep";
4408 cci0_i2c0: i2c-bus@0 {
4410 clock-frequency = <1000000>;
4411 #address-cells = <1>;
4412 #size-cells = <0>;
4415 cci0_i2c1: i2c-bus@1 {
4417 clock-frequency = <1000000>;
4418 #address-cells = <1>;
4419 #size-cells = <0>;
4424 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4425 #address-cells = <1>;
4426 #size-cells = <0>;
4430 power-domains = <&camcc TITAN_TOP_GDSC>;
4437 clock-names = "camnoc_axi",
4443 pinctrl-0 = <&cci1_default>;
4444 pinctrl-1 = <&cci1_sleep>;
4445 pinctrl-names = "default", "sleep";
4449 cci1_i2c0: i2c-bus@0 {
4451 clock-frequency = <1000000>;
4452 #address-cells = <1>;
4453 #size-cells = <0>;
4456 cci1_i2c1: i2c-bus@1 {
4458 clock-frequency = <1000000>;
4459 #address-cells = <1>;
4460 #size-cells = <0>;
4465 compatible = "qcom,sm8250-camss";
4478 reg-names = "csiphy0",
4503 interrupt-names = "csiphy0",
4518 power-domains = <&camcc IFE_0_GDSC>,
4560 clock-names = "cam_ahb_clk",
4611 interconnect-names = "cam_ahb",
4617 #address-cells = <1>;
4618 #size-cells = <0>;
4646 camcc: clock-controller@ad00000 {
4647 compatible = "qcom,sm8250-camcc";
4653 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
4654 power-domains = <&rpmhpd RPMHPD_MMCX>;
4655 required-opps = <&rpmhpd_opp_low_svs>;
4657 #clock-cells = <1>;
4658 #reset-cells = <1>;
4659 #power-domain-cells = <1>;
4662 mdss: display-subsystem@ae00000 {
4663 compatible = "qcom,sm8250-mdss";
4665 reg-names = "mdss";
4669 interconnect-names = "mdp0-mem", "mdp1-mem";
4671 power-domains = <&dispcc MDSS_GDSC>;
4677 clock-names = "iface", "bus", "nrt_bus", "core";
4680 interrupt-controller;
4681 #interrupt-cells = <1>;
4687 #address-cells = <2>;
4688 #size-cells = <2>;
4691 mdss_mdp: display-controller@ae01000 {
4692 compatible = "qcom,sm8250-dpu";
4695 reg-names = "mdp", "vbif";
4701 clock-names = "iface", "bus", "core", "vsync";
4703 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4704 assigned-clock-rates = <19200000>;
4706 operating-points-v2 = <&mdp_opp_table>;
4707 power-domains = <&rpmhpd RPMHPD_MMCX>;
4709 interrupt-parent = <&mdss>;
4713 #address-cells = <1>;
4714 #size-cells = <0>;
4719 remote-endpoint = <&mdss_dsi0_in>;
4726 remote-endpoint = <&mdss_dsi1_in>;
4734 remote-endpoint = <&mdss_dp_in>;
4739 mdp_opp_table: opp-table {
4740 compatible = "operating-points-v2";
4742 opp-200000000 {
4743 opp-hz = /bits/ 64 <200000000>;
4744 required-opps = <&rpmhpd_opp_low_svs>;
4747 opp-300000000 {
4748 opp-hz = /bits/ 64 <300000000>;
4749 required-opps = <&rpmhpd_opp_svs>;
4752 opp-345000000 {
4753 opp-hz = /bits/ 64 <345000000>;
4754 required-opps = <&rpmhpd_opp_svs_l1>;
4757 opp-460000000 {
4758 opp-hz = /bits/ 64 <460000000>;
4759 required-opps = <&rpmhpd_opp_nom>;
4764 mdss_dp: displayport-controller@ae90000 {
4765 compatible = "qcom,sm8250-dp", "qcom,sm8350-dp";
4771 interrupt-parent = <&mdss>;
4778 clock-names = "core_iface",
4784 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4786 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4790 phy-names = "dp";
4792 #sound-dai-cells = <0>;
4794 operating-points-v2 = <&dp_opp_table>;
4795 power-domains = <&rpmhpd SM8250_MMCX>;
4800 #address-cells = <1>;
4801 #size-cells = <0>;
4806 remote-endpoint = <&dpu_intf0_out>;
4818 dp_opp_table: opp-table {
4819 compatible = "operating-points-v2";
4821 opp-160000000 {
4822 opp-hz = /bits/ 64 <160000000>;
4823 required-opps = <&rpmhpd_opp_low_svs>;
4826 opp-270000000 {
4827 opp-hz = /bits/ 64 <270000000>;
4828 required-opps = <&rpmhpd_opp_svs>;
4831 opp-540000000 {
4832 opp-hz = /bits/ 64 <540000000>;
4833 required-opps = <&rpmhpd_opp_svs_l1>;
4836 opp-810000000 {
4837 opp-hz = /bits/ 64 <810000000>;
4838 required-opps = <&rpmhpd_opp_nom>;
4844 compatible = "qcom,sm8250-dsi-ctrl",
4845 "qcom,mdss-dsi-ctrl";
4847 reg-names = "dsi_ctrl";
4849 interrupt-parent = <&mdss>;
4858 clock-names = "byte",
4865 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
4867 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
4870 operating-points-v2 = <&dsi_opp_table>;
4871 power-domains = <&rpmhpd RPMHPD_MMCX>;
4877 #address-cells = <1>;
4878 #size-cells = <0>;
4881 #address-cells = <1>;
4882 #size-cells = <0>;
4887 remote-endpoint = <&dpu_intf1_out>;
4898 dsi_opp_table: opp-table {
4899 compatible = "operating-points-v2";
4901 opp-187500000 {
4902 opp-hz = /bits/ 64 <187500000>;
4903 required-opps = <&rpmhpd_opp_low_svs>;
4906 opp-300000000 {
4907 opp-hz = /bits/ 64 <300000000>;
4908 required-opps = <&rpmhpd_opp_svs>;
4911 opp-358000000 {
4912 opp-hz = /bits/ 64 <358000000>;
4913 required-opps = <&rpmhpd_opp_svs_l1>;
4919 compatible = "qcom,dsi-phy-7nm";
4923 reg-names = "dsi_phy",
4927 #clock-cells = <1>;
4928 #phy-cells = <0>;
4932 clock-names = "iface", "ref";
4938 compatible = "qcom,sm8250-dsi-ctrl",
4939 "qcom,mdss-dsi-ctrl";
4941 reg-names = "dsi_ctrl";
4943 interrupt-parent = <&mdss>;
4952 clock-names = "byte",
4959 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
4961 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
4964 operating-points-v2 = <&dsi_opp_table>;
4965 power-domains = <&rpmhpd RPMHPD_MMCX>;
4971 #address-cells = <1>;
4972 #size-cells = <0>;
4975 #address-cells = <1>;
4976 #size-cells = <0>;
4981 remote-endpoint = <&dpu_intf2_out>;
4994 compatible = "qcom,dsi-phy-7nm";
4998 reg-names = "dsi_phy",
5002 #clock-cells = <1>;
5003 #phy-cells = <0>;
5007 clock-names = "iface", "ref";
5013 dispcc: clock-controller@af00000 {
5014 compatible = "qcom,sm8250-dispcc";
5016 power-domains = <&rpmhpd RPMHPD_MMCX>;
5017 required-opps = <&rpmhpd_opp_low_svs>;
5025 clock-names = "bi_tcxo",
5032 #clock-cells = <1>;
5033 #reset-cells = <1>;
5034 #power-domain-cells = <1>;
5037 pdc: interrupt-controller@b220000 {
5038 compatible = "qcom,sm8250-pdc", "qcom,pdc";
5040 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
5042 #interrupt-cells = <2>;
5043 interrupt-parent = <&intc>;
5044 interrupt-controller;
5047 tsens0: thermal-sensor@c263000 {
5048 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5054 interrupt-names = "uplow", "critical";
5055 #thermal-sensor-cells = <1>;
5058 tsens1: thermal-sensor@c265000 {
5059 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5065 interrupt-names = "uplow", "critical";
5066 #thermal-sensor-cells = <1>;
5069 aoss_qmp: power-management@c300000 {
5070 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp";
5072 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
5078 #clock-cells = <0>;
5082 compatible = "qcom,rpmh-stats";
5087 compatible = "qcom,spmi-pmic-arb";
5093 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5094 interrupt-names = "periph_irq";
5095 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5098 #address-cells = <2>;
5099 #size-cells = <0>;
5100 interrupt-controller;
5101 #interrupt-cells = <4>;
5105 compatible = "qcom,sm8250-pinctrl";
5109 reg-names = "west", "south", "north";
5111 gpio-controller;
5112 #gpio-cells = <2>;
5113 interrupt-controller;
5114 #interrupt-cells = <2>;
5115 gpio-ranges = <&tlmm 0 0 181>;
5116 wakeup-parent = <&pdc>;
5118 cam2_default: cam2-default-state {
5119 rst-pins {
5122 drive-strength = <2>;
5123 bias-disable;
5126 mclk-pins {
5129 drive-strength = <16>;
5130 bias-disable;
5134 cam2_suspend: cam2-suspend-state {
5135 rst-pins {
5138 drive-strength = <2>;
5139 bias-pull-down;
5140 output-low;
5143 mclk-pins {
5146 drive-strength = <2>;
5147 bias-disable;
5151 cci0_default: cci0-default-state {
5152 cci0_i2c0_default: cci0-i2c0-default-pins {
5157 bias-pull-up;
5158 drive-strength = <2>; /* 2 mA */
5161 cci0_i2c1_default: cci0-i2c1-default-pins {
5166 bias-pull-up;
5167 drive-strength = <2>; /* 2 mA */
5171 cci0_sleep: cci0-sleep-state {
5172 cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
5177 drive-strength = <2>; /* 2 mA */
5178 bias-pull-down;
5181 cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
5186 drive-strength = <2>; /* 2 mA */
5187 bias-pull-down;
5191 cci1_default: cci1-default-state {
5192 cci1_i2c0_default: cci1-i2c0-default-pins {
5197 bias-pull-up;
5198 drive-strength = <2>; /* 2 mA */
5201 cci1_i2c1_default: cci1-i2c1-default-pins {
5206 bias-pull-up;
5207 drive-strength = <2>; /* 2 mA */
5211 cci1_sleep: cci1-sleep-state {
5212 cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
5217 bias-pull-down;
5218 drive-strength = <2>; /* 2 mA */
5221 cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
5226 bias-pull-down;
5227 drive-strength = <2>; /* 2 mA */
5231 pri_mi2s_active: pri-mi2s-active-state {
5232 sclk-pins {
5235 drive-strength = <8>;
5236 bias-disable;
5239 ws-pins {
5242 drive-strength = <8>;
5243 output-high;
5246 data0-pins {
5249 drive-strength = <8>;
5250 bias-disable;
5251 output-high;
5254 data1-pins {
5257 drive-strength = <8>;
5258 output-high;
5262 qup_i2c0_default: qup-i2c0-default-state {
5265 drive-strength = <2>;
5266 bias-disable;
5269 qup_i2c1_default: qup-i2c1-default-state {
5272 drive-strength = <2>;
5273 bias-disable;
5276 qup_i2c2_default: qup-i2c2-default-state {
5279 drive-strength = <2>;
5280 bias-disable;
5283 qup_i2c3_default: qup-i2c3-default-state {
5286 drive-strength = <2>;
5287 bias-disable;
5290 qup_i2c4_default: qup-i2c4-default-state {
5293 drive-strength = <2>;
5294 bias-disable;
5297 qup_i2c5_default: qup-i2c5-default-state {
5300 drive-strength = <2>;
5301 bias-disable;
5304 qup_i2c6_default: qup-i2c6-default-state {
5307 drive-strength = <2>;
5308 bias-disable;
5311 qup_i2c7_default: qup-i2c7-default-state {
5314 drive-strength = <2>;
5315 bias-disable;
5318 qup_i2c8_default: qup-i2c8-default-state {
5321 drive-strength = <2>;
5322 bias-disable;
5325 qup_i2c9_default: qup-i2c9-default-state {
5328 drive-strength = <2>;
5329 bias-disable;
5332 qup_i2c10_default: qup-i2c10-default-state {
5335 drive-strength = <2>;
5336 bias-disable;
5339 qup_i2c11_default: qup-i2c11-default-state {
5342 drive-strength = <2>;
5343 bias-disable;
5346 qup_i2c12_default: qup-i2c12-default-state {
5349 drive-strength = <2>;
5350 bias-disable;
5353 qup_i2c13_default: qup-i2c13-default-state {
5356 drive-strength = <2>;
5357 bias-disable;
5360 qup_i2c14_default: qup-i2c14-default-state {
5363 drive-strength = <2>;
5364 bias-disable;
5367 qup_i2c15_default: qup-i2c15-default-state {
5370 drive-strength = <2>;
5371 bias-disable;
5374 qup_i2c16_default: qup-i2c16-default-state {
5377 drive-strength = <2>;
5378 bias-disable;
5381 qup_i2c17_default: qup-i2c17-default-state {
5384 drive-strength = <2>;
5385 bias-disable;
5388 qup_i2c18_default: qup-i2c18-default-state {
5391 drive-strength = <2>;
5392 bias-disable;
5395 qup_i2c19_default: qup-i2c19-default-state {
5398 drive-strength = <2>;
5399 bias-disable;
5402 qup_spi0_cs: qup-spi0-cs-state {
5407 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
5412 qup_spi0_data_clk: qup-spi0-data-clk-state {
5418 qup_spi1_cs: qup-spi1-cs-state {
5423 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
5428 qup_spi1_data_clk: qup-spi1-data-clk-state {
5434 qup_spi2_cs: qup-spi2-cs-state {
5439 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
5444 qup_spi2_data_clk: qup-spi2-data-clk-state {
5450 qup_spi3_cs: qup-spi3-cs-state {
5455 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
5460 qup_spi3_data_clk: qup-spi3-data-clk-state {
5466 qup_spi4_cs: qup-spi4-cs-state {
5471 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
5476 qup_spi4_data_clk: qup-spi4-data-clk-state {
5482 qup_spi5_cs: qup-spi5-cs-state {
5487 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
5492 qup_spi5_data_clk: qup-spi5-data-clk-state {
5498 qup_spi6_cs: qup-spi6-cs-state {
5503 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
5508 qup_spi6_data_clk: qup-spi6-data-clk-state {
5514 qup_spi7_cs: qup-spi7-cs-state {
5519 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
5524 qup_spi7_data_clk: qup-spi7-data-clk-state {
5530 qup_spi8_cs: qup-spi8-cs-state {
5535 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
5540 qup_spi8_data_clk: qup-spi8-data-clk-state {
5546 qup_spi9_cs: qup-spi9-cs-state {
5551 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
5556 qup_spi9_data_clk: qup-spi9-data-clk-state {
5562 qup_spi10_cs: qup-spi10-cs-state {
5567 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
5572 qup_spi10_data_clk: qup-spi10-data-clk-state {
5578 qup_spi11_cs: qup-spi11-cs-state {
5583 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
5588 qup_spi11_data_clk: qup-spi11-data-clk-state {
5594 qup_spi12_cs: qup-spi12-cs-state {
5599 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
5604 qup_spi12_data_clk: qup-spi12-data-clk-state {
5610 qup_spi13_cs: qup-spi13-cs-state {
5615 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
5620 qup_spi13_data_clk: qup-spi13-data-clk-state {
5626 qup_spi14_cs: qup-spi14-cs-state {
5631 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
5636 qup_spi14_data_clk: qup-spi14-data-clk-state {
5642 qup_spi15_cs: qup-spi15-cs-state {
5647 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
5652 qup_spi15_data_clk: qup-spi15-data-clk-state {
5658 qup_spi16_cs: qup-spi16-cs-state {
5663 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state {
5668 qup_spi16_data_clk: qup-spi16-data-clk-state {
5674 qup_spi17_cs: qup-spi17-cs-state {
5679 qup_spi17_cs_gpio: qup-spi17-cs-gpio-state {
5684 qup_spi17_data_clk: qup-spi17-data-clk-state {
5690 qup_spi18_cs: qup-spi18-cs-state {
5695 qup_spi18_cs_gpio: qup-spi18-cs-gpio-state {
5700 qup_spi18_data_clk: qup-spi18-data-clk-state {
5706 qup_spi19_cs: qup-spi19-cs-state {
5711 qup_spi19_cs_gpio: qup-spi19-cs-gpio-state {
5716 qup_spi19_data_clk: qup-spi19-data-clk-state {
5722 qup_uart2_default: qup-uart2-default-state {
5727 qup_uart6_default: qup-uart6-default-state {
5732 qup_uart12_default: qup-uart12-default-state {
5737 qup_uart17_default: qup-uart17-default-state {
5742 qup_uart18_default: qup-uart18-default-state {
5747 tert_mi2s_active: tert-mi2s-active-state {
5748 sck-pins {
5751 drive-strength = <8>;
5752 bias-disable;
5755 data0-pins {
5758 drive-strength = <8>;
5759 bias-disable;
5760 output-high;
5763 ws-pins {
5766 drive-strength = <8>;
5767 output-high;
5771 sdc2_sleep_state: sdc2-sleep-state {
5772 clk-pins {
5774 drive-strength = <2>;
5775 bias-disable;
5778 cmd-pins {
5780 drive-strength = <2>;
5781 bias-pull-up;
5784 data-pins {
5786 drive-strength = <2>;
5787 bias-pull-up;
5791 pcie0_default_state: pcie0-default-state {
5792 perst-pins {
5795 drive-strength = <2>;
5796 bias-pull-down;
5799 clkreq-pins {
5802 drive-strength = <2>;
5803 bias-pull-up;
5806 wake-pins {
5809 drive-strength = <2>;
5810 bias-pull-up;
5814 pcie1_default_state: pcie1-default-state {
5815 perst-pins {
5818 drive-strength = <2>;
5819 bias-pull-down;
5822 clkreq-pins {
5825 drive-strength = <2>;
5826 bias-pull-up;
5829 wake-pins {
5832 drive-strength = <2>;
5833 bias-pull-up;
5837 pcie2_default_state: pcie2-default-state {
5838 perst-pins {
5841 drive-strength = <2>;
5842 bias-pull-down;
5845 clkreq-pins {
5848 drive-strength = <2>;
5849 bias-pull-up;
5852 wake-pins {
5855 drive-strength = <2>;
5856 bias-pull-up;
5862 compatible = "qcom,sm8250-smmu-500", "qcom,smmu-500", "arm,mmu-500";
5864 #iommu-cells = <2>;
5865 #global-interrupts = <2>;
5964 dma-coherent;
5968 compatible = "qcom,sm8250-adsp-pas";
5971 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
5976 interrupt-names = "wdog", "fatal", "ready",
5977 "handover", "stop-ack";
5980 clock-names = "xo";
5982 power-domains = <&rpmhpd RPMHPD_LCX>,
5984 power-domain-names = "lcx", "lmx";
5986 memory-region = <&adsp_mem>;
5990 qcom,smem-states = <&smp2p_adsp_out 0>;
5991 qcom,smem-state-names = "stop";
5995 glink-edge {
5996 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
6003 qcom,remote-pid = <2>;
6006 compatible = "qcom,apr-v2";
6007 qcom,glink-channels = "apr_audio_svc";
6009 #address-cells = <1>;
6010 #size-cells = <0>;
6015 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6021 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6023 compatible = "qcom,q6afe-dais";
6024 #address-cells = <1>;
6025 #size-cells = <0>;
6026 #sound-dai-cells = <1>;
6029 q6afecc: clock-controller {
6030 compatible = "qcom,q6afe-clocks";
6031 #clock-cells = <2>;
6038 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6040 compatible = "qcom,q6asm-dais";
6041 #address-cells = <1>;
6042 #size-cells = <0>;
6043 #sound-dai-cells = <1>;
6051 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6053 compatible = "qcom,q6adm-routing";
6054 #sound-dai-cells = <0>;
6061 qcom,glink-channels = "fastrpcglink-apps-dsp";
6063 qcom,non-secure-domain;
6064 #address-cells = <1>;
6065 #size-cells = <0>;
6067 compute-cb@3 {
6068 compatible = "qcom,fastrpc-compute-cb";
6073 compute-cb@4 {
6074 compatible = "qcom,fastrpc-compute-cb";
6079 compute-cb@5 {
6080 compatible = "qcom,fastrpc-compute-cb";
6088 intc: interrupt-controller@17a00000 {
6089 compatible = "arm,gic-v3";
6090 #interrupt-cells = <3>;
6091 interrupt-controller;
6098 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
6105 #address-cells = <1>;
6106 #size-cells = <1>;
6108 compatible = "arm,armv7-timer-mem";
6110 clock-frequency = <19200000>;
6113 frame-number = <0>;
6121 frame-number = <1>;
6128 frame-number = <2>;
6135 frame-number = <3>;
6142 frame-number = <4>;
6149 frame-number = <5>;
6156 frame-number = <6>;
6165 compatible = "qcom,rpmh-rsc";
6169 reg-names = "drv-0", "drv-1", "drv-2";
6173 qcom,tcs-offset = <0xd00>;
6174 qcom,drv-id = <2>;
6175 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
6177 power-domains = <&cluster_pd>;
6179 rpmhcc: clock-controller {
6180 compatible = "qcom,sm8250-rpmh-clk";
6181 #clock-cells = <1>;
6182 clock-names = "xo";
6186 rpmhpd: power-controller {
6187 compatible = "qcom,sm8250-rpmhpd";
6188 #power-domain-cells = <1>;
6189 operating-points-v2 = <&rpmhpd_opp_table>;
6191 rpmhpd_opp_table: opp-table {
6192 compatible = "operating-points-v2";
6195 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
6199 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
6203 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
6207 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
6211 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
6215 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
6219 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
6223 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
6227 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
6231 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
6236 apps_bcm_voter: bcm-voter {
6237 compatible = "qcom,bcm-voter";
6242 compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3";
6246 clock-names = "xo", "alternate";
6248 #interconnect-cells = <1>;
6252 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
6256 reg-names = "freq-domain0", "freq-domain1",
6257 "freq-domain2";
6260 clock-names = "xo", "alternate";
6264 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
6265 #freq-domain-cells = <1>;
6266 #clock-cells = <1>;
6274 compatible = "arm,armv8-timer";
6285 thermal-zones {
6286 cpu0-thermal {
6287 polling-delay-passive = <250>;
6289 thermal-sensors = <&tsens0 1>;
6292 cpu0_alert0: trip-point0 {
6298 cpu0_alert1: trip-point1 {
6304 cpu0_crit: cpu-crit {
6311 cooling-maps {
6314 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6321 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6329 cpu1-thermal {
6330 polling-delay-passive = <250>;
6332 thermal-sensors = <&tsens0 2>;
6335 cpu1_alert0: trip-point0 {
6341 cpu1_alert1: trip-point1 {
6347 cpu1_crit: cpu-crit {
6354 cooling-maps {
6357 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6364 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6372 cpu2-thermal {
6373 polling-delay-passive = <250>;
6375 thermal-sensors = <&tsens0 3>;
6378 cpu2_alert0: trip-point0 {
6384 cpu2_alert1: trip-point1 {
6390 cpu2_crit: cpu-crit {
6397 cooling-maps {
6400 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6407 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6415 cpu3-thermal {
6416 polling-delay-passive = <250>;
6418 thermal-sensors = <&tsens0 4>;
6421 cpu3_alert0: trip-point0 {
6427 cpu3_alert1: trip-point1 {
6433 cpu3_crit: cpu-crit {
6440 cooling-maps {
6443 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6450 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6458 cpu4-top-thermal {
6459 polling-delay-passive = <250>;
6461 thermal-sensors = <&tsens0 7>;
6464 cpu4_top_alert0: trip-point0 {
6470 cpu4_top_alert1: trip-point1 {
6476 cpu4_top_crit: cpu-crit {
6483 cooling-maps {
6486 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6493 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6501 cpu5-top-thermal {
6502 polling-delay-passive = <250>;
6504 thermal-sensors = <&tsens0 8>;
6507 cpu5_top_alert0: trip-point0 {
6513 cpu5_top_alert1: trip-point1 {
6519 cpu5_top_crit: cpu-crit {
6526 cooling-maps {
6529 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6536 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6544 cpu6-top-thermal {
6545 polling-delay-passive = <250>;
6547 thermal-sensors = <&tsens0 9>;
6550 cpu6_top_alert0: trip-point0 {
6556 cpu6_top_alert1: trip-point1 {
6562 cpu6_top_crit: cpu-crit {
6569 cooling-maps {
6572 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6579 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6587 cpu7-top-thermal {
6588 polling-delay-passive = <250>;
6590 thermal-sensors = <&tsens0 10>;
6593 cpu7_top_alert0: trip-point0 {
6599 cpu7_top_alert1: trip-point1 {
6605 cpu7_top_crit: cpu-crit {
6612 cooling-maps {
6615 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6622 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6630 cpu4-bottom-thermal {
6631 polling-delay-passive = <250>;
6633 thermal-sensors = <&tsens0 11>;
6636 cpu4_bottom_alert0: trip-point0 {
6642 cpu4_bottom_alert1: trip-point1 {
6648 cpu4_bottom_crit: cpu-crit {
6655 cooling-maps {
6658 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6665 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6673 cpu5-bottom-thermal {
6674 polling-delay-passive = <250>;
6676 thermal-sensors = <&tsens0 12>;
6679 cpu5_bottom_alert0: trip-point0 {
6685 cpu5_bottom_alert1: trip-point1 {
6691 cpu5_bottom_crit: cpu-crit {
6698 cooling-maps {
6701 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6708 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6716 cpu6-bottom-thermal {
6717 polling-delay-passive = <250>;
6719 thermal-sensors = <&tsens0 13>;
6722 cpu6_bottom_alert0: trip-point0 {
6728 cpu6_bottom_alert1: trip-point1 {
6734 cpu6_bottom_crit: cpu-crit {
6741 cooling-maps {
6744 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6751 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6759 cpu7-bottom-thermal {
6760 polling-delay-passive = <250>;
6762 thermal-sensors = <&tsens0 14>;
6765 cpu7_bottom_alert0: trip-point0 {
6771 cpu7_bottom_alert1: trip-point1 {
6777 cpu7_bottom_crit: cpu-crit {
6784 cooling-maps {
6787 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6794 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6802 aoss0-thermal {
6803 polling-delay-passive = <250>;
6805 thermal-sensors = <&tsens0 0>;
6808 aoss0_alert0: trip-point0 {
6816 cluster0-thermal {
6817 polling-delay-passive = <250>;
6819 thermal-sensors = <&tsens0 5>;
6822 cluster0_alert0: trip-point0 {
6827 cluster0_crit: cluster0-crit {
6835 cluster1-thermal {
6836 polling-delay-passive = <250>;
6838 thermal-sensors = <&tsens0 6>;
6841 cluster1_alert0: trip-point0 {
6846 cluster1_crit: cluster1-crit {
6854 gpu-top-thermal {
6855 polling-delay-passive = <250>;
6857 thermal-sensors = <&tsens0 15>;
6859 cooling-maps {
6862 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6867 gpu_top_alert0: trip-point0 {
6873 trip-point1 {
6879 trip-point2 {
6887 aoss1-thermal {
6888 polling-delay-passive = <250>;
6890 thermal-sensors = <&tsens1 0>;
6893 aoss1_alert0: trip-point0 {
6901 wlan-thermal {
6902 polling-delay-passive = <250>;
6904 thermal-sensors = <&tsens1 1>;
6907 wlan_alert0: trip-point0 {
6915 video-thermal {
6916 polling-delay-passive = <250>;
6918 thermal-sensors = <&tsens1 2>;
6921 video_alert0: trip-point0 {
6929 mem-thermal {
6930 polling-delay-passive = <250>;
6932 thermal-sensors = <&tsens1 3>;
6935 mem_alert0: trip-point0 {
6943 q6-hvx-thermal {
6944 polling-delay-passive = <250>;
6946 thermal-sensors = <&tsens1 4>;
6949 q6_hvx_alert0: trip-point0 {
6957 camera-thermal {
6958 polling-delay-passive = <250>;
6960 thermal-sensors = <&tsens1 5>;
6963 camera_alert0: trip-point0 {
6971 compute-thermal {
6972 polling-delay-passive = <250>;
6974 thermal-sensors = <&tsens1 6>;
6977 compute_alert0: trip-point0 {
6985 npu-thermal {
6986 polling-delay-passive = <250>;
6988 thermal-sensors = <&tsens1 7>;
6991 npu_alert0: trip-point0 {
6999 gpu-bottom-thermal {
7000 polling-delay-passive = <250>;
7002 thermal-sensors = <&tsens1 8>;
7004 cooling-maps {
7007 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
7012 gpu_bottom_alert0: trip-point0 {
7018 trip-point1 {
7024 trip-point2 {