Lines Matching +full:opp +full:- +full:160000000
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
9 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
10 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
15 #include <dt-bindings/interconnect/qcom,sm8250.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom-rpmpd.h>
19 #include <dt-bindings/power/qcom,rpmhpd.h>
20 #include <dt-bindings/soc/qcom,apr.h>
21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
22 #include <dt-bindings/sound/qcom,q6afe.h>
23 #include <dt-bindings/thermal/thermal.h>
24 #include <dt-bindings/clock/qcom,camcc-sm8250.h>
25 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
28 interrupt-parent = <&intc>;
30 #address-cells = <2>;
31 #size-cells = <2>;
79 xo_board: xo-board {
80 compatible = "fixed-clock";
81 #clock-cells = <0>;
82 clock-frequency = <38400000>;
83 clock-output-names = "xo_board";
86 sleep_clk: sleep-clk {
87 compatible = "fixed-clock";
88 clock-frequency = <32764>;
89 #clock-cells = <0>;
94 #address-cells = <2>;
95 #size-cells = <0>;
102 enable-method = "psci";
103 capacity-dmips-mhz = <448>;
104 dynamic-power-coefficient = <105>;
105 next-level-cache = <&l2_0>;
106 power-domains = <&cpu_pd0>;
107 power-domain-names = "psci";
108 qcom,freq-domain = <&cpufreq_hw 0>;
109 operating-points-v2 = <&cpu0_opp_table>;
112 #cooling-cells = <2>;
113 l2_0: l2-cache {
115 cache-level = <2>;
116 cache-size = <0x20000>;
117 cache-unified;
118 next-level-cache = <&l3_0>;
119 l3_0: l3-cache {
121 cache-level = <3>;
122 cache-size = <0x400000>;
123 cache-unified;
133 enable-method = "psci";
134 capacity-dmips-mhz = <448>;
135 dynamic-power-coefficient = <105>;
136 next-level-cache = <&l2_100>;
137 power-domains = <&cpu_pd1>;
138 power-domain-names = "psci";
139 qcom,freq-domain = <&cpufreq_hw 0>;
140 operating-points-v2 = <&cpu0_opp_table>;
143 #cooling-cells = <2>;
144 l2_100: l2-cache {
146 cache-level = <2>;
147 cache-size = <0x20000>;
148 cache-unified;
149 next-level-cache = <&l3_0>;
158 enable-method = "psci";
159 capacity-dmips-mhz = <448>;
160 dynamic-power-coefficient = <105>;
161 next-level-cache = <&l2_200>;
162 power-domains = <&cpu_pd2>;
163 power-domain-names = "psci";
164 qcom,freq-domain = <&cpufreq_hw 0>;
165 operating-points-v2 = <&cpu0_opp_table>;
168 #cooling-cells = <2>;
169 l2_200: l2-cache {
171 cache-level = <2>;
172 cache-size = <0x20000>;
173 cache-unified;
174 next-level-cache = <&l3_0>;
183 enable-method = "psci";
184 capacity-dmips-mhz = <448>;
185 dynamic-power-coefficient = <105>;
186 next-level-cache = <&l2_300>;
187 power-domains = <&cpu_pd3>;
188 power-domain-names = "psci";
189 qcom,freq-domain = <&cpufreq_hw 0>;
190 operating-points-v2 = <&cpu0_opp_table>;
193 #cooling-cells = <2>;
194 l2_300: l2-cache {
196 cache-level = <2>;
197 cache-size = <0x20000>;
198 cache-unified;
199 next-level-cache = <&l3_0>;
208 enable-method = "psci";
209 capacity-dmips-mhz = <1024>;
210 dynamic-power-coefficient = <379>;
211 next-level-cache = <&l2_400>;
212 power-domains = <&cpu_pd4>;
213 power-domain-names = "psci";
214 qcom,freq-domain = <&cpufreq_hw 1>;
215 operating-points-v2 = <&cpu4_opp_table>;
218 #cooling-cells = <2>;
219 l2_400: l2-cache {
221 cache-level = <2>;
222 cache-size = <0x40000>;
223 cache-unified;
224 next-level-cache = <&l3_0>;
233 enable-method = "psci";
234 capacity-dmips-mhz = <1024>;
235 dynamic-power-coefficient = <379>;
236 next-level-cache = <&l2_500>;
237 power-domains = <&cpu_pd5>;
238 power-domain-names = "psci";
239 qcom,freq-domain = <&cpufreq_hw 1>;
240 operating-points-v2 = <&cpu4_opp_table>;
243 #cooling-cells = <2>;
244 l2_500: l2-cache {
246 cache-level = <2>;
247 cache-size = <0x40000>;
248 cache-unified;
249 next-level-cache = <&l3_0>;
258 enable-method = "psci";
259 capacity-dmips-mhz = <1024>;
260 dynamic-power-coefficient = <379>;
261 next-level-cache = <&l2_600>;
262 power-domains = <&cpu_pd6>;
263 power-domain-names = "psci";
264 qcom,freq-domain = <&cpufreq_hw 1>;
265 operating-points-v2 = <&cpu4_opp_table>;
268 #cooling-cells = <2>;
269 l2_600: l2-cache {
271 cache-level = <2>;
272 cache-size = <0x40000>;
273 cache-unified;
274 next-level-cache = <&l3_0>;
283 enable-method = "psci";
284 capacity-dmips-mhz = <1024>;
285 dynamic-power-coefficient = <444>;
286 next-level-cache = <&l2_700>;
287 power-domains = <&cpu_pd7>;
288 power-domain-names = "psci";
289 qcom,freq-domain = <&cpufreq_hw 2>;
290 operating-points-v2 = <&cpu7_opp_table>;
293 #cooling-cells = <2>;
294 l2_700: l2-cache {
296 cache-level = <2>;
297 cache-size = <0x80000>;
298 cache-unified;
299 next-level-cache = <&l3_0>;
303 cpu-map {
339 idle-states {
340 entry-method = "psci";
342 little_cpu_sleep_0: cpu-sleep-0-0 {
343 compatible = "arm,idle-state";
344 idle-state-name = "silver-rail-power-collapse";
345 arm,psci-suspend-param = <0x40000004>;
346 entry-latency-us = <360>;
347 exit-latency-us = <531>;
348 min-residency-us = <3934>;
349 local-timer-stop;
352 big_cpu_sleep_0: cpu-sleep-1-0 {
353 compatible = "arm,idle-state";
354 idle-state-name = "gold-rail-power-collapse";
355 arm,psci-suspend-param = <0x40000004>;
356 entry-latency-us = <702>;
357 exit-latency-us = <1061>;
358 min-residency-us = <4488>;
359 local-timer-stop;
363 domain-idle-states {
364 cluster_sleep_0: cluster-sleep-0 {
365 compatible = "domain-idle-state";
366 arm,psci-suspend-param = <0x4100c244>;
367 entry-latency-us = <3264>;
368 exit-latency-us = <6562>;
369 min-residency-us = <9987>;
374 qup_virt: interconnect-qup-virt {
375 compatible = "qcom,sm8250-qup-virt";
376 #interconnect-cells = <2>;
377 qcom,bcm-voters = <&apps_bcm_voter>;
380 cpu0_opp_table: opp-table-cpu0 {
381 compatible = "operating-points-v2";
382 opp-shared;
384 cpu0_opp1: opp-300000000 {
385 opp-hz = /bits/ 64 <300000000>;
386 opp-peak-kBps = <800000 9600000>;
389 cpu0_opp2: opp-403200000 {
390 opp-hz = /bits/ 64 <403200000>;
391 opp-peak-kBps = <800000 9600000>;
394 cpu0_opp3: opp-518400000 {
395 opp-hz = /bits/ 64 <518400000>;
396 opp-peak-kBps = <800000 16588800>;
399 cpu0_opp4: opp-614400000 {
400 opp-hz = /bits/ 64 <614400000>;
401 opp-peak-kBps = <800000 16588800>;
404 cpu0_opp5: opp-691200000 {
405 opp-hz = /bits/ 64 <691200000>;
406 opp-peak-kBps = <800000 19660800>;
409 cpu0_opp6: opp-787200000 {
410 opp-hz = /bits/ 64 <787200000>;
411 opp-peak-kBps = <1804000 19660800>;
414 cpu0_opp7: opp-883200000 {
415 opp-hz = /bits/ 64 <883200000>;
416 opp-peak-kBps = <1804000 23347200>;
419 cpu0_opp8: opp-979200000 {
420 opp-hz = /bits/ 64 <979200000>;
421 opp-peak-kBps = <1804000 26419200>;
424 cpu0_opp9: opp-1075200000 {
425 opp-hz = /bits/ 64 <1075200000>;
426 opp-peak-kBps = <1804000 29491200>;
429 cpu0_opp10: opp-1171200000 {
430 opp-hz = /bits/ 64 <1171200000>;
431 opp-peak-kBps = <1804000 32563200>;
434 cpu0_opp11: opp-1248000000 {
435 opp-hz = /bits/ 64 <1248000000>;
436 opp-peak-kBps = <1804000 36249600>;
439 cpu0_opp12: opp-1344000000 {
440 opp-hz = /bits/ 64 <1344000000>;
441 opp-peak-kBps = <2188000 36249600>;
444 cpu0_opp13: opp-1420800000 {
445 opp-hz = /bits/ 64 <1420800000>;
446 opp-peak-kBps = <2188000 39321600>;
449 cpu0_opp14: opp-1516800000 {
450 opp-hz = /bits/ 64 <1516800000>;
451 opp-peak-kBps = <3072000 42393600>;
454 cpu0_opp15: opp-1612800000 {
455 opp-hz = /bits/ 64 <1612800000>;
456 opp-peak-kBps = <3072000 42393600>;
459 cpu0_opp16: opp-1708800000 {
460 opp-hz = /bits/ 64 <1708800000>;
461 opp-peak-kBps = <4068000 42393600>;
464 cpu0_opp17: opp-1804800000 {
465 opp-hz = /bits/ 64 <1804800000>;
466 opp-peak-kBps = <4068000 42393600>;
470 cpu4_opp_table: opp-table-cpu4 {
471 compatible = "operating-points-v2";
472 opp-shared;
474 cpu4_opp1: opp-710400000 {
475 opp-hz = /bits/ 64 <710400000>;
476 opp-peak-kBps = <1804000 19660800>;
479 cpu4_opp2: opp-825600000 {
480 opp-hz = /bits/ 64 <825600000>;
481 opp-peak-kBps = <2188000 23347200>;
484 cpu4_opp3: opp-940800000 {
485 opp-hz = /bits/ 64 <940800000>;
486 opp-peak-kBps = <2188000 26419200>;
489 cpu4_opp4: opp-1056000000 {
490 opp-hz = /bits/ 64 <1056000000>;
491 opp-peak-kBps = <3072000 26419200>;
494 cpu4_opp5: opp-1171200000 {
495 opp-hz = /bits/ 64 <1171200000>;
496 opp-peak-kBps = <3072000 29491200>;
499 cpu4_opp6: opp-1286400000 {
500 opp-hz = /bits/ 64 <1286400000>;
501 opp-peak-kBps = <4068000 29491200>;
504 cpu4_opp7: opp-1382400000 {
505 opp-hz = /bits/ 64 <1382400000>;
506 opp-peak-kBps = <4068000 32563200>;
509 cpu4_opp8: opp-1478400000 {
510 opp-hz = /bits/ 64 <1478400000>;
511 opp-peak-kBps = <4068000 32563200>;
514 cpu4_opp9: opp-1574400000 {
515 opp-hz = /bits/ 64 <1574400000>;
516 opp-peak-kBps = <5412000 39321600>;
519 cpu4_opp10: opp-1670400000 {
520 opp-hz = /bits/ 64 <1670400000>;
521 opp-peak-kBps = <5412000 42393600>;
524 cpu4_opp11: opp-1766400000 {
525 opp-hz = /bits/ 64 <1766400000>;
526 opp-peak-kBps = <5412000 45465600>;
529 cpu4_opp12: opp-1862400000 {
530 opp-hz = /bits/ 64 <1862400000>;
531 opp-peak-kBps = <6220000 45465600>;
534 cpu4_opp13: opp-1958400000 {
535 opp-hz = /bits/ 64 <1958400000>;
536 opp-peak-kBps = <6220000 48537600>;
539 cpu4_opp14: opp-2054400000 {
540 opp-hz = /bits/ 64 <2054400000>;
541 opp-peak-kBps = <7216000 48537600>;
544 cpu4_opp15: opp-2150400000 {
545 opp-hz = /bits/ 64 <2150400000>;
546 opp-peak-kBps = <7216000 51609600>;
549 cpu4_opp16: opp-2246400000 {
550 opp-hz = /bits/ 64 <2246400000>;
551 opp-peak-kBps = <7216000 51609600>;
554 cpu4_opp17: opp-2342400000 {
555 opp-hz = /bits/ 64 <2342400000>;
556 opp-peak-kBps = <8368000 51609600>;
559 cpu4_opp18: opp-2419200000 {
560 opp-hz = /bits/ 64 <2419200000>;
561 opp-peak-kBps = <8368000 51609600>;
565 cpu7_opp_table: opp-table-cpu7 {
566 compatible = "operating-points-v2";
567 opp-shared;
569 cpu7_opp1: opp-844800000 {
570 opp-hz = /bits/ 64 <844800000>;
571 opp-peak-kBps = <2188000 19660800>;
574 cpu7_opp2: opp-960000000 {
575 opp-hz = /bits/ 64 <960000000>;
576 opp-peak-kBps = <2188000 26419200>;
579 cpu7_opp3: opp-1075200000 {
580 opp-hz = /bits/ 64 <1075200000>;
581 opp-peak-kBps = <3072000 26419200>;
584 cpu7_opp4: opp-1190400000 {
585 opp-hz = /bits/ 64 <1190400000>;
586 opp-peak-kBps = <3072000 29491200>;
589 cpu7_opp5: opp-1305600000 {
590 opp-hz = /bits/ 64 <1305600000>;
591 opp-peak-kBps = <4068000 32563200>;
594 cpu7_opp6: opp-1401600000 {
595 opp-hz = /bits/ 64 <1401600000>;
596 opp-peak-kBps = <4068000 32563200>;
599 cpu7_opp7: opp-1516800000 {
600 opp-hz = /bits/ 64 <1516800000>;
601 opp-peak-kBps = <4068000 36249600>;
604 cpu7_opp8: opp-1632000000 {
605 opp-hz = /bits/ 64 <1632000000>;
606 opp-peak-kBps = <5412000 39321600>;
609 cpu7_opp9: opp-1747200000 {
610 opp-hz = /bits/ 64 <1747200000>;
611 opp-peak-kBps = <5412000 42393600>;
614 cpu7_opp10: opp-1862400000 {
615 opp-hz = /bits/ 64 <1862400000>;
616 opp-peak-kBps = <6220000 45465600>;
619 cpu7_opp11: opp-1977600000 {
620 opp-hz = /bits/ 64 <1977600000>;
621 opp-peak-kBps = <6220000 48537600>;
624 cpu7_opp12: opp-2073600000 {
625 opp-hz = /bits/ 64 <2073600000>;
626 opp-peak-kBps = <7216000 48537600>;
629 cpu7_opp13: opp-2169600000 {
630 opp-hz = /bits/ 64 <2169600000>;
631 opp-peak-kBps = <7216000 51609600>;
634 cpu7_opp14: opp-2265600000 {
635 opp-hz = /bits/ 64 <2265600000>;
636 opp-peak-kBps = <7216000 51609600>;
639 cpu7_opp15: opp-2361600000 {
640 opp-hz = /bits/ 64 <2361600000>;
641 opp-peak-kBps = <8368000 51609600>;
644 cpu7_opp16: opp-2457600000 {
645 opp-hz = /bits/ 64 <2457600000>;
646 opp-peak-kBps = <8368000 51609600>;
649 cpu7_opp17: opp-2553600000 {
650 opp-hz = /bits/ 64 <2553600000>;
651 opp-peak-kBps = <8368000 51609600>;
654 cpu7_opp18: opp-2649600000 {
655 opp-hz = /bits/ 64 <2649600000>;
656 opp-peak-kBps = <8368000 51609600>;
659 cpu7_opp19: opp-2745600000 {
660 opp-hz = /bits/ 64 <2745600000>;
661 opp-peak-kBps = <8368000 51609600>;
664 cpu7_opp20: opp-2841600000 {
665 opp-hz = /bits/ 64 <2841600000>;
666 opp-peak-kBps = <8368000 51609600>;
672 compatible = "qcom,scm-sm8250", "qcom,scm";
673 qcom,dload-mode = <&tcsr 0x13000>;
674 #reset-cells = <1>;
685 compatible = "arm,armv8-pmuv3";
690 compatible = "arm,psci-1.0";
693 cpu_pd0: power-domain-cpu0 {
694 #power-domain-cells = <0>;
695 power-domains = <&cluster_pd>;
696 domain-idle-states = <&little_cpu_sleep_0>;
699 cpu_pd1: power-domain-cpu1 {
700 #power-domain-cells = <0>;
701 power-domains = <&cluster_pd>;
702 domain-idle-states = <&little_cpu_sleep_0>;
705 cpu_pd2: power-domain-cpu2 {
706 #power-domain-cells = <0>;
707 power-domains = <&cluster_pd>;
708 domain-idle-states = <&little_cpu_sleep_0>;
711 cpu_pd3: power-domain-cpu3 {
712 #power-domain-cells = <0>;
713 power-domains = <&cluster_pd>;
714 domain-idle-states = <&little_cpu_sleep_0>;
717 cpu_pd4: power-domain-cpu4 {
718 #power-domain-cells = <0>;
719 power-domains = <&cluster_pd>;
720 domain-idle-states = <&big_cpu_sleep_0>;
723 cpu_pd5: power-domain-cpu5 {
724 #power-domain-cells = <0>;
725 power-domains = <&cluster_pd>;
726 domain-idle-states = <&big_cpu_sleep_0>;
729 cpu_pd6: power-domain-cpu6 {
730 #power-domain-cells = <0>;
731 power-domains = <&cluster_pd>;
732 domain-idle-states = <&big_cpu_sleep_0>;
735 cpu_pd7: power-domain-cpu7 {
736 #power-domain-cells = <0>;
737 power-domains = <&cluster_pd>;
738 domain-idle-states = <&big_cpu_sleep_0>;
741 cluster_pd: power-domain-cpu-cluster0 {
742 #power-domain-cells = <0>;
743 domain-idle-states = <&cluster_sleep_0>;
747 qup_opp_table: opp-table-qup {
748 compatible = "operating-points-v2";
750 opp-50000000 {
751 opp-hz = /bits/ 64 <50000000>;
752 required-opps = <&rpmhpd_opp_min_svs>;
755 opp-75000000 {
756 opp-hz = /bits/ 64 <75000000>;
757 required-opps = <&rpmhpd_opp_low_svs>;
760 opp-120000000 {
761 opp-hz = /bits/ 64 <120000000>;
762 required-opps = <&rpmhpd_opp_svs>;
766 reserved-memory {
767 #address-cells = <2>;
768 #size-cells = <2>;
773 no-map;
778 no-map;
782 compatible = "qcom,cmd-db";
784 no-map;
789 no-map;
794 no-map;
799 no-map;
804 no-map;
809 no-map;
814 no-map;
819 no-map;
824 no-map;
829 no-map;
834 no-map;
839 no-map;
844 no-map;
849 no-map;
854 no-map;
859 no-map;
865 memory-region = <&smem_mem>;
869 smp2p-adsp {
872 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
878 qcom,local-pid = <0>;
879 qcom,remote-pid = <2>;
881 smp2p_adsp_out: master-kernel {
882 qcom,entry-name = "master-kernel";
883 #qcom,smem-state-cells = <1>;
886 smp2p_adsp_in: slave-kernel {
887 qcom,entry-name = "slave-kernel";
888 interrupt-controller;
889 #interrupt-cells = <2>;
893 smp2p-cdsp {
896 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
902 qcom,local-pid = <0>;
903 qcom,remote-pid = <5>;
905 smp2p_cdsp_out: master-kernel {
906 qcom,entry-name = "master-kernel";
907 #qcom,smem-state-cells = <1>;
910 smp2p_cdsp_in: slave-kernel {
911 qcom,entry-name = "slave-kernel";
912 interrupt-controller;
913 #interrupt-cells = <2>;
917 smp2p-slpi {
920 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
926 qcom,local-pid = <0>;
927 qcom,remote-pid = <3>;
929 smp2p_slpi_out: master-kernel {
930 qcom,entry-name = "master-kernel";
931 #qcom,smem-state-cells = <1>;
934 smp2p_slpi_in: slave-kernel {
935 qcom,entry-name = "slave-kernel";
936 interrupt-controller;
937 #interrupt-cells = <2>;
942 #address-cells = <2>;
943 #size-cells = <2>;
945 dma-ranges = <0 0 0 0 0x10 0>;
946 compatible = "simple-bus";
948 gcc: clock-controller@100000 {
949 compatible = "qcom,gcc-sm8250";
951 #clock-cells = <1>;
952 #reset-cells = <1>;
953 #power-domain-cells = <1>;
954 clock-names = "bi_tcxo",
963 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
966 interrupt-controller;
967 #interrupt-cells = <3>;
968 #mbox-cells = <2>;
972 compatible = "qcom,sm8250-qfprom", "qcom,qfprom";
974 #address-cells = <1>;
975 #size-cells = <1>;
977 gpu_speed_bin: gpu-speed-bin@19b {
984 compatible = "qcom,prng-ee";
987 clock-names = "core";
990 gpi_dma2: dma-controller@800000 {
991 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1003 dma-channels = <10>;
1004 dma-channel-mask = <0x3f>;
1006 #dma-cells = <3>;
1011 compatible = "qcom,geni-se-qup";
1013 clock-names = "m-ahb", "s-ahb";
1016 #address-cells = <2>;
1017 #size-cells = <2>;
1023 compatible = "qcom,geni-i2c";
1025 clock-names = "se";
1027 pinctrl-names = "default";
1028 pinctrl-0 = <&qup_i2c14_default>;
1032 dma-names = "tx", "rx";
1033 power-domains = <&rpmhpd SM8250_CX>;
1037 interconnect-names = "qup-core",
1038 "qup-config",
1039 "qup-memory";
1040 #address-cells = <1>;
1041 #size-cells = <0>;
1046 compatible = "qcom,geni-spi";
1048 clock-names = "se";
1053 dma-names = "tx", "rx";
1054 power-domains = <&rpmhpd RPMHPD_CX>;
1055 operating-points-v2 = <&qup_opp_table>;
1059 interconnect-names = "qup-core",
1060 "qup-config",
1061 "qup-memory";
1062 #address-cells = <1>;
1063 #size-cells = <0>;
1068 compatible = "qcom,geni-i2c";
1070 clock-names = "se";
1072 pinctrl-names = "default";
1073 pinctrl-0 = <&qup_i2c15_default>;
1077 dma-names = "tx", "rx";
1078 power-domains = <&rpmhpd SM8250_CX>;
1082 interconnect-names = "qup-core",
1083 "qup-config",
1084 "qup-memory";
1085 #address-cells = <1>;
1086 #size-cells = <0>;
1091 compatible = "qcom,geni-spi";
1093 clock-names = "se";
1098 dma-names = "tx", "rx";
1099 power-domains = <&rpmhpd RPMHPD_CX>;
1100 operating-points-v2 = <&qup_opp_table>;
1104 interconnect-names = "qup-core",
1105 "qup-config",
1106 "qup-memory";
1107 #address-cells = <1>;
1108 #size-cells = <0>;
1113 compatible = "qcom,geni-i2c";
1115 clock-names = "se";
1117 pinctrl-names = "default";
1118 pinctrl-0 = <&qup_i2c16_default>;
1122 dma-names = "tx", "rx";
1123 power-domains = <&rpmhpd SM8250_CX>;
1127 interconnect-names = "qup-core",
1128 "qup-config",
1129 "qup-memory";
1130 #address-cells = <1>;
1131 #size-cells = <0>;
1136 compatible = "qcom,geni-spi";
1138 clock-names = "se";
1143 dma-names = "tx", "rx";
1144 power-domains = <&rpmhpd RPMHPD_CX>;
1145 operating-points-v2 = <&qup_opp_table>;
1149 interconnect-names = "qup-core",
1150 "qup-config",
1151 "qup-memory";
1152 #address-cells = <1>;
1153 #size-cells = <0>;
1158 compatible = "qcom,geni-i2c";
1160 clock-names = "se";
1162 pinctrl-names = "default";
1163 pinctrl-0 = <&qup_i2c17_default>;
1167 dma-names = "tx", "rx";
1168 power-domains = <&rpmhpd SM8250_CX>;
1172 interconnect-names = "qup-core",
1173 "qup-config",
1174 "qup-memory";
1175 #address-cells = <1>;
1176 #size-cells = <0>;
1181 compatible = "qcom,geni-spi";
1183 clock-names = "se";
1188 dma-names = "tx", "rx";
1189 power-domains = <&rpmhpd RPMHPD_CX>;
1190 operating-points-v2 = <&qup_opp_table>;
1194 interconnect-names = "qup-core",
1195 "qup-config",
1196 "qup-memory";
1197 #address-cells = <1>;
1198 #size-cells = <0>;
1203 compatible = "qcom,geni-uart";
1205 clock-names = "se";
1207 pinctrl-names = "default";
1208 pinctrl-0 = <&qup_uart17_default>;
1210 power-domains = <&rpmhpd RPMHPD_CX>;
1211 operating-points-v2 = <&qup_opp_table>;
1214 interconnect-names = "qup-core",
1215 "qup-config";
1220 compatible = "qcom,geni-i2c";
1222 clock-names = "se";
1224 pinctrl-names = "default";
1225 pinctrl-0 = <&qup_i2c18_default>;
1229 dma-names = "tx", "rx";
1230 power-domains = <&rpmhpd SM8250_CX>;
1234 interconnect-names = "qup-core",
1235 "qup-config",
1236 "qup-memory";
1237 #address-cells = <1>;
1238 #size-cells = <0>;
1243 compatible = "qcom,geni-spi";
1245 clock-names = "se";
1250 dma-names = "tx", "rx";
1251 power-domains = <&rpmhpd RPMHPD_CX>;
1252 operating-points-v2 = <&qup_opp_table>;
1256 interconnect-names = "qup-core",
1257 "qup-config",
1258 "qup-memory";
1259 #address-cells = <1>;
1260 #size-cells = <0>;
1265 compatible = "qcom,geni-uart";
1267 clock-names = "se";
1269 pinctrl-names = "default";
1270 pinctrl-0 = <&qup_uart18_default>;
1272 power-domains = <&rpmhpd RPMHPD_CX>;
1273 operating-points-v2 = <&qup_opp_table>;
1276 interconnect-names = "qup-core",
1277 "qup-config";
1282 compatible = "qcom,geni-i2c";
1284 clock-names = "se";
1286 pinctrl-names = "default";
1287 pinctrl-0 = <&qup_i2c19_default>;
1291 dma-names = "tx", "rx";
1292 power-domains = <&rpmhpd SM8250_CX>;
1296 interconnect-names = "qup-core",
1297 "qup-config",
1298 "qup-memory";
1299 #address-cells = <1>;
1300 #size-cells = <0>;
1305 compatible = "qcom,geni-spi";
1307 clock-names = "se";
1312 dma-names = "tx", "rx";
1313 power-domains = <&rpmhpd RPMHPD_CX>;
1314 operating-points-v2 = <&qup_opp_table>;
1318 interconnect-names = "qup-core",
1319 "qup-config",
1320 "qup-memory";
1321 #address-cells = <1>;
1322 #size-cells = <0>;
1327 gpi_dma0: dma-controller@900000 {
1328 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1343 dma-channels = <15>;
1344 dma-channel-mask = <0x7ff>;
1346 #dma-cells = <3>;
1351 compatible = "qcom,geni-se-qup";
1353 clock-names = "m-ahb", "s-ahb";
1356 #address-cells = <2>;
1357 #size-cells = <2>;
1363 compatible = "qcom,geni-i2c";
1365 clock-names = "se";
1367 pinctrl-names = "default";
1368 pinctrl-0 = <&qup_i2c0_default>;
1372 dma-names = "tx", "rx";
1373 power-domains = <&rpmhpd SM8250_CX>;
1377 interconnect-names = "qup-core",
1378 "qup-config",
1379 "qup-memory";
1380 #address-cells = <1>;
1381 #size-cells = <0>;
1386 compatible = "qcom,geni-spi";
1388 clock-names = "se";
1393 dma-names = "tx", "rx";
1394 power-domains = <&rpmhpd RPMHPD_CX>;
1395 operating-points-v2 = <&qup_opp_table>;
1399 interconnect-names = "qup-core",
1400 "qup-config",
1401 "qup-memory";
1402 #address-cells = <1>;
1403 #size-cells = <0>;
1408 compatible = "qcom,geni-i2c";
1410 clock-names = "se";
1412 pinctrl-names = "default";
1413 pinctrl-0 = <&qup_i2c1_default>;
1417 dma-names = "tx", "rx";
1418 power-domains = <&rpmhpd SM8250_CX>;
1422 interconnect-names = "qup-core",
1423 "qup-config",
1424 "qup-memory";
1425 #address-cells = <1>;
1426 #size-cells = <0>;
1431 compatible = "qcom,geni-spi";
1433 clock-names = "se";
1438 dma-names = "tx", "rx";
1439 power-domains = <&rpmhpd RPMHPD_CX>;
1440 operating-points-v2 = <&qup_opp_table>;
1444 interconnect-names = "qup-core",
1445 "qup-config",
1446 "qup-memory";
1447 #address-cells = <1>;
1448 #size-cells = <0>;
1453 compatible = "qcom,geni-i2c";
1455 clock-names = "se";
1457 pinctrl-names = "default";
1458 pinctrl-0 = <&qup_i2c2_default>;
1462 dma-names = "tx", "rx";
1463 power-domains = <&rpmhpd SM8250_CX>;
1467 interconnect-names = "qup-core",
1468 "qup-config",
1469 "qup-memory";
1470 #address-cells = <1>;
1471 #size-cells = <0>;
1476 compatible = "qcom,geni-spi";
1478 clock-names = "se";
1483 dma-names = "tx", "rx";
1484 power-domains = <&rpmhpd RPMHPD_CX>;
1485 operating-points-v2 = <&qup_opp_table>;
1489 interconnect-names = "qup-core",
1490 "qup-config",
1491 "qup-memory";
1492 #address-cells = <1>;
1493 #size-cells = <0>;
1498 compatible = "qcom,geni-debug-uart";
1500 clock-names = "se";
1502 pinctrl-names = "default";
1503 pinctrl-0 = <&qup_uart2_default>;
1505 power-domains = <&rpmhpd RPMHPD_CX>;
1506 operating-points-v2 = <&qup_opp_table>;
1509 interconnect-names = "qup-core",
1510 "qup-config";
1515 compatible = "qcom,geni-i2c";
1517 clock-names = "se";
1519 pinctrl-names = "default";
1520 pinctrl-0 = <&qup_i2c3_default>;
1524 dma-names = "tx", "rx";
1525 power-domains = <&rpmhpd SM8250_CX>;
1529 interconnect-names = "qup-core",
1530 "qup-config",
1531 "qup-memory";
1532 #address-cells = <1>;
1533 #size-cells = <0>;
1538 compatible = "qcom,geni-spi";
1540 clock-names = "se";
1545 dma-names = "tx", "rx";
1546 power-domains = <&rpmhpd RPMHPD_CX>;
1547 operating-points-v2 = <&qup_opp_table>;
1551 interconnect-names = "qup-core",
1552 "qup-config",
1553 "qup-memory";
1554 #address-cells = <1>;
1555 #size-cells = <0>;
1560 compatible = "qcom,geni-i2c";
1562 clock-names = "se";
1564 pinctrl-names = "default";
1565 pinctrl-0 = <&qup_i2c4_default>;
1569 dma-names = "tx", "rx";
1570 power-domains = <&rpmhpd SM8250_CX>;
1574 interconnect-names = "qup-core",
1575 "qup-config",
1576 "qup-memory";
1577 #address-cells = <1>;
1578 #size-cells = <0>;
1583 compatible = "qcom,geni-spi";
1585 clock-names = "se";
1590 dma-names = "tx", "rx";
1591 power-domains = <&rpmhpd RPMHPD_CX>;
1592 operating-points-v2 = <&qup_opp_table>;
1596 interconnect-names = "qup-core",
1597 "qup-config",
1598 "qup-memory";
1599 #address-cells = <1>;
1600 #size-cells = <0>;
1605 compatible = "qcom,geni-i2c";
1607 clock-names = "se";
1609 pinctrl-names = "default";
1610 pinctrl-0 = <&qup_i2c5_default>;
1614 dma-names = "tx", "rx";
1615 power-domains = <&rpmhpd SM8250_CX>;
1619 interconnect-names = "qup-core",
1620 "qup-config",
1621 "qup-memory";
1622 #address-cells = <1>;
1623 #size-cells = <0>;
1628 compatible = "qcom,geni-spi";
1630 clock-names = "se";
1635 dma-names = "tx", "rx";
1636 power-domains = <&rpmhpd RPMHPD_CX>;
1637 operating-points-v2 = <&qup_opp_table>;
1641 interconnect-names = "qup-core",
1642 "qup-config",
1643 "qup-memory";
1644 #address-cells = <1>;
1645 #size-cells = <0>;
1650 compatible = "qcom,geni-i2c";
1652 clock-names = "se";
1654 pinctrl-names = "default";
1655 pinctrl-0 = <&qup_i2c6_default>;
1659 dma-names = "tx", "rx";
1660 power-domains = <&rpmhpd SM8250_CX>;
1664 interconnect-names = "qup-core",
1665 "qup-config",
1666 "qup-memory";
1667 #address-cells = <1>;
1668 #size-cells = <0>;
1673 compatible = "qcom,geni-spi";
1675 clock-names = "se";
1680 dma-names = "tx", "rx";
1681 power-domains = <&rpmhpd RPMHPD_CX>;
1682 operating-points-v2 = <&qup_opp_table>;
1686 interconnect-names = "qup-core",
1687 "qup-config",
1688 "qup-memory";
1689 #address-cells = <1>;
1690 #size-cells = <0>;
1695 compatible = "qcom,geni-uart";
1697 clock-names = "se";
1699 pinctrl-names = "default";
1700 pinctrl-0 = <&qup_uart6_default>;
1702 power-domains = <&rpmhpd RPMHPD_CX>;
1703 operating-points-v2 = <&qup_opp_table>;
1706 interconnect-names = "qup-core",
1707 "qup-config";
1712 compatible = "qcom,geni-i2c";
1714 clock-names = "se";
1716 pinctrl-names = "default";
1717 pinctrl-0 = <&qup_i2c7_default>;
1721 dma-names = "tx", "rx";
1722 power-domains = <&rpmhpd SM8250_CX>;
1726 interconnect-names = "qup-core",
1727 "qup-config",
1728 "qup-memory";
1729 #address-cells = <1>;
1730 #size-cells = <0>;
1735 compatible = "qcom,geni-spi";
1737 clock-names = "se";
1742 dma-names = "tx", "rx";
1743 power-domains = <&rpmhpd RPMHPD_CX>;
1744 operating-points-v2 = <&qup_opp_table>;
1748 interconnect-names = "qup-core",
1749 "qup-config",
1750 "qup-memory";
1751 #address-cells = <1>;
1752 #size-cells = <0>;
1757 gpi_dma1: dma-controller@a00000 {
1758 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1770 dma-channels = <10>;
1771 dma-channel-mask = <0x3f>;
1773 #dma-cells = <3>;
1778 compatible = "qcom,geni-se-qup";
1780 clock-names = "m-ahb", "s-ahb";
1783 #address-cells = <2>;
1784 #size-cells = <2>;
1790 compatible = "qcom,geni-i2c";
1792 clock-names = "se";
1794 pinctrl-names = "default";
1795 pinctrl-0 = <&qup_i2c8_default>;
1799 dma-names = "tx", "rx";
1800 power-domains = <&rpmhpd SM8250_CX>;
1804 interconnect-names = "qup-core",
1805 "qup-config",
1806 "qup-memory";
1807 #address-cells = <1>;
1808 #size-cells = <0>;
1813 compatible = "qcom,geni-spi";
1815 clock-names = "se";
1820 dma-names = "tx", "rx";
1821 power-domains = <&rpmhpd RPMHPD_CX>;
1822 operating-points-v2 = <&qup_opp_table>;
1826 interconnect-names = "qup-core",
1827 "qup-config",
1828 "qup-memory";
1829 #address-cells = <1>;
1830 #size-cells = <0>;
1835 compatible = "qcom,geni-i2c";
1837 clock-names = "se";
1839 pinctrl-names = "default";
1840 pinctrl-0 = <&qup_i2c9_default>;
1844 dma-names = "tx", "rx";
1845 power-domains = <&rpmhpd SM8250_CX>;
1849 interconnect-names = "qup-core",
1850 "qup-config",
1851 "qup-memory";
1852 #address-cells = <1>;
1853 #size-cells = <0>;
1858 compatible = "qcom,geni-spi";
1860 clock-names = "se";
1865 dma-names = "tx", "rx";
1866 power-domains = <&rpmhpd RPMHPD_CX>;
1867 operating-points-v2 = <&qup_opp_table>;
1871 interconnect-names = "qup-core",
1872 "qup-config",
1873 "qup-memory";
1874 #address-cells = <1>;
1875 #size-cells = <0>;
1880 compatible = "qcom,geni-i2c";
1882 clock-names = "se";
1884 pinctrl-names = "default";
1885 pinctrl-0 = <&qup_i2c10_default>;
1889 dma-names = "tx", "rx";
1890 power-domains = <&rpmhpd SM8250_CX>;
1894 interconnect-names = "qup-core",
1895 "qup-config",
1896 "qup-memory";
1897 #address-cells = <1>;
1898 #size-cells = <0>;
1903 compatible = "qcom,geni-spi";
1905 clock-names = "se";
1910 dma-names = "tx", "rx";
1911 power-domains = <&rpmhpd RPMHPD_CX>;
1912 operating-points-v2 = <&qup_opp_table>;
1916 interconnect-names = "qup-core",
1917 "qup-config",
1918 "qup-memory";
1919 #address-cells = <1>;
1920 #size-cells = <0>;
1925 compatible = "qcom,geni-i2c";
1927 clock-names = "se";
1929 pinctrl-names = "default";
1930 pinctrl-0 = <&qup_i2c11_default>;
1934 dma-names = "tx", "rx";
1935 power-domains = <&rpmhpd SM8250_CX>;
1939 interconnect-names = "qup-core",
1940 "qup-config",
1941 "qup-memory";
1942 #address-cells = <1>;
1943 #size-cells = <0>;
1948 compatible = "qcom,geni-spi";
1950 clock-names = "se";
1955 dma-names = "tx", "rx";
1956 power-domains = <&rpmhpd RPMHPD_CX>;
1957 operating-points-v2 = <&qup_opp_table>;
1961 interconnect-names = "qup-core",
1962 "qup-config",
1963 "qup-memory";
1964 #address-cells = <1>;
1965 #size-cells = <0>;
1970 compatible = "qcom,geni-i2c";
1972 clock-names = "se";
1974 pinctrl-names = "default";
1975 pinctrl-0 = <&qup_i2c12_default>;
1979 dma-names = "tx", "rx";
1980 power-domains = <&rpmhpd SM8250_CX>;
1984 interconnect-names = "qup-core",
1985 "qup-config",
1986 "qup-memory";
1987 #address-cells = <1>;
1988 #size-cells = <0>;
1993 compatible = "qcom,geni-spi";
1995 clock-names = "se";
2000 dma-names = "tx", "rx";
2001 power-domains = <&rpmhpd RPMHPD_CX>;
2002 operating-points-v2 = <&qup_opp_table>;
2006 interconnect-names = "qup-core",
2007 "qup-config",
2008 "qup-memory";
2009 #address-cells = <1>;
2010 #size-cells = <0>;
2015 compatible = "qcom,geni-debug-uart";
2017 clock-names = "se";
2019 pinctrl-names = "default";
2020 pinctrl-0 = <&qup_uart12_default>;
2022 power-domains = <&rpmhpd RPMHPD_CX>;
2023 operating-points-v2 = <&qup_opp_table>;
2026 interconnect-names = "qup-core",
2027 "qup-config";
2032 compatible = "qcom,geni-i2c";
2034 clock-names = "se";
2036 pinctrl-names = "default";
2037 pinctrl-0 = <&qup_i2c13_default>;
2041 dma-names = "tx", "rx";
2042 power-domains = <&rpmhpd SM8250_CX>;
2046 interconnect-names = "qup-core",
2047 "qup-config",
2048 "qup-memory";
2049 #address-cells = <1>;
2050 #size-cells = <0>;
2055 compatible = "qcom,geni-spi";
2057 clock-names = "se";
2062 dma-names = "tx", "rx";
2063 power-domains = <&rpmhpd RPMHPD_CX>;
2064 operating-points-v2 = <&qup_opp_table>;
2068 interconnect-names = "qup-core",
2069 "qup-config",
2070 "qup-memory";
2071 #address-cells = <1>;
2072 #size-cells = <0>;
2078 compatible = "qcom,sm8250-config-noc";
2080 #interconnect-cells = <2>;
2081 qcom,bcm-voters = <&apps_bcm_voter>;
2085 compatible = "qcom,sm8250-system-noc";
2087 #interconnect-cells = <2>;
2088 qcom,bcm-voters = <&apps_bcm_voter>;
2092 compatible = "qcom,sm8250-mc-virt";
2094 #interconnect-cells = <2>;
2095 qcom,bcm-voters = <&apps_bcm_voter>;
2099 compatible = "qcom,sm8250-aggre1-noc";
2101 #interconnect-cells = <2>;
2102 qcom,bcm-voters = <&apps_bcm_voter>;
2106 compatible = "qcom,sm8250-aggre2-noc";
2108 #interconnect-cells = <2>;
2109 qcom,bcm-voters = <&apps_bcm_voter>;
2113 compatible = "qcom,sm8250-compute-noc";
2115 #interconnect-cells = <2>;
2116 qcom,bcm-voters = <&apps_bcm_voter>;
2120 compatible = "qcom,sm8250-mmss-noc";
2122 #interconnect-cells = <2>;
2123 qcom,bcm-voters = <&apps_bcm_voter>;
2127 compatible = "qcom,pcie-sm8250";
2134 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2136 linux,pci-domain = <0>;
2137 bus-range = <0x00 0xff>;
2138 num-lanes = <1>;
2140 #address-cells = <3>;
2141 #size-cells = <2>;
2155 interrupt-names = "msi0",
2164 #interrupt-cells = <1>;
2165 interrupt-map-mask = <0 0 0 0x7>;
2166 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2179 clock-names = "pipe",
2188 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2192 reset-names = "pci";
2194 power-domains = <&gcc PCIE_0_GDSC>;
2197 phy-names = "pciephy";
2199 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
2200 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
2202 pinctrl-names = "default";
2203 pinctrl-0 = <&pcie0_default_state>;
2204 dma-coherent;
2211 bus-range = <0x01 0xff>;
2213 #address-cells = <3>;
2214 #size-cells = <2>;
2220 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
2228 clock-names = "aux",
2234 clock-output-names = "pcie_0_pipe_clk";
2235 #clock-cells = <0>;
2237 #phy-cells = <0>;
2240 reset-names = "phy";
2242 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2243 assigned-clock-rates = <100000000>;
2249 compatible = "qcom,pcie-sm8250";
2256 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2258 linux,pci-domain = <1>;
2259 bus-range = <0x00 0xff>;
2260 num-lanes = <2>;
2262 #address-cells = <3>;
2263 #size-cells = <2>;
2277 interrupt-names = "msi0",
2286 #interrupt-cells = <1>;
2287 interrupt-map-mask = <0 0 0 0x7>;
2288 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2302 clock-names = "pipe",
2312 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2313 assigned-clock-rates = <19200000>;
2315 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2319 reset-names = "pci";
2321 power-domains = <&gcc PCIE_1_GDSC>;
2324 phy-names = "pciephy";
2326 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
2327 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
2329 pinctrl-names = "default";
2330 pinctrl-0 = <&pcie1_default_state>;
2331 dma-coherent;
2338 bus-range = <0x01 0xff>;
2340 #address-cells = <3>;
2341 #size-cells = <2>;
2347 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2355 clock-names = "aux",
2361 clock-output-names = "pcie_1_pipe_clk";
2362 #clock-cells = <0>;
2364 #phy-cells = <0>;
2367 reset-names = "phy";
2369 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2370 assigned-clock-rates = <100000000>;
2376 compatible = "qcom,pcie-sm8250";
2383 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2385 linux,pci-domain = <2>;
2386 bus-range = <0x00 0xff>;
2387 num-lanes = <2>;
2389 #address-cells = <3>;
2390 #size-cells = <2>;
2404 interrupt-names = "msi0",
2413 #interrupt-cells = <1>;
2414 interrupt-map-mask = <0 0 0 0x7>;
2415 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2429 clock-names = "pipe",
2439 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2440 assigned-clock-rates = <19200000>;
2442 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2446 reset-names = "pci";
2448 power-domains = <&gcc PCIE_2_GDSC>;
2451 phy-names = "pciephy";
2453 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
2454 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
2456 pinctrl-names = "default";
2457 pinctrl-0 = <&pcie2_default_state>;
2458 dma-coherent;
2465 bus-range = <0x01 0xff>;
2467 #address-cells = <3>;
2468 #size-cells = <2>;
2474 compatible = "qcom,sm8250-qmp-modem-pcie-phy";
2482 clock-names = "aux",
2488 clock-output-names = "pcie_2_pipe_clk";
2489 #clock-cells = <0>;
2491 #phy-cells = <0>;
2494 reset-names = "phy";
2496 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2497 assigned-clock-rates = <100000000>;
2503 compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
2504 "jedec,ufs-2.0";
2508 phy-names = "ufsphy";
2509 lanes-per-direction = <2>;
2510 #reset-cells = <1>;
2512 reset-names = "rst";
2514 power-domains = <&gcc UFS_PHY_GDSC>;
2518 clock-names =
2537 operating-points-v2 = <&ufs_opp_table>;
2541 interconnect-names = "ufs-ddr", "cpu-ufs";
2545 ufs_opp_table: opp-table {
2546 compatible = "operating-points-v2";
2548 opp-37500000 {
2549 opp-hz = /bits/ 64 <37500000>,
2557 required-opps = <&rpmhpd_opp_low_svs>;
2560 opp-300000000 {
2561 opp-hz = /bits/ 64 <300000000>,
2569 required-opps = <&rpmhpd_opp_nom>;
2575 compatible = "qcom,sm8250-qmp-ufs-phy";
2581 clock-names = "ref",
2586 reset-names = "ufsphy";
2588 power-domains = <&gcc UFS_PHY_GDSC>;
2590 #phy-cells = <0>;
2595 cryptobam: dma-controller@1dc4000 {
2596 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2599 #dma-cells = <1>;
2601 qcom,controlled-remotely;
2602 num-channels = <8>;
2603 qcom,num-ees = <2>;
2613 compatible = "qcom,sm8250-qce", "qcom,sm8150-qce", "qcom,qce";
2616 dma-names = "rx", "tx";
2624 interconnect-names = "memory";
2628 compatible = "qcom,tcsr-mutex";
2630 #hwlock-cells = <1>;
2634 compatible = "qcom,sm8250-tcsr", "syscon";
2639 compatible = "qcom,sm8250-lpass-wsa-macro";
2647 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2649 #clock-cells = <0>;
2650 clock-output-names = "mclk";
2651 #sound-dai-cells = <1>;
2653 pinctrl-names = "default";
2654 pinctrl-0 = <&wsa_swr_active>;
2661 compatible = "qcom,soundwire-v1.5.1";
2664 clock-names = "iface";
2666 qcom,din-ports = <2>;
2667 qcom,dout-ports = <6>;
2669 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2670 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2671 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2672 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2674 #sound-dai-cells = <1>;
2675 #address-cells = <2>;
2676 #size-cells = <0>;
2682 compatible = "qcom,sm8250-lpass-va-macro";
2688 clock-names = "mclk", "macro", "dcodec";
2690 #clock-cells = <0>;
2691 clock-output-names = "fsgen";
2692 #sound-dai-cells = <1>;
2696 pinctrl-names = "default";
2697 pinctrl-0 = <&rx_swr_active>;
2698 compatible = "qcom,sm8250-lpass-rx-macro";
2708 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2710 #clock-cells = <0>;
2711 clock-output-names = "mclk";
2712 #sound-dai-cells = <1>;
2717 compatible = "qcom,soundwire-v1.5.1";
2721 clock-names = "iface";
2723 qcom,din-ports = <0>;
2724 qcom,dout-ports = <5>;
2726 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2727 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2728 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2729 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2730 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2731 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2732 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2733 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2734 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2736 #sound-dai-cells = <1>;
2737 #address-cells = <2>;
2738 #size-cells = <0>;
2742 pinctrl-names = "default";
2743 pinctrl-0 = <&tx_swr_active>;
2744 compatible = "qcom,sm8250-lpass-tx-macro";
2754 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2756 #clock-cells = <0>;
2757 clock-output-names = "mclk";
2758 #sound-dai-cells = <1>;
2764 compatible = "qcom,soundwire-v1.5.1";
2766 interrupt-names = "core";
2770 clock-names = "iface";
2773 qcom,din-ports = <5>;
2774 qcom,dout-ports = <0>;
2775 qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>;
2776 qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>;
2777 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>;
2778 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2779 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2780 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2781 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2782 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2783 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>;
2784 #sound-dai-cells = <1>;
2785 #address-cells = <2>;
2786 #size-cells = <0>;
2790 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
2793 gpio-controller;
2794 #gpio-cells = <2>;
2795 gpio-ranges = <&lpass_tlmm 0 0 14>;
2799 clock-names = "core", "audio";
2801 wsa_swr_active: wsa-swr-active-state {
2802 clk-pins {
2805 drive-strength = <2>;
2806 slew-rate = <1>;
2807 bias-disable;
2810 data-pins {
2813 drive-strength = <2>;
2814 slew-rate = <1>;
2815 bias-bus-hold;
2819 wsa_swr_sleep: wsa-swr-sleep-state {
2820 clk-pins {
2823 drive-strength = <2>;
2824 bias-pull-down;
2827 data-pins {
2830 drive-strength = <2>;
2831 bias-pull-down;
2835 dmic01_active: dmic01-active-state {
2836 clk-pins {
2839 drive-strength = <8>;
2840 output-high;
2842 data-pins {
2845 drive-strength = <8>;
2849 dmic01_sleep: dmic01-sleep-state {
2850 clk-pins {
2853 drive-strength = <2>;
2854 bias-disable;
2855 output-low;
2858 data-pins {
2861 drive-strength = <2>;
2862 bias-pull-down;
2866 rx_swr_active: rx-swr-active-state {
2867 clk-pins {
2870 drive-strength = <2>;
2871 slew-rate = <1>;
2872 bias-disable;
2875 data-pins {
2878 drive-strength = <2>;
2879 slew-rate = <1>;
2880 bias-bus-hold;
2884 tx_swr_active: tx-swr-active-state {
2885 clk-pins {
2888 drive-strength = <2>;
2889 slew-rate = <1>;
2890 bias-disable;
2893 data-pins {
2896 drive-strength = <2>;
2897 slew-rate = <1>;
2898 bias-bus-hold;
2902 tx_swr_sleep: tx-swr-sleep-state {
2903 clk-pins {
2906 drive-strength = <2>;
2907 bias-pull-down;
2910 data1-pins {
2913 drive-strength = <2>;
2914 bias-bus-hold;
2917 data2-pins {
2920 drive-strength = <2>;
2921 bias-pull-down;
2927 compatible = "qcom,adreno-650.2",
2931 reg-names = "kgsl_3d0_reg_memory";
2937 operating-points-v2 = <&gpu_opp_table>;
2941 nvmem-cells = <&gpu_speed_bin>;
2942 nvmem-cell-names = "speed_bin";
2943 #cooling-cells = <2>;
2947 zap-shader {
2948 memory-region = <&gpu_mem>;
2951 gpu_opp_table: opp-table {
2952 compatible = "operating-points-v2";
2954 opp-670000000 {
2955 opp-hz = /bits/ 64 <670000000>;
2956 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2957 opp-supported-hw = <0xa>;
2960 opp-587000000 {
2961 opp-hz = /bits/ 64 <587000000>;
2962 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2963 opp-supported-hw = <0xb>;
2966 opp-525000000 {
2967 opp-hz = /bits/ 64 <525000000>;
2968 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2969 opp-supported-hw = <0xf>;
2972 opp-490000000 {
2973 opp-hz = /bits/ 64 <490000000>;
2974 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2975 opp-supported-hw = <0xf>;
2978 opp-441600000 {
2979 opp-hz = /bits/ 64 <441600000>;
2980 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2981 opp-supported-hw = <0xf>;
2984 opp-400000000 {
2985 opp-hz = /bits/ 64 <400000000>;
2986 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2987 opp-supported-hw = <0xf>;
2990 opp-305000000 {
2991 opp-hz = /bits/ 64 <305000000>;
2992 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2993 opp-supported-hw = <0xf>;
2999 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
3005 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
3009 interrupt-names = "hfi", "gmu";
3016 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
3018 power-domains = <&gpucc GPU_CX_GDSC>,
3020 power-domain-names = "cx", "gx";
3024 operating-points-v2 = <&gmu_opp_table>;
3028 gmu_opp_table: opp-table {
3029 compatible = "operating-points-v2";
3031 opp-200000000 {
3032 opp-hz = /bits/ 64 <200000000>;
3033 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3038 gpucc: clock-controller@3d90000 {
3039 compatible = "qcom,sm8250-gpucc";
3044 clock-names = "bi_tcxo",
3047 #clock-cells = <1>;
3048 #reset-cells = <1>;
3049 #power-domain-cells = <1>;
3053 compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu",
3054 "qcom,smmu-500", "arm,mmu-500";
3056 #iommu-cells = <2>;
3057 #global-interrupts = <2>;
3071 clock-names = "ahb", "bus", "iface";
3073 power-domains = <&gpucc GPU_CX_GDSC>;
3074 dma-coherent;
3078 compatible = "qcom,sm8250-slpi-pas";
3081 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
3086 interrupt-names = "wdog", "fatal", "ready",
3087 "handover", "stop-ack";
3090 clock-names = "xo";
3092 power-domains = <&rpmhpd RPMHPD_LCX>,
3094 power-domain-names = "lcx", "lmx";
3096 memory-region = <&slpi_mem>;
3100 qcom,smem-states = <&smp2p_slpi_out 0>;
3101 qcom,smem-state-names = "stop";
3105 glink-edge {
3106 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
3113 qcom,remote-pid = <3>;
3117 qcom,glink-channels = "fastrpcglink-apps-dsp";
3119 qcom,non-secure-domain;
3120 #address-cells = <1>;
3121 #size-cells = <0>;
3123 compute-cb@1 {
3124 compatible = "qcom,fastrpc-compute-cb";
3129 compute-cb@2 {
3130 compatible = "qcom,fastrpc-compute-cb";
3135 compute-cb@3 {
3136 compatible = "qcom,fastrpc-compute-cb";
3139 /* note: shared-cb = <4> in downstream */
3146 compatible = "arm,coresight-stm", "arm,primecell";
3148 reg-names = "stm-base", "stm-stimulus-base";
3151 clock-names = "apb_pclk";
3153 out-ports {
3156 remote-endpoint = <&funnel0_in7>;
3163 compatible = "qcom,coresight-tpda", "arm,primecell";
3167 clock-names = "apb_pclk";
3169 out-ports {
3173 remote-endpoint = <&funnel_qatb_in_tpda>;
3178 in-ports {
3179 #address-cells = <1>;
3180 #size-cells = <0>;
3185 remote-endpoint = <&tpdm_mm_out_tpda9>;
3192 remote-endpoint = <&tpdm_prng_out_tpda_23>;
3199 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3203 clock-names = "apb_pclk";
3205 out-ports {
3208 remote-endpoint = <&funnel_in0_in_funnel_qatb>;
3213 in-ports {
3216 remote-endpoint = <&tpda_out_funnel_qatb>;
3223 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3227 clock-names = "apb_pclk";
3229 out-ports {
3232 remote-endpoint = <&funnel_merg_in_funnel_in0>;
3237 in-ports {
3238 #address-cells = <1>;
3239 #size-cells = <0>;
3244 remote-endpoint = <&funnel_qatb_out_funnel_in0>;
3251 remote-endpoint = <&stm_out>;
3258 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3262 clock-names = "apb_pclk";
3264 out-ports {
3267 remote-endpoint = <&funnel_merg_in_funnel_in1>;
3272 in-ports {
3273 #address-cells = <1>;
3274 #size-cells = <0>;
3279 remote-endpoint = <&funnel_apss_merg_out_funnel_in1>;
3286 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3290 clock-names = "apb_pclk";
3292 out-ports {
3295 remote-endpoint = <&funnel_swao_in_funnel_merg>;
3300 in-ports {
3301 #address-cells = <1>;
3302 #size-cells = <0>;
3307 remote-endpoint = <&funnel_in0_out_funnel_merg>;
3314 remote-endpoint = <&funnel_in1_out_funnel_merg>;
3321 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3325 clock-names = "apb_pclk";
3327 out-ports {
3330 remote-endpoint = <&etr_in>;
3335 in-ports {
3338 remote-endpoint = <&replicator_swao_out_cx_in>;
3345 compatible = "arm,coresight-tmc", "arm,primecell";
3349 clock-names = "apb_pclk";
3350 arm,scatter-gather;
3352 in-ports {
3355 remote-endpoint = <&replicator_out>;
3362 compatible = "qcom,coresight-tpdm", "arm,primecell";
3366 clock-names = "apb_pclk";
3368 out-ports {
3371 remote-endpoint = <&tpda_23_in_tpdm_prng>;
3378 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3379 arm,primecell-periphid = <0x000bb908>;
3384 clock-names = "apb_pclk";
3386 out-ports {
3389 remote-endpoint = <&etf_in_funnel_swao_out>;
3394 in-ports {
3395 #address-cells = <1>;
3396 #size-cells = <0>;
3401 remote-endpoint = <&funnel_merg_out_funnel_swao>;
3408 compatible = "arm,coresight-tmc", "arm,primecell";
3412 clock-names = "apb_pclk";
3414 out-ports {
3417 remote-endpoint = <&replicator_in>;
3422 in-ports {
3426 remote-endpoint = <&funnel_swao_out_etf>;
3433 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3437 clock-names = "apb_pclk";
3439 out-ports {
3442 remote-endpoint = <&replicator_cx_in_swao_out>;
3447 in-ports {
3450 remote-endpoint = <&etf_out>;
3457 compatible = "qcom,coresight-tpdm", "arm,primecell";
3461 clock-names = "apb_pclk";
3463 out-ports {
3466 remote-endpoint = <&funnel_dl_mm_in_tpdm_mm>;
3473 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3477 clock-names = "apb_pclk";
3479 out-ports {
3482 remote-endpoint = <&funnel_dl_center_in_funnel_dl_mm>;
3487 in-ports {
3488 #address-cells = <1>;
3489 #size-cells = <0>;
3494 remote-endpoint = <&tpdm_mm_out_funnel_dl_mm>;
3501 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3505 clock-names = "apb_pclk";
3507 out-ports {
3510 remote-endpoint = <&tpda_9_in_tpdm_mm>;
3515 in-ports {
3516 #address-cells = <1>;
3517 #size-cells = <0>;
3522 remote-endpoint = <&funnel_dl_mm_out_funnel_dl_center>;
3529 compatible = "arm,coresight-etm4x", "arm,primecell";
3535 clock-names = "apb_pclk";
3536 arm,coresight-loses-context-with-cpu;
3538 out-ports {
3541 remote-endpoint = <&apss_funnel_in0>;
3548 compatible = "arm,coresight-etm4x", "arm,primecell";
3554 clock-names = "apb_pclk";
3555 arm,coresight-loses-context-with-cpu;
3557 out-ports {
3560 remote-endpoint = <&apss_funnel_in1>;
3567 compatible = "arm,coresight-etm4x", "arm,primecell";
3573 clock-names = "apb_pclk";
3574 arm,coresight-loses-context-with-cpu;
3576 out-ports {
3579 remote-endpoint = <&apss_funnel_in2>;
3586 compatible = "arm,coresight-etm4x", "arm,primecell";
3592 clock-names = "apb_pclk";
3593 arm,coresight-loses-context-with-cpu;
3595 out-ports {
3598 remote-endpoint = <&apss_funnel_in3>;
3605 compatible = "arm,coresight-etm4x", "arm,primecell";
3611 clock-names = "apb_pclk";
3612 arm,coresight-loses-context-with-cpu;
3614 out-ports {
3617 remote-endpoint = <&apss_funnel_in4>;
3624 compatible = "arm,coresight-etm4x", "arm,primecell";
3630 clock-names = "apb_pclk";
3631 arm,coresight-loses-context-with-cpu;
3633 out-ports {
3636 remote-endpoint = <&apss_funnel_in5>;
3643 compatible = "arm,coresight-etm4x", "arm,primecell";
3649 clock-names = "apb_pclk";
3650 arm,coresight-loses-context-with-cpu;
3652 out-ports {
3655 remote-endpoint = <&apss_funnel_in6>;
3662 compatible = "arm,coresight-etm4x", "arm,primecell";
3668 clock-names = "apb_pclk";
3669 arm,coresight-loses-context-with-cpu;
3671 out-ports {
3674 remote-endpoint = <&apss_funnel_in7>;
3681 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3685 clock-names = "apb_pclk";
3687 out-ports {
3690 remote-endpoint = <&funnel_apss_merg_in_funnel_apss>;
3695 in-ports {
3696 #address-cells = <1>;
3697 #size-cells = <0>;
3702 remote-endpoint = <&etm0_out>;
3709 remote-endpoint = <&etm1_out>;
3716 remote-endpoint = <&etm2_out>;
3723 remote-endpoint = <&etm3_out>;
3730 remote-endpoint = <&etm4_out>;
3737 remote-endpoint = <&etm5_out>;
3744 remote-endpoint = <&etm6_out>;
3751 remote-endpoint = <&etm7_out>;
3758 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3762 clock-names = "apb_pclk";
3764 out-ports {
3767 remote-endpoint = <&funnel_in1_in_funnel_apss_merg>;
3772 in-ports {
3775 remote-endpoint = <&funnel_apss_out_funnel_apss_merg>;
3782 compatible = "qcom,sm8250-cdsp-pas";
3785 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3790 interrupt-names = "wdog", "fatal", "ready",
3791 "handover", "stop-ack";
3794 clock-names = "xo";
3796 power-domains = <&rpmhpd RPMHPD_CX>;
3798 memory-region = <&cdsp_mem>;
3802 qcom,smem-states = <&smp2p_cdsp_out 0>;
3803 qcom,smem-state-names = "stop";
3807 glink-edge {
3808 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3815 qcom,remote-pid = <5>;
3819 qcom,glink-channels = "fastrpcglink-apps-dsp";
3821 qcom,non-secure-domain;
3822 #address-cells = <1>;
3823 #size-cells = <0>;
3825 compute-cb@1 {
3826 compatible = "qcom,fastrpc-compute-cb";
3831 compute-cb@2 {
3832 compatible = "qcom,fastrpc-compute-cb";
3837 compute-cb@3 {
3838 compatible = "qcom,fastrpc-compute-cb";
3843 compute-cb@4 {
3844 compatible = "qcom,fastrpc-compute-cb";
3849 compute-cb@5 {
3850 compatible = "qcom,fastrpc-compute-cb";
3855 compute-cb@6 {
3856 compatible = "qcom,fastrpc-compute-cb";
3861 compute-cb@7 {
3862 compatible = "qcom,fastrpc-compute-cb";
3867 compute-cb@8 {
3868 compatible = "qcom,fastrpc-compute-cb";
3879 compatible = "qcom,sm8250-usb-hs-phy",
3880 "qcom,usb-snps-hs-7nm-phy";
3883 #phy-cells = <0>;
3886 clock-names = "ref";
3892 compatible = "qcom,sm8250-usb-hs-phy",
3893 "qcom,usb-snps-hs-7nm-phy";
3896 #phy-cells = <0>;
3899 clock-names = "ref";
3905 compatible = "qcom,sm8250-qmp-usb3-dp-phy";
3913 clock-names = "aux",
3920 reset-names = "phy", "common";
3922 #clock-cells = <1>;
3923 #phy-cells = <1>;
3925 orientation-switch;
3928 #address-cells = <1>;
3929 #size-cells = <0>;
3940 remote-endpoint = <&usb_1_dwc3_ss_out>;
3953 compatible = "qcom,sm8250-qmp-usb3-uni-phy";
3960 clock-names = "aux",
3964 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3965 #clock-cells = <0>;
3966 #phy-cells = <0>;
3970 reset-names = "phy",
3977 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
3982 interrupt-names = "hc_irq", "pwr_irq";
3987 clock-names = "iface", "core", "xo";
3989 qcom,dll-config = <0x0007642c>;
3990 qcom,ddr-config = <0x80040868>;
3991 power-domains = <&rpmhpd RPMHPD_CX>;
3992 operating-points-v2 = <&sdhc2_opp_table>;
3996 sdhc2_opp_table: opp-table {
3997 compatible = "operating-points-v2";
3999 opp-19200000 {
4000 opp-hz = /bits/ 64 <19200000>;
4001 required-opps = <&rpmhpd_opp_min_svs>;
4004 opp-50000000 {
4005 opp-hz = /bits/ 64 <50000000>;
4006 required-opps = <&rpmhpd_opp_low_svs>;
4009 opp-100000000 {
4010 opp-hz = /bits/ 64 <100000000>;
4011 required-opps = <&rpmhpd_opp_svs>;
4014 opp-202000000 {
4015 opp-hz = /bits/ 64 <202000000>;
4016 required-opps = <&rpmhpd_opp_svs_l1>;
4022 compatible = "qcom,sm8250-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
4029 operating-points-v2 = <&llcc_bwmon_opp_table>;
4031 llcc_bwmon_opp_table: opp-table {
4032 compatible = "operating-points-v2";
4034 opp-800000 {
4035 opp-peak-kBps = <(200 * 4 * 1000)>;
4038 opp-1200000 {
4039 opp-peak-kBps = <(300 * 4 * 1000)>;
4042 opp-1804000 {
4043 opp-peak-kBps = <(451 * 4 * 1000)>;
4046 opp-2188000 {
4047 opp-peak-kBps = <(547 * 4 * 1000)>;
4050 opp-2724000 {
4051 opp-peak-kBps = <(681 * 4 * 1000)>;
4054 opp-3072000 {
4055 opp-peak-kBps = <(768 * 4 * 1000)>;
4058 opp-4068000 {
4059 opp-peak-kBps = <(1017 * 4 * 1000)>;
4064 opp-6220000 {
4065 opp-peak-kBps = <(1555 * 4 * 1000)>;
4068 opp-7216000 {
4069 opp-peak-kBps = <(1804 * 4 * 1000)>;
4072 opp-8368000 {
4073 opp-peak-kBps = <(2092 * 4 * 1000)>;
4077 opp-10944000 {
4078 opp-peak-kBps = <(2736 * 4 * 1000)>;
4084 compatible = "qcom,sm8250-cpu-bwmon", "qcom,sdm845-bwmon";
4090 operating-points-v2 = <&cpu_bwmon_opp_table>;
4092 cpu_bwmon_opp_table: opp-table {
4093 compatible = "operating-points-v2";
4095 opp-800000 {
4096 opp-peak-kBps = <(200 * 4 * 1000)>;
4099 opp-1804000 {
4100 opp-peak-kBps = <(451 * 4 * 1000)>;
4103 opp-2188000 {
4104 opp-peak-kBps = <(547 * 4 * 1000)>;
4107 opp-2724000 {
4108 opp-peak-kBps = <(681 * 4 * 1000)>;
4111 opp-3072000 {
4112 opp-peak-kBps = <(768 * 4 * 1000)>;
4117 opp-6220000 {
4118 opp-peak-kBps = <(1555 * 4 * 1000)>;
4121 opp-6832000 {
4122 opp-peak-kBps = <(1708 * 4 * 1000)>;
4125 opp-8368000 {
4126 opp-peak-kBps = <(2092 * 4 * 1000)>;
4132 opp-10944000 {
4133 opp-peak-kBps = <(2736 * 4 * 1000)>;
4137 opp-12784000 {
4138 opp-peak-kBps = <(3196 * 4 * 1000)>;
4144 compatible = "qcom,sm8250-dc-noc";
4146 #interconnect-cells = <2>;
4147 qcom,bcm-voters = <&apps_bcm_voter>;
4151 compatible = "qcom,sm8250-gem-noc";
4153 #interconnect-cells = <2>;
4154 qcom,bcm-voters = <&apps_bcm_voter>;
4158 compatible = "qcom,sm8250-npu-noc";
4160 #interconnect-cells = <2>;
4161 qcom,bcm-voters = <&apps_bcm_voter>;
4165 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4168 #address-cells = <2>;
4169 #size-cells = <2>;
4171 dma-ranges;
4179 clock-names = "cfg_noc",
4186 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4188 assigned-clock-rates = <19200000>, <200000000>;
4190 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4195 interrupt-names = "pwr_event",
4201 power-domains = <&gcc USB30_PRIM_GDSC>;
4202 wakeup-source;
4208 interconnect-names = "usb-ddr", "apps-usb";
4217 snps,dis-u1-entry-quirk;
4218 snps,dis-u2-entry-quirk;
4220 phy-names = "usb2-phy", "usb3-phy";
4223 #address-cells = <1>;
4224 #size-cells = <0>;
4237 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
4244 system-cache-controller@9200000 {
4245 compatible = "qcom,sm8250-llcc";
4249 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
4254 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4257 #address-cells = <2>;
4258 #size-cells = <2>;
4260 dma-ranges;
4268 clock-names = "cfg_noc",
4275 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4277 assigned-clock-rates = <19200000>, <200000000>;
4279 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
4284 interrupt-names = "pwr_event",
4290 power-domains = <&gcc USB30_SEC_GDSC>;
4291 wakeup-source;
4297 interconnect-names = "usb-ddr", "apps-usb";
4306 snps,dis-u1-entry-quirk;
4307 snps,dis-u2-entry-quirk;
4309 phy-names = "usb2-phy", "usb3-phy";
4313 venus: video-codec@aa00000 {
4314 compatible = "qcom,sm8250-venus";
4317 power-domains = <&videocc MVS0C_GDSC>,
4320 power-domain-names = "venus", "vcodec0", "mx";
4321 operating-points-v2 = <&venus_opp_table>;
4326 clock-names = "iface", "core", "vcodec0_core";
4330 interconnect-names = "cpu-cfg", "video-mem";
4333 memory-region = <&video_mem>;
4337 reset-names = "bus", "core";
4341 video-decoder {
4342 compatible = "venus-decoder";
4345 video-encoder {
4346 compatible = "venus-encoder";
4349 venus_opp_table: opp-table {
4350 compatible = "operating-points-v2";
4352 opp-720000000 {
4353 opp-hz = /bits/ 64 <720000000>;
4354 required-opps = <&rpmhpd_opp_low_svs>;
4357 opp-1014000000 {
4358 opp-hz = /bits/ 64 <1014000000>;
4359 required-opps = <&rpmhpd_opp_svs>;
4362 opp-1098000000 {
4363 opp-hz = /bits/ 64 <1098000000>;
4364 required-opps = <&rpmhpd_opp_svs_l1>;
4367 opp-1332000000 {
4368 opp-hz = /bits/ 64 <1332000000>;
4369 required-opps = <&rpmhpd_opp_nom>;
4374 videocc: clock-controller@abf0000 {
4375 compatible = "qcom,sm8250-videocc";
4380 power-domains = <&rpmhpd RPMHPD_MMCX>;
4381 required-opps = <&rpmhpd_opp_low_svs>;
4382 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
4383 #clock-cells = <1>;
4384 #reset-cells = <1>;
4385 #power-domain-cells = <1>;
4389 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4390 #address-cells = <1>;
4391 #size-cells = <0>;
4395 power-domains = <&camcc TITAN_TOP_GDSC>;
4402 clock-names = "camnoc_axi",
4408 pinctrl-0 = <&cci0_default>;
4409 pinctrl-1 = <&cci0_sleep>;
4410 pinctrl-names = "default", "sleep";
4414 cci0_i2c0: i2c-bus@0 {
4416 clock-frequency = <1000000>;
4417 #address-cells = <1>;
4418 #size-cells = <0>;
4421 cci0_i2c1: i2c-bus@1 {
4423 clock-frequency = <1000000>;
4424 #address-cells = <1>;
4425 #size-cells = <0>;
4430 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4431 #address-cells = <1>;
4432 #size-cells = <0>;
4436 power-domains = <&camcc TITAN_TOP_GDSC>;
4443 clock-names = "camnoc_axi",
4449 pinctrl-0 = <&cci1_default>;
4450 pinctrl-1 = <&cci1_sleep>;
4451 pinctrl-names = "default", "sleep";
4455 cci1_i2c0: i2c-bus@0 {
4457 clock-frequency = <1000000>;
4458 #address-cells = <1>;
4459 #size-cells = <0>;
4462 cci1_i2c1: i2c-bus@1 {
4464 clock-frequency = <1000000>;
4465 #address-cells = <1>;
4466 #size-cells = <0>;
4471 compatible = "qcom,sm8250-camss";
4484 reg-names = "csiphy0",
4509 interrupt-names = "csiphy0",
4524 power-domains = <&camcc IFE_0_GDSC>,
4566 clock-names = "cam_ahb_clk",
4617 interconnect-names = "cam_ahb",
4623 #address-cells = <1>;
4624 #size-cells = <0>;
4652 camcc: clock-controller@ad00000 {
4653 compatible = "qcom,sm8250-camcc";
4659 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
4660 power-domains = <&rpmhpd RPMHPD_MMCX>;
4661 required-opps = <&rpmhpd_opp_low_svs>;
4662 #clock-cells = <1>;
4663 #reset-cells = <1>;
4664 #power-domain-cells = <1>;
4667 mdss: display-subsystem@ae00000 {
4668 compatible = "qcom,sm8250-mdss";
4670 reg-names = "mdss";
4674 interconnect-names = "mdp0-mem", "mdp1-mem";
4676 power-domains = <&dispcc MDSS_GDSC>;
4682 clock-names = "iface", "bus", "nrt_bus", "core";
4685 interrupt-controller;
4686 #interrupt-cells = <1>;
4692 #address-cells = <2>;
4693 #size-cells = <2>;
4696 mdss_mdp: display-controller@ae01000 {
4697 compatible = "qcom,sm8250-dpu";
4700 reg-names = "mdp", "vbif";
4706 clock-names = "iface", "bus", "core", "vsync";
4708 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4709 assigned-clock-rates = <19200000>;
4711 operating-points-v2 = <&mdp_opp_table>;
4712 power-domains = <&rpmhpd RPMHPD_MMCX>;
4714 interrupt-parent = <&mdss>;
4718 #address-cells = <1>;
4719 #size-cells = <0>;
4724 remote-endpoint = <&mdss_dsi0_in>;
4731 remote-endpoint = <&mdss_dsi1_in>;
4739 remote-endpoint = <&mdss_dp_in>;
4744 mdp_opp_table: opp-table {
4745 compatible = "operating-points-v2";
4747 opp-200000000 {
4748 opp-hz = /bits/ 64 <200000000>;
4749 required-opps = <&rpmhpd_opp_low_svs>;
4752 opp-300000000 {
4753 opp-hz = /bits/ 64 <300000000>;
4754 required-opps = <&rpmhpd_opp_svs>;
4757 opp-345000000 {
4758 opp-hz = /bits/ 64 <345000000>;
4759 required-opps = <&rpmhpd_opp_svs_l1>;
4762 opp-460000000 {
4763 opp-hz = /bits/ 64 <460000000>;
4764 required-opps = <&rpmhpd_opp_nom>;
4769 mdss_dp: displayport-controller@ae90000 {
4770 compatible = "qcom,sm8250-dp", "qcom,sm8350-dp";
4776 interrupt-parent = <&mdss>;
4783 clock-names = "core_iface",
4789 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4791 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4795 phy-names = "dp";
4797 #sound-dai-cells = <0>;
4799 operating-points-v2 = <&dp_opp_table>;
4800 power-domains = <&rpmhpd SM8250_MMCX>;
4805 #address-cells = <1>;
4806 #size-cells = <0>;
4811 remote-endpoint = <&dpu_intf0_out>;
4823 dp_opp_table: opp-table {
4824 compatible = "operating-points-v2";
4826 opp-160000000 {
4827 opp-hz = /bits/ 64 <160000000>;
4828 required-opps = <&rpmhpd_opp_low_svs>;
4831 opp-270000000 {
4832 opp-hz = /bits/ 64 <270000000>;
4833 required-opps = <&rpmhpd_opp_svs>;
4836 opp-540000000 {
4837 opp-hz = /bits/ 64 <540000000>;
4838 required-opps = <&rpmhpd_opp_svs_l1>;
4841 opp-810000000 {
4842 opp-hz = /bits/ 64 <810000000>;
4843 required-opps = <&rpmhpd_opp_nom>;
4849 compatible = "qcom,sm8250-dsi-ctrl",
4850 "qcom,mdss-dsi-ctrl";
4852 reg-names = "dsi_ctrl";
4854 interrupt-parent = <&mdss>;
4863 clock-names = "byte",
4870 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
4872 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
4875 operating-points-v2 = <&dsi_opp_table>;
4876 power-domains = <&rpmhpd RPMHPD_MMCX>;
4882 #address-cells = <1>;
4883 #size-cells = <0>;
4886 #address-cells = <1>;
4887 #size-cells = <0>;
4892 remote-endpoint = <&dpu_intf1_out>;
4903 dsi_opp_table: opp-table {
4904 compatible = "operating-points-v2";
4906 opp-187500000 {
4907 opp-hz = /bits/ 64 <187500000>;
4908 required-opps = <&rpmhpd_opp_low_svs>;
4911 opp-300000000 {
4912 opp-hz = /bits/ 64 <300000000>;
4913 required-opps = <&rpmhpd_opp_svs>;
4916 opp-358000000 {
4917 opp-hz = /bits/ 64 <358000000>;
4918 required-opps = <&rpmhpd_opp_svs_l1>;
4924 compatible = "qcom,dsi-phy-7nm";
4928 reg-names = "dsi_phy",
4932 #clock-cells = <1>;
4933 #phy-cells = <0>;
4937 clock-names = "iface", "ref";
4943 compatible = "qcom,sm8250-dsi-ctrl",
4944 "qcom,mdss-dsi-ctrl";
4946 reg-names = "dsi_ctrl";
4948 interrupt-parent = <&mdss>;
4957 clock-names = "byte",
4964 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
4966 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
4969 operating-points-v2 = <&dsi_opp_table>;
4970 power-domains = <&rpmhpd RPMHPD_MMCX>;
4976 #address-cells = <1>;
4977 #size-cells = <0>;
4980 #address-cells = <1>;
4981 #size-cells = <0>;
4986 remote-endpoint = <&dpu_intf2_out>;
4999 compatible = "qcom,dsi-phy-7nm";
5003 reg-names = "dsi_phy",
5007 #clock-cells = <1>;
5008 #phy-cells = <0>;
5012 clock-names = "iface", "ref";
5018 dispcc: clock-controller@af00000 {
5019 compatible = "qcom,sm8250-dispcc";
5021 power-domains = <&rpmhpd RPMHPD_MMCX>;
5022 required-opps = <&rpmhpd_opp_low_svs>;
5030 clock-names = "bi_tcxo",
5037 #clock-cells = <1>;
5038 #reset-cells = <1>;
5039 #power-domain-cells = <1>;
5042 pdc: interrupt-controller@b220000 {
5043 compatible = "qcom,sm8250-pdc", "qcom,pdc";
5045 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
5047 #interrupt-cells = <2>;
5048 interrupt-parent = <&intc>;
5049 interrupt-controller;
5052 tsens0: thermal-sensor@c263000 {
5053 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5059 interrupt-names = "uplow", "critical";
5060 #thermal-sensor-cells = <1>;
5063 tsens1: thermal-sensor@c265000 {
5064 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5070 interrupt-names = "uplow", "critical";
5071 #thermal-sensor-cells = <1>;
5074 aoss_qmp: power-management@c300000 {
5075 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp";
5077 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
5083 #clock-cells = <0>;
5087 compatible = "qcom,rpmh-stats";
5092 compatible = "qcom,spmi-pmic-arb";
5098 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5099 interrupt-names = "periph_irq";
5100 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5103 #address-cells = <2>;
5104 #size-cells = <0>;
5105 interrupt-controller;
5106 #interrupt-cells = <4>;
5110 compatible = "qcom,sm8250-pinctrl";
5114 reg-names = "west", "south", "north";
5116 gpio-controller;
5117 #gpio-cells = <2>;
5118 interrupt-controller;
5119 #interrupt-cells = <2>;
5120 gpio-ranges = <&tlmm 0 0 181>;
5121 wakeup-parent = <&pdc>;
5123 cam2_default: cam2-default-state {
5124 rst-pins {
5127 drive-strength = <2>;
5128 bias-disable;
5131 mclk-pins {
5134 drive-strength = <16>;
5135 bias-disable;
5139 cam2_suspend: cam2-suspend-state {
5140 rst-pins {
5143 drive-strength = <2>;
5144 bias-pull-down;
5145 output-low;
5148 mclk-pins {
5151 drive-strength = <2>;
5152 bias-disable;
5156 cci0_default: cci0-default-state {
5157 cci0_i2c0_default: cci0-i2c0-default-pins {
5162 bias-pull-up;
5163 drive-strength = <2>; /* 2 mA */
5166 cci0_i2c1_default: cci0-i2c1-default-pins {
5171 bias-pull-up;
5172 drive-strength = <2>; /* 2 mA */
5176 cci0_sleep: cci0-sleep-state {
5177 cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
5182 drive-strength = <2>; /* 2 mA */
5183 bias-pull-down;
5186 cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
5191 drive-strength = <2>; /* 2 mA */
5192 bias-pull-down;
5196 cci1_default: cci1-default-state {
5197 cci1_i2c0_default: cci1-i2c0-default-pins {
5202 bias-pull-up;
5203 drive-strength = <2>; /* 2 mA */
5206 cci1_i2c1_default: cci1-i2c1-default-pins {
5211 bias-pull-up;
5212 drive-strength = <2>; /* 2 mA */
5216 cci1_sleep: cci1-sleep-state {
5217 cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
5222 bias-pull-down;
5223 drive-strength = <2>; /* 2 mA */
5226 cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
5231 bias-pull-down;
5232 drive-strength = <2>; /* 2 mA */
5236 pri_mi2s_active: pri-mi2s-active-state {
5237 sclk-pins {
5240 drive-strength = <8>;
5241 bias-disable;
5244 ws-pins {
5247 drive-strength = <8>;
5248 output-high;
5251 data0-pins {
5254 drive-strength = <8>;
5255 bias-disable;
5256 output-high;
5259 data1-pins {
5262 drive-strength = <8>;
5263 output-high;
5267 qup_i2c0_default: qup-i2c0-default-state {
5270 drive-strength = <2>;
5271 bias-disable;
5274 qup_i2c1_default: qup-i2c1-default-state {
5277 drive-strength = <2>;
5278 bias-disable;
5281 qup_i2c2_default: qup-i2c2-default-state {
5284 drive-strength = <2>;
5285 bias-disable;
5288 qup_i2c3_default: qup-i2c3-default-state {
5291 drive-strength = <2>;
5292 bias-disable;
5295 qup_i2c4_default: qup-i2c4-default-state {
5298 drive-strength = <2>;
5299 bias-disable;
5302 qup_i2c5_default: qup-i2c5-default-state {
5305 drive-strength = <2>;
5306 bias-disable;
5309 qup_i2c6_default: qup-i2c6-default-state {
5312 drive-strength = <2>;
5313 bias-disable;
5316 qup_i2c7_default: qup-i2c7-default-state {
5319 drive-strength = <2>;
5320 bias-disable;
5323 qup_i2c8_default: qup-i2c8-default-state {
5326 drive-strength = <2>;
5327 bias-disable;
5330 qup_i2c9_default: qup-i2c9-default-state {
5333 drive-strength = <2>;
5334 bias-disable;
5337 qup_i2c10_default: qup-i2c10-default-state {
5340 drive-strength = <2>;
5341 bias-disable;
5344 qup_i2c11_default: qup-i2c11-default-state {
5347 drive-strength = <2>;
5348 bias-disable;
5351 qup_i2c12_default: qup-i2c12-default-state {
5354 drive-strength = <2>;
5355 bias-disable;
5358 qup_i2c13_default: qup-i2c13-default-state {
5361 drive-strength = <2>;
5362 bias-disable;
5365 qup_i2c14_default: qup-i2c14-default-state {
5368 drive-strength = <2>;
5369 bias-disable;
5372 qup_i2c15_default: qup-i2c15-default-state {
5375 drive-strength = <2>;
5376 bias-disable;
5379 qup_i2c16_default: qup-i2c16-default-state {
5382 drive-strength = <2>;
5383 bias-disable;
5386 qup_i2c17_default: qup-i2c17-default-state {
5389 drive-strength = <2>;
5390 bias-disable;
5393 qup_i2c18_default: qup-i2c18-default-state {
5396 drive-strength = <2>;
5397 bias-disable;
5400 qup_i2c19_default: qup-i2c19-default-state {
5403 drive-strength = <2>;
5404 bias-disable;
5407 qup_spi0_cs: qup-spi0-cs-state {
5412 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
5417 qup_spi0_data_clk: qup-spi0-data-clk-state {
5423 qup_spi1_cs: qup-spi1-cs-state {
5428 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
5433 qup_spi1_data_clk: qup-spi1-data-clk-state {
5439 qup_spi2_cs: qup-spi2-cs-state {
5444 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
5449 qup_spi2_data_clk: qup-spi2-data-clk-state {
5455 qup_spi3_cs: qup-spi3-cs-state {
5460 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
5465 qup_spi3_data_clk: qup-spi3-data-clk-state {
5471 qup_spi4_cs: qup-spi4-cs-state {
5476 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
5481 qup_spi4_data_clk: qup-spi4-data-clk-state {
5487 qup_spi5_cs: qup-spi5-cs-state {
5492 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
5497 qup_spi5_data_clk: qup-spi5-data-clk-state {
5503 qup_spi6_cs: qup-spi6-cs-state {
5508 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
5513 qup_spi6_data_clk: qup-spi6-data-clk-state {
5519 qup_spi7_cs: qup-spi7-cs-state {
5524 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
5529 qup_spi7_data_clk: qup-spi7-data-clk-state {
5535 qup_spi8_cs: qup-spi8-cs-state {
5540 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
5545 qup_spi8_data_clk: qup-spi8-data-clk-state {
5551 qup_spi9_cs: qup-spi9-cs-state {
5556 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
5561 qup_spi9_data_clk: qup-spi9-data-clk-state {
5567 qup_spi10_cs: qup-spi10-cs-state {
5572 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
5577 qup_spi10_data_clk: qup-spi10-data-clk-state {
5583 qup_spi11_cs: qup-spi11-cs-state {
5588 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
5593 qup_spi11_data_clk: qup-spi11-data-clk-state {
5599 qup_spi12_cs: qup-spi12-cs-state {
5604 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
5609 qup_spi12_data_clk: qup-spi12-data-clk-state {
5615 qup_spi13_cs: qup-spi13-cs-state {
5620 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
5625 qup_spi13_data_clk: qup-spi13-data-clk-state {
5631 qup_spi14_cs: qup-spi14-cs-state {
5636 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
5641 qup_spi14_data_clk: qup-spi14-data-clk-state {
5647 qup_spi15_cs: qup-spi15-cs-state {
5652 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
5657 qup_spi15_data_clk: qup-spi15-data-clk-state {
5663 qup_spi16_cs: qup-spi16-cs-state {
5668 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state {
5673 qup_spi16_data_clk: qup-spi16-data-clk-state {
5679 qup_spi17_cs: qup-spi17-cs-state {
5684 qup_spi17_cs_gpio: qup-spi17-cs-gpio-state {
5689 qup_spi17_data_clk: qup-spi17-data-clk-state {
5695 qup_spi18_cs: qup-spi18-cs-state {
5700 qup_spi18_cs_gpio: qup-spi18-cs-gpio-state {
5705 qup_spi18_data_clk: qup-spi18-data-clk-state {
5711 qup_spi19_cs: qup-spi19-cs-state {
5716 qup_spi19_cs_gpio: qup-spi19-cs-gpio-state {
5721 qup_spi19_data_clk: qup-spi19-data-clk-state {
5727 qup_uart2_default: qup-uart2-default-state {
5732 qup_uart6_default: qup-uart6-default-state {
5737 qup_uart12_default: qup-uart12-default-state {
5742 qup_uart17_default: qup-uart17-default-state {
5747 qup_uart18_default: qup-uart18-default-state {
5752 tert_mi2s_active: tert-mi2s-active-state {
5753 sck-pins {
5756 drive-strength = <8>;
5757 bias-disable;
5760 data0-pins {
5763 drive-strength = <8>;
5764 bias-disable;
5765 output-high;
5768 ws-pins {
5771 drive-strength = <8>;
5772 output-high;
5776 sdc2_sleep_state: sdc2-sleep-state {
5777 clk-pins {
5779 drive-strength = <2>;
5780 bias-disable;
5783 cmd-pins {
5785 drive-strength = <2>;
5786 bias-pull-up;
5789 data-pins {
5791 drive-strength = <2>;
5792 bias-pull-up;
5796 pcie0_default_state: pcie0-default-state {
5797 perst-pins {
5800 drive-strength = <2>;
5801 bias-pull-down;
5804 clkreq-pins {
5807 drive-strength = <2>;
5808 bias-pull-up;
5811 wake-pins {
5814 drive-strength = <2>;
5815 bias-pull-up;
5819 pcie1_default_state: pcie1-default-state {
5820 perst-pins {
5823 drive-strength = <2>;
5824 bias-pull-down;
5827 clkreq-pins {
5830 drive-strength = <2>;
5831 bias-pull-up;
5834 wake-pins {
5837 drive-strength = <2>;
5838 bias-pull-up;
5842 pcie2_default_state: pcie2-default-state {
5843 perst-pins {
5846 drive-strength = <2>;
5847 bias-pull-down;
5850 clkreq-pins {
5853 drive-strength = <2>;
5854 bias-pull-up;
5857 wake-pins {
5860 drive-strength = <2>;
5861 bias-pull-up;
5867 compatible = "qcom,sm8250-smmu-500", "qcom,smmu-500", "arm,mmu-500";
5869 #iommu-cells = <2>;
5870 #global-interrupts = <2>;
5969 dma-coherent;
5973 compatible = "qcom,sm8250-adsp-pas";
5976 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
5981 interrupt-names = "wdog", "fatal", "ready",
5982 "handover", "stop-ack";
5985 clock-names = "xo";
5987 power-domains = <&rpmhpd RPMHPD_LCX>,
5989 power-domain-names = "lcx", "lmx";
5991 memory-region = <&adsp_mem>;
5995 qcom,smem-states = <&smp2p_adsp_out 0>;
5996 qcom,smem-state-names = "stop";
6000 glink-edge {
6001 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
6008 qcom,remote-pid = <2>;
6011 compatible = "qcom,apr-v2";
6012 qcom,glink-channels = "apr_audio_svc";
6014 #address-cells = <1>;
6015 #size-cells = <0>;
6020 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6026 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6028 compatible = "qcom,q6afe-dais";
6029 #address-cells = <1>;
6030 #size-cells = <0>;
6031 #sound-dai-cells = <1>;
6034 q6afecc: clock-controller {
6035 compatible = "qcom,q6afe-clocks";
6036 #clock-cells = <2>;
6043 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6045 compatible = "qcom,q6asm-dais";
6046 #address-cells = <1>;
6047 #size-cells = <0>;
6048 #sound-dai-cells = <1>;
6056 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6058 compatible = "qcom,q6adm-routing";
6059 #sound-dai-cells = <0>;
6066 qcom,glink-channels = "fastrpcglink-apps-dsp";
6068 qcom,non-secure-domain;
6069 #address-cells = <1>;
6070 #size-cells = <0>;
6072 compute-cb@3 {
6073 compatible = "qcom,fastrpc-compute-cb";
6078 compute-cb@4 {
6079 compatible = "qcom,fastrpc-compute-cb";
6084 compute-cb@5 {
6085 compatible = "qcom,fastrpc-compute-cb";
6093 intc: interrupt-controller@17a00000 {
6094 compatible = "arm,gic-v3";
6095 #interrupt-cells = <3>;
6096 interrupt-controller;
6103 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
6110 #address-cells = <1>;
6111 #size-cells = <1>;
6113 compatible = "arm,armv7-timer-mem";
6115 clock-frequency = <19200000>;
6118 frame-number = <0>;
6126 frame-number = <1>;
6133 frame-number = <2>;
6140 frame-number = <3>;
6147 frame-number = <4>;
6154 frame-number = <5>;
6161 frame-number = <6>;
6170 compatible = "qcom,rpmh-rsc";
6174 reg-names = "drv-0", "drv-1", "drv-2";
6178 qcom,tcs-offset = <0xd00>;
6179 qcom,drv-id = <2>;
6180 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
6182 power-domains = <&cluster_pd>;
6184 rpmhcc: clock-controller {
6185 compatible = "qcom,sm8250-rpmh-clk";
6186 #clock-cells = <1>;
6187 clock-names = "xo";
6191 rpmhpd: power-controller {
6192 compatible = "qcom,sm8250-rpmhpd";
6193 #power-domain-cells = <1>;
6194 operating-points-v2 = <&rpmhpd_opp_table>;
6196 rpmhpd_opp_table: opp-table {
6197 compatible = "operating-points-v2";
6200 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
6204 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
6208 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
6212 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
6216 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
6220 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
6224 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
6228 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
6232 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
6236 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
6241 apps_bcm_voter: bcm-voter {
6242 compatible = "qcom,bcm-voter";
6247 compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3";
6251 clock-names = "xo", "alternate";
6253 #interconnect-cells = <1>;
6257 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
6261 reg-names = "freq-domain0", "freq-domain1",
6262 "freq-domain2";
6265 clock-names = "xo", "alternate";
6269 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
6270 #freq-domain-cells = <1>;
6271 #clock-cells = <1>;
6279 compatible = "arm,armv8-timer";
6290 thermal-zones {
6291 cpu0-thermal {
6292 polling-delay-passive = <250>;
6294 thermal-sensors = <&tsens0 1>;
6297 cpu0_alert0: trip-point0 {
6303 cpu0_alert1: trip-point1 {
6309 cpu0_crit: cpu-crit {
6316 cooling-maps {
6319 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6326 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6334 cpu1-thermal {
6335 polling-delay-passive = <250>;
6337 thermal-sensors = <&tsens0 2>;
6340 cpu1_alert0: trip-point0 {
6346 cpu1_alert1: trip-point1 {
6352 cpu1_crit: cpu-crit {
6359 cooling-maps {
6362 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6369 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6377 cpu2-thermal {
6378 polling-delay-passive = <250>;
6380 thermal-sensors = <&tsens0 3>;
6383 cpu2_alert0: trip-point0 {
6389 cpu2_alert1: trip-point1 {
6395 cpu2_crit: cpu-crit {
6402 cooling-maps {
6405 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6412 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6420 cpu3-thermal {
6421 polling-delay-passive = <250>;
6423 thermal-sensors = <&tsens0 4>;
6426 cpu3_alert0: trip-point0 {
6432 cpu3_alert1: trip-point1 {
6438 cpu3_crit: cpu-crit {
6445 cooling-maps {
6448 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6455 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6463 cpu4-top-thermal {
6464 polling-delay-passive = <250>;
6466 thermal-sensors = <&tsens0 7>;
6469 cpu4_top_alert0: trip-point0 {
6475 cpu4_top_alert1: trip-point1 {
6481 cpu4_top_crit: cpu-crit {
6488 cooling-maps {
6491 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6498 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6506 cpu5-top-thermal {
6507 polling-delay-passive = <250>;
6509 thermal-sensors = <&tsens0 8>;
6512 cpu5_top_alert0: trip-point0 {
6518 cpu5_top_alert1: trip-point1 {
6524 cpu5_top_crit: cpu-crit {
6531 cooling-maps {
6534 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6541 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6549 cpu6-top-thermal {
6550 polling-delay-passive = <250>;
6552 thermal-sensors = <&tsens0 9>;
6555 cpu6_top_alert0: trip-point0 {
6561 cpu6_top_alert1: trip-point1 {
6567 cpu6_top_crit: cpu-crit {
6574 cooling-maps {
6577 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6584 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6592 cpu7-top-thermal {
6593 polling-delay-passive = <250>;
6595 thermal-sensors = <&tsens0 10>;
6598 cpu7_top_alert0: trip-point0 {
6604 cpu7_top_alert1: trip-point1 {
6610 cpu7_top_crit: cpu-crit {
6617 cooling-maps {
6620 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6627 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6635 cpu4-bottom-thermal {
6636 polling-delay-passive = <250>;
6638 thermal-sensors = <&tsens0 11>;
6641 cpu4_bottom_alert0: trip-point0 {
6647 cpu4_bottom_alert1: trip-point1 {
6653 cpu4_bottom_crit: cpu-crit {
6660 cooling-maps {
6663 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6670 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6678 cpu5-bottom-thermal {
6679 polling-delay-passive = <250>;
6681 thermal-sensors = <&tsens0 12>;
6684 cpu5_bottom_alert0: trip-point0 {
6690 cpu5_bottom_alert1: trip-point1 {
6696 cpu5_bottom_crit: cpu-crit {
6703 cooling-maps {
6706 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6713 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6721 cpu6-bottom-thermal {
6722 polling-delay-passive = <250>;
6724 thermal-sensors = <&tsens0 13>;
6727 cpu6_bottom_alert0: trip-point0 {
6733 cpu6_bottom_alert1: trip-point1 {
6739 cpu6_bottom_crit: cpu-crit {
6746 cooling-maps {
6749 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6756 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6764 cpu7-bottom-thermal {
6765 polling-delay-passive = <250>;
6767 thermal-sensors = <&tsens0 14>;
6770 cpu7_bottom_alert0: trip-point0 {
6776 cpu7_bottom_alert1: trip-point1 {
6782 cpu7_bottom_crit: cpu-crit {
6789 cooling-maps {
6792 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6799 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6807 aoss0-thermal {
6808 polling-delay-passive = <250>;
6810 thermal-sensors = <&tsens0 0>;
6813 aoss0_alert0: trip-point0 {
6821 cluster0-thermal {
6822 polling-delay-passive = <250>;
6824 thermal-sensors = <&tsens0 5>;
6827 cluster0_alert0: trip-point0 {
6832 cluster0_crit: cluster0-crit {
6840 cluster1-thermal {
6841 polling-delay-passive = <250>;
6843 thermal-sensors = <&tsens0 6>;
6846 cluster1_alert0: trip-point0 {
6851 cluster1_crit: cluster1-crit {
6859 gpu-top-thermal {
6860 polling-delay-passive = <250>;
6862 thermal-sensors = <&tsens0 15>;
6864 cooling-maps {
6867 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6872 gpu_top_alert0: trip-point0 {
6878 trip-point1 {
6884 trip-point2 {
6892 aoss1-thermal {
6893 polling-delay-passive = <250>;
6895 thermal-sensors = <&tsens1 0>;
6898 aoss1_alert0: trip-point0 {
6906 wlan-thermal {
6907 polling-delay-passive = <250>;
6909 thermal-sensors = <&tsens1 1>;
6912 wlan_alert0: trip-point0 {
6920 video-thermal {
6921 polling-delay-passive = <250>;
6923 thermal-sensors = <&tsens1 2>;
6926 video_alert0: trip-point0 {
6934 mem-thermal {
6935 polling-delay-passive = <250>;
6937 thermal-sensors = <&tsens1 3>;
6940 mem_alert0: trip-point0 {
6948 q6-hvx-thermal {
6949 polling-delay-passive = <250>;
6951 thermal-sensors = <&tsens1 4>;
6954 q6_hvx_alert0: trip-point0 {
6962 camera-thermal {
6963 polling-delay-passive = <250>;
6965 thermal-sensors = <&tsens1 5>;
6968 camera_alert0: trip-point0 {
6976 compute-thermal {
6977 polling-delay-passive = <250>;
6979 thermal-sensors = <&tsens1 6>;
6982 compute_alert0: trip-point0 {
6990 npu-thermal {
6991 polling-delay-passive = <250>;
6993 thermal-sensors = <&tsens1 7>;
6996 npu_alert0: trip-point0 {
7004 gpu-bottom-thermal {
7005 polling-delay-passive = <250>;
7007 thermal-sensors = <&tsens1 8>;
7009 cooling-maps {
7012 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
7017 gpu_bottom_alert0: trip-point0 {
7023 trip-point1 {
7029 trip-point2 {