Lines Matching +full:dsp +full:- +full:gpio4
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sm8250.h>
15 #include <dt-bindings/mailbox/qcom-ipcc.h>
16 #include <dt-bindings/phy/phy-qcom-qmp.h>
17 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/soc/qcom,apr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6afe.h>
22 #include <dt-bindings/thermal/thermal.h>
23 #include <dt-bindings/clock/qcom,camcc-sm8250.h>
24 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
27 interrupt-parent = <&intc>;
29 #address-cells = <2>;
30 #size-cells = <2>;
78 xo_board: xo-board {
79 compatible = "fixed-clock";
80 #clock-cells = <0>;
81 clock-frequency = <38400000>;
82 clock-output-names = "xo_board";
85 sleep_clk: sleep-clk {
86 compatible = "fixed-clock";
87 clock-frequency = <32768>;
88 #clock-cells = <0>;
93 #address-cells = <2>;
94 #size-cells = <0>;
101 enable-method = "psci";
102 capacity-dmips-mhz = <448>;
103 dynamic-power-coefficient = <105>;
104 next-level-cache = <&l2_0>;
105 power-domains = <&cpu_pd0>;
106 power-domain-names = "psci";
107 qcom,freq-domain = <&cpufreq_hw 0>;
108 operating-points-v2 = <&cpu0_opp_table>;
111 #cooling-cells = <2>;
112 l2_0: l2-cache {
114 cache-level = <2>;
115 cache-size = <0x20000>;
116 cache-unified;
117 next-level-cache = <&l3_0>;
118 l3_0: l3-cache {
120 cache-level = <3>;
121 cache-size = <0x400000>;
122 cache-unified;
132 enable-method = "psci";
133 capacity-dmips-mhz = <448>;
134 dynamic-power-coefficient = <105>;
135 next-level-cache = <&l2_100>;
136 power-domains = <&cpu_pd1>;
137 power-domain-names = "psci";
138 qcom,freq-domain = <&cpufreq_hw 0>;
139 operating-points-v2 = <&cpu0_opp_table>;
142 #cooling-cells = <2>;
143 l2_100: l2-cache {
145 cache-level = <2>;
146 cache-size = <0x20000>;
147 cache-unified;
148 next-level-cache = <&l3_0>;
157 enable-method = "psci";
158 capacity-dmips-mhz = <448>;
159 dynamic-power-coefficient = <105>;
160 next-level-cache = <&l2_200>;
161 power-domains = <&cpu_pd2>;
162 power-domain-names = "psci";
163 qcom,freq-domain = <&cpufreq_hw 0>;
164 operating-points-v2 = <&cpu0_opp_table>;
167 #cooling-cells = <2>;
168 l2_200: l2-cache {
170 cache-level = <2>;
171 cache-size = <0x20000>;
172 cache-unified;
173 next-level-cache = <&l3_0>;
182 enable-method = "psci";
183 capacity-dmips-mhz = <448>;
184 dynamic-power-coefficient = <105>;
185 next-level-cache = <&l2_300>;
186 power-domains = <&cpu_pd3>;
187 power-domain-names = "psci";
188 qcom,freq-domain = <&cpufreq_hw 0>;
189 operating-points-v2 = <&cpu0_opp_table>;
192 #cooling-cells = <2>;
193 l2_300: l2-cache {
195 cache-level = <2>;
196 cache-size = <0x20000>;
197 cache-unified;
198 next-level-cache = <&l3_0>;
207 enable-method = "psci";
208 capacity-dmips-mhz = <1024>;
209 dynamic-power-coefficient = <379>;
210 next-level-cache = <&l2_400>;
211 power-domains = <&cpu_pd4>;
212 power-domain-names = "psci";
213 qcom,freq-domain = <&cpufreq_hw 1>;
214 operating-points-v2 = <&cpu4_opp_table>;
217 #cooling-cells = <2>;
218 l2_400: l2-cache {
220 cache-level = <2>;
221 cache-size = <0x40000>;
222 cache-unified;
223 next-level-cache = <&l3_0>;
232 enable-method = "psci";
233 capacity-dmips-mhz = <1024>;
234 dynamic-power-coefficient = <379>;
235 next-level-cache = <&l2_500>;
236 power-domains = <&cpu_pd5>;
237 power-domain-names = "psci";
238 qcom,freq-domain = <&cpufreq_hw 1>;
239 operating-points-v2 = <&cpu4_opp_table>;
242 #cooling-cells = <2>;
243 l2_500: l2-cache {
245 cache-level = <2>;
246 cache-size = <0x40000>;
247 cache-unified;
248 next-level-cache = <&l3_0>;
257 enable-method = "psci";
258 capacity-dmips-mhz = <1024>;
259 dynamic-power-coefficient = <379>;
260 next-level-cache = <&l2_600>;
261 power-domains = <&cpu_pd6>;
262 power-domain-names = "psci";
263 qcom,freq-domain = <&cpufreq_hw 1>;
264 operating-points-v2 = <&cpu4_opp_table>;
267 #cooling-cells = <2>;
268 l2_600: l2-cache {
270 cache-level = <2>;
271 cache-size = <0x40000>;
272 cache-unified;
273 next-level-cache = <&l3_0>;
282 enable-method = "psci";
283 capacity-dmips-mhz = <1024>;
284 dynamic-power-coefficient = <444>;
285 next-level-cache = <&l2_700>;
286 power-domains = <&cpu_pd7>;
287 power-domain-names = "psci";
288 qcom,freq-domain = <&cpufreq_hw 2>;
289 operating-points-v2 = <&cpu7_opp_table>;
292 #cooling-cells = <2>;
293 l2_700: l2-cache {
295 cache-level = <2>;
296 cache-size = <0x80000>;
297 cache-unified;
298 next-level-cache = <&l3_0>;
302 cpu-map {
338 idle-states {
339 entry-method = "psci";
341 little_cpu_sleep_0: cpu-sleep-0-0 {
342 compatible = "arm,idle-state";
343 idle-state-name = "silver-rail-power-collapse";
344 arm,psci-suspend-param = <0x40000004>;
345 entry-latency-us = <360>;
346 exit-latency-us = <531>;
347 min-residency-us = <3934>;
348 local-timer-stop;
351 big_cpu_sleep_0: cpu-sleep-1-0 {
352 compatible = "arm,idle-state";
353 idle-state-name = "gold-rail-power-collapse";
354 arm,psci-suspend-param = <0x40000004>;
355 entry-latency-us = <702>;
356 exit-latency-us = <1061>;
357 min-residency-us = <4488>;
358 local-timer-stop;
362 domain-idle-states {
363 cluster_sleep_0: cluster-sleep-0 {
364 compatible = "domain-idle-state";
365 arm,psci-suspend-param = <0x4100c244>;
366 entry-latency-us = <3264>;
367 exit-latency-us = <6562>;
368 min-residency-us = <9987>;
373 qup_virt: interconnect-qup-virt {
374 compatible = "qcom,sm8250-qup-virt";
375 #interconnect-cells = <2>;
376 qcom,bcm-voters = <&apps_bcm_voter>;
379 cpu0_opp_table: opp-table-cpu0 {
380 compatible = "operating-points-v2";
381 opp-shared;
383 cpu0_opp1: opp-300000000 {
384 opp-hz = /bits/ 64 <300000000>;
385 opp-peak-kBps = <800000 9600000>;
388 cpu0_opp2: opp-403200000 {
389 opp-hz = /bits/ 64 <403200000>;
390 opp-peak-kBps = <800000 9600000>;
393 cpu0_opp3: opp-518400000 {
394 opp-hz = /bits/ 64 <518400000>;
395 opp-peak-kBps = <800000 16588800>;
398 cpu0_opp4: opp-614400000 {
399 opp-hz = /bits/ 64 <614400000>;
400 opp-peak-kBps = <800000 16588800>;
403 cpu0_opp5: opp-691200000 {
404 opp-hz = /bits/ 64 <691200000>;
405 opp-peak-kBps = <800000 19660800>;
408 cpu0_opp6: opp-787200000 {
409 opp-hz = /bits/ 64 <787200000>;
410 opp-peak-kBps = <1804000 19660800>;
413 cpu0_opp7: opp-883200000 {
414 opp-hz = /bits/ 64 <883200000>;
415 opp-peak-kBps = <1804000 23347200>;
418 cpu0_opp8: opp-979200000 {
419 opp-hz = /bits/ 64 <979200000>;
420 opp-peak-kBps = <1804000 26419200>;
423 cpu0_opp9: opp-1075200000 {
424 opp-hz = /bits/ 64 <1075200000>;
425 opp-peak-kBps = <1804000 29491200>;
428 cpu0_opp10: opp-1171200000 {
429 opp-hz = /bits/ 64 <1171200000>;
430 opp-peak-kBps = <1804000 32563200>;
433 cpu0_opp11: opp-1248000000 {
434 opp-hz = /bits/ 64 <1248000000>;
435 opp-peak-kBps = <1804000 36249600>;
438 cpu0_opp12: opp-1344000000 {
439 opp-hz = /bits/ 64 <1344000000>;
440 opp-peak-kBps = <2188000 36249600>;
443 cpu0_opp13: opp-1420800000 {
444 opp-hz = /bits/ 64 <1420800000>;
445 opp-peak-kBps = <2188000 39321600>;
448 cpu0_opp14: opp-1516800000 {
449 opp-hz = /bits/ 64 <1516800000>;
450 opp-peak-kBps = <3072000 42393600>;
453 cpu0_opp15: opp-1612800000 {
454 opp-hz = /bits/ 64 <1612800000>;
455 opp-peak-kBps = <3072000 42393600>;
458 cpu0_opp16: opp-1708800000 {
459 opp-hz = /bits/ 64 <1708800000>;
460 opp-peak-kBps = <4068000 42393600>;
463 cpu0_opp17: opp-1804800000 {
464 opp-hz = /bits/ 64 <1804800000>;
465 opp-peak-kBps = <4068000 42393600>;
469 cpu4_opp_table: opp-table-cpu4 {
470 compatible = "operating-points-v2";
471 opp-shared;
473 cpu4_opp1: opp-710400000 {
474 opp-hz = /bits/ 64 <710400000>;
475 opp-peak-kBps = <1804000 19660800>;
478 cpu4_opp2: opp-825600000 {
479 opp-hz = /bits/ 64 <825600000>;
480 opp-peak-kBps = <2188000 23347200>;
483 cpu4_opp3: opp-940800000 {
484 opp-hz = /bits/ 64 <940800000>;
485 opp-peak-kBps = <2188000 26419200>;
488 cpu4_opp4: opp-1056000000 {
489 opp-hz = /bits/ 64 <1056000000>;
490 opp-peak-kBps = <3072000 26419200>;
493 cpu4_opp5: opp-1171200000 {
494 opp-hz = /bits/ 64 <1171200000>;
495 opp-peak-kBps = <3072000 29491200>;
498 cpu4_opp6: opp-1286400000 {
499 opp-hz = /bits/ 64 <1286400000>;
500 opp-peak-kBps = <4068000 29491200>;
503 cpu4_opp7: opp-1382400000 {
504 opp-hz = /bits/ 64 <1382400000>;
505 opp-peak-kBps = <4068000 32563200>;
508 cpu4_opp8: opp-1478400000 {
509 opp-hz = /bits/ 64 <1478400000>;
510 opp-peak-kBps = <4068000 32563200>;
513 cpu4_opp9: opp-1574400000 {
514 opp-hz = /bits/ 64 <1574400000>;
515 opp-peak-kBps = <5412000 39321600>;
518 cpu4_opp10: opp-1670400000 {
519 opp-hz = /bits/ 64 <1670400000>;
520 opp-peak-kBps = <5412000 42393600>;
523 cpu4_opp11: opp-1766400000 {
524 opp-hz = /bits/ 64 <1766400000>;
525 opp-peak-kBps = <5412000 45465600>;
528 cpu4_opp12: opp-1862400000 {
529 opp-hz = /bits/ 64 <1862400000>;
530 opp-peak-kBps = <6220000 45465600>;
533 cpu4_opp13: opp-1958400000 {
534 opp-hz = /bits/ 64 <1958400000>;
535 opp-peak-kBps = <6220000 48537600>;
538 cpu4_opp14: opp-2054400000 {
539 opp-hz = /bits/ 64 <2054400000>;
540 opp-peak-kBps = <7216000 48537600>;
543 cpu4_opp15: opp-2150400000 {
544 opp-hz = /bits/ 64 <2150400000>;
545 opp-peak-kBps = <7216000 51609600>;
548 cpu4_opp16: opp-2246400000 {
549 opp-hz = /bits/ 64 <2246400000>;
550 opp-peak-kBps = <7216000 51609600>;
553 cpu4_opp17: opp-2342400000 {
554 opp-hz = /bits/ 64 <2342400000>;
555 opp-peak-kBps = <8368000 51609600>;
558 cpu4_opp18: opp-2419200000 {
559 opp-hz = /bits/ 64 <2419200000>;
560 opp-peak-kBps = <8368000 51609600>;
564 cpu7_opp_table: opp-table-cpu7 {
565 compatible = "operating-points-v2";
566 opp-shared;
568 cpu7_opp1: opp-844800000 {
569 opp-hz = /bits/ 64 <844800000>;
570 opp-peak-kBps = <2188000 19660800>;
573 cpu7_opp2: opp-960000000 {
574 opp-hz = /bits/ 64 <960000000>;
575 opp-peak-kBps = <2188000 26419200>;
578 cpu7_opp3: opp-1075200000 {
579 opp-hz = /bits/ 64 <1075200000>;
580 opp-peak-kBps = <3072000 26419200>;
583 cpu7_opp4: opp-1190400000 {
584 opp-hz = /bits/ 64 <1190400000>;
585 opp-peak-kBps = <3072000 29491200>;
588 cpu7_opp5: opp-1305600000 {
589 opp-hz = /bits/ 64 <1305600000>;
590 opp-peak-kBps = <4068000 32563200>;
593 cpu7_opp6: opp-1401600000 {
594 opp-hz = /bits/ 64 <1401600000>;
595 opp-peak-kBps = <4068000 32563200>;
598 cpu7_opp7: opp-1516800000 {
599 opp-hz = /bits/ 64 <1516800000>;
600 opp-peak-kBps = <4068000 36249600>;
603 cpu7_opp8: opp-1632000000 {
604 opp-hz = /bits/ 64 <1632000000>;
605 opp-peak-kBps = <5412000 39321600>;
608 cpu7_opp9: opp-1747200000 {
609 opp-hz = /bits/ 64 <1708800000>;
610 opp-peak-kBps = <5412000 42393600>;
613 cpu7_opp10: opp-1862400000 {
614 opp-hz = /bits/ 64 <1862400000>;
615 opp-peak-kBps = <6220000 45465600>;
618 cpu7_opp11: opp-1977600000 {
619 opp-hz = /bits/ 64 <1977600000>;
620 opp-peak-kBps = <6220000 48537600>;
623 cpu7_opp12: opp-2073600000 {
624 opp-hz = /bits/ 64 <2073600000>;
625 opp-peak-kBps = <7216000 48537600>;
628 cpu7_opp13: opp-2169600000 {
629 opp-hz = /bits/ 64 <2169600000>;
630 opp-peak-kBps = <7216000 51609600>;
633 cpu7_opp14: opp-2265600000 {
634 opp-hz = /bits/ 64 <2265600000>;
635 opp-peak-kBps = <7216000 51609600>;
638 cpu7_opp15: opp-2361600000 {
639 opp-hz = /bits/ 64 <2361600000>;
640 opp-peak-kBps = <8368000 51609600>;
643 cpu7_opp16: opp-2457600000 {
644 opp-hz = /bits/ 64 <2457600000>;
645 opp-peak-kBps = <8368000 51609600>;
648 cpu7_opp17: opp-2553600000 {
649 opp-hz = /bits/ 64 <2553600000>;
650 opp-peak-kBps = <8368000 51609600>;
653 cpu7_opp18: opp-2649600000 {
654 opp-hz = /bits/ 64 <2649600000>;
655 opp-peak-kBps = <8368000 51609600>;
658 cpu7_opp19: opp-2745600000 {
659 opp-hz = /bits/ 64 <2745600000>;
660 opp-peak-kBps = <8368000 51609600>;
663 cpu7_opp20: opp-2841600000 {
664 opp-hz = /bits/ 64 <2841600000>;
665 opp-peak-kBps = <8368000 51609600>;
671 compatible = "qcom,scm-sm8250", "qcom,scm";
672 qcom,dload-mode = <&tcsr 0x13000>;
673 #reset-cells = <1>;
684 compatible = "arm,armv8-pmuv3";
689 compatible = "arm,psci-1.0";
692 cpu_pd0: power-domain-cpu0 {
693 #power-domain-cells = <0>;
694 power-domains = <&cluster_pd>;
695 domain-idle-states = <&little_cpu_sleep_0>;
698 cpu_pd1: power-domain-cpu1 {
699 #power-domain-cells = <0>;
700 power-domains = <&cluster_pd>;
701 domain-idle-states = <&little_cpu_sleep_0>;
704 cpu_pd2: power-domain-cpu2 {
705 #power-domain-cells = <0>;
706 power-domains = <&cluster_pd>;
707 domain-idle-states = <&little_cpu_sleep_0>;
710 cpu_pd3: power-domain-cpu3 {
711 #power-domain-cells = <0>;
712 power-domains = <&cluster_pd>;
713 domain-idle-states = <&little_cpu_sleep_0>;
716 cpu_pd4: power-domain-cpu4 {
717 #power-domain-cells = <0>;
718 power-domains = <&cluster_pd>;
719 domain-idle-states = <&big_cpu_sleep_0>;
722 cpu_pd5: power-domain-cpu5 {
723 #power-domain-cells = <0>;
724 power-domains = <&cluster_pd>;
725 domain-idle-states = <&big_cpu_sleep_0>;
728 cpu_pd6: power-domain-cpu6 {
729 #power-domain-cells = <0>;
730 power-domains = <&cluster_pd>;
731 domain-idle-states = <&big_cpu_sleep_0>;
734 cpu_pd7: power-domain-cpu7 {
735 #power-domain-cells = <0>;
736 power-domains = <&cluster_pd>;
737 domain-idle-states = <&big_cpu_sleep_0>;
740 cluster_pd: power-domain-cpu-cluster0 {
741 #power-domain-cells = <0>;
742 domain-idle-states = <&cluster_sleep_0>;
746 qup_opp_table: opp-table-qup {
747 compatible = "operating-points-v2";
749 opp-50000000 {
750 opp-hz = /bits/ 64 <50000000>;
751 required-opps = <&rpmhpd_opp_min_svs>;
754 opp-75000000 {
755 opp-hz = /bits/ 64 <75000000>;
756 required-opps = <&rpmhpd_opp_low_svs>;
759 opp-120000000 {
760 opp-hz = /bits/ 64 <120000000>;
761 required-opps = <&rpmhpd_opp_svs>;
765 reserved-memory {
766 #address-cells = <2>;
767 #size-cells = <2>;
772 no-map;
777 no-map;
781 compatible = "qcom,cmd-db";
783 no-map;
788 no-map;
793 no-map;
798 no-map;
803 no-map;
808 no-map;
813 no-map;
818 no-map;
823 no-map;
828 no-map;
833 no-map;
838 no-map;
843 no-map;
848 no-map;
853 no-map;
858 no-map;
864 memory-region = <&smem_mem>;
868 smp2p-adsp {
871 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
877 qcom,local-pid = <0>;
878 qcom,remote-pid = <2>;
880 smp2p_adsp_out: master-kernel {
881 qcom,entry-name = "master-kernel";
882 #qcom,smem-state-cells = <1>;
885 smp2p_adsp_in: slave-kernel {
886 qcom,entry-name = "slave-kernel";
887 interrupt-controller;
888 #interrupt-cells = <2>;
892 smp2p-cdsp {
895 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
901 qcom,local-pid = <0>;
902 qcom,remote-pid = <5>;
904 smp2p_cdsp_out: master-kernel {
905 qcom,entry-name = "master-kernel";
906 #qcom,smem-state-cells = <1>;
909 smp2p_cdsp_in: slave-kernel {
910 qcom,entry-name = "slave-kernel";
911 interrupt-controller;
912 #interrupt-cells = <2>;
916 smp2p-slpi {
919 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
925 qcom,local-pid = <0>;
926 qcom,remote-pid = <3>;
928 smp2p_slpi_out: master-kernel {
929 qcom,entry-name = "master-kernel";
930 #qcom,smem-state-cells = <1>;
933 smp2p_slpi_in: slave-kernel {
934 qcom,entry-name = "slave-kernel";
935 interrupt-controller;
936 #interrupt-cells = <2>;
941 #address-cells = <2>;
942 #size-cells = <2>;
944 dma-ranges = <0 0 0 0 0x10 0>;
945 compatible = "simple-bus";
947 gcc: clock-controller@100000 {
948 compatible = "qcom,gcc-sm8250";
950 #clock-cells = <1>;
951 #reset-cells = <1>;
952 #power-domain-cells = <1>;
953 clock-names = "bi_tcxo",
962 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
965 interrupt-controller;
966 #interrupt-cells = <3>;
967 #mbox-cells = <2>;
971 compatible = "qcom,sm8250-qfprom", "qcom,qfprom";
973 #address-cells = <1>;
974 #size-cells = <1>;
976 gpu_speed_bin: gpu-speed-bin@19b {
983 compatible = "qcom,prng-ee";
986 clock-names = "core";
989 gpi_dma2: dma-controller@800000 {
990 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1002 dma-channels = <10>;
1003 dma-channel-mask = <0x3f>;
1005 #dma-cells = <3>;
1010 compatible = "qcom,geni-se-qup";
1012 clock-names = "m-ahb", "s-ahb";
1015 #address-cells = <2>;
1016 #size-cells = <2>;
1022 compatible = "qcom,geni-i2c";
1024 clock-names = "se";
1026 pinctrl-names = "default";
1027 pinctrl-0 = <&qup_i2c14_default>;
1031 dma-names = "tx", "rx";
1032 power-domains = <&rpmhpd SM8250_CX>;
1036 interconnect-names = "qup-core",
1037 "qup-config",
1038 "qup-memory";
1039 #address-cells = <1>;
1040 #size-cells = <0>;
1045 compatible = "qcom,geni-spi";
1047 clock-names = "se";
1052 dma-names = "tx", "rx";
1053 power-domains = <&rpmhpd RPMHPD_CX>;
1054 operating-points-v2 = <&qup_opp_table>;
1058 interconnect-names = "qup-core",
1059 "qup-config",
1060 "qup-memory";
1061 #address-cells = <1>;
1062 #size-cells = <0>;
1067 compatible = "qcom,geni-i2c";
1069 clock-names = "se";
1071 pinctrl-names = "default";
1072 pinctrl-0 = <&qup_i2c15_default>;
1076 dma-names = "tx", "rx";
1077 power-domains = <&rpmhpd SM8250_CX>;
1081 interconnect-names = "qup-core",
1082 "qup-config",
1083 "qup-memory";
1084 #address-cells = <1>;
1085 #size-cells = <0>;
1090 compatible = "qcom,geni-spi";
1092 clock-names = "se";
1097 dma-names = "tx", "rx";
1098 power-domains = <&rpmhpd RPMHPD_CX>;
1099 operating-points-v2 = <&qup_opp_table>;
1103 interconnect-names = "qup-core",
1104 "qup-config",
1105 "qup-memory";
1106 #address-cells = <1>;
1107 #size-cells = <0>;
1112 compatible = "qcom,geni-i2c";
1114 clock-names = "se";
1116 pinctrl-names = "default";
1117 pinctrl-0 = <&qup_i2c16_default>;
1121 dma-names = "tx", "rx";
1122 power-domains = <&rpmhpd SM8250_CX>;
1126 interconnect-names = "qup-core",
1127 "qup-config",
1128 "qup-memory";
1129 #address-cells = <1>;
1130 #size-cells = <0>;
1135 compatible = "qcom,geni-spi";
1137 clock-names = "se";
1142 dma-names = "tx", "rx";
1143 power-domains = <&rpmhpd RPMHPD_CX>;
1144 operating-points-v2 = <&qup_opp_table>;
1148 interconnect-names = "qup-core",
1149 "qup-config",
1150 "qup-memory";
1151 #address-cells = <1>;
1152 #size-cells = <0>;
1157 compatible = "qcom,geni-i2c";
1159 clock-names = "se";
1161 pinctrl-names = "default";
1162 pinctrl-0 = <&qup_i2c17_default>;
1166 dma-names = "tx", "rx";
1167 power-domains = <&rpmhpd SM8250_CX>;
1171 interconnect-names = "qup-core",
1172 "qup-config",
1173 "qup-memory";
1174 #address-cells = <1>;
1175 #size-cells = <0>;
1180 compatible = "qcom,geni-spi";
1182 clock-names = "se";
1187 dma-names = "tx", "rx";
1188 power-domains = <&rpmhpd RPMHPD_CX>;
1189 operating-points-v2 = <&qup_opp_table>;
1193 interconnect-names = "qup-core",
1194 "qup-config",
1195 "qup-memory";
1196 #address-cells = <1>;
1197 #size-cells = <0>;
1202 compatible = "qcom,geni-uart";
1204 clock-names = "se";
1206 pinctrl-names = "default";
1207 pinctrl-0 = <&qup_uart17_default>;
1209 power-domains = <&rpmhpd RPMHPD_CX>;
1210 operating-points-v2 = <&qup_opp_table>;
1213 interconnect-names = "qup-core",
1214 "qup-config";
1219 compatible = "qcom,geni-i2c";
1221 clock-names = "se";
1223 pinctrl-names = "default";
1224 pinctrl-0 = <&qup_i2c18_default>;
1228 dma-names = "tx", "rx";
1229 power-domains = <&rpmhpd SM8250_CX>;
1233 interconnect-names = "qup-core",
1234 "qup-config",
1235 "qup-memory";
1236 #address-cells = <1>;
1237 #size-cells = <0>;
1242 compatible = "qcom,geni-spi";
1244 clock-names = "se";
1249 dma-names = "tx", "rx";
1250 power-domains = <&rpmhpd RPMHPD_CX>;
1251 operating-points-v2 = <&qup_opp_table>;
1255 interconnect-names = "qup-core",
1256 "qup-config",
1257 "qup-memory";
1258 #address-cells = <1>;
1259 #size-cells = <0>;
1264 compatible = "qcom,geni-uart";
1266 clock-names = "se";
1268 pinctrl-names = "default";
1269 pinctrl-0 = <&qup_uart18_default>;
1271 power-domains = <&rpmhpd RPMHPD_CX>;
1272 operating-points-v2 = <&qup_opp_table>;
1275 interconnect-names = "qup-core",
1276 "qup-config";
1281 compatible = "qcom,geni-i2c";
1283 clock-names = "se";
1285 pinctrl-names = "default";
1286 pinctrl-0 = <&qup_i2c19_default>;
1290 dma-names = "tx", "rx";
1291 power-domains = <&rpmhpd SM8250_CX>;
1295 interconnect-names = "qup-core",
1296 "qup-config",
1297 "qup-memory";
1298 #address-cells = <1>;
1299 #size-cells = <0>;
1304 compatible = "qcom,geni-spi";
1306 clock-names = "se";
1311 dma-names = "tx", "rx";
1312 power-domains = <&rpmhpd RPMHPD_CX>;
1313 operating-points-v2 = <&qup_opp_table>;
1317 interconnect-names = "qup-core",
1318 "qup-config",
1319 "qup-memory";
1320 #address-cells = <1>;
1321 #size-cells = <0>;
1326 gpi_dma0: dma-controller@900000 {
1327 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1342 dma-channels = <15>;
1343 dma-channel-mask = <0x7ff>;
1345 #dma-cells = <3>;
1350 compatible = "qcom,geni-se-qup";
1352 clock-names = "m-ahb", "s-ahb";
1355 #address-cells = <2>;
1356 #size-cells = <2>;
1362 compatible = "qcom,geni-i2c";
1364 clock-names = "se";
1366 pinctrl-names = "default";
1367 pinctrl-0 = <&qup_i2c0_default>;
1371 dma-names = "tx", "rx";
1372 power-domains = <&rpmhpd SM8250_CX>;
1376 interconnect-names = "qup-core",
1377 "qup-config",
1378 "qup-memory";
1379 #address-cells = <1>;
1380 #size-cells = <0>;
1385 compatible = "qcom,geni-spi";
1387 clock-names = "se";
1392 dma-names = "tx", "rx";
1393 power-domains = <&rpmhpd RPMHPD_CX>;
1394 operating-points-v2 = <&qup_opp_table>;
1398 interconnect-names = "qup-core",
1399 "qup-config",
1400 "qup-memory";
1401 #address-cells = <1>;
1402 #size-cells = <0>;
1407 compatible = "qcom,geni-i2c";
1409 clock-names = "se";
1411 pinctrl-names = "default";
1412 pinctrl-0 = <&qup_i2c1_default>;
1416 dma-names = "tx", "rx";
1417 power-domains = <&rpmhpd SM8250_CX>;
1421 interconnect-names = "qup-core",
1422 "qup-config",
1423 "qup-memory";
1424 #address-cells = <1>;
1425 #size-cells = <0>;
1430 compatible = "qcom,geni-spi";
1432 clock-names = "se";
1437 dma-names = "tx", "rx";
1438 power-domains = <&rpmhpd RPMHPD_CX>;
1439 operating-points-v2 = <&qup_opp_table>;
1443 interconnect-names = "qup-core",
1444 "qup-config",
1445 "qup-memory";
1446 #address-cells = <1>;
1447 #size-cells = <0>;
1452 compatible = "qcom,geni-i2c";
1454 clock-names = "se";
1456 pinctrl-names = "default";
1457 pinctrl-0 = <&qup_i2c2_default>;
1461 dma-names = "tx", "rx";
1462 power-domains = <&rpmhpd SM8250_CX>;
1466 interconnect-names = "qup-core",
1467 "qup-config",
1468 "qup-memory";
1469 #address-cells = <1>;
1470 #size-cells = <0>;
1475 compatible = "qcom,geni-spi";
1477 clock-names = "se";
1482 dma-names = "tx", "rx";
1483 power-domains = <&rpmhpd RPMHPD_CX>;
1484 operating-points-v2 = <&qup_opp_table>;
1488 interconnect-names = "qup-core",
1489 "qup-config",
1490 "qup-memory";
1491 #address-cells = <1>;
1492 #size-cells = <0>;
1497 compatible = "qcom,geni-debug-uart";
1499 clock-names = "se";
1501 pinctrl-names = "default";
1502 pinctrl-0 = <&qup_uart2_default>;
1504 power-domains = <&rpmhpd RPMHPD_CX>;
1505 operating-points-v2 = <&qup_opp_table>;
1508 interconnect-names = "qup-core",
1509 "qup-config";
1514 compatible = "qcom,geni-i2c";
1516 clock-names = "se";
1518 pinctrl-names = "default";
1519 pinctrl-0 = <&qup_i2c3_default>;
1523 dma-names = "tx", "rx";
1524 power-domains = <&rpmhpd SM8250_CX>;
1528 interconnect-names = "qup-core",
1529 "qup-config",
1530 "qup-memory";
1531 #address-cells = <1>;
1532 #size-cells = <0>;
1537 compatible = "qcom,geni-spi";
1539 clock-names = "se";
1544 dma-names = "tx", "rx";
1545 power-domains = <&rpmhpd RPMHPD_CX>;
1546 operating-points-v2 = <&qup_opp_table>;
1550 interconnect-names = "qup-core",
1551 "qup-config",
1552 "qup-memory";
1553 #address-cells = <1>;
1554 #size-cells = <0>;
1559 compatible = "qcom,geni-i2c";
1561 clock-names = "se";
1563 pinctrl-names = "default";
1564 pinctrl-0 = <&qup_i2c4_default>;
1568 dma-names = "tx", "rx";
1569 power-domains = <&rpmhpd SM8250_CX>;
1573 interconnect-names = "qup-core",
1574 "qup-config",
1575 "qup-memory";
1576 #address-cells = <1>;
1577 #size-cells = <0>;
1582 compatible = "qcom,geni-spi";
1584 clock-names = "se";
1589 dma-names = "tx", "rx";
1590 power-domains = <&rpmhpd RPMHPD_CX>;
1591 operating-points-v2 = <&qup_opp_table>;
1595 interconnect-names = "qup-core",
1596 "qup-config",
1597 "qup-memory";
1598 #address-cells = <1>;
1599 #size-cells = <0>;
1604 compatible = "qcom,geni-i2c";
1606 clock-names = "se";
1608 pinctrl-names = "default";
1609 pinctrl-0 = <&qup_i2c5_default>;
1613 dma-names = "tx", "rx";
1614 power-domains = <&rpmhpd SM8250_CX>;
1618 interconnect-names = "qup-core",
1619 "qup-config",
1620 "qup-memory";
1621 #address-cells = <1>;
1622 #size-cells = <0>;
1627 compatible = "qcom,geni-spi";
1629 clock-names = "se";
1634 dma-names = "tx", "rx";
1635 power-domains = <&rpmhpd RPMHPD_CX>;
1636 operating-points-v2 = <&qup_opp_table>;
1640 interconnect-names = "qup-core",
1641 "qup-config",
1642 "qup-memory";
1643 #address-cells = <1>;
1644 #size-cells = <0>;
1649 compatible = "qcom,geni-i2c";
1651 clock-names = "se";
1653 pinctrl-names = "default";
1654 pinctrl-0 = <&qup_i2c6_default>;
1658 dma-names = "tx", "rx";
1659 power-domains = <&rpmhpd SM8250_CX>;
1663 interconnect-names = "qup-core",
1664 "qup-config",
1665 "qup-memory";
1666 #address-cells = <1>;
1667 #size-cells = <0>;
1672 compatible = "qcom,geni-spi";
1674 clock-names = "se";
1679 dma-names = "tx", "rx";
1680 power-domains = <&rpmhpd RPMHPD_CX>;
1681 operating-points-v2 = <&qup_opp_table>;
1685 interconnect-names = "qup-core",
1686 "qup-config",
1687 "qup-memory";
1688 #address-cells = <1>;
1689 #size-cells = <0>;
1694 compatible = "qcom,geni-uart";
1696 clock-names = "se";
1698 pinctrl-names = "default";
1699 pinctrl-0 = <&qup_uart6_default>;
1701 power-domains = <&rpmhpd RPMHPD_CX>;
1702 operating-points-v2 = <&qup_opp_table>;
1705 interconnect-names = "qup-core",
1706 "qup-config";
1711 compatible = "qcom,geni-i2c";
1713 clock-names = "se";
1715 pinctrl-names = "default";
1716 pinctrl-0 = <&qup_i2c7_default>;
1720 dma-names = "tx", "rx";
1721 power-domains = <&rpmhpd SM8250_CX>;
1725 interconnect-names = "qup-core",
1726 "qup-config",
1727 "qup-memory";
1728 #address-cells = <1>;
1729 #size-cells = <0>;
1734 compatible = "qcom,geni-spi";
1736 clock-names = "se";
1741 dma-names = "tx", "rx";
1742 power-domains = <&rpmhpd RPMHPD_CX>;
1743 operating-points-v2 = <&qup_opp_table>;
1747 interconnect-names = "qup-core",
1748 "qup-config",
1749 "qup-memory";
1750 #address-cells = <1>;
1751 #size-cells = <0>;
1756 gpi_dma1: dma-controller@a00000 {
1757 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1769 dma-channels = <10>;
1770 dma-channel-mask = <0x3f>;
1772 #dma-cells = <3>;
1777 compatible = "qcom,geni-se-qup";
1779 clock-names = "m-ahb", "s-ahb";
1782 #address-cells = <2>;
1783 #size-cells = <2>;
1789 compatible = "qcom,geni-i2c";
1791 clock-names = "se";
1793 pinctrl-names = "default";
1794 pinctrl-0 = <&qup_i2c8_default>;
1798 dma-names = "tx", "rx";
1799 power-domains = <&rpmhpd SM8250_CX>;
1803 interconnect-names = "qup-core",
1804 "qup-config",
1805 "qup-memory";
1806 #address-cells = <1>;
1807 #size-cells = <0>;
1812 compatible = "qcom,geni-spi";
1814 clock-names = "se";
1819 dma-names = "tx", "rx";
1820 power-domains = <&rpmhpd RPMHPD_CX>;
1821 operating-points-v2 = <&qup_opp_table>;
1825 interconnect-names = "qup-core",
1826 "qup-config",
1827 "qup-memory";
1828 #address-cells = <1>;
1829 #size-cells = <0>;
1834 compatible = "qcom,geni-i2c";
1836 clock-names = "se";
1838 pinctrl-names = "default";
1839 pinctrl-0 = <&qup_i2c9_default>;
1843 dma-names = "tx", "rx";
1844 power-domains = <&rpmhpd SM8250_CX>;
1848 interconnect-names = "qup-core",
1849 "qup-config",
1850 "qup-memory";
1851 #address-cells = <1>;
1852 #size-cells = <0>;
1857 compatible = "qcom,geni-spi";
1859 clock-names = "se";
1864 dma-names = "tx", "rx";
1865 power-domains = <&rpmhpd RPMHPD_CX>;
1866 operating-points-v2 = <&qup_opp_table>;
1870 interconnect-names = "qup-core",
1871 "qup-config",
1872 "qup-memory";
1873 #address-cells = <1>;
1874 #size-cells = <0>;
1879 compatible = "qcom,geni-i2c";
1881 clock-names = "se";
1883 pinctrl-names = "default";
1884 pinctrl-0 = <&qup_i2c10_default>;
1888 dma-names = "tx", "rx";
1889 power-domains = <&rpmhpd SM8250_CX>;
1893 interconnect-names = "qup-core",
1894 "qup-config",
1895 "qup-memory";
1896 #address-cells = <1>;
1897 #size-cells = <0>;
1902 compatible = "qcom,geni-spi";
1904 clock-names = "se";
1909 dma-names = "tx", "rx";
1910 power-domains = <&rpmhpd RPMHPD_CX>;
1911 operating-points-v2 = <&qup_opp_table>;
1915 interconnect-names = "qup-core",
1916 "qup-config",
1917 "qup-memory";
1918 #address-cells = <1>;
1919 #size-cells = <0>;
1924 compatible = "qcom,geni-i2c";
1926 clock-names = "se";
1928 pinctrl-names = "default";
1929 pinctrl-0 = <&qup_i2c11_default>;
1933 dma-names = "tx", "rx";
1934 power-domains = <&rpmhpd SM8250_CX>;
1938 interconnect-names = "qup-core",
1939 "qup-config",
1940 "qup-memory";
1941 #address-cells = <1>;
1942 #size-cells = <0>;
1947 compatible = "qcom,geni-spi";
1949 clock-names = "se";
1954 dma-names = "tx", "rx";
1955 power-domains = <&rpmhpd RPMHPD_CX>;
1956 operating-points-v2 = <&qup_opp_table>;
1960 interconnect-names = "qup-core",
1961 "qup-config",
1962 "qup-memory";
1963 #address-cells = <1>;
1964 #size-cells = <0>;
1969 compatible = "qcom,geni-i2c";
1971 clock-names = "se";
1973 pinctrl-names = "default";
1974 pinctrl-0 = <&qup_i2c12_default>;
1978 dma-names = "tx", "rx";
1979 power-domains = <&rpmhpd SM8250_CX>;
1983 interconnect-names = "qup-core",
1984 "qup-config",
1985 "qup-memory";
1986 #address-cells = <1>;
1987 #size-cells = <0>;
1992 compatible = "qcom,geni-spi";
1994 clock-names = "se";
1999 dma-names = "tx", "rx";
2000 power-domains = <&rpmhpd RPMHPD_CX>;
2001 operating-points-v2 = <&qup_opp_table>;
2005 interconnect-names = "qup-core",
2006 "qup-config",
2007 "qup-memory";
2008 #address-cells = <1>;
2009 #size-cells = <0>;
2014 compatible = "qcom,geni-debug-uart";
2016 clock-names = "se";
2018 pinctrl-names = "default";
2019 pinctrl-0 = <&qup_uart12_default>;
2021 power-domains = <&rpmhpd RPMHPD_CX>;
2022 operating-points-v2 = <&qup_opp_table>;
2025 interconnect-names = "qup-core",
2026 "qup-config";
2031 compatible = "qcom,geni-i2c";
2033 clock-names = "se";
2035 pinctrl-names = "default";
2036 pinctrl-0 = <&qup_i2c13_default>;
2040 dma-names = "tx", "rx";
2041 power-domains = <&rpmhpd SM8250_CX>;
2045 interconnect-names = "qup-core",
2046 "qup-config",
2047 "qup-memory";
2048 #address-cells = <1>;
2049 #size-cells = <0>;
2054 compatible = "qcom,geni-spi";
2056 clock-names = "se";
2061 dma-names = "tx", "rx";
2062 power-domains = <&rpmhpd RPMHPD_CX>;
2063 operating-points-v2 = <&qup_opp_table>;
2067 interconnect-names = "qup-core",
2068 "qup-config",
2069 "qup-memory";
2070 #address-cells = <1>;
2071 #size-cells = <0>;
2077 compatible = "qcom,sm8250-config-noc";
2079 #interconnect-cells = <2>;
2080 qcom,bcm-voters = <&apps_bcm_voter>;
2084 compatible = "qcom,sm8250-system-noc";
2086 #interconnect-cells = <2>;
2087 qcom,bcm-voters = <&apps_bcm_voter>;
2091 compatible = "qcom,sm8250-mc-virt";
2093 #interconnect-cells = <2>;
2094 qcom,bcm-voters = <&apps_bcm_voter>;
2098 compatible = "qcom,sm8250-aggre1-noc";
2100 #interconnect-cells = <2>;
2101 qcom,bcm-voters = <&apps_bcm_voter>;
2105 compatible = "qcom,sm8250-aggre2-noc";
2107 #interconnect-cells = <2>;
2108 qcom,bcm-voters = <&apps_bcm_voter>;
2112 compatible = "qcom,sm8250-compute-noc";
2114 #interconnect-cells = <2>;
2115 qcom,bcm-voters = <&apps_bcm_voter>;
2119 compatible = "qcom,sm8250-mmss-noc";
2121 #interconnect-cells = <2>;
2122 qcom,bcm-voters = <&apps_bcm_voter>;
2126 compatible = "qcom,pcie-sm8250";
2133 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2135 linux,pci-domain = <0>;
2136 bus-range = <0x00 0xff>;
2137 num-lanes = <1>;
2139 #address-cells = <3>;
2140 #size-cells = <2>;
2153 interrupt-names = "msi0",
2161 #interrupt-cells = <1>;
2162 interrupt-map-mask = <0 0 0 0x7>;
2163 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2176 clock-names = "pipe",
2185 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2189 reset-names = "pci";
2191 power-domains = <&gcc PCIE_0_GDSC>;
2194 phy-names = "pciephy";
2196 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
2197 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
2199 pinctrl-names = "default";
2200 pinctrl-0 = <&pcie0_default_state>;
2201 dma-coherent;
2208 bus-range = <0x01 0xff>;
2210 #address-cells = <3>;
2211 #size-cells = <2>;
2217 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
2225 clock-names = "aux",
2231 clock-output-names = "pcie_0_pipe_clk";
2232 #clock-cells = <0>;
2234 #phy-cells = <0>;
2237 reset-names = "phy";
2239 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2240 assigned-clock-rates = <100000000>;
2246 compatible = "qcom,pcie-sm8250";
2253 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2255 linux,pci-domain = <1>;
2256 bus-range = <0x00 0xff>;
2257 num-lanes = <2>;
2259 #address-cells = <3>;
2260 #size-cells = <2>;
2273 interrupt-names = "msi0",
2281 #interrupt-cells = <1>;
2282 interrupt-map-mask = <0 0 0 0x7>;
2283 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2297 clock-names = "pipe",
2307 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2308 assigned-clock-rates = <19200000>;
2310 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2314 reset-names = "pci";
2316 power-domains = <&gcc PCIE_1_GDSC>;
2319 phy-names = "pciephy";
2321 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
2322 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
2324 pinctrl-names = "default";
2325 pinctrl-0 = <&pcie1_default_state>;
2326 dma-coherent;
2333 bus-range = <0x01 0xff>;
2335 #address-cells = <3>;
2336 #size-cells = <2>;
2342 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2350 clock-names = "aux",
2356 clock-output-names = "pcie_1_pipe_clk";
2357 #clock-cells = <0>;
2359 #phy-cells = <0>;
2362 reset-names = "phy";
2364 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2365 assigned-clock-rates = <100000000>;
2371 compatible = "qcom,pcie-sm8250";
2378 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2380 linux,pci-domain = <2>;
2381 bus-range = <0x00 0xff>;
2382 num-lanes = <2>;
2384 #address-cells = <3>;
2385 #size-cells = <2>;
2398 interrupt-names = "msi0",
2406 #interrupt-cells = <1>;
2407 interrupt-map-mask = <0 0 0 0x7>;
2408 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2422 clock-names = "pipe",
2432 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2433 assigned-clock-rates = <19200000>;
2435 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2439 reset-names = "pci";
2441 power-domains = <&gcc PCIE_2_GDSC>;
2444 phy-names = "pciephy";
2446 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
2447 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
2449 pinctrl-names = "default";
2450 pinctrl-0 = <&pcie2_default_state>;
2451 dma-coherent;
2458 bus-range = <0x01 0xff>;
2460 #address-cells = <3>;
2461 #size-cells = <2>;
2467 compatible = "qcom,sm8250-qmp-modem-pcie-phy";
2475 clock-names = "aux",
2481 clock-output-names = "pcie_2_pipe_clk";
2482 #clock-cells = <0>;
2484 #phy-cells = <0>;
2487 reset-names = "phy";
2489 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2490 assigned-clock-rates = <100000000>;
2496 compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
2497 "jedec,ufs-2.0";
2501 phy-names = "ufsphy";
2502 lanes-per-direction = <2>;
2503 #reset-cells = <1>;
2505 reset-names = "rst";
2507 power-domains = <&gcc UFS_PHY_GDSC>;
2511 clock-names =
2530 operating-points-v2 = <&ufs_opp_table>;
2534 interconnect-names = "ufs-ddr", "cpu-ufs";
2538 ufs_opp_table: opp-table {
2539 compatible = "operating-points-v2";
2541 opp-37500000 {
2542 opp-hz = /bits/ 64 <37500000>,
2550 required-opps = <&rpmhpd_opp_low_svs>;
2553 opp-300000000 {
2554 opp-hz = /bits/ 64 <300000000>,
2562 required-opps = <&rpmhpd_opp_nom>;
2568 compatible = "qcom,sm8250-qmp-ufs-phy";
2574 clock-names = "ref",
2579 reset-names = "ufsphy";
2581 power-domains = <&gcc UFS_PHY_GDSC>;
2583 #phy-cells = <0>;
2588 cryptobam: dma-controller@1dc4000 {
2589 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2592 #dma-cells = <1>;
2594 qcom,controlled-remotely;
2595 num-channels = <8>;
2596 qcom,num-ees = <2>;
2606 compatible = "qcom,sm8250-qce", "qcom,sm8150-qce", "qcom,qce";
2609 dma-names = "rx", "tx";
2617 interconnect-names = "memory";
2621 compatible = "qcom,tcsr-mutex";
2623 #hwlock-cells = <1>;
2627 compatible = "qcom,sm8250-tcsr", "syscon";
2632 compatible = "qcom,sm8250-lpass-wsa-macro";
2640 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2642 #clock-cells = <0>;
2643 clock-output-names = "mclk";
2644 #sound-dai-cells = <1>;
2646 pinctrl-names = "default";
2647 pinctrl-0 = <&wsa_swr_active>;
2654 compatible = "qcom,soundwire-v1.5.1";
2657 clock-names = "iface";
2659 qcom,din-ports = <2>;
2660 qcom,dout-ports = <6>;
2662 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2663 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2664 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2665 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2667 #sound-dai-cells = <1>;
2668 #address-cells = <2>;
2669 #size-cells = <0>;
2675 compatible = "qcom,sm8250-lpass-va-macro";
2681 clock-names = "mclk", "macro", "dcodec";
2683 #clock-cells = <0>;
2684 clock-output-names = "fsgen";
2685 #sound-dai-cells = <1>;
2689 pinctrl-names = "default";
2690 pinctrl-0 = <&rx_swr_active>;
2691 compatible = "qcom,sm8250-lpass-rx-macro";
2701 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2703 #clock-cells = <0>;
2704 clock-output-names = "mclk";
2705 #sound-dai-cells = <1>;
2710 compatible = "qcom,soundwire-v1.5.1";
2714 clock-names = "iface";
2716 qcom,din-ports = <0>;
2717 qcom,dout-ports = <5>;
2719 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2720 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2721 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2722 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2723 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2724 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2725 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2726 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2727 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2729 #sound-dai-cells = <1>;
2730 #address-cells = <2>;
2731 #size-cells = <0>;
2735 pinctrl-names = "default";
2736 pinctrl-0 = <&tx_swr_active>;
2737 compatible = "qcom,sm8250-lpass-tx-macro";
2747 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2749 #clock-cells = <0>;
2750 clock-output-names = "mclk";
2751 #sound-dai-cells = <1>;
2757 compatible = "qcom,soundwire-v1.5.1";
2759 interrupt-names = "core";
2763 clock-names = "iface";
2766 qcom,din-ports = <5>;
2767 qcom,dout-ports = <0>;
2768 qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>;
2769 qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>;
2770 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>;
2771 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2772 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2773 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2774 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2775 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2776 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>;
2777 #sound-dai-cells = <1>;
2778 #address-cells = <2>;
2779 #size-cells = <0>;
2783 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
2786 gpio-controller;
2787 #gpio-cells = <2>;
2788 gpio-ranges = <&lpass_tlmm 0 0 14>;
2792 clock-names = "core", "audio";
2794 wsa_swr_active: wsa-swr-active-state {
2795 clk-pins {
2798 drive-strength = <2>;
2799 slew-rate = <1>;
2800 bias-disable;
2803 data-pins {
2806 drive-strength = <2>;
2807 slew-rate = <1>;
2808 bias-bus-hold;
2812 wsa_swr_sleep: wsa-swr-sleep-state {
2813 clk-pins {
2816 drive-strength = <2>;
2817 bias-pull-down;
2820 data-pins {
2823 drive-strength = <2>;
2824 bias-pull-down;
2828 dmic01_active: dmic01-active-state {
2829 clk-pins {
2832 drive-strength = <8>;
2833 output-high;
2835 data-pins {
2838 drive-strength = <8>;
2842 dmic01_sleep: dmic01-sleep-state {
2843 clk-pins {
2846 drive-strength = <2>;
2847 bias-disable;
2848 output-low;
2851 data-pins {
2854 drive-strength = <2>;
2855 bias-pull-down;
2859 rx_swr_active: rx-swr-active-state {
2860 clk-pins {
2863 drive-strength = <2>;
2864 slew-rate = <1>;
2865 bias-disable;
2868 data-pins {
2869 pins = "gpio4", "gpio5";
2871 drive-strength = <2>;
2872 slew-rate = <1>;
2873 bias-bus-hold;
2877 tx_swr_active: tx-swr-active-state {
2878 clk-pins {
2881 drive-strength = <2>;
2882 slew-rate = <1>;
2883 bias-disable;
2886 data-pins {
2889 drive-strength = <2>;
2890 slew-rate = <1>;
2891 bias-bus-hold;
2895 tx_swr_sleep: tx-swr-sleep-state {
2896 clk-pins {
2899 drive-strength = <2>;
2900 bias-pull-down;
2903 data1-pins {
2906 drive-strength = <2>;
2907 bias-bus-hold;
2910 data2-pins {
2913 drive-strength = <2>;
2914 bias-pull-down;
2920 compatible = "qcom,adreno-650.2",
2924 reg-names = "kgsl_3d0_reg_memory";
2930 operating-points-v2 = <&gpu_opp_table>;
2934 nvmem-cells = <&gpu_speed_bin>;
2935 nvmem-cell-names = "speed_bin";
2936 #cooling-cells = <2>;
2940 zap-shader {
2941 memory-region = <&gpu_mem>;
2944 gpu_opp_table: opp-table {
2945 compatible = "operating-points-v2";
2947 opp-670000000 {
2948 opp-hz = /bits/ 64 <670000000>;
2949 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2950 opp-supported-hw = <0xa>;
2953 opp-587000000 {
2954 opp-hz = /bits/ 64 <587000000>;
2955 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2956 opp-supported-hw = <0xb>;
2959 opp-525000000 {
2960 opp-hz = /bits/ 64 <525000000>;
2961 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2962 opp-supported-hw = <0xf>;
2965 opp-490000000 {
2966 opp-hz = /bits/ 64 <490000000>;
2967 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2968 opp-supported-hw = <0xf>;
2971 opp-441600000 {
2972 opp-hz = /bits/ 64 <441600000>;
2973 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2974 opp-supported-hw = <0xf>;
2977 opp-400000000 {
2978 opp-hz = /bits/ 64 <400000000>;
2979 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2980 opp-supported-hw = <0xf>;
2983 opp-305000000 {
2984 opp-hz = /bits/ 64 <305000000>;
2985 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2986 opp-supported-hw = <0xf>;
2992 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2998 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
3002 interrupt-names = "hfi", "gmu";
3009 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
3011 power-domains = <&gpucc GPU_CX_GDSC>,
3013 power-domain-names = "cx", "gx";
3017 operating-points-v2 = <&gmu_opp_table>;
3021 gmu_opp_table: opp-table {
3022 compatible = "operating-points-v2";
3024 opp-200000000 {
3025 opp-hz = /bits/ 64 <200000000>;
3026 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3031 gpucc: clock-controller@3d90000 {
3032 compatible = "qcom,sm8250-gpucc";
3037 clock-names = "bi_tcxo",
3040 #clock-cells = <1>;
3041 #reset-cells = <1>;
3042 #power-domain-cells = <1>;
3046 compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu",
3047 "qcom,smmu-500", "arm,mmu-500";
3049 #iommu-cells = <2>;
3050 #global-interrupts = <2>;
3064 clock-names = "ahb", "bus", "iface";
3066 power-domains = <&gpucc GPU_CX_GDSC>;
3067 dma-coherent;
3071 compatible = "qcom,sm8250-slpi-pas";
3074 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
3079 interrupt-names = "wdog", "fatal", "ready",
3080 "handover", "stop-ack";
3083 clock-names = "xo";
3085 power-domains = <&rpmhpd RPMHPD_LCX>,
3087 power-domain-names = "lcx", "lmx";
3089 memory-region = <&slpi_mem>;
3093 qcom,smem-states = <&smp2p_slpi_out 0>;
3094 qcom,smem-state-names = "stop";
3098 glink-edge {
3099 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
3106 qcom,remote-pid = <3>;
3110 qcom,glink-channels = "fastrpcglink-apps-dsp";
3112 qcom,non-secure-domain;
3113 #address-cells = <1>;
3114 #size-cells = <0>;
3116 compute-cb@1 {
3117 compatible = "qcom,fastrpc-compute-cb";
3122 compute-cb@2 {
3123 compatible = "qcom,fastrpc-compute-cb";
3128 compute-cb@3 {
3129 compatible = "qcom,fastrpc-compute-cb";
3132 /* note: shared-cb = <4> in downstream */
3139 compatible = "arm,coresight-stm", "arm,primecell";
3141 reg-names = "stm-base", "stm-stimulus-base";
3144 clock-names = "apb_pclk";
3146 out-ports {
3149 remote-endpoint = <&funnel0_in7>;
3156 compatible = "qcom,coresight-tpda", "arm,primecell";
3160 clock-names = "apb_pclk";
3162 out-ports {
3166 remote-endpoint = <&funnel_qatb_in_tpda>;
3171 in-ports {
3172 #address-cells = <1>;
3173 #size-cells = <0>;
3178 remote-endpoint = <&tpdm_mm_out_tpda9>;
3185 remote-endpoint = <&tpdm_prng_out_tpda_23>;
3192 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3196 clock-names = "apb_pclk";
3198 out-ports {
3201 remote-endpoint = <&funnel_in0_in_funnel_qatb>;
3206 in-ports {
3209 remote-endpoint = <&tpda_out_funnel_qatb>;
3216 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3220 clock-names = "apb_pclk";
3222 out-ports {
3225 remote-endpoint = <&funnel_merg_in_funnel_in0>;
3230 in-ports {
3231 #address-cells = <1>;
3232 #size-cells = <0>;
3237 remote-endpoint = <&funnel_qatb_out_funnel_in0>;
3244 remote-endpoint = <&stm_out>;
3251 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3255 clock-names = "apb_pclk";
3257 out-ports {
3260 remote-endpoint = <&funnel_merg_in_funnel_in1>;
3265 in-ports {
3266 #address-cells = <1>;
3267 #size-cells = <0>;
3272 remote-endpoint = <&funnel_apss_merg_out_funnel_in1>;
3279 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3283 clock-names = "apb_pclk";
3285 out-ports {
3288 remote-endpoint = <&funnel_swao_in_funnel_merg>;
3293 in-ports {
3294 #address-cells = <1>;
3295 #size-cells = <0>;
3300 remote-endpoint = <&funnel_in0_out_funnel_merg>;
3307 remote-endpoint = <&funnel_in1_out_funnel_merg>;
3314 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3318 clock-names = "apb_pclk";
3320 out-ports {
3323 remote-endpoint = <&etr_in>;
3328 in-ports {
3331 remote-endpoint = <&replicator_swao_out_cx_in>;
3338 compatible = "arm,coresight-tmc", "arm,primecell";
3342 clock-names = "apb_pclk";
3343 arm,scatter-gather;
3345 in-ports {
3348 remote-endpoint = <&replicator_out>;
3355 compatible = "qcom,coresight-tpdm", "arm,primecell";
3359 clock-names = "apb_pclk";
3361 out-ports {
3364 remote-endpoint = <&tpda_23_in_tpdm_prng>;
3371 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3372 arm,primecell-periphid = <0x000bb908>;
3377 clock-names = "apb_pclk";
3379 out-ports {
3382 remote-endpoint = <&etf_in_funnel_swao_out>;
3387 in-ports {
3388 #address-cells = <1>;
3389 #size-cells = <0>;
3394 remote-endpoint = <&funnel_merg_out_funnel_swao>;
3401 compatible = "arm,coresight-tmc", "arm,primecell";
3405 clock-names = "apb_pclk";
3407 out-ports {
3410 remote-endpoint = <&replicator_in>;
3415 in-ports {
3419 remote-endpoint = <&funnel_swao_out_etf>;
3426 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3430 clock-names = "apb_pclk";
3432 out-ports {
3435 remote-endpoint = <&replicator_cx_in_swao_out>;
3440 in-ports {
3443 remote-endpoint = <&etf_out>;
3450 compatible = "qcom,coresight-tpdm", "arm,primecell";
3454 clock-names = "apb_pclk";
3456 out-ports {
3459 remote-endpoint = <&funnel_dl_mm_in_tpdm_mm>;
3466 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3470 clock-names = "apb_pclk";
3472 out-ports {
3475 remote-endpoint = <&funnel_dl_center_in_funnel_dl_mm>;
3480 in-ports {
3481 #address-cells = <1>;
3482 #size-cells = <0>;
3487 remote-endpoint = <&tpdm_mm_out_funnel_dl_mm>;
3494 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3498 clock-names = "apb_pclk";
3500 out-ports {
3503 remote-endpoint = <&tpda_9_in_tpdm_mm>;
3508 in-ports {
3509 #address-cells = <1>;
3510 #size-cells = <0>;
3515 remote-endpoint = <&funnel_dl_mm_out_funnel_dl_center>;
3522 compatible = "arm,coresight-etm4x", "arm,primecell";
3528 clock-names = "apb_pclk";
3529 arm,coresight-loses-context-with-cpu;
3531 out-ports {
3534 remote-endpoint = <&apss_funnel_in0>;
3541 compatible = "arm,coresight-etm4x", "arm,primecell";
3547 clock-names = "apb_pclk";
3548 arm,coresight-loses-context-with-cpu;
3550 out-ports {
3553 remote-endpoint = <&apss_funnel_in1>;
3560 compatible = "arm,coresight-etm4x", "arm,primecell";
3566 clock-names = "apb_pclk";
3567 arm,coresight-loses-context-with-cpu;
3569 out-ports {
3572 remote-endpoint = <&apss_funnel_in2>;
3579 compatible = "arm,coresight-etm4x", "arm,primecell";
3585 clock-names = "apb_pclk";
3586 arm,coresight-loses-context-with-cpu;
3588 out-ports {
3591 remote-endpoint = <&apss_funnel_in3>;
3598 compatible = "arm,coresight-etm4x", "arm,primecell";
3604 clock-names = "apb_pclk";
3605 arm,coresight-loses-context-with-cpu;
3607 out-ports {
3610 remote-endpoint = <&apss_funnel_in4>;
3617 compatible = "arm,coresight-etm4x", "arm,primecell";
3623 clock-names = "apb_pclk";
3624 arm,coresight-loses-context-with-cpu;
3626 out-ports {
3629 remote-endpoint = <&apss_funnel_in5>;
3636 compatible = "arm,coresight-etm4x", "arm,primecell";
3642 clock-names = "apb_pclk";
3643 arm,coresight-loses-context-with-cpu;
3645 out-ports {
3648 remote-endpoint = <&apss_funnel_in6>;
3655 compatible = "arm,coresight-etm4x", "arm,primecell";
3661 clock-names = "apb_pclk";
3662 arm,coresight-loses-context-with-cpu;
3664 out-ports {
3667 remote-endpoint = <&apss_funnel_in7>;
3674 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3678 clock-names = "apb_pclk";
3680 out-ports {
3683 remote-endpoint = <&funnel_apss_merg_in_funnel_apss>;
3688 in-ports {
3689 #address-cells = <1>;
3690 #size-cells = <0>;
3695 remote-endpoint = <&etm0_out>;
3702 remote-endpoint = <&etm1_out>;
3709 remote-endpoint = <&etm2_out>;
3716 remote-endpoint = <&etm3_out>;
3723 remote-endpoint = <&etm4_out>;
3730 remote-endpoint = <&etm5_out>;
3737 remote-endpoint = <&etm6_out>;
3744 remote-endpoint = <&etm7_out>;
3751 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3755 clock-names = "apb_pclk";
3757 out-ports {
3760 remote-endpoint = <&funnel_in1_in_funnel_apss_merg>;
3765 in-ports {
3768 remote-endpoint = <&funnel_apss_out_funnel_apss_merg>;
3775 compatible = "qcom,sm8250-cdsp-pas";
3778 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3783 interrupt-names = "wdog", "fatal", "ready",
3784 "handover", "stop-ack";
3787 clock-names = "xo";
3789 power-domains = <&rpmhpd RPMHPD_CX>;
3791 memory-region = <&cdsp_mem>;
3795 qcom,smem-states = <&smp2p_cdsp_out 0>;
3796 qcom,smem-state-names = "stop";
3800 glink-edge {
3801 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3808 qcom,remote-pid = <5>;
3812 qcom,glink-channels = "fastrpcglink-apps-dsp";
3814 qcom,non-secure-domain;
3815 #address-cells = <1>;
3816 #size-cells = <0>;
3818 compute-cb@1 {
3819 compatible = "qcom,fastrpc-compute-cb";
3824 compute-cb@2 {
3825 compatible = "qcom,fastrpc-compute-cb";
3830 compute-cb@3 {
3831 compatible = "qcom,fastrpc-compute-cb";
3836 compute-cb@4 {
3837 compatible = "qcom,fastrpc-compute-cb";
3842 compute-cb@5 {
3843 compatible = "qcom,fastrpc-compute-cb";
3848 compute-cb@6 {
3849 compatible = "qcom,fastrpc-compute-cb";
3854 compute-cb@7 {
3855 compatible = "qcom,fastrpc-compute-cb";
3860 compute-cb@8 {
3861 compatible = "qcom,fastrpc-compute-cb";
3872 compatible = "qcom,sm8250-usb-hs-phy",
3873 "qcom,usb-snps-hs-7nm-phy";
3876 #phy-cells = <0>;
3879 clock-names = "ref";
3885 compatible = "qcom,sm8250-usb-hs-phy",
3886 "qcom,usb-snps-hs-7nm-phy";
3889 #phy-cells = <0>;
3892 clock-names = "ref";
3898 compatible = "qcom,sm8250-qmp-usb3-dp-phy";
3906 clock-names = "aux",
3913 reset-names = "phy", "common";
3915 #clock-cells = <1>;
3916 #phy-cells = <1>;
3918 orientation-switch;
3921 #address-cells = <1>;
3922 #size-cells = <0>;
3933 remote-endpoint = <&usb_1_dwc3_ss_out>;
3946 compatible = "qcom,sm8250-qmp-usb3-uni-phy";
3953 clock-names = "aux",
3957 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3958 #clock-cells = <0>;
3959 #phy-cells = <0>;
3963 reset-names = "phy",
3970 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
3975 interrupt-names = "hc_irq", "pwr_irq";
3980 clock-names = "iface", "core", "xo";
3982 qcom,dll-config = <0x0007642c>;
3983 qcom,ddr-config = <0x80040868>;
3984 power-domains = <&rpmhpd RPMHPD_CX>;
3985 operating-points-v2 = <&sdhc2_opp_table>;
3989 sdhc2_opp_table: opp-table {
3990 compatible = "operating-points-v2";
3992 opp-19200000 {
3993 opp-hz = /bits/ 64 <19200000>;
3994 required-opps = <&rpmhpd_opp_min_svs>;
3997 opp-50000000 {
3998 opp-hz = /bits/ 64 <50000000>;
3999 required-opps = <&rpmhpd_opp_low_svs>;
4002 opp-100000000 {
4003 opp-hz = /bits/ 64 <100000000>;
4004 required-opps = <&rpmhpd_opp_svs>;
4007 opp-202000000 {
4008 opp-hz = /bits/ 64 <202000000>;
4009 required-opps = <&rpmhpd_opp_svs_l1>;
4015 compatible = "qcom,sm8250-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
4022 operating-points-v2 = <&llcc_bwmon_opp_table>;
4024 llcc_bwmon_opp_table: opp-table {
4025 compatible = "operating-points-v2";
4027 opp-800000 {
4028 opp-peak-kBps = <(200 * 4 * 1000)>;
4031 opp-1200000 {
4032 opp-peak-kBps = <(300 * 4 * 1000)>;
4035 opp-1804000 {
4036 opp-peak-kBps = <(451 * 4 * 1000)>;
4039 opp-2188000 {
4040 opp-peak-kBps = <(547 * 4 * 1000)>;
4043 opp-2724000 {
4044 opp-peak-kBps = <(681 * 4 * 1000)>;
4047 opp-3072000 {
4048 opp-peak-kBps = <(768 * 4 * 1000)>;
4051 opp-4068000 {
4052 opp-peak-kBps = <(1017 * 4 * 1000)>;
4057 opp-6220000 {
4058 opp-peak-kBps = <(1555 * 4 * 1000)>;
4061 opp-7216000 {
4062 opp-peak-kBps = <(1804 * 4 * 1000)>;
4065 opp-8368000 {
4066 opp-peak-kBps = <(2092 * 4 * 1000)>;
4070 opp-10944000 {
4071 opp-peak-kBps = <(2736 * 4 * 1000)>;
4077 compatible = "qcom,sm8250-cpu-bwmon", "qcom,sdm845-bwmon";
4083 operating-points-v2 = <&cpu_bwmon_opp_table>;
4085 cpu_bwmon_opp_table: opp-table {
4086 compatible = "operating-points-v2";
4088 opp-800000 {
4089 opp-peak-kBps = <(200 * 4 * 1000)>;
4092 opp-1804000 {
4093 opp-peak-kBps = <(451 * 4 * 1000)>;
4096 opp-2188000 {
4097 opp-peak-kBps = <(547 * 4 * 1000)>;
4100 opp-2724000 {
4101 opp-peak-kBps = <(681 * 4 * 1000)>;
4104 opp-3072000 {
4105 opp-peak-kBps = <(768 * 4 * 1000)>;
4110 opp-6220000 {
4111 opp-peak-kBps = <(1555 * 4 * 1000)>;
4114 opp-6832000 {
4115 opp-peak-kBps = <(1708 * 4 * 1000)>;
4118 opp-8368000 {
4119 opp-peak-kBps = <(2092 * 4 * 1000)>;
4125 opp-10944000 {
4126 opp-peak-kBps = <(2736 * 4 * 1000)>;
4130 opp-12784000 {
4131 opp-peak-kBps = <(3196 * 4 * 1000)>;
4137 compatible = "qcom,sm8250-dc-noc";
4139 #interconnect-cells = <2>;
4140 qcom,bcm-voters = <&apps_bcm_voter>;
4144 compatible = "qcom,sm8250-gem-noc";
4146 #interconnect-cells = <2>;
4147 qcom,bcm-voters = <&apps_bcm_voter>;
4151 compatible = "qcom,sm8250-npu-noc";
4153 #interconnect-cells = <2>;
4154 qcom,bcm-voters = <&apps_bcm_voter>;
4158 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4161 #address-cells = <2>;
4162 #size-cells = <2>;
4164 dma-ranges;
4172 clock-names = "cfg_noc",
4179 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4181 assigned-clock-rates = <19200000>, <200000000>;
4183 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4188 interrupt-names = "pwr_event",
4194 power-domains = <&gcc USB30_PRIM_GDSC>;
4195 wakeup-source;
4201 interconnect-names = "usb-ddr", "apps-usb";
4211 phy-names = "usb2-phy", "usb3-phy";
4214 #address-cells = <1>;
4215 #size-cells = <0>;
4228 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
4235 system-cache-controller@9200000 {
4236 compatible = "qcom,sm8250-llcc";
4240 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
4245 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4248 #address-cells = <2>;
4249 #size-cells = <2>;
4251 dma-ranges;
4259 clock-names = "cfg_noc",
4266 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4268 assigned-clock-rates = <19200000>, <200000000>;
4270 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
4275 interrupt-names = "pwr_event",
4281 power-domains = <&gcc USB30_SEC_GDSC>;
4282 wakeup-source;
4288 interconnect-names = "usb-ddr", "apps-usb";
4298 phy-names = "usb2-phy", "usb3-phy";
4302 venus: video-codec@aa00000 {
4303 compatible = "qcom,sm8250-venus";
4306 power-domains = <&videocc MVS0C_GDSC>,
4309 power-domain-names = "venus", "vcodec0", "mx";
4310 operating-points-v2 = <&venus_opp_table>;
4315 clock-names = "iface", "core", "vcodec0_core";
4319 interconnect-names = "cpu-cfg", "video-mem";
4322 memory-region = <&video_mem>;
4326 reset-names = "bus", "core";
4330 video-decoder {
4331 compatible = "venus-decoder";
4334 video-encoder {
4335 compatible = "venus-encoder";
4338 venus_opp_table: opp-table {
4339 compatible = "operating-points-v2";
4341 opp-720000000 {
4342 opp-hz = /bits/ 64 <720000000>;
4343 required-opps = <&rpmhpd_opp_low_svs>;
4346 opp-1014000000 {
4347 opp-hz = /bits/ 64 <1014000000>;
4348 required-opps = <&rpmhpd_opp_svs>;
4351 opp-1098000000 {
4352 opp-hz = /bits/ 64 <1098000000>;
4353 required-opps = <&rpmhpd_opp_svs_l1>;
4356 opp-1332000000 {
4357 opp-hz = /bits/ 64 <1332000000>;
4358 required-opps = <&rpmhpd_opp_nom>;
4363 videocc: clock-controller@abf0000 {
4364 compatible = "qcom,sm8250-videocc";
4369 power-domains = <&rpmhpd RPMHPD_MMCX>;
4370 required-opps = <&rpmhpd_opp_low_svs>;
4371 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
4372 #clock-cells = <1>;
4373 #reset-cells = <1>;
4374 #power-domain-cells = <1>;
4378 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4379 #address-cells = <1>;
4380 #size-cells = <0>;
4384 power-domains = <&camcc TITAN_TOP_GDSC>;
4391 clock-names = "camnoc_axi",
4397 pinctrl-0 = <&cci0_default>;
4398 pinctrl-1 = <&cci0_sleep>;
4399 pinctrl-names = "default", "sleep";
4403 cci0_i2c0: i2c-bus@0 {
4405 clock-frequency = <1000000>;
4406 #address-cells = <1>;
4407 #size-cells = <0>;
4410 cci0_i2c1: i2c-bus@1 {
4412 clock-frequency = <1000000>;
4413 #address-cells = <1>;
4414 #size-cells = <0>;
4419 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4420 #address-cells = <1>;
4421 #size-cells = <0>;
4425 power-domains = <&camcc TITAN_TOP_GDSC>;
4432 clock-names = "camnoc_axi",
4438 pinctrl-0 = <&cci1_default>;
4439 pinctrl-1 = <&cci1_sleep>;
4440 pinctrl-names = "default", "sleep";
4444 cci1_i2c0: i2c-bus@0 {
4446 clock-frequency = <1000000>;
4447 #address-cells = <1>;
4448 #size-cells = <0>;
4451 cci1_i2c1: i2c-bus@1 {
4453 clock-frequency = <1000000>;
4454 #address-cells = <1>;
4455 #size-cells = <0>;
4460 compatible = "qcom,sm8250-camss";
4473 reg-names = "csiphy0",
4498 interrupt-names = "csiphy0",
4513 power-domains = <&camcc IFE_0_GDSC>,
4555 clock-names = "cam_ahb_clk",
4606 interconnect-names = "cam_ahb",
4612 #address-cells = <1>;
4613 #size-cells = <0>;
4641 camcc: clock-controller@ad00000 {
4642 compatible = "qcom,sm8250-camcc";
4648 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
4649 power-domains = <&rpmhpd RPMHPD_MMCX>;
4650 required-opps = <&rpmhpd_opp_low_svs>;
4652 #clock-cells = <1>;
4653 #reset-cells = <1>;
4654 #power-domain-cells = <1>;
4657 mdss: display-subsystem@ae00000 {
4658 compatible = "qcom,sm8250-mdss";
4660 reg-names = "mdss";
4664 interconnect-names = "mdp0-mem", "mdp1-mem";
4666 power-domains = <&dispcc MDSS_GDSC>;
4672 clock-names = "iface", "bus", "nrt_bus", "core";
4675 interrupt-controller;
4676 #interrupt-cells = <1>;
4682 #address-cells = <2>;
4683 #size-cells = <2>;
4686 mdss_mdp: display-controller@ae01000 {
4687 compatible = "qcom,sm8250-dpu";
4690 reg-names = "mdp", "vbif";
4696 clock-names = "iface", "bus", "core", "vsync";
4698 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4699 assigned-clock-rates = <19200000>;
4701 operating-points-v2 = <&mdp_opp_table>;
4702 power-domains = <&rpmhpd RPMHPD_MMCX>;
4704 interrupt-parent = <&mdss>;
4708 #address-cells = <1>;
4709 #size-cells = <0>;
4714 remote-endpoint = <&mdss_dsi0_in>;
4721 remote-endpoint = <&mdss_dsi1_in>;
4729 remote-endpoint = <&mdss_dp_in>;
4734 mdp_opp_table: opp-table {
4735 compatible = "operating-points-v2";
4737 opp-200000000 {
4738 opp-hz = /bits/ 64 <200000000>;
4739 required-opps = <&rpmhpd_opp_low_svs>;
4742 opp-300000000 {
4743 opp-hz = /bits/ 64 <300000000>;
4744 required-opps = <&rpmhpd_opp_svs>;
4747 opp-345000000 {
4748 opp-hz = /bits/ 64 <345000000>;
4749 required-opps = <&rpmhpd_opp_svs_l1>;
4752 opp-460000000 {
4753 opp-hz = /bits/ 64 <460000000>;
4754 required-opps = <&rpmhpd_opp_nom>;
4759 mdss_dp: displayport-controller@ae90000 {
4760 compatible = "qcom,sm8250-dp", "qcom,sm8350-dp";
4766 interrupt-parent = <&mdss>;
4773 clock-names = "core_iface",
4779 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4781 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4785 phy-names = "dp";
4787 #sound-dai-cells = <0>;
4789 operating-points-v2 = <&dp_opp_table>;
4790 power-domains = <&rpmhpd SM8250_MMCX>;
4795 #address-cells = <1>;
4796 #size-cells = <0>;
4801 remote-endpoint = <&dpu_intf0_out>;
4813 dp_opp_table: opp-table {
4814 compatible = "operating-points-v2";
4816 opp-160000000 {
4817 opp-hz = /bits/ 64 <160000000>;
4818 required-opps = <&rpmhpd_opp_low_svs>;
4821 opp-270000000 {
4822 opp-hz = /bits/ 64 <270000000>;
4823 required-opps = <&rpmhpd_opp_svs>;
4826 opp-540000000 {
4827 opp-hz = /bits/ 64 <540000000>;
4828 required-opps = <&rpmhpd_opp_svs_l1>;
4831 opp-810000000 {
4832 opp-hz = /bits/ 64 <810000000>;
4833 required-opps = <&rpmhpd_opp_nom>;
4839 compatible = "qcom,sm8250-dsi-ctrl",
4840 "qcom,mdss-dsi-ctrl";
4842 reg-names = "dsi_ctrl";
4844 interrupt-parent = <&mdss>;
4853 clock-names = "byte",
4860 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4861 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
4863 operating-points-v2 = <&dsi_opp_table>;
4864 power-domains = <&rpmhpd RPMHPD_MMCX>;
4870 #address-cells = <1>;
4871 #size-cells = <0>;
4874 #address-cells = <1>;
4875 #size-cells = <0>;
4880 remote-endpoint = <&dpu_intf1_out>;
4891 dsi_opp_table: opp-table {
4892 compatible = "operating-points-v2";
4894 opp-187500000 {
4895 opp-hz = /bits/ 64 <187500000>;
4896 required-opps = <&rpmhpd_opp_low_svs>;
4899 opp-300000000 {
4900 opp-hz = /bits/ 64 <300000000>;
4901 required-opps = <&rpmhpd_opp_svs>;
4904 opp-358000000 {
4905 opp-hz = /bits/ 64 <358000000>;
4906 required-opps = <&rpmhpd_opp_svs_l1>;
4912 compatible = "qcom,dsi-phy-7nm";
4916 reg-names = "dsi_phy",
4920 #clock-cells = <1>;
4921 #phy-cells = <0>;
4925 clock-names = "iface", "ref";
4931 compatible = "qcom,sm8250-dsi-ctrl",
4932 "qcom,mdss-dsi-ctrl";
4934 reg-names = "dsi_ctrl";
4936 interrupt-parent = <&mdss>;
4945 clock-names = "byte",
4952 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4953 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
4955 operating-points-v2 = <&dsi_opp_table>;
4956 power-domains = <&rpmhpd RPMHPD_MMCX>;
4962 #address-cells = <1>;
4963 #size-cells = <0>;
4966 #address-cells = <1>;
4967 #size-cells = <0>;
4972 remote-endpoint = <&dpu_intf2_out>;
4985 compatible = "qcom,dsi-phy-7nm";
4989 reg-names = "dsi_phy",
4993 #clock-cells = <1>;
4994 #phy-cells = <0>;
4998 clock-names = "iface", "ref";
5004 dispcc: clock-controller@af00000 {
5005 compatible = "qcom,sm8250-dispcc";
5007 power-domains = <&rpmhpd RPMHPD_MMCX>;
5008 required-opps = <&rpmhpd_opp_low_svs>;
5016 clock-names = "bi_tcxo",
5023 #clock-cells = <1>;
5024 #reset-cells = <1>;
5025 #power-domain-cells = <1>;
5028 pdc: interrupt-controller@b220000 {
5029 compatible = "qcom,sm8250-pdc", "qcom,pdc";
5031 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
5033 #interrupt-cells = <2>;
5034 interrupt-parent = <&intc>;
5035 interrupt-controller;
5038 tsens0: thermal-sensor@c263000 {
5039 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5045 interrupt-names = "uplow", "critical";
5046 #thermal-sensor-cells = <1>;
5049 tsens1: thermal-sensor@c265000 {
5050 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5056 interrupt-names = "uplow", "critical";
5057 #thermal-sensor-cells = <1>;
5060 aoss_qmp: power-management@c300000 {
5061 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp";
5063 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
5069 #clock-cells = <0>;
5073 compatible = "qcom,rpmh-stats";
5078 compatible = "qcom,spmi-pmic-arb";
5084 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5085 interrupt-names = "periph_irq";
5086 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5089 #address-cells = <2>;
5090 #size-cells = <0>;
5091 interrupt-controller;
5092 #interrupt-cells = <4>;
5096 compatible = "qcom,sm8250-pinctrl";
5100 reg-names = "west", "south", "north";
5102 gpio-controller;
5103 #gpio-cells = <2>;
5104 interrupt-controller;
5105 #interrupt-cells = <2>;
5106 gpio-ranges = <&tlmm 0 0 181>;
5107 wakeup-parent = <&pdc>;
5109 cam2_default: cam2-default-state {
5110 rst-pins {
5113 drive-strength = <2>;
5114 bias-disable;
5117 mclk-pins {
5120 drive-strength = <16>;
5121 bias-disable;
5125 cam2_suspend: cam2-suspend-state {
5126 rst-pins {
5129 drive-strength = <2>;
5130 bias-pull-down;
5131 output-low;
5134 mclk-pins {
5137 drive-strength = <2>;
5138 bias-disable;
5142 cci0_default: cci0-default-state {
5143 cci0_i2c0_default: cci0-i2c0-default-pins {
5148 bias-pull-up;
5149 drive-strength = <2>; /* 2 mA */
5152 cci0_i2c1_default: cci0-i2c1-default-pins {
5157 bias-pull-up;
5158 drive-strength = <2>; /* 2 mA */
5162 cci0_sleep: cci0-sleep-state {
5163 cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
5168 drive-strength = <2>; /* 2 mA */
5169 bias-pull-down;
5172 cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
5177 drive-strength = <2>; /* 2 mA */
5178 bias-pull-down;
5182 cci1_default: cci1-default-state {
5183 cci1_i2c0_default: cci1-i2c0-default-pins {
5188 bias-pull-up;
5189 drive-strength = <2>; /* 2 mA */
5192 cci1_i2c1_default: cci1-i2c1-default-pins {
5197 bias-pull-up;
5198 drive-strength = <2>; /* 2 mA */
5202 cci1_sleep: cci1-sleep-state {
5203 cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
5208 bias-pull-down;
5209 drive-strength = <2>; /* 2 mA */
5212 cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
5217 bias-pull-down;
5218 drive-strength = <2>; /* 2 mA */
5222 pri_mi2s_active: pri-mi2s-active-state {
5223 sclk-pins {
5226 drive-strength = <8>;
5227 bias-disable;
5230 ws-pins {
5233 drive-strength = <8>;
5234 output-high;
5237 data0-pins {
5240 drive-strength = <8>;
5241 bias-disable;
5242 output-high;
5245 data1-pins {
5248 drive-strength = <8>;
5249 output-high;
5253 qup_i2c0_default: qup-i2c0-default-state {
5256 drive-strength = <2>;
5257 bias-disable;
5260 qup_i2c1_default: qup-i2c1-default-state {
5261 pins = "gpio4", "gpio5";
5263 drive-strength = <2>;
5264 bias-disable;
5267 qup_i2c2_default: qup-i2c2-default-state {
5270 drive-strength = <2>;
5271 bias-disable;
5274 qup_i2c3_default: qup-i2c3-default-state {
5277 drive-strength = <2>;
5278 bias-disable;
5281 qup_i2c4_default: qup-i2c4-default-state {
5284 drive-strength = <2>;
5285 bias-disable;
5288 qup_i2c5_default: qup-i2c5-default-state {
5291 drive-strength = <2>;
5292 bias-disable;
5295 qup_i2c6_default: qup-i2c6-default-state {
5298 drive-strength = <2>;
5299 bias-disable;
5302 qup_i2c7_default: qup-i2c7-default-state {
5305 drive-strength = <2>;
5306 bias-disable;
5309 qup_i2c8_default: qup-i2c8-default-state {
5312 drive-strength = <2>;
5313 bias-disable;
5316 qup_i2c9_default: qup-i2c9-default-state {
5319 drive-strength = <2>;
5320 bias-disable;
5323 qup_i2c10_default: qup-i2c10-default-state {
5326 drive-strength = <2>;
5327 bias-disable;
5330 qup_i2c11_default: qup-i2c11-default-state {
5333 drive-strength = <2>;
5334 bias-disable;
5337 qup_i2c12_default: qup-i2c12-default-state {
5340 drive-strength = <2>;
5341 bias-disable;
5344 qup_i2c13_default: qup-i2c13-default-state {
5347 drive-strength = <2>;
5348 bias-disable;
5351 qup_i2c14_default: qup-i2c14-default-state {
5354 drive-strength = <2>;
5355 bias-disable;
5358 qup_i2c15_default: qup-i2c15-default-state {
5361 drive-strength = <2>;
5362 bias-disable;
5365 qup_i2c16_default: qup-i2c16-default-state {
5368 drive-strength = <2>;
5369 bias-disable;
5372 qup_i2c17_default: qup-i2c17-default-state {
5375 drive-strength = <2>;
5376 bias-disable;
5379 qup_i2c18_default: qup-i2c18-default-state {
5382 drive-strength = <2>;
5383 bias-disable;
5386 qup_i2c19_default: qup-i2c19-default-state {
5389 drive-strength = <2>;
5390 bias-disable;
5393 qup_spi0_cs: qup-spi0-cs-state {
5398 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
5403 qup_spi0_data_clk: qup-spi0-data-clk-state {
5409 qup_spi1_cs: qup-spi1-cs-state {
5414 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
5419 qup_spi1_data_clk: qup-spi1-data-clk-state {
5420 pins = "gpio4", "gpio5",
5425 qup_spi2_cs: qup-spi2-cs-state {
5430 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
5435 qup_spi2_data_clk: qup-spi2-data-clk-state {
5441 qup_spi3_cs: qup-spi3-cs-state {
5446 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
5451 qup_spi3_data_clk: qup-spi3-data-clk-state {
5457 qup_spi4_cs: qup-spi4-cs-state {
5462 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
5467 qup_spi4_data_clk: qup-spi4-data-clk-state {
5473 qup_spi5_cs: qup-spi5-cs-state {
5478 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
5483 qup_spi5_data_clk: qup-spi5-data-clk-state {
5489 qup_spi6_cs: qup-spi6-cs-state {
5494 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
5499 qup_spi6_data_clk: qup-spi6-data-clk-state {
5505 qup_spi7_cs: qup-spi7-cs-state {
5510 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
5515 qup_spi7_data_clk: qup-spi7-data-clk-state {
5521 qup_spi8_cs: qup-spi8-cs-state {
5526 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
5531 qup_spi8_data_clk: qup-spi8-data-clk-state {
5537 qup_spi9_cs: qup-spi9-cs-state {
5542 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
5547 qup_spi9_data_clk: qup-spi9-data-clk-state {
5553 qup_spi10_cs: qup-spi10-cs-state {
5558 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
5563 qup_spi10_data_clk: qup-spi10-data-clk-state {
5569 qup_spi11_cs: qup-spi11-cs-state {
5574 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
5579 qup_spi11_data_clk: qup-spi11-data-clk-state {
5585 qup_spi12_cs: qup-spi12-cs-state {
5590 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
5595 qup_spi12_data_clk: qup-spi12-data-clk-state {
5601 qup_spi13_cs: qup-spi13-cs-state {
5606 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
5611 qup_spi13_data_clk: qup-spi13-data-clk-state {
5617 qup_spi14_cs: qup-spi14-cs-state {
5622 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
5627 qup_spi14_data_clk: qup-spi14-data-clk-state {
5633 qup_spi15_cs: qup-spi15-cs-state {
5638 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
5643 qup_spi15_data_clk: qup-spi15-data-clk-state {
5649 qup_spi16_cs: qup-spi16-cs-state {
5654 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state {
5659 qup_spi16_data_clk: qup-spi16-data-clk-state {
5665 qup_spi17_cs: qup-spi17-cs-state {
5670 qup_spi17_cs_gpio: qup-spi17-cs-gpio-state {
5675 qup_spi17_data_clk: qup-spi17-data-clk-state {
5681 qup_spi18_cs: qup-spi18-cs-state {
5686 qup_spi18_cs_gpio: qup-spi18-cs-gpio-state {
5691 qup_spi18_data_clk: qup-spi18-data-clk-state {
5697 qup_spi19_cs: qup-spi19-cs-state {
5702 qup_spi19_cs_gpio: qup-spi19-cs-gpio-state {
5707 qup_spi19_data_clk: qup-spi19-data-clk-state {
5713 qup_uart2_default: qup-uart2-default-state {
5718 qup_uart6_default: qup-uart6-default-state {
5723 qup_uart12_default: qup-uart12-default-state {
5728 qup_uart17_default: qup-uart17-default-state {
5733 qup_uart18_default: qup-uart18-default-state {
5738 tert_mi2s_active: tert-mi2s-active-state {
5739 sck-pins {
5742 drive-strength = <8>;
5743 bias-disable;
5746 data0-pins {
5749 drive-strength = <8>;
5750 bias-disable;
5751 output-high;
5754 ws-pins {
5757 drive-strength = <8>;
5758 output-high;
5762 sdc2_sleep_state: sdc2-sleep-state {
5763 clk-pins {
5765 drive-strength = <2>;
5766 bias-disable;
5769 cmd-pins {
5771 drive-strength = <2>;
5772 bias-pull-up;
5775 data-pins {
5777 drive-strength = <2>;
5778 bias-pull-up;
5782 pcie0_default_state: pcie0-default-state {
5783 perst-pins {
5786 drive-strength = <2>;
5787 bias-pull-down;
5790 clkreq-pins {
5793 drive-strength = <2>;
5794 bias-pull-up;
5797 wake-pins {
5800 drive-strength = <2>;
5801 bias-pull-up;
5805 pcie1_default_state: pcie1-default-state {
5806 perst-pins {
5809 drive-strength = <2>;
5810 bias-pull-down;
5813 clkreq-pins {
5816 drive-strength = <2>;
5817 bias-pull-up;
5820 wake-pins {
5823 drive-strength = <2>;
5824 bias-pull-up;
5828 pcie2_default_state: pcie2-default-state {
5829 perst-pins {
5832 drive-strength = <2>;
5833 bias-pull-down;
5836 clkreq-pins {
5839 drive-strength = <2>;
5840 bias-pull-up;
5843 wake-pins {
5846 drive-strength = <2>;
5847 bias-pull-up;
5853 compatible = "qcom,sm8250-smmu-500", "qcom,smmu-500", "arm,mmu-500";
5855 #iommu-cells = <2>;
5856 #global-interrupts = <2>;
5955 dma-coherent;
5959 compatible = "qcom,sm8250-adsp-pas";
5962 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
5967 interrupt-names = "wdog", "fatal", "ready",
5968 "handover", "stop-ack";
5971 clock-names = "xo";
5973 power-domains = <&rpmhpd RPMHPD_LCX>,
5975 power-domain-names = "lcx", "lmx";
5977 memory-region = <&adsp_mem>;
5981 qcom,smem-states = <&smp2p_adsp_out 0>;
5982 qcom,smem-state-names = "stop";
5986 glink-edge {
5987 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
5994 qcom,remote-pid = <2>;
5997 compatible = "qcom,apr-v2";
5998 qcom,glink-channels = "apr_audio_svc";
6000 #address-cells = <1>;
6001 #size-cells = <0>;
6006 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6012 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6014 compatible = "qcom,q6afe-dais";
6015 #address-cells = <1>;
6016 #size-cells = <0>;
6017 #sound-dai-cells = <1>;
6020 q6afecc: clock-controller {
6021 compatible = "qcom,q6afe-clocks";
6022 #clock-cells = <2>;
6029 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6031 compatible = "qcom,q6asm-dais";
6032 #address-cells = <1>;
6033 #size-cells = <0>;
6034 #sound-dai-cells = <1>;
6042 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6044 compatible = "qcom,q6adm-routing";
6045 #sound-dai-cells = <0>;
6052 qcom,glink-channels = "fastrpcglink-apps-dsp";
6054 qcom,non-secure-domain;
6055 #address-cells = <1>;
6056 #size-cells = <0>;
6058 compute-cb@3 {
6059 compatible = "qcom,fastrpc-compute-cb";
6064 compute-cb@4 {
6065 compatible = "qcom,fastrpc-compute-cb";
6070 compute-cb@5 {
6071 compatible = "qcom,fastrpc-compute-cb";
6079 intc: interrupt-controller@17a00000 {
6080 compatible = "arm,gic-v3";
6081 #interrupt-cells = <3>;
6082 interrupt-controller;
6089 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
6096 #address-cells = <1>;
6097 #size-cells = <1>;
6099 compatible = "arm,armv7-timer-mem";
6101 clock-frequency = <19200000>;
6104 frame-number = <0>;
6112 frame-number = <1>;
6119 frame-number = <2>;
6126 frame-number = <3>;
6133 frame-number = <4>;
6140 frame-number = <5>;
6147 frame-number = <6>;
6156 compatible = "qcom,rpmh-rsc";
6160 reg-names = "drv-0", "drv-1", "drv-2";
6164 qcom,tcs-offset = <0xd00>;
6165 qcom,drv-id = <2>;
6166 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
6168 power-domains = <&cluster_pd>;
6170 rpmhcc: clock-controller {
6171 compatible = "qcom,sm8250-rpmh-clk";
6172 #clock-cells = <1>;
6173 clock-names = "xo";
6177 rpmhpd: power-controller {
6178 compatible = "qcom,sm8250-rpmhpd";
6179 #power-domain-cells = <1>;
6180 operating-points-v2 = <&rpmhpd_opp_table>;
6182 rpmhpd_opp_table: opp-table {
6183 compatible = "operating-points-v2";
6186 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
6190 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
6194 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
6198 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
6202 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
6206 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
6210 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
6214 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
6218 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
6222 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
6227 apps_bcm_voter: bcm-voter {
6228 compatible = "qcom,bcm-voter";
6233 compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3";
6237 clock-names = "xo", "alternate";
6239 #interconnect-cells = <1>;
6243 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
6247 reg-names = "freq-domain0", "freq-domain1",
6248 "freq-domain2";
6251 clock-names = "xo", "alternate";
6255 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
6256 #freq-domain-cells = <1>;
6257 #clock-cells = <1>;
6265 compatible = "arm,armv8-timer";
6276 thermal-zones {
6277 cpu0-thermal {
6278 polling-delay-passive = <250>;
6280 thermal-sensors = <&tsens0 1>;
6283 cpu0_alert0: trip-point0 {
6289 cpu0_alert1: trip-point1 {
6295 cpu0_crit: cpu-crit {
6302 cooling-maps {
6305 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6312 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6320 cpu1-thermal {
6321 polling-delay-passive = <250>;
6323 thermal-sensors = <&tsens0 2>;
6326 cpu1_alert0: trip-point0 {
6332 cpu1_alert1: trip-point1 {
6338 cpu1_crit: cpu-crit {
6345 cooling-maps {
6348 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6355 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6363 cpu2-thermal {
6364 polling-delay-passive = <250>;
6366 thermal-sensors = <&tsens0 3>;
6369 cpu2_alert0: trip-point0 {
6375 cpu2_alert1: trip-point1 {
6381 cpu2_crit: cpu-crit {
6388 cooling-maps {
6391 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6398 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6406 cpu3-thermal {
6407 polling-delay-passive = <250>;
6409 thermal-sensors = <&tsens0 4>;
6412 cpu3_alert0: trip-point0 {
6418 cpu3_alert1: trip-point1 {
6424 cpu3_crit: cpu-crit {
6431 cooling-maps {
6434 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6441 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6449 cpu4-top-thermal {
6450 polling-delay-passive = <250>;
6452 thermal-sensors = <&tsens0 7>;
6455 cpu4_top_alert0: trip-point0 {
6461 cpu4_top_alert1: trip-point1 {
6467 cpu4_top_crit: cpu-crit {
6474 cooling-maps {
6477 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6484 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6492 cpu5-top-thermal {
6493 polling-delay-passive = <250>;
6495 thermal-sensors = <&tsens0 8>;
6498 cpu5_top_alert0: trip-point0 {
6504 cpu5_top_alert1: trip-point1 {
6510 cpu5_top_crit: cpu-crit {
6517 cooling-maps {
6520 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6527 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6535 cpu6-top-thermal {
6536 polling-delay-passive = <250>;
6538 thermal-sensors = <&tsens0 9>;
6541 cpu6_top_alert0: trip-point0 {
6547 cpu6_top_alert1: trip-point1 {
6553 cpu6_top_crit: cpu-crit {
6560 cooling-maps {
6563 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6570 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6578 cpu7-top-thermal {
6579 polling-delay-passive = <250>;
6581 thermal-sensors = <&tsens0 10>;
6584 cpu7_top_alert0: trip-point0 {
6590 cpu7_top_alert1: trip-point1 {
6596 cpu7_top_crit: cpu-crit {
6603 cooling-maps {
6606 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6613 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6621 cpu4-bottom-thermal {
6622 polling-delay-passive = <250>;
6624 thermal-sensors = <&tsens0 11>;
6627 cpu4_bottom_alert0: trip-point0 {
6633 cpu4_bottom_alert1: trip-point1 {
6639 cpu4_bottom_crit: cpu-crit {
6646 cooling-maps {
6649 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6656 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6664 cpu5-bottom-thermal {
6665 polling-delay-passive = <250>;
6667 thermal-sensors = <&tsens0 12>;
6670 cpu5_bottom_alert0: trip-point0 {
6676 cpu5_bottom_alert1: trip-point1 {
6682 cpu5_bottom_crit: cpu-crit {
6689 cooling-maps {
6692 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6699 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6707 cpu6-bottom-thermal {
6708 polling-delay-passive = <250>;
6710 thermal-sensors = <&tsens0 13>;
6713 cpu6_bottom_alert0: trip-point0 {
6719 cpu6_bottom_alert1: trip-point1 {
6725 cpu6_bottom_crit: cpu-crit {
6732 cooling-maps {
6735 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6742 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6750 cpu7-bottom-thermal {
6751 polling-delay-passive = <250>;
6753 thermal-sensors = <&tsens0 14>;
6756 cpu7_bottom_alert0: trip-point0 {
6762 cpu7_bottom_alert1: trip-point1 {
6768 cpu7_bottom_crit: cpu-crit {
6775 cooling-maps {
6778 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6785 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6793 aoss0-thermal {
6794 polling-delay-passive = <250>;
6796 thermal-sensors = <&tsens0 0>;
6799 aoss0_alert0: trip-point0 {
6807 cluster0-thermal {
6808 polling-delay-passive = <250>;
6810 thermal-sensors = <&tsens0 5>;
6813 cluster0_alert0: trip-point0 {
6818 cluster0_crit: cluster0-crit {
6826 cluster1-thermal {
6827 polling-delay-passive = <250>;
6829 thermal-sensors = <&tsens0 6>;
6832 cluster1_alert0: trip-point0 {
6837 cluster1_crit: cluster1-crit {
6845 gpu-top-thermal {
6846 polling-delay-passive = <250>;
6848 thermal-sensors = <&tsens0 15>;
6850 cooling-maps {
6853 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6858 gpu_top_alert0: trip-point0 {
6864 trip-point1 {
6870 trip-point2 {
6878 aoss1-thermal {
6879 polling-delay-passive = <250>;
6881 thermal-sensors = <&tsens1 0>;
6884 aoss1_alert0: trip-point0 {
6892 wlan-thermal {
6893 polling-delay-passive = <250>;
6895 thermal-sensors = <&tsens1 1>;
6898 wlan_alert0: trip-point0 {
6906 video-thermal {
6907 polling-delay-passive = <250>;
6909 thermal-sensors = <&tsens1 2>;
6912 video_alert0: trip-point0 {
6920 mem-thermal {
6921 polling-delay-passive = <250>;
6923 thermal-sensors = <&tsens1 3>;
6926 mem_alert0: trip-point0 {
6934 q6-hvx-thermal {
6935 polling-delay-passive = <250>;
6937 thermal-sensors = <&tsens1 4>;
6940 q6_hvx_alert0: trip-point0 {
6948 camera-thermal {
6949 polling-delay-passive = <250>;
6951 thermal-sensors = <&tsens1 5>;
6954 camera_alert0: trip-point0 {
6962 compute-thermal {
6963 polling-delay-passive = <250>;
6965 thermal-sensors = <&tsens1 6>;
6968 compute_alert0: trip-point0 {
6976 npu-thermal {
6977 polling-delay-passive = <250>;
6979 thermal-sensors = <&tsens1 7>;
6982 npu_alert0: trip-point0 {
6990 gpu-bottom-thermal {
6991 polling-delay-passive = <250>;
6993 thermal-sensors = <&tsens1 8>;
6995 cooling-maps {
6998 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
7003 gpu_bottom_alert0: trip-point0 {
7009 trip-point1 {
7015 trip-point2 {