Lines Matching +full:sm8150 +full:- +full:dsi +full:- +full:ctrl
1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/dma/qcom-gpi.h>
8 #include <dt-bindings/firmware/qcom,scm.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/phy/phy-qcom-qmp.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,dispcc-sm8150.h>
15 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
16 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
17 #include <dt-bindings/clock/qcom,videocc-sm8150.h>
18 #include <dt-bindings/interconnect/qcom,osm-l3.h>
19 #include <dt-bindings/interconnect/qcom,sm8150.h>
20 #include <dt-bindings/clock/qcom,sm8150-camcc.h>
21 #include <dt-bindings/thermal/thermal.h>
24 interrupt-parent = <&intc>;
26 #address-cells = <2>;
27 #size-cells = <2>;
32 xo_board: xo-board {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
35 clock-frequency = <38400000>;
36 clock-output-names = "xo_board";
39 sleep_clk: sleep-clk {
40 compatible = "fixed-clock";
41 #clock-cells = <0>;
42 clock-frequency = <32764>;
43 clock-output-names = "sleep_clk";
48 #address-cells = <2>;
49 #size-cells = <0>;
56 enable-method = "psci";
57 capacity-dmips-mhz = <488>;
58 dynamic-power-coefficient = <232>;
59 next-level-cache = <&l2_0>;
60 qcom,freq-domain = <&cpufreq_hw 0>;
61 operating-points-v2 = <&cpu0_opp_table>;
64 power-domains = <&cpu_pd0>;
65 power-domain-names = "psci";
66 #cooling-cells = <2>;
67 l2_0: l2-cache {
69 cache-level = <2>;
70 cache-unified;
71 next-level-cache = <&l3_0>;
72 l3_0: l3-cache {
74 cache-level = <3>;
75 cache-unified;
85 enable-method = "psci";
86 capacity-dmips-mhz = <488>;
87 dynamic-power-coefficient = <232>;
88 next-level-cache = <&l2_100>;
89 qcom,freq-domain = <&cpufreq_hw 0>;
90 operating-points-v2 = <&cpu0_opp_table>;
93 power-domains = <&cpu_pd1>;
94 power-domain-names = "psci";
95 #cooling-cells = <2>;
96 l2_100: l2-cache {
98 cache-level = <2>;
99 cache-unified;
100 next-level-cache = <&l3_0>;
109 enable-method = "psci";
110 capacity-dmips-mhz = <488>;
111 dynamic-power-coefficient = <232>;
112 next-level-cache = <&l2_200>;
113 qcom,freq-domain = <&cpufreq_hw 0>;
114 operating-points-v2 = <&cpu0_opp_table>;
117 power-domains = <&cpu_pd2>;
118 power-domain-names = "psci";
119 #cooling-cells = <2>;
120 l2_200: l2-cache {
122 cache-level = <2>;
123 cache-unified;
124 next-level-cache = <&l3_0>;
133 enable-method = "psci";
134 capacity-dmips-mhz = <488>;
135 dynamic-power-coefficient = <232>;
136 next-level-cache = <&l2_300>;
137 qcom,freq-domain = <&cpufreq_hw 0>;
138 operating-points-v2 = <&cpu0_opp_table>;
141 power-domains = <&cpu_pd3>;
142 power-domain-names = "psci";
143 #cooling-cells = <2>;
144 l2_300: l2-cache {
146 cache-level = <2>;
147 cache-unified;
148 next-level-cache = <&l3_0>;
157 enable-method = "psci";
158 capacity-dmips-mhz = <1024>;
159 dynamic-power-coefficient = <369>;
160 next-level-cache = <&l2_400>;
161 qcom,freq-domain = <&cpufreq_hw 1>;
162 operating-points-v2 = <&cpu4_opp_table>;
165 power-domains = <&cpu_pd4>;
166 power-domain-names = "psci";
167 #cooling-cells = <2>;
168 l2_400: l2-cache {
170 cache-level = <2>;
171 cache-unified;
172 next-level-cache = <&l3_0>;
181 enable-method = "psci";
182 capacity-dmips-mhz = <1024>;
183 dynamic-power-coefficient = <369>;
184 next-level-cache = <&l2_500>;
185 qcom,freq-domain = <&cpufreq_hw 1>;
186 operating-points-v2 = <&cpu4_opp_table>;
189 power-domains = <&cpu_pd5>;
190 power-domain-names = "psci";
191 #cooling-cells = <2>;
192 l2_500: l2-cache {
194 cache-level = <2>;
195 cache-unified;
196 next-level-cache = <&l3_0>;
205 enable-method = "psci";
206 capacity-dmips-mhz = <1024>;
207 dynamic-power-coefficient = <369>;
208 next-level-cache = <&l2_600>;
209 qcom,freq-domain = <&cpufreq_hw 1>;
210 operating-points-v2 = <&cpu4_opp_table>;
213 power-domains = <&cpu_pd6>;
214 power-domain-names = "psci";
215 #cooling-cells = <2>;
216 l2_600: l2-cache {
218 cache-level = <2>;
219 cache-unified;
220 next-level-cache = <&l3_0>;
229 enable-method = "psci";
230 capacity-dmips-mhz = <1024>;
231 dynamic-power-coefficient = <421>;
232 next-level-cache = <&l2_700>;
233 qcom,freq-domain = <&cpufreq_hw 2>;
234 operating-points-v2 = <&cpu7_opp_table>;
237 power-domains = <&cpu_pd7>;
238 power-domain-names = "psci";
239 #cooling-cells = <2>;
240 l2_700: l2-cache {
242 cache-level = <2>;
243 cache-unified;
244 next-level-cache = <&l3_0>;
248 cpu-map {
284 idle-states {
285 entry-method = "psci";
287 little_cpu_sleep_0: cpu-sleep-0-0 {
288 compatible = "arm,idle-state";
289 idle-state-name = "little-rail-power-collapse";
290 arm,psci-suspend-param = <0x40000004>;
291 entry-latency-us = <355>;
292 exit-latency-us = <909>;
293 min-residency-us = <3934>;
294 local-timer-stop;
297 big_cpu_sleep_0: cpu-sleep-1-0 {
298 compatible = "arm,idle-state";
299 idle-state-name = "big-rail-power-collapse";
300 arm,psci-suspend-param = <0x40000004>;
301 entry-latency-us = <241>;
302 exit-latency-us = <1461>;
303 min-residency-us = <4488>;
304 local-timer-stop;
308 domain-idle-states {
309 cluster_sleep_0: cluster-sleep-0 {
310 compatible = "domain-idle-state";
311 arm,psci-suspend-param = <0x4100c244>;
312 entry-latency-us = <3263>;
313 exit-latency-us = <6562>;
314 min-residency-us = <9987>;
319 cpu0_opp_table: opp-table-cpu0 {
320 compatible = "operating-points-v2";
321 opp-shared;
323 cpu0_opp1: opp-300000000 {
324 opp-hz = /bits/ 64 <300000000>;
325 opp-peak-kBps = <800000 9600000>;
328 cpu0_opp2: opp-403200000 {
329 opp-hz = /bits/ 64 <403200000>;
330 opp-peak-kBps = <800000 9600000>;
333 cpu0_opp3: opp-499200000 {
334 opp-hz = /bits/ 64 <499200000>;
335 opp-peak-kBps = <800000 12902400>;
338 cpu0_opp4: opp-576000000 {
339 opp-hz = /bits/ 64 <576000000>;
340 opp-peak-kBps = <800000 12902400>;
343 cpu0_opp5: opp-672000000 {
344 opp-hz = /bits/ 64 <672000000>;
345 opp-peak-kBps = <800000 15974400>;
348 cpu0_opp6: opp-768000000 {
349 opp-hz = /bits/ 64 <768000000>;
350 opp-peak-kBps = <1804000 19660800>;
353 cpu0_opp7: opp-844800000 {
354 opp-hz = /bits/ 64 <844800000>;
355 opp-peak-kBps = <1804000 19660800>;
358 cpu0_opp8: opp-940800000 {
359 opp-hz = /bits/ 64 <940800000>;
360 opp-peak-kBps = <1804000 22732800>;
363 cpu0_opp9: opp-1036800000 {
364 opp-hz = /bits/ 64 <1036800000>;
365 opp-peak-kBps = <1804000 22732800>;
368 cpu0_opp10: opp-1113600000 {
369 opp-hz = /bits/ 64 <1113600000>;
370 opp-peak-kBps = <2188000 25804800>;
373 cpu0_opp11: opp-1209600000 {
374 opp-hz = /bits/ 64 <1209600000>;
375 opp-peak-kBps = <2188000 31948800>;
378 cpu0_opp12: opp-1305600000 {
379 opp-hz = /bits/ 64 <1305600000>;
380 opp-peak-kBps = <3072000 31948800>;
383 cpu0_opp13: opp-1382400000 {
384 opp-hz = /bits/ 64 <1382400000>;
385 opp-peak-kBps = <3072000 31948800>;
388 cpu0_opp14: opp-1478400000 {
389 opp-hz = /bits/ 64 <1478400000>;
390 opp-peak-kBps = <3072000 31948800>;
393 cpu0_opp15: opp-1555200000 {
394 opp-hz = /bits/ 64 <1555200000>;
395 opp-peak-kBps = <3072000 40550400>;
398 cpu0_opp16: opp-1632000000 {
399 opp-hz = /bits/ 64 <1632000000>;
400 opp-peak-kBps = <3072000 40550400>;
403 cpu0_opp17: opp-1708800000 {
404 opp-hz = /bits/ 64 <1708800000>;
405 opp-peak-kBps = <3072000 43008000>;
408 cpu0_opp18: opp-1785600000 {
409 opp-hz = /bits/ 64 <1785600000>;
410 opp-peak-kBps = <3072000 43008000>;
414 cpu4_opp_table: opp-table-cpu4 {
415 compatible = "operating-points-v2";
416 opp-shared;
418 cpu4_opp1: opp-710400000 {
419 opp-hz = /bits/ 64 <710400000>;
420 opp-peak-kBps = <1804000 15974400>;
423 cpu4_opp2: opp-825600000 {
424 opp-hz = /bits/ 64 <825600000>;
425 opp-peak-kBps = <2188000 19660800>;
428 cpu4_opp3: opp-940800000 {
429 opp-hz = /bits/ 64 <940800000>;
430 opp-peak-kBps = <2188000 22732800>;
433 cpu4_opp4: opp-1056000000 {
434 opp-hz = /bits/ 64 <1056000000>;
435 opp-peak-kBps = <3072000 25804800>;
438 cpu4_opp5: opp-1171200000 {
439 opp-hz = /bits/ 64 <1171200000>;
440 opp-peak-kBps = <3072000 31948800>;
443 cpu4_opp6: opp-1286400000 {
444 opp-hz = /bits/ 64 <1286400000>;
445 opp-peak-kBps = <4068000 31948800>;
448 cpu4_opp7: opp-1401600000 {
449 opp-hz = /bits/ 64 <1401600000>;
450 opp-peak-kBps = <4068000 31948800>;
453 cpu4_opp8: opp-1497600000 {
454 opp-hz = /bits/ 64 <1497600000>;
455 opp-peak-kBps = <4068000 40550400>;
458 cpu4_opp9: opp-1612800000 {
459 opp-hz = /bits/ 64 <1612800000>;
460 opp-peak-kBps = <4068000 40550400>;
463 cpu4_opp10: opp-1708800000 {
464 opp-hz = /bits/ 64 <1708800000>;
465 opp-peak-kBps = <4068000 43008000>;
468 cpu4_opp11: opp-1804800000 {
469 opp-hz = /bits/ 64 <1804800000>;
470 opp-peak-kBps = <6220000 43008000>;
473 cpu4_opp12: opp-1920000000 {
474 opp-hz = /bits/ 64 <1920000000>;
475 opp-peak-kBps = <6220000 49152000>;
478 cpu4_opp13: opp-2016000000 {
479 opp-hz = /bits/ 64 <2016000000>;
480 opp-peak-kBps = <7216000 49152000>;
483 cpu4_opp14: opp-2131200000 {
484 opp-hz = /bits/ 64 <2131200000>;
485 opp-peak-kBps = <8368000 49152000>;
488 cpu4_opp15: opp-2227200000 {
489 opp-hz = /bits/ 64 <2227200000>;
490 opp-peak-kBps = <8368000 51609600>;
493 cpu4_opp16: opp-2323200000 {
494 opp-hz = /bits/ 64 <2323200000>;
495 opp-peak-kBps = <8368000 51609600>;
498 cpu4_opp17: opp-2419200000 {
499 opp-hz = /bits/ 64 <2419200000>;
500 opp-peak-kBps = <8368000 51609600>;
504 cpu7_opp_table: opp-table-cpu7 {
505 compatible = "operating-points-v2";
506 opp-shared;
508 cpu7_opp1: opp-825600000 {
509 opp-hz = /bits/ 64 <825600000>;
510 opp-peak-kBps = <2188000 19660800>;
513 cpu7_opp2: opp-940800000 {
514 opp-hz = /bits/ 64 <940800000>;
515 opp-peak-kBps = <2188000 22732800>;
518 cpu7_opp3: opp-1056000000 {
519 opp-hz = /bits/ 64 <1056000000>;
520 opp-peak-kBps = <3072000 25804800>;
523 cpu7_opp4: opp-1171200000 {
524 opp-hz = /bits/ 64 <1171200000>;
525 opp-peak-kBps = <3072000 31948800>;
528 cpu7_opp5: opp-1286400000 {
529 opp-hz = /bits/ 64 <1286400000>;
530 opp-peak-kBps = <4068000 31948800>;
533 cpu7_opp6: opp-1401600000 {
534 opp-hz = /bits/ 64 <1401600000>;
535 opp-peak-kBps = <4068000 31948800>;
538 cpu7_opp7: opp-1497600000 {
539 opp-hz = /bits/ 64 <1497600000>;
540 opp-peak-kBps = <4068000 40550400>;
543 cpu7_opp8: opp-1612800000 {
544 opp-hz = /bits/ 64 <1612800000>;
545 opp-peak-kBps = <4068000 40550400>;
548 cpu7_opp9: opp-1708800000 {
549 opp-hz = /bits/ 64 <1708800000>;
550 opp-peak-kBps = <4068000 43008000>;
553 cpu7_opp10: opp-1804800000 {
554 opp-hz = /bits/ 64 <1804800000>;
555 opp-peak-kBps = <6220000 43008000>;
558 cpu7_opp11: opp-1920000000 {
559 opp-hz = /bits/ 64 <1920000000>;
560 opp-peak-kBps = <6220000 49152000>;
563 cpu7_opp12: opp-2016000000 {
564 opp-hz = /bits/ 64 <2016000000>;
565 opp-peak-kBps = <7216000 49152000>;
568 cpu7_opp13: opp-2131200000 {
569 opp-hz = /bits/ 64 <2131200000>;
570 opp-peak-kBps = <8368000 49152000>;
573 cpu7_opp14: opp-2227200000 {
574 opp-hz = /bits/ 64 <2227200000>;
575 opp-peak-kBps = <8368000 51609600>;
578 cpu7_opp15: opp-2323200000 {
579 opp-hz = /bits/ 64 <2323200000>;
580 opp-peak-kBps = <8368000 51609600>;
583 cpu7_opp16: opp-2419200000 {
584 opp-hz = /bits/ 64 <2419200000>;
585 opp-peak-kBps = <8368000 51609600>;
588 cpu7_opp17: opp-2534400000 {
589 opp-hz = /bits/ 64 <2534400000>;
590 opp-peak-kBps = <8368000 51609600>;
593 cpu7_opp18: opp-2649600000 {
594 opp-hz = /bits/ 64 <2649600000>;
595 opp-peak-kBps = <8368000 51609600>;
598 cpu7_opp19: opp-2745600000 {
599 opp-hz = /bits/ 64 <2745600000>;
600 opp-peak-kBps = <8368000 51609600>;
603 cpu7_opp20: opp-2841600000 {
604 opp-hz = /bits/ 64 <2841600000>;
605 opp-peak-kBps = <8368000 51609600>;
611 compatible = "qcom,scm-sm8150", "qcom,scm";
612 #reset-cells = <1>;
623 compatible = "arm,armv8-pmuv3";
628 compatible = "arm,psci-1.0";
631 cpu_pd0: power-domain-cpu0 {
632 #power-domain-cells = <0>;
633 power-domains = <&cluster_pd>;
634 domain-idle-states = <&little_cpu_sleep_0>;
637 cpu_pd1: power-domain-cpu1 {
638 #power-domain-cells = <0>;
639 power-domains = <&cluster_pd>;
640 domain-idle-states = <&little_cpu_sleep_0>;
643 cpu_pd2: power-domain-cpu2 {
644 #power-domain-cells = <0>;
645 power-domains = <&cluster_pd>;
646 domain-idle-states = <&little_cpu_sleep_0>;
649 cpu_pd3: power-domain-cpu3 {
650 #power-domain-cells = <0>;
651 power-domains = <&cluster_pd>;
652 domain-idle-states = <&little_cpu_sleep_0>;
655 cpu_pd4: power-domain-cpu4 {
656 #power-domain-cells = <0>;
657 power-domains = <&cluster_pd>;
658 domain-idle-states = <&big_cpu_sleep_0>;
661 cpu_pd5: power-domain-cpu5 {
662 #power-domain-cells = <0>;
663 power-domains = <&cluster_pd>;
664 domain-idle-states = <&big_cpu_sleep_0>;
667 cpu_pd6: power-domain-cpu6 {
668 #power-domain-cells = <0>;
669 power-domains = <&cluster_pd>;
670 domain-idle-states = <&big_cpu_sleep_0>;
673 cpu_pd7: power-domain-cpu7 {
674 #power-domain-cells = <0>;
675 power-domains = <&cluster_pd>;
676 domain-idle-states = <&big_cpu_sleep_0>;
679 cluster_pd: power-domain-cpu-cluster0 {
680 #power-domain-cells = <0>;
681 domain-idle-states = <&cluster_sleep_0>;
685 reserved-memory {
686 #address-cells = <2>;
687 #size-cells = <2>;
692 no-map;
697 no-map;
702 no-map;
706 compatible = "qcom,cmd-db";
708 no-map;
713 no-map;
718 no-map;
722 compatible = "qcom,rmtfs-mem";
724 no-map;
726 qcom,client-id = <1>;
732 no-map;
737 no-map;
742 no-map;
747 no-map;
752 no-map;
757 no-map;
762 no-map;
767 no-map;
772 no-map;
777 no-map;
782 no-map;
787 no-map;
792 no-map;
798 memory-region = <&smem_mem>;
802 smp2p-cdsp {
810 qcom,local-pid = <0>;
811 qcom,remote-pid = <5>;
813 cdsp_smp2p_out: master-kernel {
814 qcom,entry-name = "master-kernel";
815 #qcom,smem-state-cells = <1>;
818 cdsp_smp2p_in: slave-kernel {
819 qcom,entry-name = "slave-kernel";
821 interrupt-controller;
822 #interrupt-cells = <2>;
826 smp2p-lpass {
834 qcom,local-pid = <0>;
835 qcom,remote-pid = <2>;
837 adsp_smp2p_out: master-kernel {
838 qcom,entry-name = "master-kernel";
839 #qcom,smem-state-cells = <1>;
842 adsp_smp2p_in: slave-kernel {
843 qcom,entry-name = "slave-kernel";
845 interrupt-controller;
846 #interrupt-cells = <2>;
850 smp2p-mpss {
858 qcom,local-pid = <0>;
859 qcom,remote-pid = <1>;
861 modem_smp2p_out: master-kernel {
862 qcom,entry-name = "master-kernel";
863 #qcom,smem-state-cells = <1>;
866 modem_smp2p_in: slave-kernel {
867 qcom,entry-name = "slave-kernel";
869 interrupt-controller;
870 #interrupt-cells = <2>;
874 smp2p-slpi {
882 qcom,local-pid = <0>;
883 qcom,remote-pid = <3>;
885 slpi_smp2p_out: master-kernel {
886 qcom,entry-name = "master-kernel";
887 #qcom,smem-state-cells = <1>;
890 slpi_smp2p_in: slave-kernel {
891 qcom,entry-name = "slave-kernel";
893 interrupt-controller;
894 #interrupt-cells = <2>;
899 #address-cells = <2>;
900 #size-cells = <2>;
902 dma-ranges = <0 0 0 0 0x10 0>;
903 compatible = "simple-bus";
905 gcc: clock-controller@100000 {
906 compatible = "qcom,gcc-sm8150";
908 #clock-cells = <1>;
909 #reset-cells = <1>;
910 #power-domain-cells = <1>;
911 clock-names = "bi_tcxo",
917 gpi_dma0: dma-controller@800000 {
918 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
933 dma-channels = <13>;
934 dma-channel-mask = <0xfa>;
936 #dma-cells = <3>;
941 compatible = "qcom,sm8150-ethqos";
944 reg-names = "stmmaceth", "rgmii";
945 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
952 interrupt-names = "macirq", "eth_lpi";
954 power-domains = <&gcc EMAC_GDSC>;
960 rx-fifo-depth = <4096>;
961 tx-fifo-depth = <4096>;
967 compatible = "qcom,sm8150-qfprom", "qcom,qfprom";
969 #address-cells = <1>;
970 #size-cells = <1>;
972 gpu_speed_bin: gpu-speed-bin@133 {
979 compatible = "qcom,geni-se-qup";
981 clock-names = "m-ahb", "s-ahb";
985 #address-cells = <2>;
986 #size-cells = <2>;
991 compatible = "qcom,geni-i2c";
993 clock-names = "se";
997 dma-names = "tx", "rx";
998 pinctrl-names = "default";
999 pinctrl-0 = <&qup_i2c0_default>;
1001 #address-cells = <1>;
1002 #size-cells = <0>;
1007 compatible = "qcom,geni-spi";
1009 reg-names = "se";
1010 clock-names = "se";
1014 dma-names = "tx", "rx";
1015 pinctrl-names = "default";
1016 pinctrl-0 = <&qup_spi0_default>;
1018 spi-max-frequency = <50000000>;
1019 #address-cells = <1>;
1020 #size-cells = <0>;
1025 compatible = "qcom,geni-i2c";
1027 clock-names = "se";
1031 dma-names = "tx", "rx";
1032 pinctrl-names = "default";
1033 pinctrl-0 = <&qup_i2c1_default>;
1035 #address-cells = <1>;
1036 #size-cells = <0>;
1041 compatible = "qcom,geni-spi";
1043 reg-names = "se";
1044 clock-names = "se";
1048 dma-names = "tx", "rx";
1049 pinctrl-names = "default";
1050 pinctrl-0 = <&qup_spi1_default>;
1052 spi-max-frequency = <50000000>;
1053 #address-cells = <1>;
1054 #size-cells = <0>;
1059 compatible = "qcom,geni-i2c";
1061 clock-names = "se";
1065 dma-names = "tx", "rx";
1066 pinctrl-names = "default";
1067 pinctrl-0 = <&qup_i2c2_default>;
1069 #address-cells = <1>;
1070 #size-cells = <0>;
1075 compatible = "qcom,geni-spi";
1077 reg-names = "se";
1078 clock-names = "se";
1082 dma-names = "tx", "rx";
1083 pinctrl-names = "default";
1084 pinctrl-0 = <&qup_spi2_default>;
1086 spi-max-frequency = <50000000>;
1087 #address-cells = <1>;
1088 #size-cells = <0>;
1093 compatible = "qcom,geni-i2c";
1095 clock-names = "se";
1099 dma-names = "tx", "rx";
1100 pinctrl-names = "default";
1101 pinctrl-0 = <&qup_i2c3_default>;
1103 #address-cells = <1>;
1104 #size-cells = <0>;
1109 compatible = "qcom,geni-spi";
1111 reg-names = "se";
1112 clock-names = "se";
1116 dma-names = "tx", "rx";
1117 pinctrl-names = "default";
1118 pinctrl-0 = <&qup_spi3_default>;
1120 spi-max-frequency = <50000000>;
1121 #address-cells = <1>;
1122 #size-cells = <0>;
1127 compatible = "qcom,geni-i2c";
1129 clock-names = "se";
1133 dma-names = "tx", "rx";
1134 pinctrl-names = "default";
1135 pinctrl-0 = <&qup_i2c4_default>;
1137 #address-cells = <1>;
1138 #size-cells = <0>;
1143 compatible = "qcom,geni-spi";
1145 reg-names = "se";
1146 clock-names = "se";
1150 dma-names = "tx", "rx";
1151 pinctrl-names = "default";
1152 pinctrl-0 = <&qup_spi4_default>;
1154 spi-max-frequency = <50000000>;
1155 #address-cells = <1>;
1156 #size-cells = <0>;
1161 compatible = "qcom,geni-i2c";
1163 clock-names = "se";
1167 dma-names = "tx", "rx";
1168 pinctrl-names = "default";
1169 pinctrl-0 = <&qup_i2c5_default>;
1171 #address-cells = <1>;
1172 #size-cells = <0>;
1177 compatible = "qcom,geni-spi";
1179 reg-names = "se";
1180 clock-names = "se";
1184 dma-names = "tx", "rx";
1185 pinctrl-names = "default";
1186 pinctrl-0 = <&qup_spi5_default>;
1188 spi-max-frequency = <50000000>;
1189 #address-cells = <1>;
1190 #size-cells = <0>;
1195 compatible = "qcom,geni-i2c";
1197 clock-names = "se";
1201 dma-names = "tx", "rx";
1202 pinctrl-names = "default";
1203 pinctrl-0 = <&qup_i2c6_default>;
1205 #address-cells = <1>;
1206 #size-cells = <0>;
1211 compatible = "qcom,geni-spi";
1213 reg-names = "se";
1214 clock-names = "se";
1218 dma-names = "tx", "rx";
1219 pinctrl-names = "default";
1220 pinctrl-0 = <&qup_spi6_default>;
1222 spi-max-frequency = <50000000>;
1223 #address-cells = <1>;
1224 #size-cells = <0>;
1229 compatible = "qcom,geni-i2c";
1231 clock-names = "se";
1235 dma-names = "tx", "rx";
1236 pinctrl-names = "default";
1237 pinctrl-0 = <&qup_i2c7_default>;
1239 #address-cells = <1>;
1240 #size-cells = <0>;
1245 compatible = "qcom,geni-spi";
1247 reg-names = "se";
1248 clock-names = "se";
1252 dma-names = "tx", "rx";
1253 pinctrl-names = "default";
1254 pinctrl-0 = <&qup_spi7_default>;
1256 spi-max-frequency = <50000000>;
1257 #address-cells = <1>;
1258 #size-cells = <0>;
1263 gpi_dma1: dma-controller@a00000 {
1264 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
1279 dma-channels = <13>;
1280 dma-channel-mask = <0xfa>;
1282 #dma-cells = <3>;
1287 compatible = "qcom,geni-se-qup";
1289 clock-names = "m-ahb", "s-ahb";
1293 #address-cells = <2>;
1294 #size-cells = <2>;
1299 compatible = "qcom,geni-i2c";
1301 clock-names = "se";
1305 dma-names = "tx", "rx";
1306 pinctrl-names = "default";
1307 pinctrl-0 = <&qup_i2c8_default>;
1309 #address-cells = <1>;
1310 #size-cells = <0>;
1315 compatible = "qcom,geni-spi";
1317 reg-names = "se";
1318 clock-names = "se";
1322 dma-names = "tx", "rx";
1323 pinctrl-names = "default";
1324 pinctrl-0 = <&qup_spi8_default>;
1326 spi-max-frequency = <50000000>;
1327 #address-cells = <1>;
1328 #size-cells = <0>;
1333 compatible = "qcom,geni-i2c";
1335 clock-names = "se";
1339 dma-names = "tx", "rx";
1340 pinctrl-names = "default";
1341 pinctrl-0 = <&qup_i2c9_default>;
1343 #address-cells = <1>;
1344 #size-cells = <0>;
1349 compatible = "qcom,geni-spi";
1351 reg-names = "se";
1352 clock-names = "se";
1356 dma-names = "tx", "rx";
1357 pinctrl-names = "default";
1358 pinctrl-0 = <&qup_spi9_default>;
1360 spi-max-frequency = <50000000>;
1361 #address-cells = <1>;
1362 #size-cells = <0>;
1367 compatible = "qcom,geni-uart";
1370 clock-names = "se";
1371 pinctrl-0 = <&qup_uart9_default>;
1372 pinctrl-names = "default";
1378 compatible = "qcom,geni-i2c";
1380 clock-names = "se";
1384 dma-names = "tx", "rx";
1385 pinctrl-names = "default";
1386 pinctrl-0 = <&qup_i2c10_default>;
1388 #address-cells = <1>;
1389 #size-cells = <0>;
1394 compatible = "qcom,geni-spi";
1396 reg-names = "se";
1397 clock-names = "se";
1401 dma-names = "tx", "rx";
1402 pinctrl-names = "default";
1403 pinctrl-0 = <&qup_spi10_default>;
1405 spi-max-frequency = <50000000>;
1406 #address-cells = <1>;
1407 #size-cells = <0>;
1412 compatible = "qcom,geni-i2c";
1414 clock-names = "se";
1418 dma-names = "tx", "rx";
1419 pinctrl-names = "default";
1420 pinctrl-0 = <&qup_i2c11_default>;
1422 #address-cells = <1>;
1423 #size-cells = <0>;
1428 compatible = "qcom,geni-spi";
1430 reg-names = "se";
1431 clock-names = "se";
1435 dma-names = "tx", "rx";
1436 pinctrl-names = "default";
1437 pinctrl-0 = <&qup_spi11_default>;
1439 spi-max-frequency = <50000000>;
1440 #address-cells = <1>;
1441 #size-cells = <0>;
1446 compatible = "qcom,geni-debug-uart";
1448 clock-names = "se";
1455 compatible = "qcom,geni-i2c";
1457 clock-names = "se";
1461 dma-names = "tx", "rx";
1462 pinctrl-names = "default";
1463 pinctrl-0 = <&qup_i2c12_default>;
1465 #address-cells = <1>;
1466 #size-cells = <0>;
1471 compatible = "qcom,geni-spi";
1473 reg-names = "se";
1474 clock-names = "se";
1478 dma-names = "tx", "rx";
1479 pinctrl-names = "default";
1480 pinctrl-0 = <&qup_spi12_default>;
1482 spi-max-frequency = <50000000>;
1483 #address-cells = <1>;
1484 #size-cells = <0>;
1489 compatible = "qcom,geni-i2c";
1491 clock-names = "se";
1495 dma-names = "tx", "rx";
1496 pinctrl-names = "default";
1497 pinctrl-0 = <&qup_i2c16_default>;
1499 #address-cells = <1>;
1500 #size-cells = <0>;
1505 compatible = "qcom,geni-spi";
1507 reg-names = "se";
1508 clock-names = "se";
1512 dma-names = "tx", "rx";
1513 pinctrl-names = "default";
1514 pinctrl-0 = <&qup_spi16_default>;
1516 spi-max-frequency = <50000000>;
1517 #address-cells = <1>;
1518 #size-cells = <0>;
1523 gpi_dma2: dma-controller@c00000 {
1524 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
1539 dma-channels = <13>;
1540 dma-channel-mask = <0xfa>;
1542 #dma-cells = <3>;
1547 compatible = "qcom,geni-se-qup";
1550 clock-names = "m-ahb", "s-ahb";
1554 #address-cells = <2>;
1555 #size-cells = <2>;
1560 compatible = "qcom,geni-i2c";
1562 clock-names = "se";
1566 dma-names = "tx", "rx";
1567 pinctrl-names = "default";
1568 pinctrl-0 = <&qup_i2c17_default>;
1570 #address-cells = <1>;
1571 #size-cells = <0>;
1576 compatible = "qcom,geni-spi";
1578 reg-names = "se";
1579 clock-names = "se";
1583 dma-names = "tx", "rx";
1584 pinctrl-names = "default";
1585 pinctrl-0 = <&qup_spi17_default>;
1587 spi-max-frequency = <50000000>;
1588 #address-cells = <1>;
1589 #size-cells = <0>;
1594 compatible = "qcom,geni-i2c";
1596 clock-names = "se";
1600 dma-names = "tx", "rx";
1601 pinctrl-names = "default";
1602 pinctrl-0 = <&qup_i2c18_default>;
1604 #address-cells = <1>;
1605 #size-cells = <0>;
1610 compatible = "qcom,geni-spi";
1612 reg-names = "se";
1613 clock-names = "se";
1617 dma-names = "tx", "rx";
1618 pinctrl-names = "default";
1619 pinctrl-0 = <&qup_spi18_default>;
1621 spi-max-frequency = <50000000>;
1622 #address-cells = <1>;
1623 #size-cells = <0>;
1628 compatible = "qcom,geni-i2c";
1630 clock-names = "se";
1634 dma-names = "tx", "rx";
1635 pinctrl-names = "default";
1636 pinctrl-0 = <&qup_i2c19_default>;
1638 #address-cells = <1>;
1639 #size-cells = <0>;
1644 compatible = "qcom,geni-spi";
1646 reg-names = "se";
1647 clock-names = "se";
1651 dma-names = "tx", "rx";
1652 pinctrl-names = "default";
1653 pinctrl-0 = <&qup_spi19_default>;
1655 spi-max-frequency = <50000000>;
1656 #address-cells = <1>;
1657 #size-cells = <0>;
1662 compatible = "qcom,geni-i2c";
1664 clock-names = "se";
1668 dma-names = "tx", "rx";
1669 pinctrl-names = "default";
1670 pinctrl-0 = <&qup_i2c13_default>;
1672 #address-cells = <1>;
1673 #size-cells = <0>;
1678 compatible = "qcom,geni-spi";
1680 reg-names = "se";
1681 clock-names = "se";
1685 dma-names = "tx", "rx";
1686 pinctrl-names = "default";
1687 pinctrl-0 = <&qup_spi13_default>;
1689 spi-max-frequency = <50000000>;
1690 #address-cells = <1>;
1691 #size-cells = <0>;
1696 compatible = "qcom,geni-i2c";
1698 clock-names = "se";
1702 dma-names = "tx", "rx";
1703 pinctrl-names = "default";
1704 pinctrl-0 = <&qup_i2c14_default>;
1706 #address-cells = <1>;
1707 #size-cells = <0>;
1712 compatible = "qcom,geni-spi";
1714 reg-names = "se";
1715 clock-names = "se";
1719 dma-names = "tx", "rx";
1720 pinctrl-names = "default";
1721 pinctrl-0 = <&qup_spi14_default>;
1723 spi-max-frequency = <50000000>;
1724 #address-cells = <1>;
1725 #size-cells = <0>;
1730 compatible = "qcom,geni-i2c";
1732 clock-names = "se";
1736 dma-names = "tx", "rx";
1737 pinctrl-names = "default";
1738 pinctrl-0 = <&qup_i2c15_default>;
1740 #address-cells = <1>;
1741 #size-cells = <0>;
1746 compatible = "qcom,geni-spi";
1748 reg-names = "se";
1749 clock-names = "se";
1753 dma-names = "tx", "rx";
1754 pinctrl-names = "default";
1755 pinctrl-0 = <&qup_spi15_default>;
1757 spi-max-frequency = <50000000>;
1758 #address-cells = <1>;
1759 #size-cells = <0>;
1765 compatible = "qcom,sm8150-config-noc";
1767 #interconnect-cells = <2>;
1768 qcom,bcm-voters = <&apps_bcm_voter>;
1772 compatible = "qcom,sm8150-system-noc";
1774 #interconnect-cells = <2>;
1775 qcom,bcm-voters = <&apps_bcm_voter>;
1779 compatible = "qcom,sm8150-mc-virt";
1781 #interconnect-cells = <2>;
1782 qcom,bcm-voters = <&apps_bcm_voter>;
1786 compatible = "qcom,sm8150-aggre1-noc";
1788 #interconnect-cells = <2>;
1789 qcom,bcm-voters = <&apps_bcm_voter>;
1793 compatible = "qcom,sm8150-aggre2-noc";
1795 #interconnect-cells = <2>;
1796 qcom,bcm-voters = <&apps_bcm_voter>;
1800 compatible = "qcom,sm8150-compute-noc";
1802 #interconnect-cells = <2>;
1803 qcom,bcm-voters = <&apps_bcm_voter>;
1807 compatible = "qcom,sm8150-mmss-noc";
1809 #interconnect-cells = <2>;
1810 qcom,bcm-voters = <&apps_bcm_voter>;
1813 system-cache-controller@9200000 {
1814 compatible = "qcom,sm8150-llcc";
1818 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
1824 compatible = "qcom,sm8150-dcc", "qcom,dcc";
1830 compatible = "qcom,pcie-sm8150";
1836 reg-names = "parf", "dbi", "elbi", "atu", "config";
1838 linux,pci-domain = <0>;
1839 bus-range = <0x00 0xff>;
1840 num-lanes = <1>;
1842 #address-cells = <3>;
1843 #size-cells = <2>;
1856 interrupt-names = "msi0",
1864 #interrupt-cells = <1>;
1865 interrupt-map-mask = <0 0 0 0x7>;
1866 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1879 clock-names = "pipe",
1888 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1892 reset-names = "pci";
1894 power-domains = <&gcc PCIE_0_GDSC>;
1897 phy-names = "pciephy";
1899 perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
1900 wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
1902 pinctrl-names = "default";
1903 pinctrl-0 = <&pcie0_default_state>;
1910 bus-range = <0x01 0xff>;
1912 #address-cells = <3>;
1913 #size-cells = <2>;
1919 compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy";
1926 clock-names = "aux",
1932 clock-output-names = "pcie_0_pipe_clk";
1933 #clock-cells = <0>;
1935 #phy-cells = <0>;
1938 reset-names = "phy";
1940 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1941 assigned-clock-rates = <100000000>;
1947 compatible = "qcom,pcie-sm8150";
1953 reg-names = "parf", "dbi", "elbi", "atu", "config";
1955 linux,pci-domain = <1>;
1956 bus-range = <0x00 0xff>;
1957 num-lanes = <2>;
1959 #address-cells = <3>;
1960 #size-cells = <2>;
1973 interrupt-names = "msi0",
1981 #interrupt-cells = <1>;
1982 interrupt-map-mask = <0 0 0 0x7>;
1983 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1996 clock-names = "pipe",
2005 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2006 assigned-clock-rates = <19200000>;
2008 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
2012 reset-names = "pci";
2014 power-domains = <&gcc PCIE_1_GDSC>;
2017 phy-names = "pciephy";
2019 perst-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
2020 enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
2022 pinctrl-names = "default";
2023 pinctrl-0 = <&pcie1_default_state>;
2030 bus-range = <0x01 0xff>;
2032 #address-cells = <3>;
2033 #size-cells = <2>;
2039 compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy";
2046 clock-names = "aux",
2052 clock-output-names = "pcie_1_pipe_clk";
2053 #clock-cells = <0>;
2055 #phy-cells = <0>;
2058 reset-names = "phy";
2060 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2061 assigned-clock-rates = <100000000>;
2067 compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
2068 "jedec,ufs-2.0";
2071 reg-names = "std", "ice";
2074 phy-names = "ufsphy";
2075 lanes-per-direction = <2>;
2076 #reset-cells = <1>;
2078 reset-names = "rst";
2082 clock-names =
2102 freq-table-hz =
2117 compatible = "qcom,sm8150-qmp-ufs-phy";
2123 clock-names = "ref",
2127 power-domains = <&gcc UFS_PHY_GDSC>;
2130 reset-names = "ufsphy";
2132 #phy-cells = <0>;
2137 cryptobam: dma-controller@1dc4000 {
2138 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2141 #dma-cells = <1>;
2143 qcom,controlled-remotely;
2144 num-channels = <8>;
2145 qcom,num-ees = <2>;
2154 compatible = "qcom,sm8150-qce", "qcom,qce";
2157 dma-names = "rx", "tx";
2164 interconnect-names = "memory";
2168 compatible = "qcom,tcsr-mutex";
2170 #hwlock-cells = <1>;
2174 compatible = "qcom,sm8150-tcsr", "syscon";
2179 compatible = "qcom,sm8150-slpi-pas";
2182 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
2187 interrupt-names = "wdog", "fatal", "ready",
2188 "handover", "stop-ack";
2191 clock-names = "xo";
2193 power-domains = <&rpmhpd SM8150_LCX>,
2195 power-domain-names = "lcx", "lmx";
2197 memory-region = <&slpi_mem>;
2201 qcom,smem-states = <&slpi_smp2p_out 0>;
2202 qcom,smem-state-names = "stop";
2206 glink-edge {
2209 qcom,remote-pid = <3>;
2214 qcom,glink-channels = "fastrpcglink-apps-dsp";
2216 qcom,non-secure-domain;
2217 #address-cells = <1>;
2218 #size-cells = <0>;
2220 compute-cb@1 {
2221 compatible = "qcom,fastrpc-compute-cb";
2226 compute-cb@2 {
2227 compatible = "qcom,fastrpc-compute-cb";
2232 compute-cb@3 {
2233 compatible = "qcom,fastrpc-compute-cb";
2236 /* note: shared-cb = <4> in downstream */
2243 compatible = "qcom,adreno-640.1", "qcom,adreno";
2245 reg-names = "kgsl_3d0_reg_memory";
2251 operating-points-v2 = <&gpu_opp_table>;
2255 nvmem-cells = <&gpu_speed_bin>;
2256 nvmem-cell-names = "speed_bin";
2257 #cooling-cells = <2>;
2261 zap-shader {
2262 memory-region = <&gpu_mem>;
2265 gpu_opp_table: opp-table {
2266 compatible = "operating-points-v2";
2268 opp-675000000 {
2269 opp-hz = /bits/ 64 <675000000>;
2270 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2271 opp-supported-hw = <0x2>;
2274 opp-585000000 {
2275 opp-hz = /bits/ 64 <585000000>;
2276 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2277 opp-supported-hw = <0x3>;
2280 opp-499200000 {
2281 opp-hz = /bits/ 64 <499200000>;
2282 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2283 opp-supported-hw = <0x3>;
2286 opp-427000000 {
2287 opp-hz = /bits/ 64 <427000000>;
2288 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2289 opp-supported-hw = <0x3>;
2292 opp-345000000 {
2293 opp-hz = /bits/ 64 <345000000>;
2294 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2295 opp-supported-hw = <0x3>;
2298 opp-257000000 {
2299 opp-hz = /bits/ 64 <257000000>;
2300 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2301 opp-supported-hw = <0x3>;
2307 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
2312 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2316 interrupt-names = "hfi", "gmu";
2323 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2325 power-domains = <&gpucc GPU_CX_GDSC>,
2327 power-domain-names = "cx", "gx";
2331 operating-points-v2 = <&gmu_opp_table>;
2335 gmu_opp_table: opp-table {
2336 compatible = "operating-points-v2";
2338 opp-200000000 {
2339 opp-hz = /bits/ 64 <200000000>;
2340 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2345 gpucc: clock-controller@2c90000 {
2346 compatible = "qcom,sm8150-gpucc";
2351 clock-names = "bi_tcxo",
2354 #clock-cells = <1>;
2355 #reset-cells = <1>;
2356 #power-domain-cells = <1>;
2360 compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu",
2361 "qcom,smmu-500", "arm,mmu-500";
2363 #iommu-cells = <2>;
2364 #global-interrupts = <1>;
2377 clock-names = "ahb", "bus", "iface";
2379 power-domains = <&gpucc GPU_CX_GDSC>;
2383 compatible = "qcom,sm8150-pinctrl";
2388 reg-names = "west", "east", "north", "south";
2390 gpio-ranges = <&tlmm 0 0 176>;
2391 gpio-controller;
2392 #gpio-cells = <2>;
2393 interrupt-controller;
2394 #interrupt-cells = <2>;
2395 wakeup-parent = <&pdc>;
2397 qup_i2c0_default: qup-i2c0-default-state {
2400 drive-strength = <0x02>;
2401 bias-disable;
2404 qup_spi0_default: qup-spi0-default-state {
2407 drive-strength = <6>;
2408 bias-disable;
2411 qup_i2c1_default: qup-i2c1-default-state {
2414 drive-strength = <2>;
2415 bias-disable;
2418 qup_spi1_default: qup-spi1-default-state {
2421 drive-strength = <6>;
2422 bias-disable;
2425 qup_i2c2_default: qup-i2c2-default-state {
2428 drive-strength = <2>;
2429 bias-disable;
2432 qup_spi2_default: qup-spi2-default-state {
2435 drive-strength = <6>;
2436 bias-disable;
2439 qup_i2c3_default: qup-i2c3-default-state {
2442 drive-strength = <2>;
2443 bias-disable;
2446 qup_spi3_default: qup-spi3-default-state {
2449 drive-strength = <6>;
2450 bias-disable;
2453 qup_i2c4_default: qup-i2c4-default-state {
2456 drive-strength = <2>;
2457 bias-disable;
2460 qup_spi4_default: qup-spi4-default-state {
2463 drive-strength = <6>;
2464 bias-disable;
2467 qup_i2c5_default: qup-i2c5-default-state {
2470 drive-strength = <2>;
2471 bias-disable;
2474 qup_spi5_default: qup-spi5-default-state {
2477 drive-strength = <6>;
2478 bias-disable;
2481 qup_i2c6_default: qup-i2c6-default-state {
2484 drive-strength = <2>;
2485 bias-disable;
2488 qup_spi6_default: qup-spi6-default-state {
2491 drive-strength = <6>;
2492 bias-disable;
2495 qup_i2c7_default: qup-i2c7-default-state {
2498 drive-strength = <2>;
2499 bias-disable;
2502 qup_spi7_default: qup-spi7-default-state {
2505 drive-strength = <6>;
2506 bias-disable;
2509 qup_i2c8_default: qup-i2c8-default-state {
2512 drive-strength = <2>;
2513 bias-disable;
2516 qup_spi8_default: qup-spi8-default-state {
2519 drive-strength = <6>;
2520 bias-disable;
2523 qup_i2c9_default: qup-i2c9-default-state {
2526 drive-strength = <2>;
2527 bias-disable;
2530 qup_spi9_default: qup-spi9-default-state {
2533 drive-strength = <6>;
2534 bias-disable;
2537 qup_uart9_default: qup-uart9-default-state {
2540 drive-strength = <2>;
2541 bias-disable;
2544 qup_i2c10_default: qup-i2c10-default-state {
2547 drive-strength = <2>;
2548 bias-disable;
2551 qup_spi10_default: qup-spi10-default-state {
2554 drive-strength = <6>;
2555 bias-disable;
2558 qup_i2c11_default: qup-i2c11-default-state {
2561 drive-strength = <2>;
2562 bias-disable;
2565 qup_spi11_default: qup-spi11-default-state {
2568 drive-strength = <6>;
2569 bias-disable;
2572 qup_i2c12_default: qup-i2c12-default-state {
2575 drive-strength = <2>;
2576 bias-disable;
2579 qup_spi12_default: qup-spi12-default-state {
2582 drive-strength = <6>;
2583 bias-disable;
2586 qup_i2c13_default: qup-i2c13-default-state {
2589 drive-strength = <2>;
2590 bias-disable;
2593 qup_spi13_default: qup-spi13-default-state {
2596 drive-strength = <6>;
2597 bias-disable;
2600 qup_i2c14_default: qup-i2c14-default-state {
2603 drive-strength = <2>;
2604 bias-disable;
2607 qup_spi14_default: qup-spi14-default-state {
2610 drive-strength = <6>;
2611 bias-disable;
2614 qup_i2c15_default: qup-i2c15-default-state {
2617 drive-strength = <2>;
2618 bias-disable;
2621 qup_spi15_default: qup-spi15-default-state {
2624 drive-strength = <6>;
2625 bias-disable;
2628 qup_i2c16_default: qup-i2c16-default-state {
2631 drive-strength = <2>;
2632 bias-disable;
2635 qup_spi16_default: qup-spi16-default-state {
2638 drive-strength = <6>;
2639 bias-disable;
2642 qup_i2c17_default: qup-i2c17-default-state {
2645 drive-strength = <2>;
2646 bias-disable;
2649 qup_spi17_default: qup-spi17-default-state {
2652 drive-strength = <6>;
2653 bias-disable;
2656 qup_i2c18_default: qup-i2c18-default-state {
2659 drive-strength = <2>;
2660 bias-disable;
2663 qup_spi18_default: qup-spi18-default-state {
2666 drive-strength = <6>;
2667 bias-disable;
2670 qup_i2c19_default: qup-i2c19-default-state {
2673 drive-strength = <2>;
2674 bias-disable;
2677 qup_spi19_default: qup-spi19-default-state {
2680 drive-strength = <6>;
2681 bias-disable;
2684 pcie0_default_state: pcie0-default-state {
2685 perst-pins {
2688 drive-strength = <2>;
2689 bias-pull-down;
2692 clkreq-pins {
2695 drive-strength = <2>;
2696 bias-pull-up;
2699 wake-pins {
2702 drive-strength = <2>;
2703 bias-pull-up;
2707 pcie1_default_state: pcie1-default-state {
2708 perst-pins {
2711 drive-strength = <2>;
2712 bias-pull-down;
2715 clkreq-pins {
2718 drive-strength = <2>;
2719 bias-pull-up;
2722 wake-pins {
2725 drive-strength = <2>;
2726 bias-pull-up;
2732 compatible = "qcom,sm8150-mpss-pas";
2735 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2741 interrupt-names = "wdog", "fatal", "ready", "handover",
2742 "stop-ack", "shutdown-ack";
2745 clock-names = "xo";
2747 power-domains = <&rpmhpd SM8150_CX>,
2749 power-domain-names = "cx", "mss";
2751 memory-region = <&mpss_mem>;
2755 qcom,smem-states = <&modem_smp2p_out 0>;
2756 qcom,smem-state-names = "stop";
2760 glink-edge {
2763 qcom,remote-pid = <1>;
2769 compatible = "arm,coresight-stm", "arm,primecell";
2772 reg-names = "stm-base", "stm-stimulus-base";
2775 clock-names = "apb_pclk";
2777 out-ports {
2780 remote-endpoint = <&funnel0_in7>;
2787 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2791 clock-names = "apb_pclk";
2793 out-ports {
2796 remote-endpoint = <&merge_funnel_in0>;
2801 in-ports {
2802 #address-cells = <1>;
2803 #size-cells = <0>;
2808 remote-endpoint = <&stm_out>;
2815 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2819 clock-names = "apb_pclk";
2821 out-ports {
2824 remote-endpoint = <&merge_funnel_in1>;
2829 in-ports {
2830 #address-cells = <1>;
2831 #size-cells = <0>;
2836 remote-endpoint = <&swao_replicator_out>;
2843 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2847 clock-names = "apb_pclk";
2849 out-ports {
2852 remote-endpoint = <&merge_funnel_in2>;
2857 in-ports {
2858 #address-cells = <1>;
2859 #size-cells = <0>;
2864 remote-endpoint = <&apss_merge_funnel_out>;
2871 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2875 clock-names = "apb_pclk";
2877 out-ports {
2880 remote-endpoint = <&etf_in>;
2885 in-ports {
2886 #address-cells = <1>;
2887 #size-cells = <0>;
2892 remote-endpoint = <&funnel0_out>;
2899 remote-endpoint = <&funnel1_out>;
2906 remote-endpoint = <&funnel2_out>;
2913 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2917 clock-names = "apb_pclk";
2919 out-ports {
2920 #address-cells = <1>;
2921 #size-cells = <0>;
2926 remote-endpoint = <&etr_in>;
2933 remote-endpoint = <&replicator1_in>;
2938 in-ports {
2941 remote-endpoint = <&etf_out>;
2948 compatible = "arm,coresight-tmc", "arm,primecell";
2952 clock-names = "apb_pclk";
2954 out-ports {
2957 remote-endpoint = <&replicator_in0>;
2962 in-ports {
2965 remote-endpoint = <&merge_funnel_out>;
2972 compatible = "arm,coresight-tmc", "arm,primecell";
2977 clock-names = "apb_pclk";
2978 arm,scatter-gather;
2980 in-ports {
2983 remote-endpoint = <&replicator_out0>;
2990 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2994 clock-names = "apb_pclk";
2996 out-ports {
2997 #address-cells = <1>;
2998 #size-cells = <0>;
3003 remote-endpoint = <&swao_funnel_in>;
3008 in-ports {
3012 remote-endpoint = <&replicator_out1>;
3019 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3023 clock-names = "apb_pclk";
3025 out-ports {
3028 remote-endpoint = <&swao_etf_in>;
3033 in-ports {
3034 #address-cells = <1>;
3035 #size-cells = <0>;
3040 remote-endpoint = <&replicator1_out>;
3047 compatible = "arm,coresight-tmc", "arm,primecell";
3051 clock-names = "apb_pclk";
3053 out-ports {
3056 remote-endpoint = <&swao_replicator_in>;
3061 in-ports {
3064 remote-endpoint = <&swao_funnel_out>;
3071 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3075 clock-names = "apb_pclk";
3076 qcom,replicator-loses-context;
3078 out-ports {
3081 remote-endpoint = <&funnel1_in4>;
3086 in-ports {
3089 remote-endpoint = <&swao_etf_out>;
3096 compatible = "arm,coresight-etm4x", "arm,primecell";
3102 clock-names = "apb_pclk";
3103 arm,coresight-loses-context-with-cpu;
3104 qcom,skip-power-up;
3106 out-ports {
3109 remote-endpoint = <&apss_funnel_in0>;
3116 compatible = "arm,coresight-etm4x", "arm,primecell";
3122 clock-names = "apb_pclk";
3123 arm,coresight-loses-context-with-cpu;
3124 qcom,skip-power-up;
3126 out-ports {
3129 remote-endpoint = <&apss_funnel_in1>;
3136 compatible = "arm,coresight-etm4x", "arm,primecell";
3142 clock-names = "apb_pclk";
3143 arm,coresight-loses-context-with-cpu;
3144 qcom,skip-power-up;
3146 out-ports {
3149 remote-endpoint = <&apss_funnel_in2>;
3156 compatible = "arm,coresight-etm4x", "arm,primecell";
3162 clock-names = "apb_pclk";
3163 arm,coresight-loses-context-with-cpu;
3164 qcom,skip-power-up;
3166 out-ports {
3169 remote-endpoint = <&apss_funnel_in3>;
3176 compatible = "arm,coresight-etm4x", "arm,primecell";
3182 clock-names = "apb_pclk";
3183 arm,coresight-loses-context-with-cpu;
3184 qcom,skip-power-up;
3186 out-ports {
3189 remote-endpoint = <&apss_funnel_in4>;
3196 compatible = "arm,coresight-etm4x", "arm,primecell";
3202 clock-names = "apb_pclk";
3203 arm,coresight-loses-context-with-cpu;
3204 qcom,skip-power-up;
3206 out-ports {
3209 remote-endpoint = <&apss_funnel_in5>;
3216 compatible = "arm,coresight-etm4x", "arm,primecell";
3222 clock-names = "apb_pclk";
3223 arm,coresight-loses-context-with-cpu;
3224 qcom,skip-power-up;
3226 out-ports {
3229 remote-endpoint = <&apss_funnel_in6>;
3236 compatible = "arm,coresight-etm4x", "arm,primecell";
3242 clock-names = "apb_pclk";
3243 arm,coresight-loses-context-with-cpu;
3244 qcom,skip-power-up;
3246 out-ports {
3249 remote-endpoint = <&apss_funnel_in7>;
3256 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3260 clock-names = "apb_pclk";
3262 out-ports {
3265 remote-endpoint = <&apss_merge_funnel_in>;
3270 in-ports {
3271 #address-cells = <1>;
3272 #size-cells = <0>;
3277 remote-endpoint = <&etm0_out>;
3284 remote-endpoint = <&etm1_out>;
3291 remote-endpoint = <&etm2_out>;
3298 remote-endpoint = <&etm3_out>;
3305 remote-endpoint = <&etm4_out>;
3312 remote-endpoint = <&etm5_out>;
3319 remote-endpoint = <&etm6_out>;
3326 remote-endpoint = <&etm7_out>;
3333 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3337 clock-names = "apb_pclk";
3339 out-ports {
3342 remote-endpoint = <&funnel2_in2>;
3347 in-ports {
3350 remote-endpoint = <&apss_funnel_out>;
3357 compatible = "qcom,sm8150-cdsp-pas";
3360 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3365 interrupt-names = "wdog", "fatal", "ready",
3366 "handover", "stop-ack";
3369 clock-names = "xo";
3371 power-domains = <&rpmhpd SM8150_CX>;
3373 memory-region = <&cdsp_mem>;
3377 qcom,smem-states = <&cdsp_smp2p_out 0>;
3378 qcom,smem-state-names = "stop";
3382 glink-edge {
3385 qcom,remote-pid = <5>;
3390 qcom,glink-channels = "fastrpcglink-apps-dsp";
3392 qcom,non-secure-domain;
3393 #address-cells = <1>;
3394 #size-cells = <0>;
3396 compute-cb@1 {
3397 compatible = "qcom,fastrpc-compute-cb";
3402 compute-cb@2 {
3403 compatible = "qcom,fastrpc-compute-cb";
3408 compute-cb@3 {
3409 compatible = "qcom,fastrpc-compute-cb";
3414 compute-cb@4 {
3415 compatible = "qcom,fastrpc-compute-cb";
3420 compute-cb@5 {
3421 compatible = "qcom,fastrpc-compute-cb";
3426 compute-cb@6 {
3427 compatible = "qcom,fastrpc-compute-cb";
3432 compute-cb@7 {
3433 compatible = "qcom,fastrpc-compute-cb";
3438 compute-cb@8 {
3439 compatible = "qcom,fastrpc-compute-cb";
3450 compatible = "qcom,sm8150-usb-hs-phy",
3451 "qcom,usb-snps-hs-7nm-phy";
3454 #phy-cells = <0>;
3457 clock-names = "ref";
3463 compatible = "qcom,sm8150-usb-hs-phy",
3464 "qcom,usb-snps-hs-7nm-phy";
3467 #phy-cells = <0>;
3470 clock-names = "ref";
3476 compatible = "qcom,sm8150-qmp-usb3-dp-phy";
3483 clock-names = "aux",
3490 reset-names = "phy", "common";
3492 #clock-cells = <1>;
3493 #phy-cells = <1>;
3498 #address-cells = <1>;
3499 #size-cells = <0>;
3512 remote-endpoint = <&usb_1_dwc3_ss>;
3520 remote-endpoint = <&mdss_dp_out>;
3527 compatible = "qcom,sm8150-qmp-usb3-uni-phy";
3534 clock-names = "aux",
3538 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3539 #clock-cells = <0>;
3540 #phy-cells = <0>;
3544 reset-names = "phy",
3551 compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5";
3556 interrupt-names = "hc_irq", "pwr_irq";
3561 clock-names = "iface", "core", "xo";
3563 qcom,dll-config = <0x0007642c>;
3564 qcom,ddr-config = <0x80040868>;
3565 power-domains = <&rpmhpd 0>;
3566 operating-points-v2 = <&sdhc2_opp_table>;
3570 sdhc2_opp_table: opp-table {
3571 compatible = "operating-points-v2";
3573 opp-19200000 {
3574 opp-hz = /bits/ 64 <19200000>;
3575 required-opps = <&rpmhpd_opp_min_svs>;
3578 opp-50000000 {
3579 opp-hz = /bits/ 64 <50000000>;
3580 required-opps = <&rpmhpd_opp_low_svs>;
3583 opp-100000000 {
3584 opp-hz = /bits/ 64 <100000000>;
3585 required-opps = <&rpmhpd_opp_svs>;
3588 opp-202000000 {
3589 opp-hz = /bits/ 64 <202000000>;
3590 required-opps = <&rpmhpd_opp_svs_l1>;
3596 compatible = "qcom,sm8150-dc-noc";
3598 #interconnect-cells = <2>;
3599 qcom,bcm-voters = <&apps_bcm_voter>;
3603 compatible = "qcom,sm8150-gem-noc";
3605 #interconnect-cells = <2>;
3606 qcom,bcm-voters = <&apps_bcm_voter>;
3610 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3613 #address-cells = <2>;
3614 #size-cells = <2>;
3616 dma-ranges;
3624 clock-names = "cfg_noc",
3631 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3633 assigned-clock-rates = <19200000>, <200000000>;
3635 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3640 interrupt-names = "pwr_event",
3646 power-domains = <&gcc USB30_PRIM_GDSC>;
3652 interconnect-names = "usb-ddr", "apps-usb";
3662 phy-names = "usb2-phy", "usb3-phy";
3665 #address-cells = <1>;
3666 #size-cells = <0>;
3679 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
3687 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3690 #address-cells = <2>;
3691 #size-cells = <2>;
3693 dma-ranges;
3701 clock-names = "cfg_noc",
3708 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3710 assigned-clock-rates = <19200000>, <200000000>;
3712 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
3717 interrupt-names = "pwr_event",
3723 power-domains = <&gcc USB30_SEC_GDSC>;
3729 interconnect-names = "usb-ddr", "apps-usb";
3739 phy-names = "usb2-phy", "usb3-phy";
3743 videocc: clock-controller@ab00000 {
3744 compatible = "qcom,sm8150-videocc";
3748 clock-names = "iface", "bi_tcxo";
3749 power-domains = <&rpmhpd SM8150_MMCX>;
3750 required-opps = <&rpmhpd_opp_low_svs>;
3751 #clock-cells = <1>;
3752 #reset-cells = <1>;
3753 #power-domain-cells = <1>;
3757 compatible = "qcom,sm8150-camnoc-virt";
3759 #interconnect-cells = <2>;
3760 qcom,bcm-voters = <&apps_bcm_voter>;
3763 camcc: clock-controller@ad00000 {
3764 compatible = "qcom,sm8150-camcc";
3768 power-domains = <&rpmhpd SM8150_MMCX>;
3769 required-opps = <&rpmhpd_opp_low_svs>;
3770 #clock-cells = <1>;
3771 #reset-cells = <1>;
3772 #power-domain-cells = <1>;
3775 mdss: display-subsystem@ae00000 {
3776 compatible = "qcom,sm8150-mdss";
3778 reg-names = "mdss";
3782 interconnect-names = "mdp0-mem", "mdp1-mem";
3784 power-domains = <&dispcc MDSS_GDSC>;
3790 clock-names = "iface", "bus", "nrt_bus", "core";
3793 interrupt-controller;
3794 #interrupt-cells = <1>;
3800 #address-cells = <2>;
3801 #size-cells = <2>;
3804 mdss_mdp: display-controller@ae01000 {
3805 compatible = "qcom,sm8150-dpu";
3808 reg-names = "mdp", "vbif";
3814 clock-names = "iface", "bus", "core", "vsync";
3816 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3817 assigned-clock-rates = <19200000>;
3819 operating-points-v2 = <&mdp_opp_table>;
3820 power-domains = <&rpmhpd SM8150_MMCX>;
3822 interrupt-parent = <&mdss>;
3826 #address-cells = <1>;
3827 #size-cells = <0>;
3832 remote-endpoint = <&mdss_dsi0_in>;
3839 remote-endpoint = <&mdss_dsi1_in>;
3846 remote-endpoint = <&mdss_dp_in>;
3851 mdp_opp_table: opp-table {
3852 compatible = "operating-points-v2";
3854 opp-171428571 {
3855 opp-hz = /bits/ 64 <171428571>;
3856 required-opps = <&rpmhpd_opp_low_svs>;
3859 opp-300000000 {
3860 opp-hz = /bits/ 64 <300000000>;
3861 required-opps = <&rpmhpd_opp_svs>;
3864 opp-345000000 {
3865 opp-hz = /bits/ 64 <345000000>;
3866 required-opps = <&rpmhpd_opp_svs_l1>;
3869 opp-460000000 {
3870 opp-hz = /bits/ 64 <460000000>;
3871 required-opps = <&rpmhpd_opp_nom>;
3876 mdss_dp: displayport-controller@ae90000 {
3877 compatible = "qcom,sm8150-dp", "qcom,sm8350-dp";
3884 interrupt-parent = <&mdss>;
3891 clock-names = "core_iface",
3897 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3899 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3903 phy-names = "dp";
3905 #sound-dai-cells = <0>;
3907 operating-points-v2 = <&dp_opp_table>;
3908 power-domains = <&rpmhpd SM8250_MMCX>;
3913 #address-cells = <1>;
3914 #size-cells = <0>;
3919 remote-endpoint = <&dpu_intf0_out>;
3927 remote-endpoint = <&usb_1_qmpphy_dp_in>;
3932 dp_opp_table: opp-table {
3933 compatible = "operating-points-v2";
3935 opp-160000000 {
3936 opp-hz = /bits/ 64 <160000000>;
3937 required-opps = <&rpmhpd_opp_low_svs>;
3940 opp-270000000 {
3941 opp-hz = /bits/ 64 <270000000>;
3942 required-opps = <&rpmhpd_opp_svs>;
3945 opp-540000000 {
3946 opp-hz = /bits/ 64 <540000000>;
3947 required-opps = <&rpmhpd_opp_svs_l1>;
3950 opp-810000000 {
3951 opp-hz = /bits/ 64 <810000000>;
3952 required-opps = <&rpmhpd_opp_nom>;
3957 mdss_dsi0: dsi@ae94000 {
3958 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3960 reg-names = "dsi_ctrl";
3962 interrupt-parent = <&mdss>;
3971 clock-names = "byte",
3978 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
3980 assigned-clock-parents = <&mdss_dsi0_phy 0>,
3983 operating-points-v2 = <&dsi_opp_table>;
3984 power-domains = <&rpmhpd SM8150_MMCX>;
3990 #address-cells = <1>;
3991 #size-cells = <0>;
3994 #address-cells = <1>;
3995 #size-cells = <0>;
4000 remote-endpoint = <&dpu_intf1_out>;
4011 dsi_opp_table: opp-table {
4012 compatible = "operating-points-v2";
4014 opp-187500000 {
4015 opp-hz = /bits/ 64 <187500000>;
4016 required-opps = <&rpmhpd_opp_low_svs>;
4019 opp-300000000 {
4020 opp-hz = /bits/ 64 <300000000>;
4021 required-opps = <&rpmhpd_opp_svs>;
4024 opp-358000000 {
4025 opp-hz = /bits/ 64 <358000000>;
4026 required-opps = <&rpmhpd_opp_svs_l1>;
4032 compatible = "qcom,dsi-phy-7nm-8150";
4036 reg-names = "dsi_phy",
4040 #clock-cells = <1>;
4041 #phy-cells = <0>;
4045 clock-names = "iface", "ref";
4050 mdss_dsi1: dsi@ae96000 {
4051 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
4053 reg-names = "dsi_ctrl";
4055 interrupt-parent = <&mdss>;
4064 clock-names = "byte",
4071 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
4073 assigned-clock-parents = <&mdss_dsi1_phy 0>,
4076 operating-points-v2 = <&dsi_opp_table>;
4077 power-domains = <&rpmhpd SM8150_MMCX>;
4083 #address-cells = <1>;
4084 #size-cells = <0>;
4087 #address-cells = <1>;
4088 #size-cells = <0>;
4093 remote-endpoint = <&dpu_intf2_out>;
4106 compatible = "qcom,dsi-phy-7nm-8150";
4110 reg-names = "dsi_phy",
4114 #clock-cells = <1>;
4115 #phy-cells = <0>;
4119 clock-names = "iface", "ref";
4125 dispcc: clock-controller@af00000 {
4126 compatible = "qcom,sm8150-dispcc";
4135 clock-names = "bi_tcxo",
4142 power-domains = <&rpmhpd SM8150_MMCX>;
4143 required-opps = <&rpmhpd_opp_low_svs>;
4144 #clock-cells = <1>;
4145 #reset-cells = <1>;
4146 #power-domain-cells = <1>;
4149 pdc: interrupt-controller@b220000 {
4150 compatible = "qcom,sm8150-pdc", "qcom,pdc";
4152 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
4154 #interrupt-cells = <2>;
4155 interrupt-parent = <&intc>;
4156 interrupt-controller;
4159 aoss_qmp: power-management@c300000 {
4160 compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp";
4165 #clock-cells = <0>;
4169 compatible = "qcom,rpmh-stats";
4173 tsens0: thermal-sensor@c263000 {
4174 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4180 interrupt-names = "uplow", "critical";
4181 #thermal-sensor-cells = <1>;
4184 tsens1: thermal-sensor@c265000 {
4185 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4191 interrupt-names = "uplow", "critical";
4192 #thermal-sensor-cells = <1>;
4196 compatible = "qcom,spmi-pmic-arb";
4202 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4203 interrupt-names = "periph_irq";
4207 #address-cells = <2>;
4208 #size-cells = <0>;
4209 interrupt-controller;
4210 #interrupt-cells = <4>;
4214 compatible = "qcom,sm8150-smmu-500", "qcom,smmu-500", "arm,mmu-500";
4216 #iommu-cells = <2>;
4217 #global-interrupts = <1>;
4299 dma-coherent;
4303 compatible = "qcom,sm8150-adsp-pas";
4306 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
4311 interrupt-names = "wdog", "fatal", "ready",
4312 "handover", "stop-ack";
4315 clock-names = "xo";
4317 power-domains = <&rpmhpd SM8150_CX>;
4319 memory-region = <&adsp_mem>;
4323 qcom,smem-states = <&adsp_smp2p_out 0>;
4324 qcom,smem-state-names = "stop";
4328 glink-edge {
4331 qcom,remote-pid = <2>;
4336 qcom,glink-channels = "fastrpcglink-apps-dsp";
4338 qcom,non-secure-domain;
4339 #address-cells = <1>;
4340 #size-cells = <0>;
4342 compute-cb@3 {
4343 compatible = "qcom,fastrpc-compute-cb";
4348 compute-cb@4 {
4349 compatible = "qcom,fastrpc-compute-cb";
4354 compute-cb@5 {
4355 compatible = "qcom,fastrpc-compute-cb";
4363 intc: interrupt-controller@17a00000 {
4364 compatible = "arm,gic-v3";
4365 interrupt-controller;
4366 #interrupt-cells = <3>;
4373 compatible = "qcom,sm8150-apss-shared",
4374 "qcom,sdm845-apss-shared";
4376 #mbox-cells = <1>;
4380 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
4387 #address-cells = <1>;
4388 #size-cells = <1>;
4390 compatible = "arm,armv7-timer-mem";
4392 clock-frequency = <19200000>;
4395 frame-number = <0>;
4403 frame-number = <1>;
4410 frame-number = <2>;
4417 frame-number = <3>;
4424 frame-number = <4>;
4431 frame-number = <5>;
4438 frame-number = <6>;
4447 compatible = "qcom,rpmh-rsc";
4451 reg-names = "drv-0", "drv-1", "drv-2";
4455 qcom,tcs-offset = <0xd00>;
4456 qcom,drv-id = <2>;
4457 qcom,tcs-config = <ACTIVE_TCS 2>,
4461 power-domains = <&cluster_pd>;
4463 rpmhcc: clock-controller {
4464 compatible = "qcom,sm8150-rpmh-clk";
4465 #clock-cells = <1>;
4466 clock-names = "xo";
4470 rpmhpd: power-controller {
4471 compatible = "qcom,sm8150-rpmhpd";
4472 #power-domain-cells = <1>;
4473 operating-points-v2 = <&rpmhpd_opp_table>;
4475 rpmhpd_opp_table: opp-table {
4476 compatible = "operating-points-v2";
4479 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4483 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4487 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4491 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4495 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4499 opp-level = <224>;
4503 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4507 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4511 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4515 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4519 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4524 apps_bcm_voter: bcm-voter {
4525 compatible = "qcom,bcm-voter";
4530 compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3";
4534 clock-names = "xo", "alternate";
4536 #interconnect-cells = <1>;
4540 compatible = "qcom,sm8150-cpufreq-hw", "qcom,cpufreq-hw";
4543 reg-names = "freq-domain0", "freq-domain1",
4544 "freq-domain2";
4547 clock-names = "xo", "alternate";
4549 #freq-domain-cells = <1>;
4550 #clock-cells = <1>;
4554 compatible = "qcom,sm8150-lmh";
4558 qcom,lmh-temp-arm-millicelsius = <60000>;
4559 qcom,lmh-temp-low-millicelsius = <84500>;
4560 qcom,lmh-temp-high-millicelsius = <85000>;
4561 interrupt-controller;
4562 #interrupt-cells = <1>;
4566 compatible = "qcom,sm8150-lmh";
4570 qcom,lmh-temp-arm-millicelsius = <60000>;
4571 qcom,lmh-temp-low-millicelsius = <84500>;
4572 qcom,lmh-temp-high-millicelsius = <85000>;
4573 interrupt-controller;
4574 #interrupt-cells = <1>;
4578 compatible = "qcom,wcn3990-wifi";
4580 reg-names = "membase";
4581 memory-region = <&wlan_mem>;
4582 clock-names = "cxo_ref_clk_pin", "qdss";
4602 compatible = "arm,armv8-timer";
4609 thermal-zones {
4610 cpu0-thermal {
4611 polling-delay-passive = <250>;
4613 thermal-sensors = <&tsens0 1>;
4616 cpu0_alert0: trip-point0 {
4622 cpu0_alert1: trip-point1 {
4628 cpu0_crit: cpu-crit {
4635 cooling-maps {
4638 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4645 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4653 cpu1-thermal {
4654 polling-delay-passive = <250>;
4656 thermal-sensors = <&tsens0 2>;
4659 cpu1_alert0: trip-point0 {
4665 cpu1_alert1: trip-point1 {
4671 cpu1_crit: cpu-crit {
4678 cooling-maps {
4681 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4688 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4696 cpu2-thermal {
4697 polling-delay-passive = <250>;
4699 thermal-sensors = <&tsens0 3>;
4702 cpu2_alert0: trip-point0 {
4708 cpu2_alert1: trip-point1 {
4714 cpu2_crit: cpu-crit {
4721 cooling-maps {
4724 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4731 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4739 cpu3-thermal {
4740 polling-delay-passive = <250>;
4742 thermal-sensors = <&tsens0 4>;
4745 cpu3_alert0: trip-point0 {
4751 cpu3_alert1: trip-point1 {
4757 cpu3_crit: cpu-crit {
4764 cooling-maps {
4767 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4774 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4782 cpu4-top-thermal {
4783 polling-delay-passive = <250>;
4785 thermal-sensors = <&tsens0 7>;
4788 cpu4_top_alert0: trip-point0 {
4794 cpu4_top_alert1: trip-point1 {
4800 cpu4_top_crit: cpu-crit {
4807 cooling-maps {
4810 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4817 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4825 cpu5-top-thermal {
4826 polling-delay-passive = <250>;
4828 thermal-sensors = <&tsens0 8>;
4831 cpu5_top_alert0: trip-point0 {
4837 cpu5_top_alert1: trip-point1 {
4843 cpu5_top_crit: cpu-crit {
4850 cooling-maps {
4853 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4860 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4868 cpu6-top-thermal {
4869 polling-delay-passive = <250>;
4871 thermal-sensors = <&tsens0 9>;
4874 cpu6_top_alert0: trip-point0 {
4880 cpu6_top_alert1: trip-point1 {
4886 cpu6_top_crit: cpu-crit {
4893 cooling-maps {
4896 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4903 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4911 cpu7-top-thermal {
4912 polling-delay-passive = <250>;
4914 thermal-sensors = <&tsens0 10>;
4917 cpu7_top_alert0: trip-point0 {
4923 cpu7_top_alert1: trip-point1 {
4929 cpu7_top_crit: cpu-crit {
4936 cooling-maps {
4939 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4946 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4954 cpu4-bottom-thermal {
4955 polling-delay-passive = <250>;
4957 thermal-sensors = <&tsens0 11>;
4960 cpu4_bottom_alert0: trip-point0 {
4966 cpu4_bottom_alert1: trip-point1 {
4972 cpu4_bottom_crit: cpu-crit {
4979 cooling-maps {
4982 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4989 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4997 cpu5-bottom-thermal {
4998 polling-delay-passive = <250>;
5000 thermal-sensors = <&tsens0 12>;
5003 cpu5_bottom_alert0: trip-point0 {
5009 cpu5_bottom_alert1: trip-point1 {
5015 cpu5_bottom_crit: cpu-crit {
5022 cooling-maps {
5025 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5032 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5040 cpu6-bottom-thermal {
5041 polling-delay-passive = <250>;
5043 thermal-sensors = <&tsens0 13>;
5046 cpu6_bottom_alert0: trip-point0 {
5052 cpu6_bottom_alert1: trip-point1 {
5058 cpu6_bottom_crit: cpu-crit {
5065 cooling-maps {
5068 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5075 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5083 cpu7-bottom-thermal {
5084 polling-delay-passive = <250>;
5086 thermal-sensors = <&tsens0 14>;
5089 cpu7_bottom_alert0: trip-point0 {
5095 cpu7_bottom_alert1: trip-point1 {
5101 cpu7_bottom_crit: cpu-crit {
5108 cooling-maps {
5111 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5118 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5126 aoss0-thermal {
5127 polling-delay-passive = <250>;
5129 thermal-sensors = <&tsens0 0>;
5132 aoss0_alert0: trip-point0 {
5140 cluster0-thermal {
5141 polling-delay-passive = <250>;
5143 thermal-sensors = <&tsens0 5>;
5146 cluster0_alert0: trip-point0 {
5151 cluster0_crit: cluster0-crit {
5159 cluster1-thermal {
5160 polling-delay-passive = <250>;
5162 thermal-sensors = <&tsens0 6>;
5165 cluster1_alert0: trip-point0 {
5170 cluster1_crit: cluster1-crit {
5178 gpu-top-thermal {
5179 polling-delay-passive = <250>;
5181 thermal-sensors = <&tsens0 15>;
5183 cooling-maps {
5186 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5191 gpu_top_alert0: trip-point0 {
5197 trip-point1 {
5203 trip-point2 {
5211 aoss1-thermal {
5212 polling-delay-passive = <250>;
5214 thermal-sensors = <&tsens1 0>;
5217 aoss1_alert0: trip-point0 {
5225 wlan-thermal {
5226 polling-delay-passive = <250>;
5228 thermal-sensors = <&tsens1 1>;
5231 wlan_alert0: trip-point0 {
5239 video-thermal {
5240 polling-delay-passive = <250>;
5242 thermal-sensors = <&tsens1 2>;
5245 video_alert0: trip-point0 {
5253 mem-thermal {
5254 polling-delay-passive = <250>;
5256 thermal-sensors = <&tsens1 3>;
5259 mem_alert0: trip-point0 {
5267 q6-hvx-thermal {
5268 polling-delay-passive = <250>;
5270 thermal-sensors = <&tsens1 4>;
5273 q6_hvx_alert0: trip-point0 {
5281 camera-thermal {
5282 polling-delay-passive = <250>;
5284 thermal-sensors = <&tsens1 5>;
5287 camera_alert0: trip-point0 {
5295 compute-thermal {
5296 polling-delay-passive = <250>;
5298 thermal-sensors = <&tsens1 6>;
5301 compute_alert0: trip-point0 {
5309 modem-thermal {
5310 polling-delay-passive = <250>;
5312 thermal-sensors = <&tsens1 7>;
5315 modem_alert0: trip-point0 {
5323 npu-thermal {
5324 polling-delay-passive = <250>;
5326 thermal-sensors = <&tsens1 8>;
5329 npu_alert0: trip-point0 {
5337 modem-vec-thermal {
5338 polling-delay-passive = <250>;
5340 thermal-sensors = <&tsens1 9>;
5343 modem_vec_alert0: trip-point0 {
5351 modem-scl-thermal {
5352 polling-delay-passive = <250>;
5354 thermal-sensors = <&tsens1 10>;
5357 modem_scl_alert0: trip-point0 {
5365 gpu-bottom-thermal {
5366 polling-delay-passive = <250>;
5368 thermal-sensors = <&tsens1 11>;
5370 cooling-maps {
5373 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5378 gpu_bottom_alert0: trip-point0 {
5384 trip-point1 {
5390 trip-point2 {