Lines Matching +full:gpi +full:- +full:dma
1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/dma/qcom-gpi.h>
8 #include <dt-bindings/firmware/qcom,scm.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/phy/phy-qcom-qmp.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,dispcc-sm8150.h>
15 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
16 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
17 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
18 #include <dt-bindings/clock/qcom,videocc-sm8150.h>
19 #include <dt-bindings/interconnect/qcom,osm-l3.h>
20 #include <dt-bindings/interconnect/qcom,sm8150.h>
21 #include <dt-bindings/clock/qcom,sm8150-camcc.h>
22 #include <dt-bindings/thermal/thermal.h>
25 interrupt-parent = <&intc>;
27 #address-cells = <2>;
28 #size-cells = <2>;
33 xo_board: xo-board {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <38400000>;
37 clock-output-names = "xo_board";
40 sleep_clk: sleep-clk {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <32764>;
44 clock-output-names = "sleep_clk";
49 #address-cells = <2>;
50 #size-cells = <0>;
57 enable-method = "psci";
58 capacity-dmips-mhz = <488>;
59 dynamic-power-coefficient = <232>;
60 next-level-cache = <&l2_0>;
61 qcom,freq-domain = <&cpufreq_hw 0>;
62 operating-points-v2 = <&cpu0_opp_table>;
65 power-domains = <&cpu_pd0>;
66 power-domain-names = "psci";
67 #cooling-cells = <2>;
68 l2_0: l2-cache {
70 cache-level = <2>;
71 cache-unified;
72 next-level-cache = <&l3_0>;
73 l3_0: l3-cache {
75 cache-level = <3>;
76 cache-unified;
86 enable-method = "psci";
87 capacity-dmips-mhz = <488>;
88 dynamic-power-coefficient = <232>;
89 next-level-cache = <&l2_100>;
90 qcom,freq-domain = <&cpufreq_hw 0>;
91 operating-points-v2 = <&cpu0_opp_table>;
94 power-domains = <&cpu_pd1>;
95 power-domain-names = "psci";
96 #cooling-cells = <2>;
97 l2_100: l2-cache {
99 cache-level = <2>;
100 cache-unified;
101 next-level-cache = <&l3_0>;
110 enable-method = "psci";
111 capacity-dmips-mhz = <488>;
112 dynamic-power-coefficient = <232>;
113 next-level-cache = <&l2_200>;
114 qcom,freq-domain = <&cpufreq_hw 0>;
115 operating-points-v2 = <&cpu0_opp_table>;
118 power-domains = <&cpu_pd2>;
119 power-domain-names = "psci";
120 #cooling-cells = <2>;
121 l2_200: l2-cache {
123 cache-level = <2>;
124 cache-unified;
125 next-level-cache = <&l3_0>;
134 enable-method = "psci";
135 capacity-dmips-mhz = <488>;
136 dynamic-power-coefficient = <232>;
137 next-level-cache = <&l2_300>;
138 qcom,freq-domain = <&cpufreq_hw 0>;
139 operating-points-v2 = <&cpu0_opp_table>;
142 power-domains = <&cpu_pd3>;
143 power-domain-names = "psci";
144 #cooling-cells = <2>;
145 l2_300: l2-cache {
147 cache-level = <2>;
148 cache-unified;
149 next-level-cache = <&l3_0>;
158 enable-method = "psci";
159 capacity-dmips-mhz = <1024>;
160 dynamic-power-coefficient = <369>;
161 next-level-cache = <&l2_400>;
162 qcom,freq-domain = <&cpufreq_hw 1>;
163 operating-points-v2 = <&cpu4_opp_table>;
166 power-domains = <&cpu_pd4>;
167 power-domain-names = "psci";
168 #cooling-cells = <2>;
169 l2_400: l2-cache {
171 cache-level = <2>;
172 cache-unified;
173 next-level-cache = <&l3_0>;
182 enable-method = "psci";
183 capacity-dmips-mhz = <1024>;
184 dynamic-power-coefficient = <369>;
185 next-level-cache = <&l2_500>;
186 qcom,freq-domain = <&cpufreq_hw 1>;
187 operating-points-v2 = <&cpu4_opp_table>;
190 power-domains = <&cpu_pd5>;
191 power-domain-names = "psci";
192 #cooling-cells = <2>;
193 l2_500: l2-cache {
195 cache-level = <2>;
196 cache-unified;
197 next-level-cache = <&l3_0>;
206 enable-method = "psci";
207 capacity-dmips-mhz = <1024>;
208 dynamic-power-coefficient = <369>;
209 next-level-cache = <&l2_600>;
210 qcom,freq-domain = <&cpufreq_hw 1>;
211 operating-points-v2 = <&cpu4_opp_table>;
214 power-domains = <&cpu_pd6>;
215 power-domain-names = "psci";
216 #cooling-cells = <2>;
217 l2_600: l2-cache {
219 cache-level = <2>;
220 cache-unified;
221 next-level-cache = <&l3_0>;
230 enable-method = "psci";
231 capacity-dmips-mhz = <1024>;
232 dynamic-power-coefficient = <421>;
233 next-level-cache = <&l2_700>;
234 qcom,freq-domain = <&cpufreq_hw 2>;
235 operating-points-v2 = <&cpu7_opp_table>;
238 power-domains = <&cpu_pd7>;
239 power-domain-names = "psci";
240 #cooling-cells = <2>;
241 l2_700: l2-cache {
243 cache-level = <2>;
244 cache-unified;
245 next-level-cache = <&l3_0>;
249 cpu-map {
285 idle-states {
286 entry-method = "psci";
288 little_cpu_sleep_0: cpu-sleep-0-0 {
289 compatible = "arm,idle-state";
290 idle-state-name = "little-rail-power-collapse";
291 arm,psci-suspend-param = <0x40000004>;
292 entry-latency-us = <355>;
293 exit-latency-us = <909>;
294 min-residency-us = <3934>;
295 local-timer-stop;
298 big_cpu_sleep_0: cpu-sleep-1-0 {
299 compatible = "arm,idle-state";
300 idle-state-name = "big-rail-power-collapse";
301 arm,psci-suspend-param = <0x40000004>;
302 entry-latency-us = <241>;
303 exit-latency-us = <1461>;
304 min-residency-us = <4488>;
305 local-timer-stop;
309 domain-idle-states {
310 cluster_sleep_0: cluster-sleep-0 {
311 compatible = "domain-idle-state";
312 arm,psci-suspend-param = <0x4100c244>;
313 entry-latency-us = <3263>;
314 exit-latency-us = <6562>;
315 min-residency-us = <9987>;
320 cpu0_opp_table: opp-table-cpu0 {
321 compatible = "operating-points-v2";
322 opp-shared;
324 cpu0_opp1: opp-300000000 {
325 opp-hz = /bits/ 64 <300000000>;
326 opp-peak-kBps = <800000 9600000>;
329 cpu0_opp2: opp-403200000 {
330 opp-hz = /bits/ 64 <403200000>;
331 opp-peak-kBps = <800000 9600000>;
334 cpu0_opp3: opp-499200000 {
335 opp-hz = /bits/ 64 <499200000>;
336 opp-peak-kBps = <800000 12902400>;
339 cpu0_opp4: opp-576000000 {
340 opp-hz = /bits/ 64 <576000000>;
341 opp-peak-kBps = <800000 12902400>;
344 cpu0_opp5: opp-672000000 {
345 opp-hz = /bits/ 64 <672000000>;
346 opp-peak-kBps = <800000 15974400>;
349 cpu0_opp6: opp-768000000 {
350 opp-hz = /bits/ 64 <768000000>;
351 opp-peak-kBps = <1804000 19660800>;
354 cpu0_opp7: opp-844800000 {
355 opp-hz = /bits/ 64 <844800000>;
356 opp-peak-kBps = <1804000 19660800>;
359 cpu0_opp8: opp-940800000 {
360 opp-hz = /bits/ 64 <940800000>;
361 opp-peak-kBps = <1804000 22732800>;
364 cpu0_opp9: opp-1036800000 {
365 opp-hz = /bits/ 64 <1036800000>;
366 opp-peak-kBps = <1804000 22732800>;
369 cpu0_opp10: opp-1113600000 {
370 opp-hz = /bits/ 64 <1113600000>;
371 opp-peak-kBps = <2188000 25804800>;
374 cpu0_opp11: opp-1209600000 {
375 opp-hz = /bits/ 64 <1209600000>;
376 opp-peak-kBps = <2188000 31948800>;
379 cpu0_opp12: opp-1305600000 {
380 opp-hz = /bits/ 64 <1305600000>;
381 opp-peak-kBps = <3072000 31948800>;
384 cpu0_opp13: opp-1382400000 {
385 opp-hz = /bits/ 64 <1382400000>;
386 opp-peak-kBps = <3072000 31948800>;
389 cpu0_opp14: opp-1478400000 {
390 opp-hz = /bits/ 64 <1478400000>;
391 opp-peak-kBps = <3072000 31948800>;
394 cpu0_opp15: opp-1555200000 {
395 opp-hz = /bits/ 64 <1555200000>;
396 opp-peak-kBps = <3072000 40550400>;
399 cpu0_opp16: opp-1632000000 {
400 opp-hz = /bits/ 64 <1632000000>;
401 opp-peak-kBps = <3072000 40550400>;
404 cpu0_opp17: opp-1708800000 {
405 opp-hz = /bits/ 64 <1708800000>;
406 opp-peak-kBps = <3072000 43008000>;
409 cpu0_opp18: opp-1785600000 {
410 opp-hz = /bits/ 64 <1785600000>;
411 opp-peak-kBps = <3072000 43008000>;
415 cpu4_opp_table: opp-table-cpu4 {
416 compatible = "operating-points-v2";
417 opp-shared;
419 cpu4_opp1: opp-710400000 {
420 opp-hz = /bits/ 64 <710400000>;
421 opp-peak-kBps = <1804000 15974400>;
424 cpu4_opp2: opp-825600000 {
425 opp-hz = /bits/ 64 <825600000>;
426 opp-peak-kBps = <2188000 19660800>;
429 cpu4_opp3: opp-940800000 {
430 opp-hz = /bits/ 64 <940800000>;
431 opp-peak-kBps = <2188000 22732800>;
434 cpu4_opp4: opp-1056000000 {
435 opp-hz = /bits/ 64 <1056000000>;
436 opp-peak-kBps = <3072000 25804800>;
439 cpu4_opp5: opp-1171200000 {
440 opp-hz = /bits/ 64 <1171200000>;
441 opp-peak-kBps = <3072000 31948800>;
444 cpu4_opp6: opp-1286400000 {
445 opp-hz = /bits/ 64 <1286400000>;
446 opp-peak-kBps = <4068000 31948800>;
449 cpu4_opp7: opp-1401600000 {
450 opp-hz = /bits/ 64 <1401600000>;
451 opp-peak-kBps = <4068000 31948800>;
454 cpu4_opp8: opp-1497600000 {
455 opp-hz = /bits/ 64 <1497600000>;
456 opp-peak-kBps = <4068000 40550400>;
459 cpu4_opp9: opp-1612800000 {
460 opp-hz = /bits/ 64 <1612800000>;
461 opp-peak-kBps = <4068000 40550400>;
464 cpu4_opp10: opp-1708800000 {
465 opp-hz = /bits/ 64 <1708800000>;
466 opp-peak-kBps = <4068000 43008000>;
469 cpu4_opp11: opp-1804800000 {
470 opp-hz = /bits/ 64 <1804800000>;
471 opp-peak-kBps = <6220000 43008000>;
474 cpu4_opp12: opp-1920000000 {
475 opp-hz = /bits/ 64 <1920000000>;
476 opp-peak-kBps = <6220000 49152000>;
479 cpu4_opp13: opp-2016000000 {
480 opp-hz = /bits/ 64 <2016000000>;
481 opp-peak-kBps = <7216000 49152000>;
484 cpu4_opp14: opp-2131200000 {
485 opp-hz = /bits/ 64 <2131200000>;
486 opp-peak-kBps = <8368000 49152000>;
489 cpu4_opp15: opp-2227200000 {
490 opp-hz = /bits/ 64 <2227200000>;
491 opp-peak-kBps = <8368000 51609600>;
494 cpu4_opp16: opp-2323200000 {
495 opp-hz = /bits/ 64 <2323200000>;
496 opp-peak-kBps = <8368000 51609600>;
499 cpu4_opp17: opp-2419200000 {
500 opp-hz = /bits/ 64 <2419200000>;
501 opp-peak-kBps = <8368000 51609600>;
505 cpu7_opp_table: opp-table-cpu7 {
506 compatible = "operating-points-v2";
507 opp-shared;
509 cpu7_opp1: opp-825600000 {
510 opp-hz = /bits/ 64 <825600000>;
511 opp-peak-kBps = <2188000 19660800>;
514 cpu7_opp2: opp-940800000 {
515 opp-hz = /bits/ 64 <940800000>;
516 opp-peak-kBps = <2188000 22732800>;
519 cpu7_opp3: opp-1056000000 {
520 opp-hz = /bits/ 64 <1056000000>;
521 opp-peak-kBps = <3072000 25804800>;
524 cpu7_opp4: opp-1171200000 {
525 opp-hz = /bits/ 64 <1171200000>;
526 opp-peak-kBps = <3072000 31948800>;
529 cpu7_opp5: opp-1286400000 {
530 opp-hz = /bits/ 64 <1286400000>;
531 opp-peak-kBps = <4068000 31948800>;
534 cpu7_opp6: opp-1401600000 {
535 opp-hz = /bits/ 64 <1401600000>;
536 opp-peak-kBps = <4068000 31948800>;
539 cpu7_opp7: opp-1497600000 {
540 opp-hz = /bits/ 64 <1497600000>;
541 opp-peak-kBps = <4068000 40550400>;
544 cpu7_opp8: opp-1612800000 {
545 opp-hz = /bits/ 64 <1612800000>;
546 opp-peak-kBps = <4068000 40550400>;
549 cpu7_opp9: opp-1708800000 {
550 opp-hz = /bits/ 64 <1708800000>;
551 opp-peak-kBps = <4068000 43008000>;
554 cpu7_opp10: opp-1804800000 {
555 opp-hz = /bits/ 64 <1804800000>;
556 opp-peak-kBps = <6220000 43008000>;
559 cpu7_opp11: opp-1920000000 {
560 opp-hz = /bits/ 64 <1920000000>;
561 opp-peak-kBps = <6220000 49152000>;
564 cpu7_opp12: opp-2016000000 {
565 opp-hz = /bits/ 64 <2016000000>;
566 opp-peak-kBps = <7216000 49152000>;
569 cpu7_opp13: opp-2131200000 {
570 opp-hz = /bits/ 64 <2131200000>;
571 opp-peak-kBps = <8368000 49152000>;
574 cpu7_opp14: opp-2227200000 {
575 opp-hz = /bits/ 64 <2227200000>;
576 opp-peak-kBps = <8368000 51609600>;
579 cpu7_opp15: opp-2323200000 {
580 opp-hz = /bits/ 64 <2323200000>;
581 opp-peak-kBps = <8368000 51609600>;
584 cpu7_opp16: opp-2419200000 {
585 opp-hz = /bits/ 64 <2419200000>;
586 opp-peak-kBps = <8368000 51609600>;
589 cpu7_opp17: opp-2534400000 {
590 opp-hz = /bits/ 64 <2534400000>;
591 opp-peak-kBps = <8368000 51609600>;
594 cpu7_opp18: opp-2649600000 {
595 opp-hz = /bits/ 64 <2649600000>;
596 opp-peak-kBps = <8368000 51609600>;
599 cpu7_opp19: opp-2745600000 {
600 opp-hz = /bits/ 64 <2745600000>;
601 opp-peak-kBps = <8368000 51609600>;
604 cpu7_opp20: opp-2841600000 {
605 opp-hz = /bits/ 64 <2841600000>;
606 opp-peak-kBps = <8368000 51609600>;
612 compatible = "qcom,scm-sm8150", "qcom,scm";
613 #reset-cells = <1>;
624 compatible = "arm,armv8-pmuv3";
629 compatible = "arm,psci-1.0";
632 cpu_pd0: power-domain-cpu0 {
633 #power-domain-cells = <0>;
634 power-domains = <&cluster_pd>;
635 domain-idle-states = <&little_cpu_sleep_0>;
638 cpu_pd1: power-domain-cpu1 {
639 #power-domain-cells = <0>;
640 power-domains = <&cluster_pd>;
641 domain-idle-states = <&little_cpu_sleep_0>;
644 cpu_pd2: power-domain-cpu2 {
645 #power-domain-cells = <0>;
646 power-domains = <&cluster_pd>;
647 domain-idle-states = <&little_cpu_sleep_0>;
650 cpu_pd3: power-domain-cpu3 {
651 #power-domain-cells = <0>;
652 power-domains = <&cluster_pd>;
653 domain-idle-states = <&little_cpu_sleep_0>;
656 cpu_pd4: power-domain-cpu4 {
657 #power-domain-cells = <0>;
658 power-domains = <&cluster_pd>;
659 domain-idle-states = <&big_cpu_sleep_0>;
662 cpu_pd5: power-domain-cpu5 {
663 #power-domain-cells = <0>;
664 power-domains = <&cluster_pd>;
665 domain-idle-states = <&big_cpu_sleep_0>;
668 cpu_pd6: power-domain-cpu6 {
669 #power-domain-cells = <0>;
670 power-domains = <&cluster_pd>;
671 domain-idle-states = <&big_cpu_sleep_0>;
674 cpu_pd7: power-domain-cpu7 {
675 #power-domain-cells = <0>;
676 power-domains = <&cluster_pd>;
677 domain-idle-states = <&big_cpu_sleep_0>;
680 cluster_pd: power-domain-cpu-cluster0 {
681 #power-domain-cells = <0>;
682 domain-idle-states = <&cluster_sleep_0>;
686 reserved-memory {
687 #address-cells = <2>;
688 #size-cells = <2>;
693 no-map;
698 no-map;
703 no-map;
707 compatible = "qcom,cmd-db";
709 no-map;
714 no-map;
719 no-map;
723 compatible = "qcom,rmtfs-mem";
725 no-map;
727 qcom,client-id = <1>;
733 no-map;
738 no-map;
743 no-map;
748 no-map;
753 no-map;
758 no-map;
763 no-map;
768 no-map;
773 no-map;
778 no-map;
783 no-map;
788 no-map;
793 no-map;
799 memory-region = <&smem_mem>;
803 smp2p-cdsp {
811 qcom,local-pid = <0>;
812 qcom,remote-pid = <5>;
814 cdsp_smp2p_out: master-kernel {
815 qcom,entry-name = "master-kernel";
816 #qcom,smem-state-cells = <1>;
819 cdsp_smp2p_in: slave-kernel {
820 qcom,entry-name = "slave-kernel";
822 interrupt-controller;
823 #interrupt-cells = <2>;
827 smp2p-lpass {
835 qcom,local-pid = <0>;
836 qcom,remote-pid = <2>;
838 adsp_smp2p_out: master-kernel {
839 qcom,entry-name = "master-kernel";
840 #qcom,smem-state-cells = <1>;
843 adsp_smp2p_in: slave-kernel {
844 qcom,entry-name = "slave-kernel";
846 interrupt-controller;
847 #interrupt-cells = <2>;
851 smp2p-mpss {
859 qcom,local-pid = <0>;
860 qcom,remote-pid = <1>;
862 modem_smp2p_out: master-kernel {
863 qcom,entry-name = "master-kernel";
864 #qcom,smem-state-cells = <1>;
867 modem_smp2p_in: slave-kernel {
868 qcom,entry-name = "slave-kernel";
870 interrupt-controller;
871 #interrupt-cells = <2>;
875 smp2p-slpi {
883 qcom,local-pid = <0>;
884 qcom,remote-pid = <3>;
886 slpi_smp2p_out: master-kernel {
887 qcom,entry-name = "master-kernel";
888 #qcom,smem-state-cells = <1>;
891 slpi_smp2p_in: slave-kernel {
892 qcom,entry-name = "slave-kernel";
894 interrupt-controller;
895 #interrupt-cells = <2>;
900 #address-cells = <2>;
901 #size-cells = <2>;
903 dma-ranges = <0 0 0 0 0x10 0>;
904 compatible = "simple-bus";
906 gcc: clock-controller@100000 {
907 compatible = "qcom,gcc-sm8150";
909 #clock-cells = <1>;
910 #reset-cells = <1>;
911 #power-domain-cells = <1>;
912 clock-names = "bi_tcxo",
918 gpi_dma0: dma-controller@800000 {
919 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
934 dma-channels = <13>;
935 dma-channel-mask = <0xfa>;
937 #dma-cells = <3>;
942 compatible = "qcom,sm8150-ethqos";
945 reg-names = "stmmaceth", "rgmii";
946 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
953 interrupt-names = "macirq", "eth_lpi";
955 power-domains = <&gcc EMAC_GDSC>;
961 rx-fifo-depth = <4096>;
962 tx-fifo-depth = <4096>;
968 compatible = "qcom,sm8150-qfprom", "qcom,qfprom";
970 #address-cells = <1>;
971 #size-cells = <1>;
973 gpu_speed_bin: gpu-speed-bin@133 {
980 compatible = "qcom,geni-se-qup";
982 clock-names = "m-ahb", "s-ahb";
986 #address-cells = <2>;
987 #size-cells = <2>;
992 compatible = "qcom,geni-i2c";
994 clock-names = "se";
998 dma-names = "tx", "rx";
999 pinctrl-names = "default";
1000 pinctrl-0 = <&qup_i2c0_default>;
1002 #address-cells = <1>;
1003 #size-cells = <0>;
1008 compatible = "qcom,geni-spi";
1010 reg-names = "se";
1011 clock-names = "se";
1015 dma-names = "tx", "rx";
1016 pinctrl-names = "default";
1017 pinctrl-0 = <&qup_spi0_default>;
1019 spi-max-frequency = <50000000>;
1020 #address-cells = <1>;
1021 #size-cells = <0>;
1026 compatible = "qcom,geni-i2c";
1028 clock-names = "se";
1032 dma-names = "tx", "rx";
1033 pinctrl-names = "default";
1034 pinctrl-0 = <&qup_i2c1_default>;
1036 #address-cells = <1>;
1037 #size-cells = <0>;
1042 compatible = "qcom,geni-spi";
1044 reg-names = "se";
1045 clock-names = "se";
1049 dma-names = "tx", "rx";
1050 pinctrl-names = "default";
1051 pinctrl-0 = <&qup_spi1_default>;
1053 spi-max-frequency = <50000000>;
1054 #address-cells = <1>;
1055 #size-cells = <0>;
1060 compatible = "qcom,geni-i2c";
1062 clock-names = "se";
1066 dma-names = "tx", "rx";
1067 pinctrl-names = "default";
1068 pinctrl-0 = <&qup_i2c2_default>;
1070 #address-cells = <1>;
1071 #size-cells = <0>;
1076 compatible = "qcom,geni-spi";
1078 reg-names = "se";
1079 clock-names = "se";
1083 dma-names = "tx", "rx";
1084 pinctrl-names = "default";
1085 pinctrl-0 = <&qup_spi2_default>;
1087 spi-max-frequency = <50000000>;
1088 #address-cells = <1>;
1089 #size-cells = <0>;
1094 compatible = "qcom,geni-i2c";
1096 clock-names = "se";
1100 dma-names = "tx", "rx";
1101 pinctrl-names = "default";
1102 pinctrl-0 = <&qup_i2c3_default>;
1104 #address-cells = <1>;
1105 #size-cells = <0>;
1110 compatible = "qcom,geni-spi";
1112 reg-names = "se";
1113 clock-names = "se";
1117 dma-names = "tx", "rx";
1118 pinctrl-names = "default";
1119 pinctrl-0 = <&qup_spi3_default>;
1121 spi-max-frequency = <50000000>;
1122 #address-cells = <1>;
1123 #size-cells = <0>;
1128 compatible = "qcom,geni-i2c";
1130 clock-names = "se";
1134 dma-names = "tx", "rx";
1135 pinctrl-names = "default";
1136 pinctrl-0 = <&qup_i2c4_default>;
1138 #address-cells = <1>;
1139 #size-cells = <0>;
1144 compatible = "qcom,geni-spi";
1146 reg-names = "se";
1147 clock-names = "se";
1151 dma-names = "tx", "rx";
1152 pinctrl-names = "default";
1153 pinctrl-0 = <&qup_spi4_default>;
1155 spi-max-frequency = <50000000>;
1156 #address-cells = <1>;
1157 #size-cells = <0>;
1162 compatible = "qcom,geni-i2c";
1164 clock-names = "se";
1168 dma-names = "tx", "rx";
1169 pinctrl-names = "default";
1170 pinctrl-0 = <&qup_i2c5_default>;
1172 #address-cells = <1>;
1173 #size-cells = <0>;
1178 compatible = "qcom,geni-spi";
1180 reg-names = "se";
1181 clock-names = "se";
1185 dma-names = "tx", "rx";
1186 pinctrl-names = "default";
1187 pinctrl-0 = <&qup_spi5_default>;
1189 spi-max-frequency = <50000000>;
1190 #address-cells = <1>;
1191 #size-cells = <0>;
1196 compatible = "qcom,geni-i2c";
1198 clock-names = "se";
1202 dma-names = "tx", "rx";
1203 pinctrl-names = "default";
1204 pinctrl-0 = <&qup_i2c6_default>;
1206 #address-cells = <1>;
1207 #size-cells = <0>;
1212 compatible = "qcom,geni-spi";
1214 reg-names = "se";
1215 clock-names = "se";
1219 dma-names = "tx", "rx";
1220 pinctrl-names = "default";
1221 pinctrl-0 = <&qup_spi6_default>;
1223 spi-max-frequency = <50000000>;
1224 #address-cells = <1>;
1225 #size-cells = <0>;
1230 compatible = "qcom,geni-i2c";
1232 clock-names = "se";
1236 dma-names = "tx", "rx";
1237 pinctrl-names = "default";
1238 pinctrl-0 = <&qup_i2c7_default>;
1240 #address-cells = <1>;
1241 #size-cells = <0>;
1246 compatible = "qcom,geni-spi";
1248 reg-names = "se";
1249 clock-names = "se";
1253 dma-names = "tx", "rx";
1254 pinctrl-names = "default";
1255 pinctrl-0 = <&qup_spi7_default>;
1257 spi-max-frequency = <50000000>;
1258 #address-cells = <1>;
1259 #size-cells = <0>;
1264 gpi_dma1: dma-controller@a00000 {
1265 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
1280 dma-channels = <13>;
1281 dma-channel-mask = <0xfa>;
1283 #dma-cells = <3>;
1288 compatible = "qcom,geni-se-qup";
1290 clock-names = "m-ahb", "s-ahb";
1294 #address-cells = <2>;
1295 #size-cells = <2>;
1300 compatible = "qcom,geni-i2c";
1302 clock-names = "se";
1306 dma-names = "tx", "rx";
1307 pinctrl-names = "default";
1308 pinctrl-0 = <&qup_i2c8_default>;
1310 #address-cells = <1>;
1311 #size-cells = <0>;
1316 compatible = "qcom,geni-spi";
1318 reg-names = "se";
1319 clock-names = "se";
1323 dma-names = "tx", "rx";
1324 pinctrl-names = "default";
1325 pinctrl-0 = <&qup_spi8_default>;
1327 spi-max-frequency = <50000000>;
1328 #address-cells = <1>;
1329 #size-cells = <0>;
1334 compatible = "qcom,geni-i2c";
1336 clock-names = "se";
1340 dma-names = "tx", "rx";
1341 pinctrl-names = "default";
1342 pinctrl-0 = <&qup_i2c9_default>;
1344 #address-cells = <1>;
1345 #size-cells = <0>;
1350 compatible = "qcom,geni-spi";
1352 reg-names = "se";
1353 clock-names = "se";
1357 dma-names = "tx", "rx";
1358 pinctrl-names = "default";
1359 pinctrl-0 = <&qup_spi9_default>;
1361 spi-max-frequency = <50000000>;
1362 #address-cells = <1>;
1363 #size-cells = <0>;
1368 compatible = "qcom,geni-uart";
1371 clock-names = "se";
1372 pinctrl-0 = <&qup_uart9_default>;
1373 pinctrl-names = "default";
1379 compatible = "qcom,geni-i2c";
1381 clock-names = "se";
1385 dma-names = "tx", "rx";
1386 pinctrl-names = "default";
1387 pinctrl-0 = <&qup_i2c10_default>;
1389 #address-cells = <1>;
1390 #size-cells = <0>;
1395 compatible = "qcom,geni-spi";
1397 reg-names = "se";
1398 clock-names = "se";
1402 dma-names = "tx", "rx";
1403 pinctrl-names = "default";
1404 pinctrl-0 = <&qup_spi10_default>;
1406 spi-max-frequency = <50000000>;
1407 #address-cells = <1>;
1408 #size-cells = <0>;
1413 compatible = "qcom,geni-i2c";
1415 clock-names = "se";
1419 dma-names = "tx", "rx";
1420 pinctrl-names = "default";
1421 pinctrl-0 = <&qup_i2c11_default>;
1423 #address-cells = <1>;
1424 #size-cells = <0>;
1429 compatible = "qcom,geni-spi";
1431 reg-names = "se";
1432 clock-names = "se";
1436 dma-names = "tx", "rx";
1437 pinctrl-names = "default";
1438 pinctrl-0 = <&qup_spi11_default>;
1440 spi-max-frequency = <50000000>;
1441 #address-cells = <1>;
1442 #size-cells = <0>;
1447 compatible = "qcom,geni-debug-uart";
1449 clock-names = "se";
1456 compatible = "qcom,geni-i2c";
1458 clock-names = "se";
1462 dma-names = "tx", "rx";
1463 pinctrl-names = "default";
1464 pinctrl-0 = <&qup_i2c12_default>;
1466 #address-cells = <1>;
1467 #size-cells = <0>;
1472 compatible = "qcom,geni-spi";
1474 reg-names = "se";
1475 clock-names = "se";
1479 dma-names = "tx", "rx";
1480 pinctrl-names = "default";
1481 pinctrl-0 = <&qup_spi12_default>;
1483 spi-max-frequency = <50000000>;
1484 #address-cells = <1>;
1485 #size-cells = <0>;
1490 compatible = "qcom,geni-i2c";
1492 clock-names = "se";
1496 dma-names = "tx", "rx";
1497 pinctrl-names = "default";
1498 pinctrl-0 = <&qup_i2c16_default>;
1500 #address-cells = <1>;
1501 #size-cells = <0>;
1506 compatible = "qcom,geni-spi";
1508 reg-names = "se";
1509 clock-names = "se";
1513 dma-names = "tx", "rx";
1514 pinctrl-names = "default";
1515 pinctrl-0 = <&qup_spi16_default>;
1517 spi-max-frequency = <50000000>;
1518 #address-cells = <1>;
1519 #size-cells = <0>;
1524 gpi_dma2: dma-controller@c00000 {
1525 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
1540 dma-channels = <13>;
1541 dma-channel-mask = <0xfa>;
1543 #dma-cells = <3>;
1548 compatible = "qcom,geni-se-qup";
1551 clock-names = "m-ahb", "s-ahb";
1555 #address-cells = <2>;
1556 #size-cells = <2>;
1561 compatible = "qcom,geni-i2c";
1563 clock-names = "se";
1567 dma-names = "tx", "rx";
1568 pinctrl-names = "default";
1569 pinctrl-0 = <&qup_i2c17_default>;
1571 #address-cells = <1>;
1572 #size-cells = <0>;
1577 compatible = "qcom,geni-spi";
1579 reg-names = "se";
1580 clock-names = "se";
1584 dma-names = "tx", "rx";
1585 pinctrl-names = "default";
1586 pinctrl-0 = <&qup_spi17_default>;
1588 spi-max-frequency = <50000000>;
1589 #address-cells = <1>;
1590 #size-cells = <0>;
1595 compatible = "qcom,geni-i2c";
1597 clock-names = "se";
1601 dma-names = "tx", "rx";
1602 pinctrl-names = "default";
1603 pinctrl-0 = <&qup_i2c18_default>;
1605 #address-cells = <1>;
1606 #size-cells = <0>;
1611 compatible = "qcom,geni-spi";
1613 reg-names = "se";
1614 clock-names = "se";
1618 dma-names = "tx", "rx";
1619 pinctrl-names = "default";
1620 pinctrl-0 = <&qup_spi18_default>;
1622 spi-max-frequency = <50000000>;
1623 #address-cells = <1>;
1624 #size-cells = <0>;
1629 compatible = "qcom,geni-i2c";
1631 clock-names = "se";
1635 dma-names = "tx", "rx";
1636 pinctrl-names = "default";
1637 pinctrl-0 = <&qup_i2c19_default>;
1639 #address-cells = <1>;
1640 #size-cells = <0>;
1645 compatible = "qcom,geni-spi";
1647 reg-names = "se";
1648 clock-names = "se";
1652 dma-names = "tx", "rx";
1653 pinctrl-names = "default";
1654 pinctrl-0 = <&qup_spi19_default>;
1656 spi-max-frequency = <50000000>;
1657 #address-cells = <1>;
1658 #size-cells = <0>;
1663 compatible = "qcom,geni-i2c";
1665 clock-names = "se";
1669 dma-names = "tx", "rx";
1670 pinctrl-names = "default";
1671 pinctrl-0 = <&qup_i2c13_default>;
1673 #address-cells = <1>;
1674 #size-cells = <0>;
1679 compatible = "qcom,geni-spi";
1681 reg-names = "se";
1682 clock-names = "se";
1686 dma-names = "tx", "rx";
1687 pinctrl-names = "default";
1688 pinctrl-0 = <&qup_spi13_default>;
1690 spi-max-frequency = <50000000>;
1691 #address-cells = <1>;
1692 #size-cells = <0>;
1697 compatible = "qcom,geni-i2c";
1699 clock-names = "se";
1703 dma-names = "tx", "rx";
1704 pinctrl-names = "default";
1705 pinctrl-0 = <&qup_i2c14_default>;
1707 #address-cells = <1>;
1708 #size-cells = <0>;
1713 compatible = "qcom,geni-spi";
1715 reg-names = "se";
1716 clock-names = "se";
1720 dma-names = "tx", "rx";
1721 pinctrl-names = "default";
1722 pinctrl-0 = <&qup_spi14_default>;
1724 spi-max-frequency = <50000000>;
1725 #address-cells = <1>;
1726 #size-cells = <0>;
1731 compatible = "qcom,geni-i2c";
1733 clock-names = "se";
1737 dma-names = "tx", "rx";
1738 pinctrl-names = "default";
1739 pinctrl-0 = <&qup_i2c15_default>;
1741 #address-cells = <1>;
1742 #size-cells = <0>;
1747 compatible = "qcom,geni-spi";
1749 reg-names = "se";
1750 clock-names = "se";
1754 dma-names = "tx", "rx";
1755 pinctrl-names = "default";
1756 pinctrl-0 = <&qup_spi15_default>;
1758 spi-max-frequency = <50000000>;
1759 #address-cells = <1>;
1760 #size-cells = <0>;
1766 compatible = "qcom,sm8150-config-noc";
1768 #interconnect-cells = <2>;
1769 qcom,bcm-voters = <&apps_bcm_voter>;
1773 compatible = "qcom,sm8150-system-noc";
1775 #interconnect-cells = <2>;
1776 qcom,bcm-voters = <&apps_bcm_voter>;
1780 compatible = "qcom,sm8150-mc-virt";
1782 #interconnect-cells = <2>;
1783 qcom,bcm-voters = <&apps_bcm_voter>;
1787 compatible = "qcom,sm8150-aggre1-noc";
1789 #interconnect-cells = <2>;
1790 qcom,bcm-voters = <&apps_bcm_voter>;
1794 compatible = "qcom,sm8150-aggre2-noc";
1796 #interconnect-cells = <2>;
1797 qcom,bcm-voters = <&apps_bcm_voter>;
1801 compatible = "qcom,sm8150-compute-noc";
1803 #interconnect-cells = <2>;
1804 qcom,bcm-voters = <&apps_bcm_voter>;
1808 compatible = "qcom,sm8150-mmss-noc";
1810 #interconnect-cells = <2>;
1811 qcom,bcm-voters = <&apps_bcm_voter>;
1814 system-cache-controller@9200000 {
1815 compatible = "qcom,sm8150-llcc";
1819 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
1824 dma@10a2000 {
1825 compatible = "qcom,sm8150-dcc", "qcom,dcc";
1831 compatible = "qcom,pcie-sm8150";
1837 reg-names = "parf", "dbi", "elbi", "atu", "config";
1839 linux,pci-domain = <0>;
1840 bus-range = <0x00 0xff>;
1841 num-lanes = <1>;
1843 #address-cells = <3>;
1844 #size-cells = <2>;
1858 interrupt-names = "msi0",
1867 #interrupt-cells = <1>;
1868 interrupt-map-mask = <0 0 0 0x7>;
1869 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1880 clock-names = "pipe",
1887 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1891 reset-names = "pci";
1893 power-domains = <&gcc PCIE_0_GDSC>;
1896 phy-names = "pciephy";
1898 perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
1899 wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
1901 pinctrl-names = "default";
1902 pinctrl-0 = <&pcie0_default_state>;
1909 bus-range = <0x01 0xff>;
1911 #address-cells = <3>;
1912 #size-cells = <2>;
1918 compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy";
1925 clock-names = "aux",
1931 clock-output-names = "pcie_0_pipe_clk";
1932 #clock-cells = <0>;
1934 #phy-cells = <0>;
1937 reset-names = "phy";
1939 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1940 assigned-clock-rates = <100000000>;
1946 compatible = "qcom,pcie-sm8150";
1952 reg-names = "parf", "dbi", "elbi", "atu", "config";
1954 linux,pci-domain = <1>;
1955 bus-range = <0x00 0xff>;
1956 num-lanes = <2>;
1958 #address-cells = <3>;
1959 #size-cells = <2>;
1973 interrupt-names = "msi0",
1982 #interrupt-cells = <1>;
1983 interrupt-map-mask = <0 0 0 0x7>;
1984 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1995 clock-names = "pipe",
2002 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2003 assigned-clock-rates = <19200000>;
2005 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
2009 reset-names = "pci";
2011 power-domains = <&gcc PCIE_1_GDSC>;
2014 phy-names = "pciephy";
2016 perst-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
2017 enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
2019 pinctrl-names = "default";
2020 pinctrl-0 = <&pcie1_default_state>;
2027 bus-range = <0x01 0xff>;
2029 #address-cells = <3>;
2030 #size-cells = <2>;
2036 compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy";
2043 clock-names = "aux",
2049 clock-output-names = "pcie_1_pipe_clk";
2050 #clock-cells = <0>;
2052 #phy-cells = <0>;
2055 reset-names = "phy";
2057 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2058 assigned-clock-rates = <100000000>;
2064 compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
2065 "jedec,ufs-2.0";
2068 reg-names = "std", "ice";
2071 phy-names = "ufsphy";
2072 lanes-per-direction = <2>;
2073 #reset-cells = <1>;
2075 reset-names = "rst";
2079 clock-names =
2099 freq-table-hz =
2114 compatible = "qcom,sm8150-qmp-ufs-phy";
2120 clock-names = "ref",
2124 power-domains = <&gcc UFS_PHY_GDSC>;
2127 reset-names = "ufsphy";
2129 #phy-cells = <0>;
2134 cryptobam: dma-controller@1dc4000 {
2135 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2138 #dma-cells = <1>;
2140 qcom,controlled-remotely;
2141 num-channels = <8>;
2142 qcom,num-ees = <2>;
2151 compatible = "qcom,sm8150-qce", "qcom,qce";
2154 dma-names = "rx", "tx";
2161 interconnect-names = "memory";
2165 compatible = "qcom,tcsr-mutex";
2167 #hwlock-cells = <1>;
2171 compatible = "qcom,sm8150-tcsr", "syscon";
2176 compatible = "qcom,sm8150-slpi-pas";
2179 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
2184 interrupt-names = "wdog", "fatal", "ready",
2185 "handover", "stop-ack";
2188 clock-names = "xo";
2190 power-domains = <&rpmhpd SM8150_LCX>,
2192 power-domain-names = "lcx", "lmx";
2194 memory-region = <&slpi_mem>;
2198 qcom,smem-states = <&slpi_smp2p_out 0>;
2199 qcom,smem-state-names = "stop";
2203 glink-edge {
2206 qcom,remote-pid = <3>;
2211 qcom,glink-channels = "fastrpcglink-apps-dsp";
2213 qcom,non-secure-domain;
2214 #address-cells = <1>;
2215 #size-cells = <0>;
2217 compute-cb@1 {
2218 compatible = "qcom,fastrpc-compute-cb";
2223 compute-cb@2 {
2224 compatible = "qcom,fastrpc-compute-cb";
2229 compute-cb@3 {
2230 compatible = "qcom,fastrpc-compute-cb";
2233 /* note: shared-cb = <4> in downstream */
2240 compatible = "qcom,adreno-640.1", "qcom,adreno";
2242 reg-names = "kgsl_3d0_reg_memory";
2248 operating-points-v2 = <&gpu_opp_table>;
2252 nvmem-cells = <&gpu_speed_bin>;
2253 nvmem-cell-names = "speed_bin";
2254 #cooling-cells = <2>;
2258 zap-shader {
2259 memory-region = <&gpu_mem>;
2262 gpu_opp_table: opp-table {
2263 compatible = "operating-points-v2";
2265 opp-675000000 {
2266 opp-hz = /bits/ 64 <675000000>;
2267 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2268 opp-supported-hw = <0x2>;
2271 opp-585000000 {
2272 opp-hz = /bits/ 64 <585000000>;
2273 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2274 opp-supported-hw = <0x3>;
2277 opp-499200000 {
2278 opp-hz = /bits/ 64 <499200000>;
2279 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2280 opp-supported-hw = <0x3>;
2283 opp-427000000 {
2284 opp-hz = /bits/ 64 <427000000>;
2285 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2286 opp-supported-hw = <0x3>;
2289 opp-345000000 {
2290 opp-hz = /bits/ 64 <345000000>;
2291 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2292 opp-supported-hw = <0x3>;
2295 opp-257000000 {
2296 opp-hz = /bits/ 64 <257000000>;
2297 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2298 opp-supported-hw = <0x3>;
2304 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
2309 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2313 interrupt-names = "hfi", "gmu";
2320 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2322 power-domains = <&gpucc GPU_CX_GDSC>,
2324 power-domain-names = "cx", "gx";
2328 operating-points-v2 = <&gmu_opp_table>;
2332 gmu_opp_table: opp-table {
2333 compatible = "operating-points-v2";
2335 opp-200000000 {
2336 opp-hz = /bits/ 64 <200000000>;
2337 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2342 gpucc: clock-controller@2c90000 {
2343 compatible = "qcom,sm8150-gpucc";
2348 clock-names = "bi_tcxo",
2351 #clock-cells = <1>;
2352 #reset-cells = <1>;
2353 #power-domain-cells = <1>;
2357 compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu",
2358 "qcom,smmu-500", "arm,mmu-500";
2360 #iommu-cells = <2>;
2361 #global-interrupts = <1>;
2374 clock-names = "ahb", "bus", "iface";
2376 power-domains = <&gpucc GPU_CX_GDSC>;
2380 compatible = "qcom,sm8150-pinctrl";
2385 reg-names = "west", "east", "north", "south";
2387 gpio-ranges = <&tlmm 0 0 176>;
2388 gpio-controller;
2389 #gpio-cells = <2>;
2390 interrupt-controller;
2391 #interrupt-cells = <2>;
2392 wakeup-parent = <&pdc>;
2394 qup_i2c0_default: qup-i2c0-default-state {
2397 drive-strength = <0x02>;
2398 bias-disable;
2401 qup_spi0_default: qup-spi0-default-state {
2404 drive-strength = <6>;
2405 bias-disable;
2408 qup_i2c1_default: qup-i2c1-default-state {
2411 drive-strength = <2>;
2412 bias-disable;
2415 qup_spi1_default: qup-spi1-default-state {
2418 drive-strength = <6>;
2419 bias-disable;
2422 qup_i2c2_default: qup-i2c2-default-state {
2425 drive-strength = <2>;
2426 bias-disable;
2429 qup_spi2_default: qup-spi2-default-state {
2432 drive-strength = <6>;
2433 bias-disable;
2436 qup_i2c3_default: qup-i2c3-default-state {
2439 drive-strength = <2>;
2440 bias-disable;
2443 qup_spi3_default: qup-spi3-default-state {
2446 drive-strength = <6>;
2447 bias-disable;
2450 qup_i2c4_default: qup-i2c4-default-state {
2453 drive-strength = <2>;
2454 bias-disable;
2457 qup_spi4_default: qup-spi4-default-state {
2460 drive-strength = <6>;
2461 bias-disable;
2464 qup_i2c5_default: qup-i2c5-default-state {
2467 drive-strength = <2>;
2468 bias-disable;
2471 qup_spi5_default: qup-spi5-default-state {
2474 drive-strength = <6>;
2475 bias-disable;
2478 qup_i2c6_default: qup-i2c6-default-state {
2481 drive-strength = <2>;
2482 bias-disable;
2485 qup_spi6_default: qup-spi6-default-state {
2488 drive-strength = <6>;
2489 bias-disable;
2492 qup_i2c7_default: qup-i2c7-default-state {
2495 drive-strength = <2>;
2496 bias-disable;
2499 qup_spi7_default: qup-spi7-default-state {
2502 drive-strength = <6>;
2503 bias-disable;
2506 qup_i2c8_default: qup-i2c8-default-state {
2509 drive-strength = <2>;
2510 bias-disable;
2513 qup_spi8_default: qup-spi8-default-state {
2516 drive-strength = <6>;
2517 bias-disable;
2520 qup_i2c9_default: qup-i2c9-default-state {
2523 drive-strength = <2>;
2524 bias-disable;
2527 qup_spi9_default: qup-spi9-default-state {
2530 drive-strength = <6>;
2531 bias-disable;
2534 qup_uart9_default: qup-uart9-default-state {
2537 drive-strength = <2>;
2538 bias-disable;
2541 qup_i2c10_default: qup-i2c10-default-state {
2544 drive-strength = <2>;
2545 bias-disable;
2548 qup_spi10_default: qup-spi10-default-state {
2551 drive-strength = <6>;
2552 bias-disable;
2555 qup_i2c11_default: qup-i2c11-default-state {
2558 drive-strength = <2>;
2559 bias-disable;
2562 qup_spi11_default: qup-spi11-default-state {
2565 drive-strength = <6>;
2566 bias-disable;
2569 qup_i2c12_default: qup-i2c12-default-state {
2572 drive-strength = <2>;
2573 bias-disable;
2576 qup_spi12_default: qup-spi12-default-state {
2579 drive-strength = <6>;
2580 bias-disable;
2583 qup_i2c13_default: qup-i2c13-default-state {
2586 drive-strength = <2>;
2587 bias-disable;
2590 qup_spi13_default: qup-spi13-default-state {
2593 drive-strength = <6>;
2594 bias-disable;
2597 qup_i2c14_default: qup-i2c14-default-state {
2600 drive-strength = <2>;
2601 bias-disable;
2604 qup_spi14_default: qup-spi14-default-state {
2607 drive-strength = <6>;
2608 bias-disable;
2611 qup_i2c15_default: qup-i2c15-default-state {
2614 drive-strength = <2>;
2615 bias-disable;
2618 qup_spi15_default: qup-spi15-default-state {
2621 drive-strength = <6>;
2622 bias-disable;
2625 qup_i2c16_default: qup-i2c16-default-state {
2628 drive-strength = <2>;
2629 bias-disable;
2632 qup_spi16_default: qup-spi16-default-state {
2635 drive-strength = <6>;
2636 bias-disable;
2639 qup_i2c17_default: qup-i2c17-default-state {
2642 drive-strength = <2>;
2643 bias-disable;
2646 qup_spi17_default: qup-spi17-default-state {
2649 drive-strength = <6>;
2650 bias-disable;
2653 qup_i2c18_default: qup-i2c18-default-state {
2656 drive-strength = <2>;
2657 bias-disable;
2660 qup_spi18_default: qup-spi18-default-state {
2663 drive-strength = <6>;
2664 bias-disable;
2667 qup_i2c19_default: qup-i2c19-default-state {
2670 drive-strength = <2>;
2671 bias-disable;
2674 qup_spi19_default: qup-spi19-default-state {
2677 drive-strength = <6>;
2678 bias-disable;
2681 pcie0_default_state: pcie0-default-state {
2682 perst-pins {
2685 drive-strength = <2>;
2686 bias-pull-down;
2689 clkreq-pins {
2692 drive-strength = <2>;
2693 bias-pull-up;
2696 wake-pins {
2699 drive-strength = <2>;
2700 bias-pull-up;
2704 pcie1_default_state: pcie1-default-state {
2705 perst-pins {
2708 drive-strength = <2>;
2709 bias-pull-down;
2712 clkreq-pins {
2715 drive-strength = <2>;
2716 bias-pull-up;
2719 wake-pins {
2722 drive-strength = <2>;
2723 bias-pull-up;
2729 compatible = "qcom,sm8150-mpss-pas";
2732 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2738 interrupt-names = "wdog", "fatal", "ready", "handover",
2739 "stop-ack", "shutdown-ack";
2742 clock-names = "xo";
2744 power-domains = <&rpmhpd SM8150_CX>,
2746 power-domain-names = "cx", "mss";
2748 memory-region = <&mpss_mem>;
2752 qcom,smem-states = <&modem_smp2p_out 0>;
2753 qcom,smem-state-names = "stop";
2757 glink-edge {
2760 qcom,remote-pid = <1>;
2766 compatible = "arm,coresight-stm", "arm,primecell";
2769 reg-names = "stm-base", "stm-stimulus-base";
2772 clock-names = "apb_pclk";
2774 out-ports {
2777 remote-endpoint = <&funnel0_in7>;
2784 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2788 clock-names = "apb_pclk";
2790 out-ports {
2793 remote-endpoint = <&merge_funnel_in0>;
2798 in-ports {
2799 #address-cells = <1>;
2800 #size-cells = <0>;
2805 remote-endpoint = <&stm_out>;
2812 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2816 clock-names = "apb_pclk";
2818 out-ports {
2821 remote-endpoint = <&merge_funnel_in1>;
2826 in-ports {
2827 #address-cells = <1>;
2828 #size-cells = <0>;
2833 remote-endpoint = <&swao_replicator_out>;
2840 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2844 clock-names = "apb_pclk";
2846 out-ports {
2849 remote-endpoint = <&merge_funnel_in2>;
2854 in-ports {
2855 #address-cells = <1>;
2856 #size-cells = <0>;
2861 remote-endpoint = <&apss_merge_funnel_out>;
2868 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2872 clock-names = "apb_pclk";
2874 out-ports {
2877 remote-endpoint = <&etf_in>;
2882 in-ports {
2883 #address-cells = <1>;
2884 #size-cells = <0>;
2889 remote-endpoint = <&funnel0_out>;
2896 remote-endpoint = <&funnel1_out>;
2903 remote-endpoint = <&funnel2_out>;
2910 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2914 clock-names = "apb_pclk";
2916 out-ports {
2917 #address-cells = <1>;
2918 #size-cells = <0>;
2923 remote-endpoint = <&etr_in>;
2930 remote-endpoint = <&replicator1_in>;
2935 in-ports {
2938 remote-endpoint = <&etf_out>;
2945 compatible = "arm,coresight-tmc", "arm,primecell";
2949 clock-names = "apb_pclk";
2951 out-ports {
2954 remote-endpoint = <&replicator_in0>;
2959 in-ports {
2962 remote-endpoint = <&merge_funnel_out>;
2969 compatible = "arm,coresight-tmc", "arm,primecell";
2974 clock-names = "apb_pclk";
2975 arm,scatter-gather;
2977 in-ports {
2980 remote-endpoint = <&replicator_out0>;
2987 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2991 clock-names = "apb_pclk";
2993 out-ports {
2994 #address-cells = <1>;
2995 #size-cells = <0>;
3000 remote-endpoint = <&swao_funnel_in>;
3005 in-ports {
3009 remote-endpoint = <&replicator_out1>;
3016 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3020 clock-names = "apb_pclk";
3022 out-ports {
3025 remote-endpoint = <&swao_etf_in>;
3030 in-ports {
3031 #address-cells = <1>;
3032 #size-cells = <0>;
3037 remote-endpoint = <&replicator1_out>;
3044 compatible = "arm,coresight-tmc", "arm,primecell";
3048 clock-names = "apb_pclk";
3050 out-ports {
3053 remote-endpoint = <&swao_replicator_in>;
3058 in-ports {
3061 remote-endpoint = <&swao_funnel_out>;
3068 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3072 clock-names = "apb_pclk";
3073 qcom,replicator-loses-context;
3075 out-ports {
3078 remote-endpoint = <&funnel1_in4>;
3083 in-ports {
3086 remote-endpoint = <&swao_etf_out>;
3093 compatible = "arm,coresight-etm4x", "arm,primecell";
3099 clock-names = "apb_pclk";
3100 arm,coresight-loses-context-with-cpu;
3101 qcom,skip-power-up;
3103 out-ports {
3106 remote-endpoint = <&apss_funnel_in0>;
3113 compatible = "arm,coresight-etm4x", "arm,primecell";
3119 clock-names = "apb_pclk";
3120 arm,coresight-loses-context-with-cpu;
3121 qcom,skip-power-up;
3123 out-ports {
3126 remote-endpoint = <&apss_funnel_in1>;
3133 compatible = "arm,coresight-etm4x", "arm,primecell";
3139 clock-names = "apb_pclk";
3140 arm,coresight-loses-context-with-cpu;
3141 qcom,skip-power-up;
3143 out-ports {
3146 remote-endpoint = <&apss_funnel_in2>;
3153 compatible = "arm,coresight-etm4x", "arm,primecell";
3159 clock-names = "apb_pclk";
3160 arm,coresight-loses-context-with-cpu;
3161 qcom,skip-power-up;
3163 out-ports {
3166 remote-endpoint = <&apss_funnel_in3>;
3173 compatible = "arm,coresight-etm4x", "arm,primecell";
3179 clock-names = "apb_pclk";
3180 arm,coresight-loses-context-with-cpu;
3181 qcom,skip-power-up;
3183 out-ports {
3186 remote-endpoint = <&apss_funnel_in4>;
3193 compatible = "arm,coresight-etm4x", "arm,primecell";
3199 clock-names = "apb_pclk";
3200 arm,coresight-loses-context-with-cpu;
3201 qcom,skip-power-up;
3203 out-ports {
3206 remote-endpoint = <&apss_funnel_in5>;
3213 compatible = "arm,coresight-etm4x", "arm,primecell";
3219 clock-names = "apb_pclk";
3220 arm,coresight-loses-context-with-cpu;
3221 qcom,skip-power-up;
3223 out-ports {
3226 remote-endpoint = <&apss_funnel_in6>;
3233 compatible = "arm,coresight-etm4x", "arm,primecell";
3239 clock-names = "apb_pclk";
3240 arm,coresight-loses-context-with-cpu;
3241 qcom,skip-power-up;
3243 out-ports {
3246 remote-endpoint = <&apss_funnel_in7>;
3253 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3257 clock-names = "apb_pclk";
3259 out-ports {
3262 remote-endpoint = <&apss_merge_funnel_in>;
3267 in-ports {
3268 #address-cells = <1>;
3269 #size-cells = <0>;
3274 remote-endpoint = <&etm0_out>;
3281 remote-endpoint = <&etm1_out>;
3288 remote-endpoint = <&etm2_out>;
3295 remote-endpoint = <&etm3_out>;
3302 remote-endpoint = <&etm4_out>;
3309 remote-endpoint = <&etm5_out>;
3316 remote-endpoint = <&etm6_out>;
3323 remote-endpoint = <&etm7_out>;
3330 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3334 clock-names = "apb_pclk";
3336 out-ports {
3339 remote-endpoint = <&funnel2_in2>;
3344 in-ports {
3347 remote-endpoint = <&apss_funnel_out>;
3354 compatible = "qcom,sm8150-cdsp-pas";
3357 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3362 interrupt-names = "wdog", "fatal", "ready",
3363 "handover", "stop-ack";
3366 clock-names = "xo";
3368 power-domains = <&rpmhpd SM8150_CX>;
3370 memory-region = <&cdsp_mem>;
3374 qcom,smem-states = <&cdsp_smp2p_out 0>;
3375 qcom,smem-state-names = "stop";
3379 glink-edge {
3382 qcom,remote-pid = <5>;
3387 qcom,glink-channels = "fastrpcglink-apps-dsp";
3389 qcom,non-secure-domain;
3390 #address-cells = <1>;
3391 #size-cells = <0>;
3393 compute-cb@1 {
3394 compatible = "qcom,fastrpc-compute-cb";
3399 compute-cb@2 {
3400 compatible = "qcom,fastrpc-compute-cb";
3405 compute-cb@3 {
3406 compatible = "qcom,fastrpc-compute-cb";
3411 compute-cb@4 {
3412 compatible = "qcom,fastrpc-compute-cb";
3417 compute-cb@5 {
3418 compatible = "qcom,fastrpc-compute-cb";
3423 compute-cb@6 {
3424 compatible = "qcom,fastrpc-compute-cb";
3429 compute-cb@7 {
3430 compatible = "qcom,fastrpc-compute-cb";
3435 compute-cb@8 {
3436 compatible = "qcom,fastrpc-compute-cb";
3447 compatible = "qcom,sm8150-usb-hs-phy",
3448 "qcom,usb-snps-hs-7nm-phy";
3451 #phy-cells = <0>;
3454 clock-names = "ref";
3460 compatible = "qcom,sm8150-usb-hs-phy",
3461 "qcom,usb-snps-hs-7nm-phy";
3464 #phy-cells = <0>;
3467 clock-names = "ref";
3473 compatible = "qcom,sm8150-qmp-usb3-dp-phy";
3480 clock-names = "aux",
3487 reset-names = "phy", "common";
3489 #clock-cells = <1>;
3490 #phy-cells = <1>;
3495 #address-cells = <1>;
3496 #size-cells = <0>;
3509 remote-endpoint = <&usb_1_dwc3_ss>;
3517 remote-endpoint = <&mdss_dp_out>;
3524 compatible = "qcom,sm8150-qmp-usb3-uni-phy";
3531 clock-names = "aux",
3535 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3536 #clock-cells = <0>;
3537 #phy-cells = <0>;
3541 reset-names = "phy",
3548 compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5";
3553 interrupt-names = "hc_irq", "pwr_irq";
3558 clock-names = "iface", "core", "xo";
3560 qcom,dll-config = <0x0007642c>;
3561 qcom,ddr-config = <0x80040868>;
3562 power-domains = <&rpmhpd 0>;
3563 operating-points-v2 = <&sdhc2_opp_table>;
3567 sdhc2_opp_table: opp-table {
3568 compatible = "operating-points-v2";
3570 opp-19200000 {
3571 opp-hz = /bits/ 64 <19200000>;
3572 required-opps = <&rpmhpd_opp_min_svs>;
3575 opp-50000000 {
3576 opp-hz = /bits/ 64 <50000000>;
3577 required-opps = <&rpmhpd_opp_low_svs>;
3580 opp-100000000 {
3581 opp-hz = /bits/ 64 <100000000>;
3582 required-opps = <&rpmhpd_opp_svs>;
3585 opp-202000000 {
3586 opp-hz = /bits/ 64 <202000000>;
3587 required-opps = <&rpmhpd_opp_svs_l1>;
3593 compatible = "qcom,sm8150-dc-noc";
3595 #interconnect-cells = <2>;
3596 qcom,bcm-voters = <&apps_bcm_voter>;
3600 compatible = "qcom,sm8150-gem-noc";
3602 #interconnect-cells = <2>;
3603 qcom,bcm-voters = <&apps_bcm_voter>;
3607 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3610 #address-cells = <2>;
3611 #size-cells = <2>;
3613 dma-ranges;
3621 clock-names = "cfg_noc",
3628 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3630 assigned-clock-rates = <19200000>, <200000000>;
3632 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3637 interrupt-names = "pwr_event",
3643 power-domains = <&gcc USB30_PRIM_GDSC>;
3649 interconnect-names = "usb-ddr", "apps-usb";
3659 snps,dis-u1-entry-quirk;
3660 snps,dis-u2-entry-quirk;
3662 phy-names = "usb2-phy", "usb3-phy";
3665 #address-cells = <1>;
3666 #size-cells = <0>;
3679 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
3687 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3690 #address-cells = <2>;
3691 #size-cells = <2>;
3693 dma-ranges;
3701 clock-names = "cfg_noc",
3708 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3710 assigned-clock-rates = <19200000>, <200000000>;
3712 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
3717 interrupt-names = "pwr_event",
3723 power-domains = <&gcc USB30_SEC_GDSC>;
3729 interconnect-names = "usb-ddr", "apps-usb";
3739 snps,dis-u1-entry-quirk;
3740 snps,dis-u2-entry-quirk;
3742 phy-names = "usb2-phy", "usb3-phy";
3746 videocc: clock-controller@ab00000 {
3747 compatible = "qcom,sm8150-videocc";
3751 clock-names = "iface", "bi_tcxo";
3752 power-domains = <&rpmhpd SM8150_MMCX>;
3753 required-opps = <&rpmhpd_opp_low_svs>;
3754 #clock-cells = <1>;
3755 #reset-cells = <1>;
3756 #power-domain-cells = <1>;
3760 compatible = "qcom,sm8150-camnoc-virt";
3762 #interconnect-cells = <2>;
3763 qcom,bcm-voters = <&apps_bcm_voter>;
3766 camcc: clock-controller@ad00000 {
3767 compatible = "qcom,sm8150-camcc";
3771 power-domains = <&rpmhpd SM8150_MMCX>;
3772 required-opps = <&rpmhpd_opp_low_svs>;
3773 #clock-cells = <1>;
3774 #reset-cells = <1>;
3775 #power-domain-cells = <1>;
3778 mdss: display-subsystem@ae00000 {
3779 compatible = "qcom,sm8150-mdss";
3781 reg-names = "mdss";
3785 interconnect-names = "mdp0-mem", "mdp1-mem";
3787 power-domains = <&dispcc MDSS_GDSC>;
3793 clock-names = "iface", "bus", "nrt_bus", "core";
3796 interrupt-controller;
3797 #interrupt-cells = <1>;
3803 #address-cells = <2>;
3804 #size-cells = <2>;
3807 mdss_mdp: display-controller@ae01000 {
3808 compatible = "qcom,sm8150-dpu";
3811 reg-names = "mdp", "vbif";
3817 clock-names = "iface", "bus", "core", "vsync";
3819 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3820 assigned-clock-rates = <19200000>;
3822 operating-points-v2 = <&mdp_opp_table>;
3823 power-domains = <&rpmhpd SM8150_MMCX>;
3825 interrupt-parent = <&mdss>;
3829 #address-cells = <1>;
3830 #size-cells = <0>;
3835 remote-endpoint = <&mdss_dsi0_in>;
3842 remote-endpoint = <&mdss_dsi1_in>;
3849 remote-endpoint = <&mdss_dp_in>;
3854 mdp_opp_table: opp-table {
3855 compatible = "operating-points-v2";
3857 opp-171428571 {
3858 opp-hz = /bits/ 64 <171428571>;
3859 required-opps = <&rpmhpd_opp_low_svs>;
3862 opp-300000000 {
3863 opp-hz = /bits/ 64 <300000000>;
3864 required-opps = <&rpmhpd_opp_svs>;
3867 opp-345000000 {
3868 opp-hz = /bits/ 64 <345000000>;
3869 required-opps = <&rpmhpd_opp_svs_l1>;
3872 opp-460000000 {
3873 opp-hz = /bits/ 64 <460000000>;
3874 required-opps = <&rpmhpd_opp_nom>;
3879 mdss_dp: displayport-controller@ae90000 {
3880 compatible = "qcom,sm8150-dp", "qcom,sm8350-dp";
3887 interrupt-parent = <&mdss>;
3894 clock-names = "core_iface",
3900 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3902 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3906 phy-names = "dp";
3908 #sound-dai-cells = <0>;
3910 operating-points-v2 = <&dp_opp_table>;
3911 power-domains = <&rpmhpd SM8250_MMCX>;
3916 #address-cells = <1>;
3917 #size-cells = <0>;
3922 remote-endpoint = <&dpu_intf0_out>;
3930 remote-endpoint = <&usb_1_qmpphy_dp_in>;
3935 dp_opp_table: opp-table {
3936 compatible = "operating-points-v2";
3938 opp-160000000 {
3939 opp-hz = /bits/ 64 <160000000>;
3940 required-opps = <&rpmhpd_opp_low_svs>;
3943 opp-270000000 {
3944 opp-hz = /bits/ 64 <270000000>;
3945 required-opps = <&rpmhpd_opp_svs>;
3948 opp-540000000 {
3949 opp-hz = /bits/ 64 <540000000>;
3950 required-opps = <&rpmhpd_opp_svs_l1>;
3953 opp-810000000 {
3954 opp-hz = /bits/ 64 <810000000>;
3955 required-opps = <&rpmhpd_opp_nom>;
3961 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3963 reg-names = "dsi_ctrl";
3965 interrupt-parent = <&mdss>;
3974 clock-names = "byte",
3981 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
3983 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
3986 operating-points-v2 = <&dsi_opp_table>;
3987 power-domains = <&rpmhpd SM8150_MMCX>;
3993 #address-cells = <1>;
3994 #size-cells = <0>;
3997 #address-cells = <1>;
3998 #size-cells = <0>;
4003 remote-endpoint = <&dpu_intf1_out>;
4014 dsi_opp_table: opp-table {
4015 compatible = "operating-points-v2";
4017 opp-187500000 {
4018 opp-hz = /bits/ 64 <187500000>;
4019 required-opps = <&rpmhpd_opp_low_svs>;
4022 opp-300000000 {
4023 opp-hz = /bits/ 64 <300000000>;
4024 required-opps = <&rpmhpd_opp_svs>;
4027 opp-358000000 {
4028 opp-hz = /bits/ 64 <358000000>;
4029 required-opps = <&rpmhpd_opp_svs_l1>;
4035 compatible = "qcom,dsi-phy-7nm-8150";
4039 reg-names = "dsi_phy",
4043 #clock-cells = <1>;
4044 #phy-cells = <0>;
4048 clock-names = "iface", "ref";
4054 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
4056 reg-names = "dsi_ctrl";
4058 interrupt-parent = <&mdss>;
4067 clock-names = "byte",
4074 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
4076 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
4079 operating-points-v2 = <&dsi_opp_table>;
4080 power-domains = <&rpmhpd SM8150_MMCX>;
4086 #address-cells = <1>;
4087 #size-cells = <0>;
4090 #address-cells = <1>;
4091 #size-cells = <0>;
4096 remote-endpoint = <&dpu_intf2_out>;
4109 compatible = "qcom,dsi-phy-7nm-8150";
4113 reg-names = "dsi_phy",
4117 #clock-cells = <1>;
4118 #phy-cells = <0>;
4122 clock-names = "iface", "ref";
4128 dispcc: clock-controller@af00000 {
4129 compatible = "qcom,sm8150-dispcc";
4138 clock-names = "bi_tcxo",
4145 power-domains = <&rpmhpd SM8150_MMCX>;
4146 required-opps = <&rpmhpd_opp_low_svs>;
4147 #clock-cells = <1>;
4148 #reset-cells = <1>;
4149 #power-domain-cells = <1>;
4152 pdc: interrupt-controller@b220000 {
4153 compatible = "qcom,sm8150-pdc", "qcom,pdc";
4155 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
4157 #interrupt-cells = <2>;
4158 interrupt-parent = <&intc>;
4159 interrupt-controller;
4162 aoss_qmp: power-management@c300000 {
4163 compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp";
4168 #clock-cells = <0>;
4172 compatible = "qcom,rpmh-stats";
4176 tsens0: thermal-sensor@c263000 {
4177 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4183 interrupt-names = "uplow", "critical";
4184 #thermal-sensor-cells = <1>;
4187 tsens1: thermal-sensor@c265000 {
4188 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4194 interrupt-names = "uplow", "critical";
4195 #thermal-sensor-cells = <1>;
4199 compatible = "qcom,spmi-pmic-arb";
4205 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4206 interrupt-names = "periph_irq";
4210 #address-cells = <2>;
4211 #size-cells = <0>;
4212 interrupt-controller;
4213 #interrupt-cells = <4>;
4217 compatible = "qcom,sm8150-smmu-500", "qcom,smmu-500", "arm,mmu-500";
4219 #iommu-cells = <2>;
4220 #global-interrupts = <1>;
4302 dma-coherent;
4306 compatible = "qcom,sm8150-adsp-pas";
4309 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
4314 interrupt-names = "wdog", "fatal", "ready",
4315 "handover", "stop-ack";
4318 clock-names = "xo";
4320 power-domains = <&rpmhpd SM8150_CX>;
4322 memory-region = <&adsp_mem>;
4326 qcom,smem-states = <&adsp_smp2p_out 0>;
4327 qcom,smem-state-names = "stop";
4331 glink-edge {
4334 qcom,remote-pid = <2>;
4339 qcom,glink-channels = "fastrpcglink-apps-dsp";
4341 qcom,non-secure-domain;
4342 #address-cells = <1>;
4343 #size-cells = <0>;
4345 compute-cb@3 {
4346 compatible = "qcom,fastrpc-compute-cb";
4351 compute-cb@4 {
4352 compatible = "qcom,fastrpc-compute-cb";
4357 compute-cb@5 {
4358 compatible = "qcom,fastrpc-compute-cb";
4366 intc: interrupt-controller@17a00000 {
4367 compatible = "arm,gic-v3";
4368 interrupt-controller;
4369 #interrupt-cells = <3>;
4376 compatible = "qcom,sm8150-apss-shared",
4377 "qcom,sdm845-apss-shared";
4379 #mbox-cells = <1>;
4383 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
4390 #address-cells = <1>;
4391 #size-cells = <1>;
4393 compatible = "arm,armv7-timer-mem";
4395 clock-frequency = <19200000>;
4398 frame-number = <0>;
4406 frame-number = <1>;
4413 frame-number = <2>;
4420 frame-number = <3>;
4427 frame-number = <4>;
4434 frame-number = <5>;
4441 frame-number = <6>;
4450 compatible = "qcom,rpmh-rsc";
4454 reg-names = "drv-0", "drv-1", "drv-2";
4458 qcom,tcs-offset = <0xd00>;
4459 qcom,drv-id = <2>;
4460 qcom,tcs-config = <ACTIVE_TCS 2>,
4464 power-domains = <&cluster_pd>;
4466 rpmhcc: clock-controller {
4467 compatible = "qcom,sm8150-rpmh-clk";
4468 #clock-cells = <1>;
4469 clock-names = "xo";
4473 rpmhpd: power-controller {
4474 compatible = "qcom,sm8150-rpmhpd";
4475 #power-domain-cells = <1>;
4476 operating-points-v2 = <&rpmhpd_opp_table>;
4478 rpmhpd_opp_table: opp-table {
4479 compatible = "operating-points-v2";
4482 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4486 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4490 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4494 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4498 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4502 opp-level = <224>;
4506 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4510 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4514 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4518 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4522 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4527 apps_bcm_voter: bcm-voter {
4528 compatible = "qcom,bcm-voter";
4533 compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3";
4537 clock-names = "xo", "alternate";
4539 #interconnect-cells = <1>;
4543 compatible = "qcom,sm8150-cpufreq-hw", "qcom,cpufreq-hw";
4546 reg-names = "freq-domain0", "freq-domain1",
4547 "freq-domain2";
4550 clock-names = "xo", "alternate";
4552 #freq-domain-cells = <1>;
4553 #clock-cells = <1>;
4557 compatible = "qcom,sm8150-lmh";
4561 qcom,lmh-temp-arm-millicelsius = <60000>;
4562 qcom,lmh-temp-low-millicelsius = <84500>;
4563 qcom,lmh-temp-high-millicelsius = <85000>;
4564 interrupt-controller;
4565 #interrupt-cells = <1>;
4569 compatible = "qcom,sm8150-lmh";
4573 qcom,lmh-temp-arm-millicelsius = <60000>;
4574 qcom,lmh-temp-low-millicelsius = <84500>;
4575 qcom,lmh-temp-high-millicelsius = <85000>;
4576 interrupt-controller;
4577 #interrupt-cells = <1>;
4581 compatible = "qcom,wcn3990-wifi";
4583 reg-names = "membase";
4584 memory-region = <&wlan_mem>;
4585 clock-names = "cxo_ref_clk_pin", "qdss";
4605 compatible = "arm,armv8-timer";
4612 thermal-zones {
4613 cpu0-thermal {
4614 polling-delay-passive = <250>;
4616 thermal-sensors = <&tsens0 1>;
4619 cpu0_alert0: trip-point0 {
4625 cpu0_alert1: trip-point1 {
4631 cpu0_crit: cpu-crit {
4638 cooling-maps {
4641 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4648 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4656 cpu1-thermal {
4657 polling-delay-passive = <250>;
4659 thermal-sensors = <&tsens0 2>;
4662 cpu1_alert0: trip-point0 {
4668 cpu1_alert1: trip-point1 {
4674 cpu1_crit: cpu-crit {
4681 cooling-maps {
4684 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4691 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4699 cpu2-thermal {
4700 polling-delay-passive = <250>;
4702 thermal-sensors = <&tsens0 3>;
4705 cpu2_alert0: trip-point0 {
4711 cpu2_alert1: trip-point1 {
4717 cpu2_crit: cpu-crit {
4724 cooling-maps {
4727 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4734 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4742 cpu3-thermal {
4743 polling-delay-passive = <250>;
4745 thermal-sensors = <&tsens0 4>;
4748 cpu3_alert0: trip-point0 {
4754 cpu3_alert1: trip-point1 {
4760 cpu3_crit: cpu-crit {
4767 cooling-maps {
4770 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4777 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4785 cpu4-top-thermal {
4786 polling-delay-passive = <250>;
4788 thermal-sensors = <&tsens0 7>;
4791 cpu4_top_alert0: trip-point0 {
4797 cpu4_top_alert1: trip-point1 {
4803 cpu4_top_crit: cpu-crit {
4810 cooling-maps {
4813 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4820 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4828 cpu5-top-thermal {
4829 polling-delay-passive = <250>;
4831 thermal-sensors = <&tsens0 8>;
4834 cpu5_top_alert0: trip-point0 {
4840 cpu5_top_alert1: trip-point1 {
4846 cpu5_top_crit: cpu-crit {
4853 cooling-maps {
4856 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4863 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4871 cpu6-top-thermal {
4872 polling-delay-passive = <250>;
4874 thermal-sensors = <&tsens0 9>;
4877 cpu6_top_alert0: trip-point0 {
4883 cpu6_top_alert1: trip-point1 {
4889 cpu6_top_crit: cpu-crit {
4896 cooling-maps {
4899 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4906 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4914 cpu7-top-thermal {
4915 polling-delay-passive = <250>;
4917 thermal-sensors = <&tsens0 10>;
4920 cpu7_top_alert0: trip-point0 {
4926 cpu7_top_alert1: trip-point1 {
4932 cpu7_top_crit: cpu-crit {
4939 cooling-maps {
4942 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4949 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4957 cpu4-bottom-thermal {
4958 polling-delay-passive = <250>;
4960 thermal-sensors = <&tsens0 11>;
4963 cpu4_bottom_alert0: trip-point0 {
4969 cpu4_bottom_alert1: trip-point1 {
4975 cpu4_bottom_crit: cpu-crit {
4982 cooling-maps {
4985 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4992 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5000 cpu5-bottom-thermal {
5001 polling-delay-passive = <250>;
5003 thermal-sensors = <&tsens0 12>;
5006 cpu5_bottom_alert0: trip-point0 {
5012 cpu5_bottom_alert1: trip-point1 {
5018 cpu5_bottom_crit: cpu-crit {
5025 cooling-maps {
5028 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5035 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5043 cpu6-bottom-thermal {
5044 polling-delay-passive = <250>;
5046 thermal-sensors = <&tsens0 13>;
5049 cpu6_bottom_alert0: trip-point0 {
5055 cpu6_bottom_alert1: trip-point1 {
5061 cpu6_bottom_crit: cpu-crit {
5068 cooling-maps {
5071 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5078 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5086 cpu7-bottom-thermal {
5087 polling-delay-passive = <250>;
5089 thermal-sensors = <&tsens0 14>;
5092 cpu7_bottom_alert0: trip-point0 {
5098 cpu7_bottom_alert1: trip-point1 {
5104 cpu7_bottom_crit: cpu-crit {
5111 cooling-maps {
5114 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5121 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5129 aoss0-thermal {
5130 polling-delay-passive = <250>;
5132 thermal-sensors = <&tsens0 0>;
5135 aoss0_alert0: trip-point0 {
5143 cluster0-thermal {
5144 polling-delay-passive = <250>;
5146 thermal-sensors = <&tsens0 5>;
5149 cluster0_alert0: trip-point0 {
5154 cluster0_crit: cluster0-crit {
5162 cluster1-thermal {
5163 polling-delay-passive = <250>;
5165 thermal-sensors = <&tsens0 6>;
5168 cluster1_alert0: trip-point0 {
5173 cluster1_crit: cluster1-crit {
5181 gpu-top-thermal {
5182 polling-delay-passive = <250>;
5184 thermal-sensors = <&tsens0 15>;
5186 cooling-maps {
5189 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5194 gpu_top_alert0: trip-point0 {
5200 trip-point1 {
5206 trip-point2 {
5214 aoss1-thermal {
5215 polling-delay-passive = <250>;
5217 thermal-sensors = <&tsens1 0>;
5220 aoss1_alert0: trip-point0 {
5228 wlan-thermal {
5229 polling-delay-passive = <250>;
5231 thermal-sensors = <&tsens1 1>;
5234 wlan_alert0: trip-point0 {
5242 video-thermal {
5243 polling-delay-passive = <250>;
5245 thermal-sensors = <&tsens1 2>;
5248 video_alert0: trip-point0 {
5256 mem-thermal {
5257 polling-delay-passive = <250>;
5259 thermal-sensors = <&tsens1 3>;
5262 mem_alert0: trip-point0 {
5270 q6-hvx-thermal {
5271 polling-delay-passive = <250>;
5273 thermal-sensors = <&tsens1 4>;
5276 q6_hvx_alert0: trip-point0 {
5284 camera-thermal {
5285 polling-delay-passive = <250>;
5287 thermal-sensors = <&tsens1 5>;
5290 camera_alert0: trip-point0 {
5298 compute-thermal {
5299 polling-delay-passive = <250>;
5301 thermal-sensors = <&tsens1 6>;
5304 compute_alert0: trip-point0 {
5312 modem-thermal {
5313 polling-delay-passive = <250>;
5315 thermal-sensors = <&tsens1 7>;
5318 modem_alert0: trip-point0 {
5326 npu-thermal {
5327 polling-delay-passive = <250>;
5329 thermal-sensors = <&tsens1 8>;
5332 npu_alert0: trip-point0 {
5340 modem-vec-thermal {
5341 polling-delay-passive = <250>;
5343 thermal-sensors = <&tsens1 9>;
5346 modem_vec_alert0: trip-point0 {
5354 modem-scl-thermal {
5355 polling-delay-passive = <250>;
5357 thermal-sensors = <&tsens1 10>;
5360 modem_scl_alert0: trip-point0 {
5368 gpu-bottom-thermal {
5369 polling-delay-passive = <250>;
5371 thermal-sensors = <&tsens1 11>;
5373 cooling-maps {
5376 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5381 gpu_bottom_alert0: trip-point0 {
5387 trip-point1 {
5393 trip-point2 {