Lines Matching +full:0 +full:x18220000
34 #clock-cells = <0>;
41 #clock-cells = <0>;
49 #size-cells = <0>;
51 CPU0: cpu@0 {
54 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw 0>;
60 qcom,freq-domain = <&cpufreq_hw 0>;
62 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
83 reg = <0x0 0x100>;
84 clocks = <&cpufreq_hw 0>;
89 qcom,freq-domain = <&cpufreq_hw 0>;
91 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
107 reg = <0x0 0x200>;
108 clocks = <&cpufreq_hw 0>;
113 qcom,freq-domain = <&cpufreq_hw 0>;
115 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
131 reg = <0x0 0x300>;
132 clocks = <&cpufreq_hw 0>;
137 qcom,freq-domain = <&cpufreq_hw 0>;
139 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
155 reg = <0x0 0x400>;
163 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
179 reg = <0x0 0x500>;
187 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
203 reg = <0x0 0x600>;
211 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
227 reg = <0x0 0x700>;
235 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
287 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
290 arm,psci-suspend-param = <0x40000004>;
297 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
300 arm,psci-suspend-param = <0x40000004>;
309 CLUSTER_SLEEP_0: cluster-sleep-0 {
311 arm,psci-suspend-param = <0x4100c244>;
619 reg = <0x0 0x80000000 0x0 0x0>;
632 #power-domain-cells = <0>;
638 #power-domain-cells = <0>;
644 #power-domain-cells = <0>;
650 #power-domain-cells = <0>;
656 #power-domain-cells = <0>;
662 #power-domain-cells = <0>;
668 #power-domain-cells = <0>;
674 #power-domain-cells = <0>;
680 #power-domain-cells = <0>;
691 reg = <0x0 0x85700000 0x0 0x600000>;
696 reg = <0x0 0x85d00000 0x0 0x140000>;
701 reg = <0x0 0x85f00000 0x0 0x20000>;
707 reg = <0x0 0x85f20000 0x0 0x20000>;
712 reg = <0x0 0x86000000 0x0 0x200000>;
717 reg = <0x0 0x86200000 0x0 0x3900000>;
723 reg = <0x0 0x89b00000 0x0 0x200000>;
731 reg = <0x0 0x8b700000 0x0 0x500000>;
736 reg = <0x0 0x8bc00000 0x0 0x180000>;
741 reg = <0x0 0x8bd80000 0x0 0x80000>;
746 reg = <0x0 0x8be00000 0x0 0x1a00000>;
751 reg = <0x0 0x8d800000 0x0 0x9600000>;
756 reg = <0x0 0x96e00000 0x0 0x500000>;
761 reg = <0x0 0x97300000 0x0 0x1400000>;
766 reg = <0x0 0x98700000 0x0 0x10000>;
771 reg = <0x0 0x98710000 0x0 0x5000>;
776 reg = <0x0 0x98715000 0x0 0x2000>;
781 reg = <0x0 0x98800000 0x0 0x100000>;
786 reg = <0x0 0x98900000 0x0 0x1400000>;
791 reg = <0x0 0x9e400000 0x0 0x1400000>;
810 qcom,local-pid = <0>;
834 qcom,local-pid = <0>;
858 qcom,local-pid = <0>;
882 qcom,local-pid = <0>;
898 soc: soc@0 {
901 ranges = <0 0 0 0 0x10 0>;
902 dma-ranges = <0 0 0 0 0x10 0>;
907 reg = <0x0 0x00100000 0x0 0x1f0000>;
919 reg = <0 0x00800000 0 0x60000>;
934 dma-channel-mask = <0xfa>;
935 iommus = <&apps_smmu 0x00d6 0x0>;
942 reg = <0x0 0x00020000 0x0 0x10000>,
943 <0x0 0x00036000 0x0 0x100>;
957 iommus = <&apps_smmu 0x3c0 0x0>;
968 reg = <0 0x00784000 0 0x8ff>;
973 reg = <0x133 0x1>;
980 reg = <0x0 0x008c0000 0x0 0x6000>;
984 iommus = <&apps_smmu 0xc3 0x0>;
992 reg = <0 0x00880000 0 0x4000>;
995 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
996 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
999 pinctrl-0 = <&qup_i2c0_default>;
1002 #size-cells = <0>;
1008 reg = <0 0x00880000 0 0x4000>;
1012 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1013 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1016 pinctrl-0 = <&qup_spi0_default>;
1020 #size-cells = <0>;
1026 reg = <0 0x00884000 0 0x4000>;
1029 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1033 pinctrl-0 = <&qup_i2c1_default>;
1036 #size-cells = <0>;
1042 reg = <0 0x00884000 0 0x4000>;
1046 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1050 pinctrl-0 = <&qup_spi1_default>;
1054 #size-cells = <0>;
1060 reg = <0 0x00888000 0 0x4000>;
1063 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1067 pinctrl-0 = <&qup_i2c2_default>;
1070 #size-cells = <0>;
1076 reg = <0 0x00888000 0 0x4000>;
1080 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1084 pinctrl-0 = <&qup_spi2_default>;
1088 #size-cells = <0>;
1094 reg = <0 0x0088c000 0 0x4000>;
1097 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1101 pinctrl-0 = <&qup_i2c3_default>;
1104 #size-cells = <0>;
1110 reg = <0 0x0088c000 0 0x4000>;
1114 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1118 pinctrl-0 = <&qup_spi3_default>;
1122 #size-cells = <0>;
1128 reg = <0 0x00890000 0 0x4000>;
1131 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1135 pinctrl-0 = <&qup_i2c4_default>;
1138 #size-cells = <0>;
1144 reg = <0 0x00890000 0 0x4000>;
1148 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1152 pinctrl-0 = <&qup_spi4_default>;
1156 #size-cells = <0>;
1162 reg = <0 0x00894000 0 0x4000>;
1165 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1169 pinctrl-0 = <&qup_i2c5_default>;
1172 #size-cells = <0>;
1178 reg = <0 0x00894000 0 0x4000>;
1182 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1186 pinctrl-0 = <&qup_spi5_default>;
1190 #size-cells = <0>;
1196 reg = <0 0x00898000 0 0x4000>;
1199 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1203 pinctrl-0 = <&qup_i2c6_default>;
1206 #size-cells = <0>;
1212 reg = <0 0x00898000 0 0x4000>;
1216 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1220 pinctrl-0 = <&qup_spi6_default>;
1224 #size-cells = <0>;
1230 reg = <0 0x0089c000 0 0x4000>;
1233 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1237 pinctrl-0 = <&qup_i2c7_default>;
1240 #size-cells = <0>;
1246 reg = <0 0x0089c000 0 0x4000>;
1250 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1254 pinctrl-0 = <&qup_spi7_default>;
1258 #size-cells = <0>;
1265 reg = <0 0x00a00000 0 0x60000>;
1280 dma-channel-mask = <0xfa>;
1281 iommus = <&apps_smmu 0x0616 0x0>;
1288 reg = <0x0 0x00ac0000 0x0 0x6000>;
1292 iommus = <&apps_smmu 0x603 0x0>;
1300 reg = <0 0x00a80000 0 0x4000>;
1303 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1304 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1307 pinctrl-0 = <&qup_i2c8_default>;
1310 #size-cells = <0>;
1316 reg = <0 0x00a80000 0 0x4000>;
1320 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1321 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1324 pinctrl-0 = <&qup_spi8_default>;
1328 #size-cells = <0>;
1334 reg = <0 0x00a84000 0 0x4000>;
1337 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1341 pinctrl-0 = <&qup_i2c9_default>;
1344 #size-cells = <0>;
1350 reg = <0 0x00a84000 0 0x4000>;
1354 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1358 pinctrl-0 = <&qup_spi9_default>;
1362 #size-cells = <0>;
1368 reg = <0x0 0x00a84000 0x0 0x4000>;
1371 pinctrl-0 = <&qup_uart9_default>;
1379 reg = <0 0x00a88000 0 0x4000>;
1382 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1386 pinctrl-0 = <&qup_i2c10_default>;
1389 #size-cells = <0>;
1395 reg = <0 0x00a88000 0 0x4000>;
1399 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1403 pinctrl-0 = <&qup_spi10_default>;
1407 #size-cells = <0>;
1413 reg = <0 0x00a8c000 0 0x4000>;
1416 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1420 pinctrl-0 = <&qup_i2c11_default>;
1423 #size-cells = <0>;
1429 reg = <0 0x00a8c000 0 0x4000>;
1433 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1437 pinctrl-0 = <&qup_spi11_default>;
1441 #size-cells = <0>;
1447 reg = <0x0 0x00a90000 0x0 0x4000>;
1456 reg = <0 0x00a90000 0 0x4000>;
1459 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1463 pinctrl-0 = <&qup_i2c12_default>;
1466 #size-cells = <0>;
1472 reg = <0 0x00a90000 0 0x4000>;
1476 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1480 pinctrl-0 = <&qup_spi12_default>;
1484 #size-cells = <0>;
1490 reg = <0 0x00094000 0 0x4000>;
1493 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1497 pinctrl-0 = <&qup_i2c16_default>;
1500 #size-cells = <0>;
1506 reg = <0 0x00a94000 0 0x4000>;
1510 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1514 pinctrl-0 = <&qup_spi16_default>;
1518 #size-cells = <0>;
1525 reg = <0 0x00c00000 0 0x60000>;
1540 dma-channel-mask = <0xfa>;
1541 iommus = <&apps_smmu 0x07b6 0x0>;
1548 reg = <0x0 0x00cc0000 0x0 0x6000>;
1553 iommus = <&apps_smmu 0x7a3 0x0>;
1561 reg = <0 0x00c80000 0 0x4000>;
1564 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1565 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1568 pinctrl-0 = <&qup_i2c17_default>;
1571 #size-cells = <0>;
1577 reg = <0 0x00c80000 0 0x4000>;
1581 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1582 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1585 pinctrl-0 = <&qup_spi17_default>;
1589 #size-cells = <0>;
1595 reg = <0 0x00c84000 0 0x4000>;
1598 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1602 pinctrl-0 = <&qup_i2c18_default>;
1605 #size-cells = <0>;
1611 reg = <0 0x00c84000 0 0x4000>;
1615 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1619 pinctrl-0 = <&qup_spi18_default>;
1623 #size-cells = <0>;
1629 reg = <0 0x00c88000 0 0x4000>;
1632 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1636 pinctrl-0 = <&qup_i2c19_default>;
1639 #size-cells = <0>;
1645 reg = <0 0x00c88000 0 0x4000>;
1649 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1653 pinctrl-0 = <&qup_spi19_default>;
1657 #size-cells = <0>;
1663 reg = <0 0x00c8c000 0 0x4000>;
1666 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1670 pinctrl-0 = <&qup_i2c13_default>;
1673 #size-cells = <0>;
1679 reg = <0 0x00c8c000 0 0x4000>;
1683 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1687 pinctrl-0 = <&qup_spi13_default>;
1691 #size-cells = <0>;
1697 reg = <0 0x00c90000 0 0x4000>;
1700 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1704 pinctrl-0 = <&qup_i2c14_default>;
1707 #size-cells = <0>;
1713 reg = <0 0x00c90000 0 0x4000>;
1717 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1721 pinctrl-0 = <&qup_spi14_default>;
1725 #size-cells = <0>;
1731 reg = <0 0x00c94000 0 0x4000>;
1734 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1738 pinctrl-0 = <&qup_i2c15_default>;
1741 #size-cells = <0>;
1747 reg = <0 0x00c94000 0 0x4000>;
1751 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1755 pinctrl-0 = <&qup_spi15_default>;
1759 #size-cells = <0>;
1766 reg = <0 0x01500000 0 0x7400>;
1773 reg = <0 0x01620000 0 0x19400>;
1780 reg = <0 0x0163a000 0 0x1000>;
1787 reg = <0 0x016e0000 0 0xd080>;
1794 reg = <0 0x01700000 0 0x20000>;
1801 reg = <0 0x01720000 0 0x7000>;
1808 reg = <0 0x01740000 0 0x1c100>;
1815 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
1816 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
1817 <0 0x09600000 0 0x50000>;
1825 reg = <0x0 0x010a2000 0x0 0x1000>,
1826 <0x0 0x010ad000 0x0 0x3000>;
1831 reg = <0 0x01c00000 0 0x3000>,
1832 <0 0x60000000 0 0xf1d>,
1833 <0 0x60000f20 0 0xa8>,
1834 <0 0x60001000 0 0x1000>,
1835 <0 0x60100000 0 0x100000>;
1838 linux,pci-domain = <0>;
1839 bus-range = <0x00 0xff>;
1845 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1846 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1865 interrupt-map-mask = <0 0 0 0x7>;
1866 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1867 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1868 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1869 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1888 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1889 <0x100 &apps_smmu 0x1d81 0x1>;
1903 pinctrl-0 = <&pcie0_default_state>;
1907 pcie@0 {
1909 reg = <0x0 0x0 0x0 0x0 0x0>;
1910 bus-range = <0x01 0xff>;
1920 reg = <0 0x01c06000 0 0x1000>;
1933 #clock-cells = <0>;
1935 #phy-cells = <0>;
1948 reg = <0 0x01c08000 0 0x3000>,
1949 <0 0x40000000 0 0xf1d>,
1950 <0 0x40000f20 0 0xa8>,
1951 <0 0x40001000 0 0x1000>,
1952 <0 0x40100000 0 0x100000>;
1956 bus-range = <0x00 0xff>;
1962 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1963 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1982 interrupt-map-mask = <0 0 0 0x7>;
1983 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1984 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1985 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1986 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2008 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
2009 <0x100 &apps_smmu 0x1e01 0x1>;
2023 pinctrl-0 = <&pcie1_default_state>;
2027 pcie@0 {
2029 reg = <0x0 0x0 0x0 0x0 0x0>;
2030 bus-range = <0x01 0xff>;
2040 reg = <0 0x01c0e000 0 0x1000>;
2053 #clock-cells = <0>;
2055 #phy-cells = <0>;
2069 reg = <0 0x01d84000 0 0x2500>,
2070 <0 0x01d90000 0 0x8000>;
2080 iommus = <&apps_smmu 0x300 0>;
2104 <0 0>,
2105 <0 0>,
2107 <0 0>,
2108 <0 0>,
2109 <0 0>,
2110 <0 0>,
2111 <0 300000000>;
2118 reg = <0 0x01d87000 0 0x1000>;
2129 resets = <&ufs_mem_hc 0>;
2132 #phy-cells = <0>;
2139 reg = <0 0x01dc4000 0 0x24000>;
2142 qcom,ee = <0>;
2146 iommus = <&apps_smmu 0x502 0x0641>,
2147 <&apps_smmu 0x504 0x0011>,
2148 <&apps_smmu 0x506 0x0011>,
2149 <&apps_smmu 0x508 0x0011>,
2150 <&apps_smmu 0x512 0x0000>;
2155 reg = <0 0x01dfa000 0 0x6000>;
2158 iommus = <&apps_smmu 0x502 0x0641>,
2159 <&apps_smmu 0x504 0x0011>,
2160 <&apps_smmu 0x506 0x0011>,
2161 <&apps_smmu 0x508 0x0011>,
2162 <&apps_smmu 0x512 0x0000>;
2163 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>;
2169 reg = <0x0 0x01f40000 0x0 0x20000>;
2175 reg = <0x0 0x01f60000 0x0 0x20000>;
2180 reg = <0x0 0x02400000 0x0 0x4040>;
2183 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2201 qcom,smem-states = <&slpi_smp2p_out 0>;
2218 #size-cells = <0>;
2223 iommus = <&apps_smmu 0x05a1 0x0>;
2229 iommus = <&apps_smmu 0x05a2 0x0>;
2235 iommus = <&apps_smmu 0x05a3 0x0>;
2244 reg = <0 0x02c00000 0 0x40000>;
2249 iommus = <&adreno_smmu 0 0x401>;
2271 opp-supported-hw = <0x2>;
2277 opp-supported-hw = <0x3>;
2283 opp-supported-hw = <0x3>;
2289 opp-supported-hw = <0x3>;
2295 opp-supported-hw = <0x3>;
2301 opp-supported-hw = <0x3>;
2309 reg = <0 0x02c6a000 0 0x30000>,
2310 <0 0x0b290000 0 0x10000>,
2311 <0 0x0b490000 0 0x10000>;
2329 iommus = <&adreno_smmu 5 0x400>;
2347 reg = <0 0x02c90000 0 0x9000>;
2362 reg = <0 0x02ca0000 0 0x10000>;
2384 reg = <0x0 0x03100000 0x0 0x300000>,
2385 <0x0 0x03500000 0x0 0x300000>,
2386 <0x0 0x03900000 0x0 0x300000>,
2387 <0x0 0x03D00000 0x0 0x300000>;
2390 gpio-ranges = <&tlmm 0 0 176>;
2400 drive-strength = <0x02>;
2733 reg = <0x0 0x04080000 0x0 0x4040>;
2736 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2755 qcom,smem-states = <&modem_smp2p_out 0>;
2770 reg = <0 0x06002000 0 0x1000>,
2771 <0 0x16280000 0 0x180000>;
2788 reg = <0 0x06041000 0 0x1000>;
2803 #size-cells = <0>;
2816 reg = <0 0x06042000 0 0x1000>;
2831 #size-cells = <0>;
2844 reg = <0 0x06043000 0 0x1000>;
2859 #size-cells = <0>;
2872 reg = <0 0x06045000 0 0x1000>;
2887 #size-cells = <0>;
2889 port@0 {
2890 reg = <0>;
2914 reg = <0 0x06046000 0 0x1000>;
2921 #size-cells = <0>;
2923 port@0 {
2924 reg = <0>;
2949 reg = <0 0x06047000 0 0x1000>;
2973 reg = <0 0x06048000 0 0x1000>;
2974 iommus = <&apps_smmu 0x05e0 0x0>;
2991 reg = <0 0x0604a000 0 0x1000>;
2998 #size-cells = <0>;
3020 reg = <0 0x06b08000 0 0x1000>;
3035 #size-cells = <0>;
3048 reg = <0 0x06b09000 0 0x1000>;
3072 reg = <0 0x06b0a000 0 0x1000>;
3097 reg = <0 0x07040000 0 0x1000>;
3117 reg = <0 0x07140000 0 0x1000>;
3137 reg = <0 0x07240000 0 0x1000>;
3157 reg = <0 0x07340000 0 0x1000>;
3177 reg = <0 0x07440000 0 0x1000>;
3197 reg = <0 0x07540000 0 0x1000>;
3217 reg = <0 0x07640000 0 0x1000>;
3237 reg = <0 0x07740000 0 0x1000>;
3257 reg = <0 0x07800000 0 0x1000>;
3272 #size-cells = <0>;
3274 port@0 {
3275 reg = <0>;
3334 reg = <0 0x07810000 0 0x1000>;
3358 reg = <0x0 0x08300000 0x0 0x4040>;
3361 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3377 qcom,smem-states = <&cdsp_smp2p_out 0>;
3394 #size-cells = <0>;
3399 iommus = <&apps_smmu 0x1001 0x0460>;
3405 iommus = <&apps_smmu 0x1002 0x0460>;
3411 iommus = <&apps_smmu 0x1003 0x0460>;
3417 iommus = <&apps_smmu 0x1004 0x0460>;
3423 iommus = <&apps_smmu 0x1005 0x0460>;
3429 iommus = <&apps_smmu 0x1006 0x0460>;
3435 iommus = <&apps_smmu 0x1007 0x0460>;
3441 iommus = <&apps_smmu 0x1008 0x0460>;
3452 reg = <0 0x088e2000 0 0x400>;
3454 #phy-cells = <0>;
3465 reg = <0 0x088e3000 0 0x400>;
3467 #phy-cells = <0>;
3477 reg = <0 0x088e8000 0 0x3000>;
3499 #size-cells = <0>;
3501 port@0 {
3502 reg = <0>;
3528 reg = <0 0x088eb000 0 0x1000>;
3539 #clock-cells = <0>;
3540 #phy-cells = <0>;
3552 reg = <0 0x08804000 0 0x1000>;
3562 iommus = <&apps_smmu 0x6a0 0x0>;
3563 qcom,dll-config = <0x0007642c>;
3564 qcom,ddr-config = <0x80040868>;
3565 power-domains = <&rpmhpd 0>;
3597 reg = <0 0x09160000 0 0x3200>;
3604 reg = <0 0x09680000 0 0x3e200>;
3611 reg = <0 0x0a6f8800 0 0x400>;
3650 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
3651 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
3656 reg = <0 0x0a600000 0 0xcd00>;
3658 iommus = <&apps_smmu 0x140 0>;
3666 #size-cells = <0>;
3668 port@0 {
3669 reg = <0>;
3688 reg = <0 0x0a8f8800 0 0x400>;
3727 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
3728 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
3733 reg = <0 0x0a800000 0 0xcd00>;
3735 iommus = <&apps_smmu 0x160 0>;
3745 reg = <0 0x0ab00000 0 0x10000>;
3758 reg = <0 0x0ac00000 0 0x1000>;
3765 reg = <0 0x0ad00000 0 0x10000>;
3777 reg = <0 0x0ae00000 0 0x1000>;
3780 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
3781 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
3796 iommus = <&apps_smmu 0x800 0x420>;
3806 reg = <0 0x0ae01000 0 0x8f000>,
3807 <0 0x0aeb0000 0 0x2008>;
3823 interrupts = <0>;
3827 #size-cells = <0>;
3829 port@0 {
3830 reg = <0>;
3878 reg = <0 0xae90000 0 0x200>,
3879 <0 0xae90200 0 0x200>,
3880 <0 0xae90400 0 0x600>,
3881 <0 0x0ae90a00 0 0x600>,
3882 <0 0x0ae91000 0 0x600>;
3905 #sound-dai-cells = <0>;
3914 #size-cells = <0>;
3916 port@0 {
3917 reg = <0>;
3959 reg = <0 0x0ae94000 0 0x400>;
3980 assigned-clock-parents = <&mdss_dsi0_phy 0>,
3991 #size-cells = <0>;
3995 #size-cells = <0>;
3997 port@0 {
3998 reg = <0>;
4033 reg = <0 0x0ae94400 0 0x200>,
4034 <0 0x0ae94600 0 0x280>,
4035 <0 0x0ae94900 0 0x260>;
4041 #phy-cells = <0>;
4052 reg = <0 0x0ae96000 0 0x400>;
4073 assigned-clock-parents = <&mdss_dsi1_phy 0>,
4084 #size-cells = <0>;
4088 #size-cells = <0>;
4090 port@0 {
4091 reg = <0>;
4107 reg = <0 0x0ae96400 0 0x200>,
4108 <0 0x0ae96600 0 0x280>,
4109 <0 0x0ae96900 0 0x260>;
4115 #phy-cells = <0>;
4127 reg = <0 0x0af00000 0 0x10000>;
4129 <&mdss_dsi0_phy 0>,
4131 <&mdss_dsi1_phy 0>,
4151 reg = <0 0x0b220000 0 0x30000>;
4152 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
4161 reg = <0x0 0x0c300000 0x0 0x400>;
4163 mboxes = <&apss_shared 0>;
4165 #clock-cells = <0>;
4170 reg = <0 0x0c3f0000 0 0x400>;
4175 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4176 <0 0x0c222000 0 0x1ff>; /* SROT */
4186 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4187 <0 0x0c223000 0 0x1ff>; /* SROT */
4197 reg = <0x0 0x0c440000 0x0 0x0001100>,
4198 <0x0 0x0c600000 0x0 0x2000000>,
4199 <0x0 0x0e600000 0x0 0x0100000>,
4200 <0x0 0x0e700000 0x0 0x00a0000>,
4201 <0x0 0x0c40a000 0x0 0x0026000>;
4205 qcom,ee = <0>;
4206 qcom,channel = <0>;
4208 #size-cells = <0>;
4215 reg = <0 0x15000000 0 0x100000>;
4303 reg = <0x0 0x17300000 0x0 0x4040>;
4306 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
4322 qcom,smem-states = <&adsp_smp2p_out 0>;
4339 #size-cells = <0>;
4344 iommus = <&apps_smmu 0x1b23 0x0>;
4350 iommus = <&apps_smmu 0x1b24 0x0>;
4356 iommus = <&apps_smmu 0x1b25 0x0>;
4366 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
4367 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
4374 reg = <0x0 0x17c00000 0x0 0x1000>;
4380 reg = <0 0x17c10000 0 0x1000>;
4382 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
4388 ranges = <0 0 0 0x20000000>;
4390 reg = <0x0 0x17c20000 0x0 0x1000>;
4394 frame-number = <0>;
4397 reg = <0x17c21000 0x1000>,
4398 <0x17c22000 0x1000>;
4404 reg = <0x17c23000 0x1000>;
4411 reg = <0x17c25000 0x1000>;
4418 reg = <0x17c26000 0x1000>;
4425 reg = <0x17c29000 0x1000>;
4432 reg = <0x17c2b000 0x1000>;
4439 reg = <0x17c2d000 0x1000>;
4447 reg = <0x0 0x18200000 0x0 0x10000>,
4448 <0x0 0x18210000 0x0 0x10000>,
4449 <0x0 0x18220000 0x0 0x10000>;
4450 reg-names = "drv-0", "drv-1", "drv-2";
4454 qcom,tcs-offset = <0xd00>;
4530 reg = <0 0x18321000 0 0x1400>;
4540 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
4541 <0 0x18327800 0 0x1400>;
4554 reg = <0 0x18350800 0 0x400>;
4566 reg = <0 0x18358800 0 0x400>;
4578 reg = <0 0x18800000 0 0x800000>;
4595 iommus = <&apps_smmu 0x0640 0x1>;
4605 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
5128 thermal-sensors = <&tsens0 0>;
5213 thermal-sensors = <&tsens1 0>;