Lines Matching +full:pil +full:- +full:reloc +full:- +full:info
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,sm6375-gcc.h>
8 #include <dt-bindings/clock/qcom,sm6375-gpucc.h>
9 #include <dt-bindings/dma/qcom-gpi.h>
10 #include <dt-bindings/firmware/qcom,scm.h>
11 #include <dt-bindings/interconnect/qcom,osm-l3.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/mailbox/qcom-ipcc.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
17 interrupt-parent = <&intc>;
19 #address-cells = <2>;
20 #size-cells = <2>;
25 xo_board_clk: xo-board-clk {
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
30 sleep_clk: sleep-clk {
31 compatible = "fixed-clock";
32 clock-frequency = <32000>;
33 #clock-cells = <0>;
38 #address-cells = <2>;
39 #size-cells = <0>;
46 enable-method = "psci";
47 next-level-cache = <&L2_0>;
48 qcom,freq-domain = <&cpufreq_hw 0>;
49 operating-points-v2 = <&cpu0_opp_table>;
51 power-domains = <&CPU_PD0>;
52 power-domain-names = "psci";
53 #cooling-cells = <2>;
54 L2_0: l2-cache {
56 cache-level = <2>;
57 cache-unified;
58 next-level-cache = <&L3_0>;
59 L3_0: l3-cache {
61 cache-level = <3>;
62 cache-unified;
72 enable-method = "psci";
73 next-level-cache = <&L2_100>;
74 qcom,freq-domain = <&cpufreq_hw 0>;
75 operating-points-v2 = <&cpu0_opp_table>;
77 power-domains = <&CPU_PD1>;
78 power-domain-names = "psci";
79 #cooling-cells = <2>;
80 L2_100: l2-cache {
82 cache-level = <2>;
83 cache-unified;
84 next-level-cache = <&L3_0>;
93 enable-method = "psci";
94 next-level-cache = <&L2_200>;
95 qcom,freq-domain = <&cpufreq_hw 0>;
96 operating-points-v2 = <&cpu0_opp_table>;
98 power-domains = <&CPU_PD2>;
99 power-domain-names = "psci";
100 #cooling-cells = <2>;
101 L2_200: l2-cache {
103 cache-level = <2>;
104 cache-unified;
105 next-level-cache = <&L3_0>;
114 enable-method = "psci";
115 next-level-cache = <&L2_300>;
116 qcom,freq-domain = <&cpufreq_hw 0>;
117 operating-points-v2 = <&cpu0_opp_table>;
119 power-domains = <&CPU_PD3>;
120 power-domain-names = "psci";
121 #cooling-cells = <2>;
122 L2_300: l2-cache {
124 cache-level = <2>;
125 cache-unified;
126 next-level-cache = <&L3_0>;
135 enable-method = "psci";
136 next-level-cache = <&L2_400>;
137 qcom,freq-domain = <&cpufreq_hw 0>;
138 operating-points-v2 = <&cpu0_opp_table>;
140 power-domains = <&CPU_PD4>;
141 power-domain-names = "psci";
142 #cooling-cells = <2>;
143 L2_400: l2-cache {
145 cache-level = <2>;
146 cache-unified;
147 next-level-cache = <&L3_0>;
156 enable-method = "psci";
157 next-level-cache = <&L2_500>;
158 qcom,freq-domain = <&cpufreq_hw 0>;
159 operating-points-v2 = <&cpu0_opp_table>;
161 power-domains = <&CPU_PD5>;
162 power-domain-names = "psci";
163 #cooling-cells = <2>;
164 L2_500: l2-cache {
166 cache-level = <2>;
167 cache-unified;
168 next-level-cache = <&L3_0>;
177 enable-method = "psci";
178 next-level-cache = <&L2_600>;
179 qcom,freq-domain = <&cpufreq_hw 1>;
180 operating-points-v2 = <&cpu6_opp_table>;
182 power-domains = <&CPU_PD6>;
183 power-domain-names = "psci";
184 #cooling-cells = <2>;
185 L2_600: l2-cache {
187 cache-level = <2>;
188 cache-unified;
189 next-level-cache = <&L3_0>;
198 enable-method = "psci";
199 next-level-cache = <&L2_700>;
200 qcom,freq-domain = <&cpufreq_hw 1>;
201 operating-points-v2 = <&cpu6_opp_table>;
203 power-domains = <&CPU_PD7>;
204 power-domain-names = "psci";
205 #cooling-cells = <2>;
206 L2_700: l2-cache {
208 cache-level = <2>;
209 cache-unified;
210 next-level-cache = <&L3_0>;
214 cpu-map {
250 idle-states {
251 entry-method = "psci";
253 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
254 compatible = "arm,idle-state";
255 idle-state-name = "silver-power-collapse";
256 arm,psci-suspend-param = <0x40000003>;
257 entry-latency-us = <549>;
258 exit-latency-us = <901>;
259 min-residency-us = <1774>;
260 local-timer-stop;
263 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
264 compatible = "arm,idle-state";
265 idle-state-name = "silver-rail-power-collapse";
266 arm,psci-suspend-param = <0x40000004>;
267 entry-latency-us = <702>;
268 exit-latency-us = <915>;
269 min-residency-us = <4001>;
270 local-timer-stop;
273 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
274 compatible = "arm,idle-state";
275 idle-state-name = "gold-power-collapse";
276 arm,psci-suspend-param = <0x40000003>;
277 entry-latency-us = <523>;
278 exit-latency-us = <1244>;
279 min-residency-us = <2207>;
280 local-timer-stop;
283 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
284 compatible = "arm,idle-state";
285 idle-state-name = "gold-rail-power-collapse";
286 arm,psci-suspend-param = <0x40000004>;
287 entry-latency-us = <526>;
288 exit-latency-us = <1854>;
289 min-residency-us = <5555>;
290 local-timer-stop;
294 domain-idle-states {
295 CLUSTER_SLEEP_0: cluster-sleep-0 {
296 compatible = "domain-idle-state";
297 arm,psci-suspend-param = <0x41000044>;
298 entry-latency-us = <2752>;
299 exit-latency-us = <3048>;
300 min-residency-us = <6118>;
307 compatible = "qcom,scm-sm6375", "qcom,scm";
309 clock-names = "core";
310 #reset-cells = <1>;
314 mpm: interrupt-controller {
316 qcom,rpm-msg-ram = <&apss_mpm>;
319 interrupt-controller;
320 #interrupt-cells = <2>;
321 #power-domain-cells = <0>;
322 interrupt-parent = <&intc>;
323 qcom,mpm-pin-count = <96>;
324 qcom,mpm-pin-map = <5 296>, /* Soundwire wake_irq */
339 cpu0_opp_table: opp-table-cpu0 {
340 compatible = "operating-points-v2";
341 opp-shared;
343 opp-300000000 {
344 opp-hz = /bits/ 64 <300000000>;
345 opp-peak-kBps = <(300000 * 32)>;
348 opp-576000000 {
349 opp-hz = /bits/ 64 <576000000>;
350 opp-peak-kBps = <(556800 * 32)>;
353 opp-691200000 {
354 opp-hz = /bits/ 64 <691200000>;
355 opp-peak-kBps = <(652800 * 32)>;
358 opp-940800000 {
359 opp-hz = /bits/ 64 <940800000>;
360 opp-peak-kBps = <(921600 * 32)>;
363 opp-1113600000 {
364 opp-hz = /bits/ 64 <1113600000>;
365 opp-peak-kBps = <(921600 * 32)>;
368 opp-1324800000 {
369 opp-hz = /bits/ 64 <1324800000>;
370 opp-peak-kBps = <(1171200 * 32)>;
373 opp-1516800000 {
374 opp-hz = /bits/ 64 <1516800000>;
375 opp-peak-kBps = <(1497600 * 32)>;
378 opp-1651200000 {
379 opp-hz = /bits/ 64 <1651200000>;
380 opp-peak-kBps = <(1497600 * 32)>;
383 opp-1708800000 {
384 opp-hz = /bits/ 64 <1708800000>;
385 opp-peak-kBps = <(1497600 * 32)>;
388 opp-1804800000 {
389 opp-hz = /bits/ 64 <1804800000>;
390 opp-peak-kBps = <(1497600 * 32)>;
394 cpu6_opp_table: opp-table-cpu6 {
395 compatible = "operating-points-v2";
396 opp-shared;
398 opp-691200000 {
399 opp-hz = /bits/ 64 <691200000>;
400 opp-peak-kBps = <(556800 * 32)>;
403 opp-940800000 {
404 opp-hz = /bits/ 64 <940800000>;
405 opp-peak-kBps = <(921600 * 32)>;
408 opp-1228800000 {
409 opp-hz = /bits/ 64 <1228800000>;
410 opp-peak-kBps = <(1171200 * 32)>;
413 opp-1401600000 {
414 opp-hz = /bits/ 64 <1401600000>;
415 opp-peak-kBps = <(1382400 * 32)>;
418 opp-1516800000 {
419 opp-hz = /bits/ 64 <1516800000>;
420 opp-peak-kBps = <(1497600 * 32)>;
423 opp-1651200000 {
424 opp-hz = /bits/ 64 <1651200000>;
425 opp-peak-kBps = <(1497600 * 32)>;
428 opp-1804800000 {
429 opp-hz = /bits/ 64 <1804800000>;
430 opp-peak-kBps = <(1497600 * 32)>;
433 opp-1900800000 {
434 opp-hz = /bits/ 64 <1900800000>;
435 opp-peak-kBps = <(1497600 * 32)>;
438 opp-2054400000 {
439 opp-hz = /bits/ 64 <2054400000>;
440 opp-peak-kBps = <(1497600 * 32)>;
443 opp-2208000000 {
444 opp-hz = /bits/ 64 <2208000000>;
445 opp-peak-kBps = <(1497600 * 32)>;
450 compatible = "arm,armv8-pmuv3";
455 compatible = "arm,psci-1.0";
458 CPU_PD0: power-domain-cpu0 {
459 #power-domain-cells = <0>;
460 power-domains = <&CLUSTER_PD>;
461 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
464 CPU_PD1: power-domain-cpu1 {
465 #power-domain-cells = <0>;
466 power-domains = <&CLUSTER_PD>;
467 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
470 CPU_PD2: power-domain-cpu2 {
471 #power-domain-cells = <0>;
472 power-domains = <&CLUSTER_PD>;
473 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
476 CPU_PD3: power-domain-cpu3 {
477 #power-domain-cells = <0>;
478 power-domains = <&CLUSTER_PD>;
479 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
482 CPU_PD4: power-domain-cpu4 {
483 #power-domain-cells = <0>;
484 power-domains = <&CLUSTER_PD>;
485 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
488 CPU_PD5: power-domain-cpu5 {
489 #power-domain-cells = <0>;
490 power-domains = <&CLUSTER_PD>;
491 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
494 CPU_PD6: power-domain-cpu6 {
495 #power-domain-cells = <0>;
496 power-domains = <&CLUSTER_PD>;
497 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
500 CPU_PD7: power-domain-cpu7 {
501 #power-domain-cells = <0>;
502 power-domains = <&CLUSTER_PD>;
503 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
506 CLUSTER_PD: power-domain-cpu-cluster0 {
507 #power-domain-cells = <0>;
508 power-domains = <&mpm>;
509 domain-idle-states = <&CLUSTER_SLEEP_0>;
513 qup_opp_table: opp-table-qup {
514 compatible = "operating-points-v2";
516 opp-75000000 {
517 opp-hz = /bits/ 64 <75000000>;
518 required-opps = <&rpmpd_opp_low_svs>;
521 opp-100000000 {
522 opp-hz = /bits/ 64 <100000000>;
523 required-opps = <&rpmpd_opp_svs>;
526 opp-128000000 {
527 opp-hz = /bits/ 64 <128000000>;
528 required-opps = <&rpmpd_opp_nom>;
532 reserved_memory: reserved-memory {
533 #address-cells = <2>;
534 #size-cells = <2>;
539 no-map;
542 xbl_aop_mem: xbl-aop@80700000 {
544 no-map;
547 reserved_xbl_uefi: xbl-uefi-res@80880000 {
549 no-map;
556 no-map;
561 no-map;
564 cdsp_secure_heap_mem: cdsp-sec-heap@80c00000 {
566 no-map;
569 dfps_data_mem: dpfs-data@85e00000 {
571 no-map;
574 pil_wlan_mem: pil-wlan@86500000 {
576 no-map;
579 pil_adsp_mem: pil-adsp@86700000 {
581 no-map;
584 pil_cdsp_mem: pil-cdsp@88700000 {
586 no-map;
589 pil_video_mem: pil-video@8a500000 {
591 no-map;
594 pil_ipa_fw_mem: pil-ipa-fw@8aa00000 {
596 no-map;
599 pil_ipa_gsi_mem: pil-ipa-gsi@8aa10000 {
601 no-map;
604 pil_gpu_micro_code_mem: pil-gpu-ucode@8aa1a000 {
606 no-map;
609 pil_mpss_wlan_mem: pil-mpss-wlan@8b800000 {
611 no-map;
616 no-map;
620 compatible = "qcom,rmtfs-mem";
622 no-map;
624 qcom,client-id = <1>;
630 no-map;
635 no-map;
640 no-map;
645 compatible = "qcom,sm6375-rpm-proc", "qcom,rpm-proc";
647 glink-edge {
648 compatible = "qcom,glink-rpm";
649 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
652 qcom,rpm-msg-ram = <&rpm_msg_ram>;
655 rpm_requests: rpm-requests {
656 compatible = "qcom,rpm-sm6375", "qcom,glink-smd-rpm";
657 qcom,glink-channels = "rpm_requests";
659 rpmcc: clock-controller {
660 compatible = "qcom,rpmcc-sm6375", "qcom,rpmcc";
662 clock-names = "xo";
663 #clock-cells = <1>;
666 rpmpd: power-controller {
667 compatible = "qcom,sm6375-rpmpd";
668 #power-domain-cells = <1>;
669 operating-points-v2 = <&rpmpd_opp_table>;
671 rpmpd_opp_table: opp-table {
672 compatible = "operating-points-v2";
675 opp-level = <RPM_SMD_LEVEL_RETENTION>;
679 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
683 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
687 opp-level = <RPM_SMD_LEVEL_SVS>;
691 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
695 opp-level = <RPM_SMD_LEVEL_NOM>;
699 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
703 opp-level = <RPM_SMD_LEVEL_TURBO>;
707 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
715 smp2p-adsp {
718 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
724 qcom,local-pid = <0>;
725 qcom,remote-pid = <2>;
727 smp2p_adsp_out: master-kernel {
728 qcom,entry-name = "master-kernel";
729 #qcom,smem-state-cells = <1>;
732 smp2p_adsp_in: slave-kernel {
733 qcom,entry-name = "slave-kernel";
734 interrupt-controller;
735 #interrupt-cells = <2>;
739 smp2p-cdsp {
742 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
748 qcom,local-pid = <0>;
749 qcom,remote-pid = <5>;
751 smp2p_cdsp_out: master-kernel {
752 qcom,entry-name = "master-kernel";
753 #qcom,smem-state-cells = <1>;
756 smp2p_cdsp_in: slave-kernel {
757 qcom,entry-name = "slave-kernel";
758 interrupt-controller;
759 #interrupt-cells = <2>;
763 smp2p-modem {
766 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
772 qcom,local-pid = <0>;
773 qcom,remote-pid = <1>;
775 smp2p_modem_out: master-kernel {
776 qcom,entry-name = "master-kernel";
777 #qcom,smem-state-cells = <1>;
780 smp2p_modem_in: slave-kernel {
781 qcom,entry-name = "slave-kernel";
782 interrupt-controller;
783 #interrupt-cells = <2>;
786 ipa_smp2p_out: ipa-ap-to-modem {
787 qcom,entry-name = "ipa";
788 #qcom,smem-state-cells = <1>;
791 ipa_smp2p_in: ipa-modem-to-ap {
792 qcom,entry-name = "ipa";
793 interrupt-controller;
794 #interrupt-cells = <2>;
797 wlan_smp2p_in: wlan-wpss-to-ap {
798 qcom,entry-name = "wlan";
799 interrupt-controller;
800 #interrupt-cells = <2>;
805 #address-cells = <2>;
806 #size-cells = <2>;
808 dma-ranges = <0 0 0 0 0x10 0>;
809 compatible = "simple-bus";
812 compatible = "qcom,sm6375-ipcc", "qcom,ipcc";
815 interrupt-controller;
816 #interrupt-cells = <3>;
817 #mbox-cells = <2>;
821 compatible = "qcom,tcsr-mutex";
823 #hwlock-cells = <1>;
827 compatible = "qcom,sm6375-tlmm";
830 gpio-ranges = <&tlmm 0 0 157>;
831 wakeup-parent = <&mpm>;
832 interrupt-controller;
833 gpio-controller;
834 #interrupt-cells = <2>;
835 #gpio-cells = <2>;
837 sdc2_off_state: sdc2-off-state {
838 clk-pins {
840 drive-strength = <2>;
841 bias-disable;
844 cmd-pins {
846 drive-strength = <2>;
847 bias-pull-up;
850 data-pins {
852 drive-strength = <2>;
853 bias-pull-up;
857 sdc2_on_state: sdc2-on-state {
858 clk-pins {
860 drive-strength = <16>;
861 bias-disable;
864 cmd-pins {
866 drive-strength = <10>;
867 bias-pull-up;
870 data-pins {
872 drive-strength = <10>;
873 bias-pull-up;
877 qup_i2c0_default: qup-i2c0-default-state {
880 drive-strength = <2>;
881 bias-pull-up;
884 qup_i2c1_default: qup-i2c1-default-state {
887 drive-strength = <2>;
888 bias-pull-up;
891 qup_i2c2_default: qup-i2c2-default-state {
894 drive-strength = <2>;
895 bias-pull-up;
898 qup_i2c8_default: qup-i2c8-default-state {
902 drive-strength = <2>;
903 bias-pull-up;
906 qup_i2c10_default: qup-i2c10-default-state {
909 drive-strength = <2>;
910 bias-pull-up;
913 qup_spi0_default: qup-spi0-default-state {
916 drive-strength = <6>;
917 bias-disable;
920 qup_uart1_default: qup-uart1-default-state {
921 cts-pins {
924 drive-strength = <2>;
925 bias-pull-down;
928 rts-pins {
931 drive-strength = <2>;
932 bias-disable;
935 tx-pins {
938 drive-strength = <2>;
939 bias-disable;
942 rx-pins {
945 drive-strength = <2>;
946 bias-pull-up;
951 gcc: clock-controller@1400000 {
952 compatible = "qcom,sm6375-gcc";
957 #power-domain-cells = <1>;
958 #clock-cells = <1>;
959 #reset-cells = <1>;
963 compatible = "qcom,sm6375-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy";
967 clock-names = "ref";
969 #phy-cells = <0>;
975 compatible = "qcom,spmi-pmic-arb";
981 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
982 interrupt-names = "periph_irq";
983 interrupts-extended = <&mpm 86 IRQ_TYPE_LEVEL_HIGH>;
986 #address-cells = <2>;
987 #size-cells = <0>;
988 interrupt-controller;
989 #interrupt-cells = <4>;
992 tsens0: thermal-sensor@4411000 {
993 compatible = "qcom,sm6375-tsens", "qcom,tsens-v2";
998 interrupt-names = "uplow", "critical";
999 #thermal-sensor-cells = <1>;
1003 tsens1: thermal-sensor@4413000 {
1004 compatible = "qcom,sm6375-tsens", "qcom,tsens-v2";
1009 interrupt-names = "uplow", "critical";
1010 #thermal-sensor-cells = <1>;
1015 compatible = "qcom,rpm-msg-ram", "mmio-sram";
1017 #address-cells = <1>;
1018 #size-cells = <1>;
1027 compatible = "qcom,rpm-stats";
1032 compatible = "qcom,sm6375-sdhci", "qcom,sdhci-msm-v5";
1037 interrupt-names = "hc_irq", "pwr_irq";
1042 clock-names = "iface", "core", "xo";
1046 pinctrl-0 = <&sdc2_on_state>;
1047 pinctrl-1 = <&sdc2_off_state>;
1048 pinctrl-names = "default", "sleep";
1050 qcom,dll-config = <0x0007642c>;
1051 qcom,ddr-config = <0x80040868>;
1052 power-domains = <&rpmpd SM6375_VDDCX>;
1053 operating-points-v2 = <&sdhc2_opp_table>;
1054 bus-width = <4>;
1058 sdhc2_opp_table: opp-table {
1059 compatible = "operating-points-v2";
1061 opp-100000000 {
1062 opp-hz = /bits/ 64 <100000000>;
1063 required-opps = <&rpmpd_opp_low_svs>;
1066 opp-202000000 {
1067 opp-hz = /bits/ 64 <202000000>;
1068 required-opps = <&rpmpd_opp_svs_plus>;
1073 gpi_dma0: dma-controller@4a00000 {
1074 compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma";
1086 dma-channels = <10>;
1087 dma-channel-mask = <0x1f>;
1089 #dma-cells = <3>;
1094 compatible = "qcom,geni-se-qup";
1096 clock-names = "m-ahb", "s-ahb";
1100 #address-cells = <2>;
1101 #size-cells = <2>;
1106 compatible = "qcom,geni-i2c";
1108 clock-names = "se";
1111 pinctrl-names = "default";
1112 pinctrl-0 = <&qup_i2c0_default>;
1115 dma-names = "tx", "rx";
1116 #address-cells = <1>;
1117 #size-cells = <0>;
1122 compatible = "qcom,geni-spi";
1124 clock-names = "se";
1127 pinctrl-names = "default";
1128 pinctrl-0 = <&qup_spi0_default>;
1129 power-domains = <&rpmpd SM6375_VDDCX>;
1130 operating-points-v2 = <&qup_opp_table>;
1133 dma-names = "tx", "rx";
1134 #address-cells = <1>;
1135 #size-cells = <0>;
1140 compatible = "qcom,geni-i2c";
1142 clock-names = "se";
1145 pinctrl-names = "default";
1146 pinctrl-0 = <&qup_i2c1_default>;
1149 dma-names = "tx", "rx";
1150 #address-cells = <1>;
1151 #size-cells = <0>;
1156 compatible = "qcom,geni-spi";
1158 clock-names = "se";
1161 power-domains = <&rpmpd SM6375_VDDCX>;
1162 operating-points-v2 = <&qup_opp_table>;
1165 dma-names = "tx", "rx";
1166 #address-cells = <1>;
1167 #size-cells = <0>;
1172 compatible = "qcom,geni-uart";
1176 clock-names = "se";
1177 power-domains = <&rpmpd SM6375_VDDCX>;
1178 operating-points-v2 = <&qup_opp_table>;
1179 pinctrl-0 = <&qup_uart1_default>;
1180 pinctrl-names = "default";
1185 compatible = "qcom,geni-i2c";
1187 clock-names = "se";
1190 pinctrl-names = "default";
1191 pinctrl-0 = <&qup_i2c2_default>;
1194 dma-names = "tx", "rx";
1195 #address-cells = <1>;
1196 #size-cells = <0>;
1201 compatible = "qcom,geni-spi";
1203 clock-names = "se";
1206 power-domains = <&rpmpd SM6375_VDDCX>;
1207 operating-points-v2 = <&qup_opp_table>;
1210 dma-names = "tx", "rx";
1211 #address-cells = <1>;
1212 #size-cells = <0>;
1225 gpi_dma1: dma-controller@4c00000 {
1226 compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma";
1238 dma-channels = <10>;
1239 dma-channel-mask = <0x1f>;
1241 #dma-cells = <3>;
1246 compatible = "qcom,geni-se-qup";
1248 clock-names = "m-ahb", "s-ahb";
1252 #address-cells = <2>;
1253 #size-cells = <2>;
1258 compatible = "qcom,geni-i2c";
1260 clock-names = "se";
1265 dma-names = "tx", "rx";
1266 #address-cells = <1>;
1267 #size-cells = <0>;
1272 compatible = "qcom,geni-spi";
1274 clock-names = "se";
1277 power-domains = <&rpmpd SM6375_VDDCX>;
1278 operating-points-v2 = <&qup_opp_table>;
1281 dma-names = "tx", "rx";
1282 #address-cells = <1>;
1283 #size-cells = <0>;
1288 compatible = "qcom,geni-i2c";
1290 clock-names = "se";
1295 dma-names = "tx", "rx";
1296 #address-cells = <1>;
1297 #size-cells = <0>;
1302 compatible = "qcom,geni-spi";
1304 clock-names = "se";
1307 power-domains = <&rpmpd SM6375_VDDCX>;
1308 operating-points-v2 = <&qup_opp_table>;
1311 dma-names = "tx", "rx";
1312 #address-cells = <1>;
1313 #size-cells = <0>;
1318 compatible = "qcom,geni-i2c";
1320 clock-names = "se";
1323 pinctrl-names = "default";
1324 pinctrl-0 = <&qup_i2c8_default>;
1327 dma-names = "tx", "rx";
1328 #address-cells = <1>;
1329 #size-cells = <0>;
1334 compatible = "qcom,geni-spi";
1336 clock-names = "se";
1339 power-domains = <&rpmpd SM6375_VDDCX>;
1340 operating-points-v2 = <&qup_opp_table>;
1343 dma-names = "tx", "rx";
1344 #address-cells = <1>;
1345 #size-cells = <0>;
1350 compatible = "qcom,geni-i2c";
1352 clock-names = "se";
1357 dma-names = "tx", "rx";
1358 #address-cells = <1>;
1359 #size-cells = <0>;
1364 compatible = "qcom,geni-spi";
1366 clock-names = "se";
1369 power-domains = <&rpmpd SM6375_VDDCX>;
1370 operating-points-v2 = <&qup_opp_table>;
1373 dma-names = "tx", "rx";
1374 #address-cells = <1>;
1375 #size-cells = <0>;
1380 compatible = "qcom,geni-i2c";
1382 clock-names = "se";
1385 pinctrl-names = "default";
1386 pinctrl-0 = <&qup_i2c10_default>;
1389 dma-names = "tx", "rx";
1390 #address-cells = <1>;
1391 #size-cells = <0>;
1396 compatible = "qcom,geni-spi";
1398 clock-names = "se";
1401 power-domains = <&rpmpd SM6375_VDDCX>;
1402 operating-points-v2 = <&qup_opp_table>;
1405 dma-names = "tx", "rx";
1406 #address-cells = <1>;
1407 #size-cells = <0>;
1413 compatible = "qcom,sm6375-dwc3", "qcom,dwc3";
1422 clock-names = "cfg_noc",
1429 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1431 assigned-clock-rates = <19200000>, <133333333>;
1433 interrupts-extended = <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
1438 interrupt-names = "pwr_event",
1444 power-domains = <&gcc USB30_PRIM_GDSC>;
1450 * USB3 is not implemented yet - (re)move it when
1453 qcom,select-utmi-as-pipe-clk;
1455 #address-cells = <2>;
1456 #size-cells = <2>;
1465 maximum-speed = "high-speed";
1467 phy-names = "usb2-phy";
1471 snps,hird-threshold = /bits/ 8 <0x10>;
1472 snps,usb2-gadget-lpm-disable;
1474 snps,is-utmi-l1-suspend;
1475 snps,dis-u1-entry-quirk;
1476 snps,dis-u2-entry-quirk;
1478 snps,has-lpm-erratum;
1479 tx-fifo-resize;
1484 compatible = "qcom,sm6375-smmu-v2", "qcom,smmu-v2";
1486 #iommu-cells = <1>;
1487 #global-interrupts = <2>;
1500 clock-names = "bus";
1502 power-domains = <&gpucc GPU_CX_GDSC>;
1505 gpucc: clock-controller@5990000 {
1506 compatible = "qcom,sm6375-gpucc";
1512 power-domains = <&rpmpd SM6375_VDDGX>;
1513 required-opps = <&rpmpd_opp_low_svs>;
1514 #clock-cells = <1>;
1515 #reset-cells = <1>;
1516 #power-domain-cells = <1>;
1520 compatible = "qcom,sm6375-mpss-pas";
1523 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
1529 interrupt-names = "wdog",
1533 "stop-ack",
1534 "shutdown-ack";
1537 clock-names = "xo";
1539 power-domains = <&rpmpd SM6375_VDDCX>;
1540 power-domain-names = "cx";
1542 memory-region = <&pil_mpss_wlan_mem>;
1544 qcom,smem-states = <&smp2p_modem_out 0>;
1545 qcom,smem-state-names = "stop";
1549 glink-edge {
1550 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
1556 qcom,remote-pid = <1>;
1561 compatible = "qcom,sm6375-adsp-pas";
1564 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
1569 interrupt-names = "wdog", "fatal", "ready",
1570 "handover", "stop-ack";
1573 clock-names = "xo";
1575 power-domains = <&rpmpd SM6375_VDD_LPI_CX>,
1577 power-domain-names = "lcx", "lmx";
1579 memory-region = <&pil_adsp_mem>;
1581 qcom,smem-states = <&smp2p_adsp_out 0>;
1582 qcom,smem-state-names = "stop";
1586 glink-edge {
1587 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
1594 qcom,remote-pid = <2>;
1599 compatible = "qcom,sm6375-cdsp-pas";
1602 interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
1607 interrupt-names = "wdog", "fatal", "ready",
1608 "handover", "stop-ack";
1611 clock-names = "xo";
1613 power-domains = <&rpmpd SM6375_VDDCX>;
1614 power-domain-names = "cx";
1616 memory-region = <&pil_cdsp_mem>;
1618 qcom,smem-states = <&smp2p_cdsp_out 0>;
1619 qcom,smem-state-names = "stop";
1623 glink-edge {
1624 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
1630 qcom,remote-pid = <5>;
1635 compatible = "qcom,sm6375-imem", "syscon", "simple-mfd";
1639 #address-cells = <1>;
1640 #size-cells = <1>;
1642 pil-reloc@94c {
1643 compatible = "qcom,pil-reloc-info";
1649 compatible = "qcom,sm6375-smmu-500", "arm,mmu-500";
1717 power-domains = <&gcc HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC>,
1720 #global-interrupts = <1>;
1721 #iommu-cells = <2>;
1725 compatible = "qcom,wcn3990-wifi";
1727 reg-names = "membase";
1728 memory-region = <&pil_wlan_mem>;
1742 qcom,msa-fixed-perm;
1746 intc: interrupt-controller@f200000 {
1747 compatible = "arm,gic-v3";
1751 #redistributor-regions = <1>;
1752 #interrupt-cells = <3>;
1753 redistributor-stride = <0 0x20000>;
1754 interrupt-controller;
1758 compatible = "arm,armv7-timer-mem";
1761 #address-cells = <1>;
1762 #size-cells = <1>;
1768 frame-number = <0>;
1774 frame-number = <1>;
1781 frame-number = <2>;
1788 frame-number = <3>;
1795 frame-number = <4>;
1802 frame-number = <5>;
1809 frame-number = <6>;
1815 compatible = "qcom,sm6375-cpucp-l3", "qcom,epss-l3";
1819 clock-names = "xo", "alternate";
1820 #interconnect-cells = <1>;
1824 compatible = "qcom,sm6375-cpufreq-epss", "qcom,cpufreq-epss";
1826 reg-names = "freq-domain0", "freq-domain1";
1829 clock-names = "xo", "alternate";
1832 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1";
1833 #freq-domain-cells = <1>;
1834 #clock-cells = <1>;
1838 thermal-zones {
1839 mapss0-thermal {
1840 thermal-sensors = <&tsens0 0>;
1843 mapss0_alert0: trip-point0 {
1849 mapss0_alert1: trip-point1 {
1855 mapss0_crit: mapss-crit {
1863 cpu0-thermal {
1864 thermal-sensors = <&tsens0 1>;
1867 cpu0_alert0: trip-point0 {
1873 cpu0_alert1: trip-point1 {
1879 cpu0_crit: cpu-crit {
1887 cpu1-thermal {
1888 thermal-sensors = <&tsens0 2>;
1891 cpu1_alert0: trip-point0 {
1897 cpu1_alert1: trip-point1 {
1903 cpu1_crit: cpu-crit {
1911 cpu2-thermal {
1912 thermal-sensors = <&tsens0 3>;
1915 cpu2_alert0: trip-point0 {
1921 cpu2_alert1: trip-point1 {
1927 cpu2_crit: cpu-crit {
1935 cpu3-thermal {
1936 thermal-sensors = <&tsens0 4>;
1939 cpu3_alert0: trip-point0 {
1945 cpu3_alert1: trip-point1 {
1951 cpu3_crit: cpu-crit {
1959 cpu4-thermal {
1960 thermal-sensors = <&tsens0 5>;
1963 cpu4_alert0: trip-point0 {
1969 cpu4_alert1: trip-point1 {
1975 cpu4_crit: cpu-crit {
1983 cpu5-thermal {
1984 thermal-sensors = <&tsens0 6>;
1987 cpu5_alert0: trip-point0 {
1993 cpu5_alert1: trip-point1 {
1999 cpu5_crit: cpu-crit {
2007 cluster0-thermal {
2008 thermal-sensors = <&tsens0 7>;
2011 cluster0_alert0: trip-point0 {
2017 cluster0_alert1: trip-point1 {
2023 cluster0_crit: cpu-crit {
2031 cluster1-thermal {
2032 thermal-sensors = <&tsens0 8>;
2035 cluster1_alert0: trip-point0 {
2041 cluster1_alert1: trip-point1 {
2047 cluster1_crit: cpu-crit {
2055 cpu6-thermal {
2056 thermal-sensors = <&tsens0 9>;
2059 cpu6_alert0: trip-point0 {
2065 cpu6_alert1: trip-point1 {
2071 cpu6_crit: cpu-crit {
2079 cpu7-thermal {
2080 thermal-sensors = <&tsens0 10>;
2083 cpu7_alert0: trip-point0 {
2089 cpu7_alert1: trip-point1 {
2095 cpu7_crit: cpu-crit {
2103 cpu-unk0-thermal {
2104 thermal-sensors = <&tsens0 11>;
2107 cpu_unk0_alert0: trip-point0 {
2113 cpu_unk0_alert1: trip-point1 {
2119 cpu_unk0_crit: cpu-crit {
2127 cpu-unk1-thermal {
2128 thermal-sensors = <&tsens0 12>;
2131 cpu_unk1_alert0: trip-point0 {
2137 cpu_unk1_alert1: trip-point1 {
2143 cpu_unk1_crit: cpu-crit {
2151 gpuss0-thermal {
2152 thermal-sensors = <&tsens0 13>;
2155 gpuss0_alert0: trip-point0 {
2161 gpuss0_alert1: trip-point1 {
2167 gpuss0_crit: gpu-crit {
2175 gpuss1-thermal {
2176 thermal-sensors = <&tsens0 14>;
2179 gpuss1_alert0: trip-point0 {
2185 gpuss1_alert1: trip-point1 {
2191 gpuss1_crit: gpu-crit {
2199 mapss1-thermal {
2200 thermal-sensors = <&tsens1 0>;
2203 mapss1_alert0: trip-point0 {
2209 mapss1_alert1: trip-point1 {
2215 mapss1_crit: mapss-crit {
2223 cwlan-thermal {
2224 thermal-sensors = <&tsens1 1>;
2227 cwlan_alert0: trip-point0 {
2233 cwlan_alert1: trip-point1 {
2239 cwlan_crit: cwlan-crit {
2247 audio-thermal {
2248 thermal-sensors = <&tsens1 2>;
2251 audio_alert0: trip-point0 {
2257 audio_alert1: trip-point1 {
2263 audio_crit: audio-crit {
2271 ddr-thermal {
2272 thermal-sensors = <&tsens1 3>;
2275 ddr_alert0: trip-point0 {
2281 ddr_alert1: trip-point1 {
2287 ddr_crit: ddr-crit {
2295 q6hvx-thermal {
2296 thermal-sensors = <&tsens1 4>;
2299 q6hvx_alert0: trip-point0 {
2305 q6hvx_alert1: trip-point1 {
2311 q6hvx_crit: q6hvx-crit {
2319 camera-thermal {
2320 thermal-sensors = <&tsens1 5>;
2323 camera_alert0: trip-point0 {
2329 camera_alert1: trip-point1 {
2335 camera_crit: camera-crit {
2343 mdm-core0-thermal {
2344 thermal-sensors = <&tsens1 6>;
2347 mdm_core0_alert0: trip-point0 {
2353 mdm_core0_alert1: trip-point1 {
2359 mdm_core0_crit: mdm-core0-crit {
2367 mdm-core1-thermal {
2368 thermal-sensors = <&tsens1 7>;
2371 mdm_core1_alert0: trip-point0 {
2377 mdm_core1_alert1: trip-point1 {
2383 mdm_core1_crit: mdm-core1-crit {
2391 mdm-vec-thermal {
2392 thermal-sensors = <&tsens1 8>;
2395 mdm_vec_alert0: trip-point0 {
2401 mdm_vec_alert1: trip-point1 {
2407 mdm_vec_crit: mdm-vec-crit {
2415 msm-scl-thermal {
2416 thermal-sensors = <&tsens1 9>;
2419 msm_scl_alert0: trip-point0 {
2425 msm_scl_alert1: trip-point1 {
2431 msm_scl_crit: msm-scl-crit {
2439 video-thermal {
2440 thermal-sensors = <&tsens1 10>;
2443 video_alert0: trip-point0 {
2449 video_alert1: trip-point1 {
2455 video_crit: video-crit {
2465 compatible = "arm,armv8-timer";