Lines Matching +full:smp2p +full:- +full:mpss
1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,dispcc-sm6350.h>
8 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
9 #include <dt-bindings/clock/qcom,gcc-sm6350.h>
10 #include <dt-bindings/clock/qcom,gpucc-sm6350.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/clock/qcom,sm6350-camcc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interconnect/qcom,icc.h>
16 #include <dt-bindings/interconnect/qcom,osm-l3.h>
17 #include <dt-bindings/interconnect/qcom,sm6350.h>
18 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/mailbox/qcom-ipcc.h>
20 #include <dt-bindings/phy/phy-qcom-qmp.h>
21 #include <dt-bindings/power/qcom-rpmpd.h>
22 #include <dt-bindings/soc/qcom,apr.h>
23 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
24 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
25 #include <dt-bindings/thermal/thermal.h>
28 interrupt-parent = <&intc>;
29 #address-cells = <2>;
30 #size-cells = <2>;
33 xo_board: xo-board {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <76800000>;
37 clock-output-names = "xo_board";
40 sleep_clk: sleep-clk {
41 compatible = "fixed-clock";
42 clock-frequency = <32764>;
43 #clock-cells = <0>;
48 #address-cells = <2>;
49 #size-cells = <0>;
56 enable-method = "psci";
57 capacity-dmips-mhz = <1024>;
58 dynamic-power-coefficient = <100>;
59 next-level-cache = <&l2_0>;
60 qcom,freq-domain = <&cpufreq_hw 0>;
61 operating-points-v2 = <&cpu0_opp_table>;
65 power-domains = <&cpu_pd0>;
66 power-domain-names = "psci";
67 #cooling-cells = <2>;
68 l2_0: l2-cache {
70 cache-level = <2>;
71 cache-unified;
72 next-level-cache = <&l3_0>;
73 l3_0: l3-cache {
75 cache-level = <3>;
76 cache-unified;
86 enable-method = "psci";
87 capacity-dmips-mhz = <1024>;
88 dynamic-power-coefficient = <100>;
89 next-level-cache = <&l2_100>;
90 qcom,freq-domain = <&cpufreq_hw 0>;
91 operating-points-v2 = <&cpu0_opp_table>;
95 power-domains = <&cpu_pd1>;
96 power-domain-names = "psci";
97 #cooling-cells = <2>;
98 l2_100: l2-cache {
100 cache-level = <2>;
101 cache-unified;
102 next-level-cache = <&l3_0>;
111 enable-method = "psci";
112 capacity-dmips-mhz = <1024>;
113 dynamic-power-coefficient = <100>;
114 next-level-cache = <&l2_200>;
115 qcom,freq-domain = <&cpufreq_hw 0>;
116 operating-points-v2 = <&cpu0_opp_table>;
120 power-domains = <&cpu_pd2>;
121 power-domain-names = "psci";
122 #cooling-cells = <2>;
123 l2_200: l2-cache {
125 cache-level = <2>;
126 cache-unified;
127 next-level-cache = <&l3_0>;
136 enable-method = "psci";
137 capacity-dmips-mhz = <1024>;
138 dynamic-power-coefficient = <100>;
139 next-level-cache = <&l2_300>;
140 qcom,freq-domain = <&cpufreq_hw 0>;
141 operating-points-v2 = <&cpu0_opp_table>;
145 power-domains = <&cpu_pd3>;
146 power-domain-names = "psci";
147 #cooling-cells = <2>;
148 l2_300: l2-cache {
150 cache-level = <2>;
151 cache-unified;
152 next-level-cache = <&l3_0>;
161 enable-method = "psci";
162 capacity-dmips-mhz = <1024>;
163 dynamic-power-coefficient = <100>;
164 next-level-cache = <&l2_400>;
165 qcom,freq-domain = <&cpufreq_hw 0>;
166 operating-points-v2 = <&cpu0_opp_table>;
170 power-domains = <&cpu_pd4>;
171 power-domain-names = "psci";
172 #cooling-cells = <2>;
173 l2_400: l2-cache {
175 cache-level = <2>;
176 cache-unified;
177 next-level-cache = <&l3_0>;
186 enable-method = "psci";
187 capacity-dmips-mhz = <1024>;
188 dynamic-power-coefficient = <100>;
189 next-level-cache = <&l2_500>;
190 qcom,freq-domain = <&cpufreq_hw 0>;
191 operating-points-v2 = <&cpu0_opp_table>;
195 power-domains = <&cpu_pd5>;
196 power-domain-names = "psci";
197 #cooling-cells = <2>;
198 l2_500: l2-cache {
200 cache-level = <2>;
201 cache-unified;
202 next-level-cache = <&l3_0>;
211 enable-method = "psci";
212 capacity-dmips-mhz = <1894>;
213 dynamic-power-coefficient = <703>;
214 next-level-cache = <&l2_600>;
215 qcom,freq-domain = <&cpufreq_hw 1>;
216 operating-points-v2 = <&cpu6_opp_table>;
220 power-domains = <&cpu_pd6>;
221 power-domain-names = "psci";
222 #cooling-cells = <2>;
223 l2_600: l2-cache {
225 cache-level = <2>;
226 cache-unified;
227 next-level-cache = <&l3_0>;
236 enable-method = "psci";
237 capacity-dmips-mhz = <1894>;
238 dynamic-power-coefficient = <703>;
239 next-level-cache = <&l2_700>;
240 qcom,freq-domain = <&cpufreq_hw 1>;
241 operating-points-v2 = <&cpu6_opp_table>;
245 power-domains = <&cpu_pd7>;
246 power-domain-names = "psci";
247 #cooling-cells = <2>;
248 l2_700: l2-cache {
250 cache-level = <2>;
251 cache-unified;
252 next-level-cache = <&l3_0>;
256 cpu-map {
292 domain-idle-states {
293 cluster_sleep_pc: cluster-sleep-0 {
294 compatible = "domain-idle-state";
295 arm,psci-suspend-param = <0x41000044>;
296 entry-latency-us = <2752>;
297 exit-latency-us = <3048>;
298 min-residency-us = <6118>;
301 cluster_sleep_cx_ret: cluster-sleep-1 {
302 compatible = "domain-idle-state";
303 arm,psci-suspend-param = <0x41001244>;
304 entry-latency-us = <3638>;
305 exit-latency-us = <4562>;
306 min-residency-us = <8467>;
309 cluster_aoss_sleep: cluster-sleep-2 {
310 compatible = "domain-idle-state";
311 arm,psci-suspend-param = <0x4100b244>;
312 entry-latency-us = <3263>;
313 exit-latency-us = <6562>;
314 min-residency-us = <9987>;
318 cpu_idle_states: idle-states {
319 entry-method = "psci";
321 little_cpu_sleep_0: cpu-sleep-0-0 {
322 compatible = "arm,idle-state";
323 idle-state-name = "little-power-collapse";
324 arm,psci-suspend-param = <0x40000003>;
325 entry-latency-us = <549>;
326 exit-latency-us = <901>;
327 min-residency-us = <1774>;
328 local-timer-stop;
331 little_cpu_sleep_1: cpu-sleep-0-1 {
332 compatible = "arm,idle-state";
333 idle-state-name = "little-rail-power-collapse";
334 arm,psci-suspend-param = <0x40000004>;
335 entry-latency-us = <702>;
336 exit-latency-us = <915>;
337 min-residency-us = <4001>;
338 local-timer-stop;
341 big_cpu_sleep_0: cpu-sleep-1-0 {
342 compatible = "arm,idle-state";
343 idle-state-name = "big-power-collapse";
344 arm,psci-suspend-param = <0x40000003>;
345 entry-latency-us = <523>;
346 exit-latency-us = <1244>;
347 min-residency-us = <2207>;
348 local-timer-stop;
351 big_cpu_sleep_1: cpu-sleep-1-1 {
352 compatible = "arm,idle-state";
353 idle-state-name = "big-rail-power-collapse";
354 arm,psci-suspend-param = <0x40000004>;
355 entry-latency-us = <526>;
356 exit-latency-us = <1854>;
357 min-residency-us = <5555>;
358 local-timer-stop;
365 compatible = "qcom,scm-sm6350", "qcom,scm";
366 #reset-cells = <1>;
376 cpu0_opp_table: opp-table-cpu0 {
377 compatible = "operating-points-v2";
378 opp-shared;
380 opp-300000000 {
381 opp-hz = /bits/ 64 <300000000>;
382 /* DDR: 4-wide, 2 channels, double data rate, L3: 16-wide, 2 channels */
383 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>;
386 opp-576000000 {
387 opp-hz = /bits/ 64 <576000000>;
388 opp-peak-kBps = <(547000 * 4 * 2 * 2) (556800 * 16 * 2)>;
391 opp-768000000 {
392 opp-hz = /bits/ 64 <768000000>;
393 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>;
396 opp-1017600000 {
397 opp-hz = /bits/ 64 <1017600000>;
398 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>;
401 opp-1248000000 {
402 opp-hz = /bits/ 64 <1248000000>;
403 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>;
406 opp-1324800000 {
407 opp-hz = /bits/ 64 <1324800000>;
408 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1286400 * 16 * 2)>;
411 opp-1516800000 {
412 opp-hz = /bits/ 64 <1516800000>;
413 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
416 opp-1612800000 {
417 opp-hz = /bits/ 64 <1612800000>;
418 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
421 opp-1708800000 {
422 opp-hz = /bits/ 64 <1708800000>;
423 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
427 cpu6_opp_table: opp-table-cpu6 {
428 compatible = "operating-points-v2";
429 opp-shared;
431 opp-300000000 {
432 opp-hz = /bits/ 64 <300000000>;
433 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>;
436 opp-787200000 {
437 opp-hz = /bits/ 64 <787200000>;
438 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>;
441 opp-979200000 {
442 opp-hz = /bits/ 64 <979200000>;
443 opp-peak-kBps = <(768000 * 4 * 2 * 2) (940800 * 16 * 2)>;
446 opp-1036800000 {
447 opp-hz = /bits/ 64 <1036800000>;
448 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>;
451 opp-1248000000 {
452 opp-hz = /bits/ 64 <1248000000>;
453 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>;
456 opp-1401600000 {
457 opp-hz = /bits/ 64 <1401600000>;
458 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1401600 * 16 * 2)>;
461 opp-1555200000 {
462 opp-hz = /bits/ 64 <1555200000>;
463 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
466 opp-1766400000 {
467 opp-hz = /bits/ 64 <1766400000>;
468 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
471 opp-1900800000 {
472 opp-hz = /bits/ 64 <1900800000>;
473 opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
476 opp-2073600000 {
477 opp-hz = /bits/ 64 <2073600000>;
478 opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
482 qup_opp_table: opp-table-qup {
483 compatible = "operating-points-v2";
485 opp-75000000 {
486 opp-hz = /bits/ 64 <75000000>;
487 required-opps = <&rpmhpd_opp_low_svs>;
490 opp-100000000 {
491 opp-hz = /bits/ 64 <100000000>;
492 required-opps = <&rpmhpd_opp_svs>;
495 opp-128000000 {
496 opp-hz = /bits/ 64 <128000000>;
497 required-opps = <&rpmhpd_opp_nom>;
502 compatible = "arm,armv8-pmuv3";
507 compatible = "arm,psci-1.0";
510 cpu_pd0: power-domain-cpu0 {
511 #power-domain-cells = <0>;
512 power-domains = <&cluster_pd>;
513 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
516 cpu_pd1: power-domain-cpu1 {
517 #power-domain-cells = <0>;
518 power-domains = <&cluster_pd>;
519 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
522 cpu_pd2: power-domain-cpu2 {
523 #power-domain-cells = <0>;
524 power-domains = <&cluster_pd>;
525 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
528 cpu_pd3: power-domain-cpu3 {
529 #power-domain-cells = <0>;
530 power-domains = <&cluster_pd>;
531 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
534 cpu_pd4: power-domain-cpu4 {
535 #power-domain-cells = <0>;
536 power-domains = <&cluster_pd>;
537 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
540 cpu_pd5: power-domain-cpu5 {
541 #power-domain-cells = <0>;
542 power-domains = <&cluster_pd>;
543 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
546 cpu_pd6: power-domain-cpu6 {
547 #power-domain-cells = <0>;
548 power-domains = <&cluster_pd>;
549 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
552 cpu_pd7: power-domain-cpu7 {
553 #power-domain-cells = <0>;
554 power-domains = <&cluster_pd>;
555 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
558 cluster_pd: power-domain-cpu-cluster0 {
559 #power-domain-cells = <0>;
560 domain-idle-states = <&cluster_sleep_pc
566 reserved_memory: reserved-memory {
567 #address-cells = <2>;
568 #size-cells = <2>;
573 no-map;
578 no-map;
582 compatible = "qcom,cmd-db";
584 no-map;
589 no-map;
594 no-map;
599 no-map;
604 no-map;
609 no-map;
614 no-map;
619 no-map;
624 no-map;
629 no-map;
634 no-map;
639 no-map;
644 no-map;
649 no-map;
654 no-map;
659 no-map;
664 no-map;
669 no-map;
674 no-map;
680 record-size = <0x1000>;
681 console-size = <0x40000>;
682 pmsg-size = <0x20000>;
683 ecc-size = <16>;
684 no-map;
689 no-map;
695 memory-region = <&smem_mem>;
699 smp2p-adsp {
700 compatible = "qcom,smp2p";
702 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
708 qcom,local-pid = <0>;
709 qcom,remote-pid = <2>;
711 smp2p_adsp_out: master-kernel {
712 qcom,entry-name = "master-kernel";
713 #qcom,smem-state-cells = <1>;
716 smp2p_adsp_in: slave-kernel {
717 qcom,entry-name = "slave-kernel";
718 interrupt-controller;
719 #interrupt-cells = <2>;
723 smp2p-cdsp {
724 compatible = "qcom,smp2p";
726 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
732 qcom,local-pid = <0>;
733 qcom,remote-pid = <5>;
735 smp2p_cdsp_out: master-kernel {
736 qcom,entry-name = "master-kernel";
737 #qcom,smem-state-cells = <1>;
740 smp2p_cdsp_in: slave-kernel {
741 qcom,entry-name = "slave-kernel";
742 interrupt-controller;
743 #interrupt-cells = <2>;
747 smp2p-mpss {
748 compatible = "qcom,smp2p";
751 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
757 qcom,local-pid = <0>;
758 qcom,remote-pid = <1>;
760 modem_smp2p_out: master-kernel {
761 qcom,entry-name = "master-kernel";
762 #qcom,smem-state-cells = <1>;
765 modem_smp2p_in: slave-kernel {
766 qcom,entry-name = "slave-kernel";
767 interrupt-controller;
768 #interrupt-cells = <2>;
771 ipa_smp2p_out: ipa-ap-to-modem {
772 qcom,entry-name = "ipa";
773 #qcom,smem-state-cells = <1>;
776 ipa_smp2p_in: ipa-modem-to-ap {
777 qcom,entry-name = "ipa";
778 interrupt-controller;
779 #interrupt-cells = <2>;
784 #address-cells = <2>;
785 #size-cells = <2>;
787 dma-ranges = <0 0 0 0 0x10 0>;
788 compatible = "simple-bus";
790 gcc: clock-controller@100000 {
791 compatible = "qcom,gcc-sm6350";
793 #clock-cells = <1>;
794 #reset-cells = <1>;
795 #power-domain-cells = <1>;
796 clock-names = "bi_tcxo",
805 compatible = "qcom,sm6350-ipcc", "qcom,ipcc";
808 interrupt-controller;
809 #interrupt-cells = <3>;
810 #mbox-cells = <2>;
814 compatible = "qcom,sm6350-qfprom", "qcom,qfprom";
816 #address-cells = <1>;
817 #size-cells = <1>;
819 gpu_speed_bin: gpu-speed-bin@2015 {
826 compatible = "qcom,prng-ee";
829 clock-names = "core";
833 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
837 reg-names = "hc", "cqhci", "ice";
841 interrupt-names = "hc_irq", "pwr_irq";
847 clock-names = "iface", "core", "xo";
849 qcom,dll-config = <0x000f642c>;
850 qcom,ddr-config = <0x80040868>;
851 power-domains = <&rpmhpd SM6350_CX>;
852 operating-points-v2 = <&sdhc1_opp_table>;
853 bus-width = <8>;
854 non-removable;
855 supports-cqe;
859 sdhc1_opp_table: opp-table {
860 compatible = "operating-points-v2";
862 opp-19200000 {
863 opp-hz = /bits/ 64 <19200000>;
864 required-opps = <&rpmhpd_opp_min_svs>;
867 opp-100000000 {
868 opp-hz = /bits/ 64 <100000000>;
869 required-opps = <&rpmhpd_opp_low_svs>;
872 opp-384000000 {
873 opp-hz = /bits/ 64 <384000000>;
874 required-opps = <&rpmhpd_opp_svs_l1>;
879 gpi_dma0: dma-controller@800000 {
880 compatible = "qcom,sm6350-gpi-dma";
892 dma-channels = <10>;
893 dma-channel-mask = <0x1f>;
895 #dma-cells = <3>;
900 compatible = "qcom,geni-se-qup";
902 clock-names = "m-ahb", "s-ahb";
905 #address-cells = <2>;
906 #size-cells = <2>;
912 compatible = "qcom,geni-i2c";
914 clock-names = "se";
916 pinctrl-names = "default";
917 pinctrl-0 = <&qup_i2c0_default>;
921 dma-names = "tx", "rx";
922 #address-cells = <1>;
923 #size-cells = <0>;
927 interconnect-names = "qup-core", "qup-config", "qup-memory";
932 compatible = "qcom,geni-uart";
934 clock-names = "se";
936 pinctrl-names = "default";
937 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
939 power-domains = <&rpmhpd SM6350_CX>;
940 operating-points-v2 = <&qup_opp_table>;
943 interconnect-names = "qup-core", "qup-config";
948 compatible = "qcom,geni-i2c";
950 clock-names = "se";
952 pinctrl-names = "default";
953 pinctrl-0 = <&qup_i2c2_default>;
957 dma-names = "tx", "rx";
958 #address-cells = <1>;
959 #size-cells = <0>;
963 interconnect-names = "qup-core", "qup-config", "qup-memory";
968 gpi_dma1: dma-controller@900000 {
969 compatible = "qcom,sm6350-gpi-dma";
981 dma-channels = <10>;
982 dma-channel-mask = <0x3f>;
984 #dma-cells = <3>;
989 compatible = "qcom,geni-se-qup";
991 clock-names = "m-ahb", "s-ahb";
994 #address-cells = <2>;
995 #size-cells = <2>;
1001 compatible = "qcom,geni-i2c";
1003 clock-names = "se";
1005 pinctrl-names = "default";
1006 pinctrl-0 = <&qup_i2c6_default>;
1010 dma-names = "tx", "rx";
1011 #address-cells = <1>;
1012 #size-cells = <0>;
1016 interconnect-names = "qup-core", "qup-config", "qup-memory";
1021 compatible = "qcom,geni-i2c";
1023 clock-names = "se";
1025 pinctrl-names = "default";
1026 pinctrl-0 = <&qup_i2c7_default>;
1030 dma-names = "tx", "rx";
1031 #address-cells = <1>;
1032 #size-cells = <0>;
1036 interconnect-names = "qup-core", "qup-config", "qup-memory";
1041 compatible = "qcom,geni-i2c";
1043 clock-names = "se";
1045 pinctrl-names = "default";
1046 pinctrl-0 = <&qup_i2c8_default>;
1050 dma-names = "tx", "rx";
1051 #address-cells = <1>;
1052 #size-cells = <0>;
1056 interconnect-names = "qup-core", "qup-config", "qup-memory";
1061 compatible = "qcom,geni-debug-uart";
1063 clock-names = "se";
1065 pinctrl-names = "default";
1066 pinctrl-0 = <&qup_uart9_default>;
1070 interconnect-names = "qup-core", "qup-config";
1075 compatible = "qcom,geni-i2c";
1077 clock-names = "se";
1079 pinctrl-names = "default";
1080 pinctrl-0 = <&qup_i2c10_default>;
1084 dma-names = "tx", "rx";
1085 #address-cells = <1>;
1086 #size-cells = <0>;
1090 interconnect-names = "qup-core", "qup-config", "qup-memory";
1096 compatible = "qcom,sm6350-config-noc";
1098 #interconnect-cells = <2>;
1099 qcom,bcm-voters = <&apps_bcm_voter>;
1103 compatible = "qcom,sm6350-system-noc";
1105 #interconnect-cells = <2>;
1106 qcom,bcm-voters = <&apps_bcm_voter>;
1108 clk_virt: interconnect-clk-virt {
1109 compatible = "qcom,sm6350-clk-virt";
1110 #interconnect-cells = <2>;
1111 qcom,bcm-voters = <&apps_bcm_voter>;
1116 compatible = "qcom,sm6350-aggre1-noc";
1118 #interconnect-cells = <2>;
1119 qcom,bcm-voters = <&apps_bcm_voter>;
1123 compatible = "qcom,sm6350-aggre2-noc";
1125 #interconnect-cells = <2>;
1126 qcom,bcm-voters = <&apps_bcm_voter>;
1128 compute_noc: interconnect-compute-noc {
1129 compatible = "qcom,sm6350-compute-noc";
1130 #interconnect-cells = <2>;
1131 qcom,bcm-voters = <&apps_bcm_voter>;
1136 compatible = "qcom,sm6350-mmss-noc";
1138 #interconnect-cells = <2>;
1139 qcom,bcm-voters = <&apps_bcm_voter>;
1143 compatible = "qcom,sm6350-ufshc", "qcom,ufshc",
1144 "jedec,ufs-2.0";
1147 reg-names = "std", "ice";
1150 phy-names = "ufsphy";
1151 lanes-per-direction = <2>;
1152 #reset-cells = <1>;
1154 reset-names = "rst";
1156 power-domains = <&gcc UFS_PHY_GDSC>;
1160 clock-names = "core_clk",
1178 freq-table-hz =
1193 compatible = "qcom,sm6350-qmp-ufs-phy";
1199 clock-names = "ref",
1203 power-domains = <&gcc UFS_PHY_GDSC>;
1206 reset-names = "ufsphy";
1208 #phy-cells = <0>;
1213 cryptobam: dma-controller@1dc4000 {
1214 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
1217 #dma-cells = <1>;
1219 qcom,controlled-remotely;
1220 num-channels = <16>;
1221 qcom,num-ees = <4>;
1230 compatible = "qcom,sm6350-qce", "qcom,sm8150-qce", "qcom,qce";
1233 dma-names = "rx", "tx";
1241 interconnect-names = "memory";
1245 compatible = "qcom,sm6350-ipa";
1252 reg-names = "ipa-reg",
1253 "ipa-shared",
1256 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1260 interrupt-names = "ipa",
1262 "ipa-clock-query",
1263 "ipa-setup-ready";
1266 clock-names = "core";
1271 interconnect-names = "memory", "imem", "config";
1273 qcom,smem-states = <&ipa_smp2p_out 0>,
1275 qcom,smem-state-names = "ipa-clock-enabled-valid",
1276 "ipa-clock-enabled";
1282 compatible = "qcom,tcsr-mutex";
1284 #hwlock-cells = <1>;
1288 compatible = "qcom,sm6350-adsp-pas";
1291 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
1296 interrupt-names = "wdog", "fatal", "ready",
1297 "handover", "stop-ack";
1300 clock-names = "xo";
1302 power-domains = <&rpmhpd SM6350_LCX>,
1304 power-domain-names = "lcx", "lmx";
1306 memory-region = <&pil_adsp_mem>;
1310 qcom,smem-states = <&smp2p_adsp_out 0>;
1311 qcom,smem-state-names = "stop";
1315 glink-edge {
1316 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
1323 qcom,remote-pid = <2>;
1326 compatible = "qcom,apr-v2";
1327 qcom,glink-channels = "apr_audio_svc";
1329 #address-cells = <1>;
1330 #size-cells = <0>;
1335 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
1341 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
1344 compatible = "qcom,q6afe-dais";
1345 #address-cells = <1>;
1346 #size-cells = <0>;
1347 #sound-dai-cells = <1>;
1350 q6afecc: clock-controller {
1351 compatible = "qcom,q6afe-clocks";
1352 #clock-cells = <2>;
1359 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
1362 compatible = "qcom,q6asm-dais";
1363 #address-cells = <1>;
1364 #size-cells = <0>;
1365 #sound-dai-cells = <1>;
1373 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
1376 compatible = "qcom,q6adm-routing";
1377 #sound-dai-cells = <0>;
1384 qcom,glink-channels = "fastrpcglink-apps-dsp";
1386 qcom,non-secure-domain;
1387 #address-cells = <1>;
1388 #size-cells = <0>;
1390 compute-cb@3 {
1391 compatible = "qcom,fastrpc-compute-cb";
1396 compute-cb@4 {
1397 compatible = "qcom,fastrpc-compute-cb";
1402 compute-cb@5 {
1403 compatible = "qcom,fastrpc-compute-cb";
1413 compatible = "qcom,adreno-619.0", "qcom,adreno";
1416 reg-names = "kgsl_3d0_reg_memory",
1421 operating-points-v2 = <&gpu_opp_table>;
1423 nvmem-cells = <&gpu_speed_bin>;
1424 nvmem-cell-names = "speed_bin";
1425 #cooling-cells = <2>;
1429 gpu_zap_shader: zap-shader {
1430 memory-region = <&pil_gpu_mem>;
1433 gpu_opp_table: opp-table {
1434 compatible = "operating-points-v2";
1436 opp-850000000 {
1437 opp-hz = /bits/ 64 <850000000>;
1438 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1439 opp-supported-hw = <0x03>;
1442 opp-800000000 {
1443 opp-hz = /bits/ 64 <800000000>;
1444 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1445 opp-supported-hw = <0x07>;
1448 opp-650000000 {
1449 opp-hz = /bits/ 64 <650000000>;
1450 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1451 opp-supported-hw = <0x0f>;
1454 opp-565000000 {
1455 opp-hz = /bits/ 64 <565000000>;
1456 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1457 opp-supported-hw = <0x1f>;
1460 opp-430000000 {
1461 opp-hz = /bits/ 64 <430000000>;
1462 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1463 opp-supported-hw = <0x1f>;
1466 opp-355000000 {
1467 opp-hz = /bits/ 64 <355000000>;
1468 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1469 opp-supported-hw = <0x1f>;
1472 opp-253000000 {
1473 opp-hz = /bits/ 64 <253000000>;
1474 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1475 opp-supported-hw = <0x1f>;
1481 compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
1483 #iommu-cells = <1>;
1484 #global-interrupts = <2>;
1499 clock-names = "ahb",
1503 power-domains = <&gpucc GPU_CX_GDSC>;
1507 compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu";
1511 reg-names = "gmu",
1517 interrupt-names = "hfi",
1525 clock-names = "ahb",
1531 power-domains = <&gpucc GPU_CX_GDSC>,
1533 power-domain-names = "cx",
1538 operating-points-v2 = <&gmu_opp_table>;
1540 gmu_opp_table: opp-table {
1541 compatible = "operating-points-v2";
1543 opp-200000000 {
1544 opp-hz = /bits/ 64 <200000000>;
1545 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1550 gpucc: clock-controller@3d90000 {
1551 compatible = "qcom,sm6350-gpucc";
1556 clock-names = "bi_tcxo",
1559 #clock-cells = <1>;
1560 #reset-cells = <1>;
1561 #power-domain-cells = <1>;
1564 mpss: remoteproc@4080000 { label
1565 compatible = "qcom,sm6350-mpss-pas";
1568 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
1574 interrupt-names = "wdog", "fatal", "ready", "handover",
1575 "stop-ack", "shutdown-ack";
1578 clock-names = "xo";
1580 power-domains = <&rpmhpd SM6350_CX>,
1582 power-domain-names = "cx", "mss";
1584 memory-region = <&pil_modem_mem>;
1588 qcom,smem-states = <&modem_smp2p_out 0>;
1589 qcom,smem-state-names = "stop";
1593 glink-edge {
1594 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
1600 qcom,remote-pid = <1>;
1605 compatible = "qcom,sm6350-cdsp-pas";
1608 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
1613 interrupt-names = "wdog", "fatal", "ready",
1614 "handover", "stop-ack";
1617 clock-names = "xo";
1619 power-domains = <&rpmhpd SM6350_CX>,
1621 power-domain-names = "cx", "mx";
1623 memory-region = <&pil_cdsp_mem>;
1627 qcom,smem-states = <&smp2p_cdsp_out 0>;
1628 qcom,smem-state-names = "stop";
1632 glink-edge {
1633 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
1640 qcom,remote-pid = <5>;
1644 qcom,glink-channels = "fastrpcglink-apps-dsp";
1646 qcom,non-secure-domain;
1647 #address-cells = <1>;
1648 #size-cells = <0>;
1650 compute-cb@1 {
1651 compatible = "qcom,fastrpc-compute-cb";
1656 compute-cb@2 {
1657 compatible = "qcom,fastrpc-compute-cb";
1662 compute-cb@3 {
1663 compatible = "qcom,fastrpc-compute-cb";
1668 compute-cb@4 {
1669 compatible = "qcom,fastrpc-compute-cb";
1674 compute-cb@5 {
1675 compatible = "qcom,fastrpc-compute-cb";
1680 compute-cb@6 {
1681 compatible = "qcom,fastrpc-compute-cb";
1686 compute-cb@7 {
1687 compatible = "qcom,fastrpc-compute-cb";
1692 compute-cb@8 {
1693 compatible = "qcom,fastrpc-compute-cb";
1704 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
1709 interrupt-names = "hc_irq", "pwr_irq";
1715 clock-names = "iface", "core", "xo";
1719 interconnect-names = "sdhc-ddr", "cpu-sdhc";
1721 pinctrl-0 = <&sdc2_on_state>;
1722 pinctrl-1 = <&sdc2_off_state>;
1723 pinctrl-names = "default", "sleep";
1725 qcom,dll-config = <0x0007642c>;
1726 qcom,ddr-config = <0x80040868>;
1727 power-domains = <&rpmhpd SM6350_CX>;
1728 operating-points-v2 = <&sdhc2_opp_table>;
1729 bus-width = <4>;
1733 sdhc2_opp_table: opp-table {
1734 compatible = "operating-points-v2";
1736 opp-100000000 {
1737 opp-hz = /bits/ 64 <100000000>;
1738 required-opps = <&rpmhpd_opp_svs_l1>;
1739 opp-peak-kBps = <790000 131000>;
1740 opp-avg-kBps = <50000 50000>;
1743 opp-202000000 {
1744 opp-hz = /bits/ 64 <202000000>;
1745 required-opps = <&rpmhpd_opp_nom>;
1746 opp-peak-kBps = <3190000 294000>;
1747 opp-avg-kBps = <261438 300000>;
1753 compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy";
1756 #phy-cells = <0>;
1759 clock-names = "cfg_ahb", "ref";
1765 compatible = "qcom,sm6350-qmp-usb3-dp-phy";
1772 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
1774 power-domains = <&gcc USB30_PRIM_GDSC>;
1778 reset-names = "phy", "common";
1780 orientation-switch;
1782 #clock-cells = <1>;
1783 #phy-cells = <1>;
1788 #address-cells = <1>;
1789 #size-cells = <0>;
1802 remote-endpoint = <&usb_1_dwc3_ss_out>;
1816 compatible = "qcom,sm6350-dc-noc";
1818 #interconnect-cells = <2>;
1819 qcom,bcm-voters = <&apps_bcm_voter>;
1822 system-cache-controller@9200000 {
1823 compatible = "qcom,sm6350-llcc";
1825 reg-names = "llcc0_base", "llcc_broadcast_base";
1829 compatible = "qcom,sm6350-gem-noc";
1831 #interconnect-cells = <2>;
1832 qcom,bcm-voters = <&apps_bcm_voter>;
1836 compatible = "qcom,sm6350-npu-noc";
1838 #interconnect-cells = <2>;
1839 qcom,bcm-voters = <&apps_bcm_voter>;
1843 compatible = "qcom,sm6350-llcc-bwmon", "qcom,sdm845-bwmon";
1847 operating-points-v2 = <&llcc_bwmon_opp_table>;
1851 llcc_bwmon_opp_table: opp-table {
1852 compatible = "operating-points-v2";
1854 opp-0 {
1855 opp-peak-kBps = <2288000>;
1858 opp-1 {
1859 opp-peak-kBps = <4577000>;
1862 opp-2 {
1863 opp-peak-kBps = <7110000>;
1866 opp-3 {
1867 opp-peak-kBps = <9155000>;
1870 opp-4 {
1871 opp-peak-kBps = <12298000>;
1874 opp-5 {
1875 opp-peak-kBps = <14236000>;
1882 compatible = "qcom,sm6350-cpu-bwmon", "qcom,sc7280-llcc-bwmon";
1886 operating-points-v2 = <&cpu_bwmon_opp_table>;
1890 cpu_bwmon_opp_table: opp-table {
1891 compatible = "operating-points-v2";
1893 opp-0 {
1894 opp-peak-kBps = <762000>;
1897 opp-1 {
1898 opp-peak-kBps = <1144000>;
1901 opp-2 {
1902 opp-peak-kBps = <1720000>;
1905 opp-3 {
1906 opp-peak-kBps = <2086000>;
1909 opp-4 {
1910 opp-peak-kBps = <2597000>;
1913 opp-5 {
1914 opp-peak-kBps = <2929000>;
1917 opp-6 {
1918 opp-peak-kBps = <3879000>;
1921 opp-7 {
1922 opp-peak-kBps = <5161000>;
1925 opp-8 {
1926 opp-peak-kBps = <5931000>;
1929 opp-9 {
1930 opp-peak-kBps = <6881000>;
1933 opp-10 {
1934 opp-peak-kBps = <7980000>;
1940 compatible = "qcom,sm6350-dwc3", "qcom,dwc3";
1943 #address-cells = <2>;
1944 #size-cells = <2>;
1952 clock-names = "cfg_noc",
1958 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1963 interrupt-names = "pwr_event",
1969 power-domains = <&gcc USB30_PRIM_GDSC>;
1975 interconnect-names = "usb-ddr", "apps-usb";
1984 snps,has-lpm-erratum;
1985 snps,hird-threshold = /bits/ 8 <0x10>;
1986 snps,parkmode-disable-ss-quirk;
1987 snps,dis-u1-entry-quirk;
1988 snps,dis-u2-entry-quirk;
1990 phy-names = "usb2-phy", "usb3-phy";
1991 usb-role-switch;
1994 #address-cells = <1>;
1995 #size-cells = <0>;
2008 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
2015 videocc: clock-controller@aaf0000 {
2016 compatible = "qcom,sm6350-videocc";
2021 clock-names = "iface",
2024 #clock-cells = <1>;
2025 #reset-cells = <1>;
2026 #power-domain-cells = <1>;
2030 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci";
2033 power-domains = <&camcc TITAN_TOP_GDSC>;
2041 clock-names = "camnoc_axi",
2048 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
2050 assigned-clock-rates = <80000000>, <37500000>;
2052 pinctrl-0 = <&cci0_default &cci1_default>;
2053 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
2054 pinctrl-names = "default", "sleep";
2056 #address-cells = <1>;
2057 #size-cells = <0>;
2061 cci0_i2c0: i2c-bus@0 {
2063 clock-frequency = <1000000>;
2064 #address-cells = <1>;
2065 #size-cells = <0>;
2068 cci0_i2c1: i2c-bus@1 {
2070 clock-frequency = <1000000>;
2071 #address-cells = <1>;
2072 #size-cells = <0>;
2077 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci";
2080 power-domains = <&camcc TITAN_TOP_GDSC>;
2088 clock-names = "camnoc_axi",
2095 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
2097 assigned-clock-rates = <80000000>, <37500000>;
2099 pinctrl-0 = <&cci2_default>;
2100 pinctrl-1 = <&cci2_sleep>;
2101 pinctrl-names = "default", "sleep";
2103 #address-cells = <1>;
2104 #size-cells = <0>;
2108 cci1_i2c0: i2c-bus@0 {
2110 clock-frequency = <1000000>;
2111 #address-cells = <1>;
2112 #size-cells = <0>;
2118 camcc: clock-controller@ad00000 {
2119 compatible = "qcom,sm6350-camcc";
2122 #clock-cells = <1>;
2123 #reset-cells = <1>;
2124 #power-domain-cells = <1>;
2127 mdss: display-subsystem@ae00000 {
2128 compatible = "qcom,sm6350-mdss";
2130 reg-names = "mdss";
2133 interrupt-controller;
2134 #interrupt-cells = <1>;
2140 interconnect-names = "mdp0-mem",
2141 "cpu-cfg";
2146 clock-names = "iface",
2150 power-domains = <&dispcc MDSS_GDSC>;
2153 #address-cells = <2>;
2154 #size-cells = <2>;
2159 mdss_mdp: display-controller@ae01000 {
2160 compatible = "qcom,sm6350-dpu";
2163 reg-names = "mdp", "vbif";
2165 interrupt-parent = <&mdss>;
2174 clock-names = "bus",
2181 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2182 assigned-clock-rates = <19200000>;
2184 operating-points-v2 = <&mdp_opp_table>;
2185 power-domains = <&rpmhpd SM6350_CX>;
2188 #address-cells = <1>;
2189 #size-cells = <0>;
2195 remote-endpoint = <&mdss_dsi0_in>;
2203 remote-endpoint = <&mdss_dp_in>;
2208 mdp_opp_table: opp-table {
2209 compatible = "operating-points-v2";
2211 opp-19200000 {
2212 opp-hz = /bits/ 64 <19200000>;
2213 required-opps = <&rpmhpd_opp_min_svs>;
2216 opp-200000000 {
2217 opp-hz = /bits/ 64 <200000000>;
2218 required-opps = <&rpmhpd_opp_low_svs>;
2221 opp-300000000 {
2222 opp-hz = /bits/ 64 <300000000>;
2223 required-opps = <&rpmhpd_opp_svs>;
2226 opp-373333333 {
2227 opp-hz = /bits/ 64 <373333333>;
2228 required-opps = <&rpmhpd_opp_svs_l1>;
2231 opp-448000000 {
2232 opp-hz = /bits/ 64 <448000000>;
2233 required-opps = <&rpmhpd_opp_nom>;
2236 opp-560000000 {
2237 opp-hz = /bits/ 64 <560000000>;
2238 required-opps = <&rpmhpd_opp_turbo>;
2243 mdss_dp: displayport-controller@ae90000 {
2244 compatible = "qcom,sm6350-dp", "qcom,sm8350-dp";
2250 interrupt-parent = <&mdss>;
2257 clock-names = "core_iface",
2263 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
2265 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2269 phy-names = "dp";
2271 #sound-dai-cells = <0>;
2273 operating-points-v2 = <&dp_opp_table>;
2274 power-domains = <&rpmhpd SM6350_CX>;
2279 #address-cells = <1>;
2280 #size-cells = <0>;
2286 remote-endpoint = <&dpu_intf0_out>;
2298 dp_opp_table: opp-table {
2299 compatible = "operating-points-v2";
2301 opp-160000000 {
2302 opp-hz = /bits/ 64 <160000000>;
2303 required-opps = <&rpmhpd_opp_low_svs>;
2306 opp-270000000 {
2307 opp-hz = /bits/ 64 <270000000>;
2308 required-opps = <&rpmhpd_opp_svs>;
2311 opp-540000000 {
2312 opp-hz = /bits/ 64 <540000000>;
2313 required-opps = <&rpmhpd_opp_svs_l1>;
2316 opp-810000000 {
2317 opp-hz = /bits/ 64 <810000000>;
2318 required-opps = <&rpmhpd_opp_nom>;
2324 compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2326 reg-names = "dsi_ctrl";
2328 interrupt-parent = <&mdss>;
2337 clock-names = "byte",
2344 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2346 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
2349 operating-points-v2 = <&mdss_dsi_opp_table>;
2350 power-domains = <&rpmhpd SM6350_MX>;
2353 phy-names = "dsi";
2355 #address-cells = <1>;
2356 #size-cells = <0>;
2361 #address-cells = <1>;
2362 #size-cells = <0>;
2368 remote-endpoint = <&dpu_intf1_out>;
2380 mdss_dsi_opp_table: opp-table {
2381 compatible = "operating-points-v2";
2383 opp-187500000 {
2384 opp-hz = /bits/ 64 <187500000>;
2385 required-opps = <&rpmhpd_opp_low_svs>;
2388 opp-300000000 {
2389 opp-hz = /bits/ 64 <300000000>;
2390 required-opps = <&rpmhpd_opp_svs>;
2393 opp-358000000 {
2394 opp-hz = /bits/ 64 <358000000>;
2395 required-opps = <&rpmhpd_opp_svs_l1>;
2401 compatible = "qcom,dsi-phy-10nm";
2405 reg-names = "dsi_phy",
2409 #clock-cells = <1>;
2410 #phy-cells = <0>;
2414 clock-names = "iface", "ref";
2420 dispcc: clock-controller@af00000 {
2421 compatible = "qcom,sm6350-dispcc";
2429 clock-names = "bi_tcxo",
2435 #clock-cells = <1>;
2436 #reset-cells = <1>;
2437 #power-domain-cells = <1>;
2440 pdc: interrupt-controller@b220000 {
2441 compatible = "qcom,sm6350-pdc", "qcom,pdc";
2443 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
2445 #interrupt-cells = <2>;
2446 interrupt-parent = <&intc>;
2447 interrupt-controller;
2450 tsens0: thermal-sensor@c263000 {
2451 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2";
2455 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
2457 interrupt-names = "uplow", "critical";
2458 #thermal-sensor-cells = <1>;
2461 tsens1: thermal-sensor@c265000 {
2462 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2";
2466 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
2468 interrupt-names = "uplow", "critical";
2469 #thermal-sensor-cells = <1>;
2472 aoss_qmp: power-management@c300000 {
2473 compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp";
2475 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
2479 #clock-cells = <0>;
2483 compatible = "qcom,spmi-pmic-arb";
2489 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2490 interrupt-names = "periph_irq";
2491 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2494 #address-cells = <2>;
2495 #size-cells = <0>;
2496 interrupt-controller;
2497 #interrupt-cells = <4>;
2501 compatible = "qcom,sm6350-tlmm";
2512 gpio-controller;
2513 #gpio-cells = <2>;
2514 interrupt-controller;
2515 #interrupt-cells = <2>;
2516 gpio-ranges = <&tlmm 0 0 157>;
2517 wakeup-parent = <&pdc>;
2519 cci0_default: cci0-default-state {
2522 drive-strength = <2>;
2523 bias-pull-up;
2526 cci0_sleep: cci0-sleep-state {
2529 drive-strength = <2>;
2530 bias-pull-down;
2533 cci1_default: cci1-default-state {
2536 drive-strength = <2>;
2537 bias-pull-up;
2540 cci1_sleep: cci1-sleep-state {
2543 drive-strength = <2>;
2544 bias-pull-down;
2547 cci2_default: cci2-default-state {
2550 drive-strength = <2>;
2551 bias-pull-up;
2554 cci2_sleep: cci2-sleep-state {
2557 drive-strength = <2>;
2558 bias-pull-down;
2561 sdc2_off_state: sdc2-off-state {
2562 clk-pins {
2564 drive-strength = <2>;
2565 bias-disable;
2568 cmd-pins {
2570 drive-strength = <2>;
2571 bias-pull-up;
2574 data-pins {
2576 drive-strength = <2>;
2577 bias-pull-up;
2581 sdc2_on_state: sdc2-on-state {
2582 clk-pins {
2584 drive-strength = <16>;
2585 bias-disable;
2588 cmd-pins {
2590 drive-strength = <10>;
2591 bias-pull-up;
2594 data-pins {
2596 drive-strength = <10>;
2597 bias-pull-up;
2601 qup_uart9_default: qup-uart9-default-state {
2604 drive-strength = <2>;
2605 bias-disable;
2608 qup_i2c0_default: qup-i2c0-default-state {
2611 drive-strength = <2>;
2612 bias-pull-up;
2615 qup_i2c2_default: qup-i2c2-default-state {
2618 drive-strength = <2>;
2619 bias-pull-up;
2622 qup_i2c6_default: qup-i2c6-default-state {
2625 drive-strength = <2>;
2626 bias-pull-up;
2629 qup_i2c7_default: qup-i2c7-default-state {
2632 drive-strength = <2>;
2633 bias-pull-up;
2636 qup_i2c8_default: qup-i2c8-default-state {
2639 drive-strength = <2>;
2640 bias-pull-up;
2643 qup_i2c10_default: qup-i2c10-default-state {
2646 drive-strength = <2>;
2647 bias-pull-up;
2650 qup_uart1_cts: qup-uart1-cts-default-state {
2653 drive-strength = <2>;
2654 bias-disable;
2657 qup_uart1_rts: qup-uart1-rts-default-state {
2660 drive-strength = <2>;
2661 bias-pull-down;
2664 qup_uart1_rx: qup-uart1-rx-default-state {
2667 drive-strength = <2>;
2668 bias-disable;
2671 qup_uart1_tx: qup-uart1-tx-default-state {
2674 drive-strength = <2>;
2675 bias-pull-up;
2680 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500";
2682 #iommu-cells = <2>;
2683 #global-interrupts = <1>;
2765 dma-coherent;
2768 intc: interrupt-controller@17a00000 {
2769 compatible = "arm,gic-v3";
2770 #interrupt-cells = <3>;
2771 interrupt-controller;
2778 compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt";
2785 compatible = "arm,armv7-timer-mem";
2787 clock-frequency = <19200000>;
2788 #address-cells = <1>;
2789 #size-cells = <1>;
2793 frame-number = <0>;
2801 frame-number = <1>;
2808 frame-number = <2>;
2815 frame-number = <3>;
2822 frame-number = <4>;
2829 frame-number = <5>;
2836 frame-number = <6>;
2844 compatible = "qcom,rpmh-rsc";
2849 reg-names = "drv-0", "drv-1", "drv-2";
2853 qcom,tcs-offset = <0xd00>;
2854 qcom,drv-id = <2>;
2855 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
2857 power-domains = <&cluster_pd>;
2859 rpmhcc: clock-controller {
2860 compatible = "qcom,sm6350-rpmh-clk";
2861 #clock-cells = <1>;
2862 clock-names = "xo";
2866 rpmhpd: power-controller {
2867 compatible = "qcom,sm6350-rpmhpd";
2868 #power-domain-cells = <1>;
2869 operating-points-v2 = <&rpmhpd_opp_table>;
2871 rpmhpd_opp_table: opp-table {
2872 compatible = "operating-points-v2";
2875 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
2879 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2883 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2887 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2891 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2895 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2899 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2903 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
2907 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2911 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2916 apps_bcm_voter: bcm-voter {
2917 compatible = "qcom,bcm-voter";
2922 compatible = "qcom,sm6350-osm-l3", "qcom,osm-l3";
2926 clock-names = "xo", "alternate";
2928 #interconnect-cells = <1>;
2932 compatible = "qcom,sm6350-cpufreq-hw", "qcom,cpufreq-hw";
2934 reg-names = "freq-domain0", "freq-domain1";
2936 clock-names = "xo", "alternate";
2938 #freq-domain-cells = <1>;
2939 #clock-cells = <1>;
2943 compatible = "qcom,wcn3990-wifi";
2945 reg-names = "membase";
2946 memory-region = <&wlan_fw_mem>;
2960 qcom,msa-fixed-perm;
2965 thermal-zones {
2966 aoss0-thermal {
2967 thermal-sensors = <&tsens0 0>;
2970 aoss0-crit {
2978 aoss1-thermal {
2979 thermal-sensors = <&tsens1 0>;
2982 aoss1-crit {
2990 audio-thermal {
2991 thermal-sensors = <&tsens1 2>;
2994 audio-crit {
3002 camera-thermal {
3003 thermal-sensors = <&tsens1 5>;
3006 camera-crit {
3014 cpu0-thermal {
3015 thermal-sensors = <&tsens0 1>;
3018 cpu0_alert0: trip-point0 {
3024 cpu0-crit {
3031 cooling-maps {
3034 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3039 cpu1-thermal {
3040 thermal-sensors = <&tsens0 2>;
3043 cpu1_alert0: trip-point0 {
3049 cpu1-crit {
3056 cooling-maps {
3059 cooling-device = <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3064 cpu2-thermal {
3065 thermal-sensors = <&tsens0 3>;
3068 cpu2_alert0: trip-point0 {
3074 cpu2-crit {
3081 cooling-maps {
3084 cooling-device = <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3089 cpu3-thermal {
3090 thermal-sensors = <&tsens0 4>;
3093 cpu3_alert0: trip-point0 {
3099 cpu3-crit {
3106 cooling-maps {
3109 cooling-device = <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3114 cpu4-thermal {
3115 thermal-sensors = <&tsens0 5>;
3118 cpu4_alert0: trip-point0 {
3124 cpu4-crit {
3131 cooling-maps {
3134 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3139 cpu5-thermal {
3140 thermal-sensors = <&tsens0 6>;
3143 cpu5_alert0: trip-point0 {
3149 cpu5-crit {
3156 cooling-maps {
3159 cooling-device = <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3164 cpu6-left-thermal {
3165 thermal-sensors = <&tsens0 9>;
3168 cpu6_left_alert0: trip-point0 {
3174 cpu6-left-crit {
3181 cooling-maps {
3184 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3189 cpu6-right-thermal {
3190 thermal-sensors = <&tsens0 10>;
3193 cpu6_right_alert0: trip-point0 {
3199 cpu6-right-crit {
3206 cooling-maps {
3209 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3214 cpu7-left-thermal {
3215 thermal-sensors = <&tsens0 11>;
3218 cpu7_left_alert0: trip-point0 {
3224 cpu7-left-crit {
3231 cooling-maps {
3234 cooling-device = <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3239 cpu7-right-thermal {
3240 thermal-sensors = <&tsens0 12>;
3243 cpu7_right_alert0: trip-point0 {
3249 cpu7-right-crit {
3256 cooling-maps {
3259 cooling-device = <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3264 cpuss0-thermal {
3265 thermal-sensors = <&tsens0 7>;
3268 cpuss0-crit {
3276 cpuss1-thermal {
3277 thermal-sensors = <&tsens0 8>;
3280 cpuss1-crit {
3288 cwlan-thermal {
3289 thermal-sensors = <&tsens1 1>;
3292 cwlan-crit {
3300 ddr-thermal {
3301 thermal-sensors = <&tsens1 3>;
3304 ddr-crit {
3312 gpuss0-thermal {
3313 polling-delay-passive = <250>;
3315 thermal-sensors = <&tsens0 13>;
3318 gpuss0_alert0: trip-point0 {
3324 gpuss0-crit {
3331 cooling-maps {
3334 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3339 gpuss1-thermal {
3340 polling-delay-passive = <250>;
3342 thermal-sensors = <&tsens0 14>;
3345 gpuss1_alert0: trip-point0 {
3351 gpuss1-crit {
3358 cooling-maps {
3361 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3366 modem-core0-thermal {
3367 thermal-sensors = <&tsens1 6>;
3370 modem-core0-crit {
3378 modem-core1-thermal {
3379 thermal-sensors = <&tsens1 7>;
3382 modem-core1-crit {
3390 modem-scl-thermal {
3391 thermal-sensors = <&tsens1 9>;
3394 modem-scl-crit {
3402 modem-vec-thermal {
3403 thermal-sensors = <&tsens1 8>;
3406 modem-vec-crit {
3414 npu-thermal {
3415 thermal-sensors = <&tsens1 10>;
3418 npu-crit {
3426 q6-hvx-thermal {
3427 thermal-sensors = <&tsens1 4>;
3430 q6-hvx-crit {
3438 video-thermal {
3439 thermal-sensors = <&tsens1 11>;
3442 video-crit {
3452 compatible = "arm,armv8-timer";
3453 clock-frequency = <19200000>;