Lines Matching +full:rpmh +full:- +full:rsc
1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,dispcc-sm6350.h>
8 #include <dt-bindings/clock/qcom,gcc-sm6350.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm6350.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/clock/qcom,sm6350-camcc.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interconnect/qcom,icc.h>
15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
16 #include <dt-bindings/interconnect/qcom,sm6350.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/mailbox/qcom-ipcc.h>
19 #include <dt-bindings/phy/phy-qcom-qmp.h>
20 #include <dt-bindings/power/qcom-rpmpd.h>
21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
22 #include <dt-bindings/thermal/thermal.h>
25 interrupt-parent = <&intc>;
26 #address-cells = <2>;
27 #size-cells = <2>;
30 xo_board: xo-board {
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
33 clock-frequency = <76800000>;
34 clock-output-names = "xo_board";
37 sleep_clk: sleep-clk {
38 compatible = "fixed-clock";
39 clock-frequency = <32764>;
40 #clock-cells = <0>;
45 #address-cells = <2>;
46 #size-cells = <0>;
53 enable-method = "psci";
54 capacity-dmips-mhz = <1024>;
55 dynamic-power-coefficient = <100>;
56 next-level-cache = <&L2_0>;
57 qcom,freq-domain = <&cpufreq_hw 0>;
58 operating-points-v2 = <&cpu0_opp_table>;
62 power-domains = <&CPU_PD0>;
63 power-domain-names = "psci";
64 #cooling-cells = <2>;
65 L2_0: l2-cache {
67 cache-level = <2>;
68 cache-unified;
69 next-level-cache = <&L3_0>;
70 L3_0: l3-cache {
72 cache-level = <3>;
73 cache-unified;
83 enable-method = "psci";
84 capacity-dmips-mhz = <1024>;
85 dynamic-power-coefficient = <100>;
86 next-level-cache = <&L2_100>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
88 operating-points-v2 = <&cpu0_opp_table>;
92 power-domains = <&CPU_PD1>;
93 power-domain-names = "psci";
94 #cooling-cells = <2>;
95 L2_100: l2-cache {
97 cache-level = <2>;
98 cache-unified;
99 next-level-cache = <&L3_0>;
108 enable-method = "psci";
109 capacity-dmips-mhz = <1024>;
110 dynamic-power-coefficient = <100>;
111 next-level-cache = <&L2_200>;
112 qcom,freq-domain = <&cpufreq_hw 0>;
113 operating-points-v2 = <&cpu0_opp_table>;
117 power-domains = <&CPU_PD2>;
118 power-domain-names = "psci";
119 #cooling-cells = <2>;
120 L2_200: l2-cache {
122 cache-level = <2>;
123 cache-unified;
124 next-level-cache = <&L3_0>;
133 enable-method = "psci";
134 capacity-dmips-mhz = <1024>;
135 dynamic-power-coefficient = <100>;
136 next-level-cache = <&L2_300>;
137 qcom,freq-domain = <&cpufreq_hw 0>;
138 operating-points-v2 = <&cpu0_opp_table>;
142 power-domains = <&CPU_PD3>;
143 power-domain-names = "psci";
144 #cooling-cells = <2>;
145 L2_300: l2-cache {
147 cache-level = <2>;
148 cache-unified;
149 next-level-cache = <&L3_0>;
158 enable-method = "psci";
159 capacity-dmips-mhz = <1024>;
160 dynamic-power-coefficient = <100>;
161 next-level-cache = <&L2_400>;
162 qcom,freq-domain = <&cpufreq_hw 0>;
163 operating-points-v2 = <&cpu0_opp_table>;
167 power-domains = <&CPU_PD4>;
168 power-domain-names = "psci";
169 #cooling-cells = <2>;
170 L2_400: l2-cache {
172 cache-level = <2>;
173 cache-unified;
174 next-level-cache = <&L3_0>;
183 enable-method = "psci";
184 capacity-dmips-mhz = <1024>;
185 dynamic-power-coefficient = <100>;
186 next-level-cache = <&L2_500>;
187 qcom,freq-domain = <&cpufreq_hw 0>;
188 operating-points-v2 = <&cpu0_opp_table>;
192 power-domains = <&CPU_PD5>;
193 power-domain-names = "psci";
194 #cooling-cells = <2>;
195 L2_500: l2-cache {
197 cache-level = <2>;
198 cache-unified;
199 next-level-cache = <&L3_0>;
208 enable-method = "psci";
209 capacity-dmips-mhz = <1894>;
210 dynamic-power-coefficient = <703>;
211 next-level-cache = <&L2_600>;
212 qcom,freq-domain = <&cpufreq_hw 1>;
213 operating-points-v2 = <&cpu6_opp_table>;
217 power-domains = <&CPU_PD6>;
218 power-domain-names = "psci";
219 #cooling-cells = <2>;
220 L2_600: l2-cache {
222 cache-level = <2>;
223 cache-unified;
224 next-level-cache = <&L3_0>;
233 enable-method = "psci";
234 capacity-dmips-mhz = <1894>;
235 dynamic-power-coefficient = <703>;
236 next-level-cache = <&L2_700>;
237 qcom,freq-domain = <&cpufreq_hw 1>;
238 operating-points-v2 = <&cpu6_opp_table>;
242 power-domains = <&CPU_PD7>;
243 power-domain-names = "psci";
244 #cooling-cells = <2>;
245 L2_700: l2-cache {
247 cache-level = <2>;
248 cache-unified;
249 next-level-cache = <&L3_0>;
253 cpu-map {
289 domain-idle-states {
290 CLUSTER_SLEEP_PC: cluster-sleep-0 {
291 compatible = "domain-idle-state";
292 arm,psci-suspend-param = <0x41000044>;
293 entry-latency-us = <2752>;
294 exit-latency-us = <3048>;
295 min-residency-us = <6118>;
298 CLUSTER_SLEEP_CX_RET: cluster-sleep-1 {
299 compatible = "domain-idle-state";
300 arm,psci-suspend-param = <0x41001244>;
301 entry-latency-us = <3638>;
302 exit-latency-us = <4562>;
303 min-residency-us = <8467>;
306 CLUSTER_AOSS_SLEEP: cluster-sleep-2 {
307 compatible = "domain-idle-state";
308 arm,psci-suspend-param = <0x4100b244>;
309 entry-latency-us = <3263>;
310 exit-latency-us = <6562>;
311 min-residency-us = <9987>;
315 cpu_idle_states: idle-states {
316 entry-method = "psci";
318 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
319 compatible = "arm,idle-state";
320 idle-state-name = "little-power-collapse";
321 arm,psci-suspend-param = <0x40000003>;
322 entry-latency-us = <549>;
323 exit-latency-us = <901>;
324 min-residency-us = <1774>;
325 local-timer-stop;
328 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
329 compatible = "arm,idle-state";
330 idle-state-name = "little-rail-power-collapse";
331 arm,psci-suspend-param = <0x40000004>;
332 entry-latency-us = <702>;
333 exit-latency-us = <915>;
334 min-residency-us = <4001>;
335 local-timer-stop;
338 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
339 compatible = "arm,idle-state";
340 idle-state-name = "big-power-collapse";
341 arm,psci-suspend-param = <0x40000003>;
342 entry-latency-us = <523>;
343 exit-latency-us = <1244>;
344 min-residency-us = <2207>;
345 local-timer-stop;
348 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
349 compatible = "arm,idle-state";
350 idle-state-name = "big-rail-power-collapse";
351 arm,psci-suspend-param = <0x40000004>;
352 entry-latency-us = <526>;
353 exit-latency-us = <1854>;
354 min-residency-us = <5555>;
355 local-timer-stop;
362 compatible = "qcom,scm-sm6350", "qcom,scm";
363 #reset-cells = <1>;
373 cpu0_opp_table: opp-table-cpu0 {
374 compatible = "operating-points-v2";
375 opp-shared;
377 opp-300000000 {
378 opp-hz = /bits/ 64 <300000000>;
379 /* DDR: 4-wide, 2 channels, double data rate, L3: 16-wide, 2 channels */
380 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>;
383 opp-576000000 {
384 opp-hz = /bits/ 64 <576000000>;
385 opp-peak-kBps = <(547000 * 4 * 2 * 2) (556800 * 16 * 2)>;
388 opp-768000000 {
389 opp-hz = /bits/ 64 <768000000>;
390 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>;
393 opp-1017600000 {
394 opp-hz = /bits/ 64 <1017600000>;
395 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>;
398 opp-1248000000 {
399 opp-hz = /bits/ 64 <1248000000>;
400 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>;
403 opp-1324800000 {
404 opp-hz = /bits/ 64 <1324800000>;
405 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1286400 * 16 * 2)>;
408 opp-1516800000 {
409 opp-hz = /bits/ 64 <1516800000>;
410 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
413 opp-1612800000 {
414 opp-hz = /bits/ 64 <1612800000>;
415 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
418 opp-1708800000 {
419 opp-hz = /bits/ 64 <1708800000>;
420 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
424 cpu6_opp_table: opp-table-cpu6 {
425 compatible = "operating-points-v2";
426 opp-shared;
428 opp-300000000 {
429 opp-hz = /bits/ 64 <300000000>;
430 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>;
433 opp-787200000 {
434 opp-hz = /bits/ 64 <787200000>;
435 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>;
438 opp-979200000 {
439 opp-hz = /bits/ 64 <979200000>;
440 opp-peak-kBps = <(768000 * 4 * 2 * 2) (940800 * 16 * 2)>;
443 opp-1036800000 {
444 opp-hz = /bits/ 64 <1036800000>;
445 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>;
448 opp-1248000000 {
449 opp-hz = /bits/ 64 <1248000000>;
450 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>;
453 opp-1401600000 {
454 opp-hz = /bits/ 64 <1401600000>;
455 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1401600 * 16 * 2)>;
458 opp-1555200000 {
459 opp-hz = /bits/ 64 <1555200000>;
460 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
463 opp-1766400000 {
464 opp-hz = /bits/ 64 <1766400000>;
465 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
468 opp-1900800000 {
469 opp-hz = /bits/ 64 <1900800000>;
470 opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
473 opp-2073600000 {
474 opp-hz = /bits/ 64 <2073600000>;
475 opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
479 qup_opp_table: opp-table-qup {
480 compatible = "operating-points-v2";
482 opp-75000000 {
483 opp-hz = /bits/ 64 <75000000>;
484 required-opps = <&rpmhpd_opp_low_svs>;
487 opp-100000000 {
488 opp-hz = /bits/ 64 <100000000>;
489 required-opps = <&rpmhpd_opp_svs>;
492 opp-128000000 {
493 opp-hz = /bits/ 64 <128000000>;
494 required-opps = <&rpmhpd_opp_nom>;
499 compatible = "arm,armv8-pmuv3";
504 compatible = "arm,psci-1.0";
507 CPU_PD0: power-domain-cpu0 {
508 #power-domain-cells = <0>;
509 power-domains = <&CLUSTER_PD>;
510 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
513 CPU_PD1: power-domain-cpu1 {
514 #power-domain-cells = <0>;
515 power-domains = <&CLUSTER_PD>;
516 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
519 CPU_PD2: power-domain-cpu2 {
520 #power-domain-cells = <0>;
521 power-domains = <&CLUSTER_PD>;
522 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
525 CPU_PD3: power-domain-cpu3 {
526 #power-domain-cells = <0>;
527 power-domains = <&CLUSTER_PD>;
528 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
531 CPU_PD4: power-domain-cpu4 {
532 #power-domain-cells = <0>;
533 power-domains = <&CLUSTER_PD>;
534 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
537 CPU_PD5: power-domain-cpu5 {
538 #power-domain-cells = <0>;
539 power-domains = <&CLUSTER_PD>;
540 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
543 CPU_PD6: power-domain-cpu6 {
544 #power-domain-cells = <0>;
545 power-domains = <&CLUSTER_PD>;
546 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
549 CPU_PD7: power-domain-cpu7 {
550 #power-domain-cells = <0>;
551 power-domains = <&CLUSTER_PD>;
552 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
555 CLUSTER_PD: power-domain-cpu-cluster0 {
556 #power-domain-cells = <0>;
557 domain-idle-states = <&CLUSTER_SLEEP_PC
563 reserved_memory: reserved-memory {
564 #address-cells = <2>;
565 #size-cells = <2>;
570 no-map;
575 no-map;
579 compatible = "qcom,cmd-db";
581 no-map;
586 no-map;
591 no-map;
596 no-map;
601 no-map;
606 no-map;
611 no-map;
616 no-map;
621 no-map;
626 no-map;
631 no-map;
636 no-map;
641 no-map;
646 no-map;
651 no-map;
656 no-map;
661 no-map;
666 no-map;
671 no-map;
677 record-size = <0x1000>;
678 console-size = <0x40000>;
679 pmsg-size = <0x20000>;
680 ecc-size = <16>;
681 no-map;
686 no-map;
692 memory-region = <&smem_mem>;
696 smp2p-adsp {
699 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
705 qcom,local-pid = <0>;
706 qcom,remote-pid = <2>;
708 smp2p_adsp_out: master-kernel {
709 qcom,entry-name = "master-kernel";
710 #qcom,smem-state-cells = <1>;
713 smp2p_adsp_in: slave-kernel {
714 qcom,entry-name = "slave-kernel";
715 interrupt-controller;
716 #interrupt-cells = <2>;
720 smp2p-cdsp {
723 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
729 qcom,local-pid = <0>;
730 qcom,remote-pid = <5>;
732 smp2p_cdsp_out: master-kernel {
733 qcom,entry-name = "master-kernel";
734 #qcom,smem-state-cells = <1>;
737 smp2p_cdsp_in: slave-kernel {
738 qcom,entry-name = "slave-kernel";
739 interrupt-controller;
740 #interrupt-cells = <2>;
744 smp2p-mpss {
748 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
754 qcom,local-pid = <0>;
755 qcom,remote-pid = <1>;
757 modem_smp2p_out: master-kernel {
758 qcom,entry-name = "master-kernel";
759 #qcom,smem-state-cells = <1>;
762 modem_smp2p_in: slave-kernel {
763 qcom,entry-name = "slave-kernel";
764 interrupt-controller;
765 #interrupt-cells = <2>;
768 ipa_smp2p_out: ipa-ap-to-modem {
769 qcom,entry-name = "ipa";
770 #qcom,smem-state-cells = <1>;
773 ipa_smp2p_in: ipa-modem-to-ap {
774 qcom,entry-name = "ipa";
775 interrupt-controller;
776 #interrupt-cells = <2>;
781 #address-cells = <2>;
782 #size-cells = <2>;
784 dma-ranges = <0 0 0 0 0x10 0>;
785 compatible = "simple-bus";
787 gcc: clock-controller@100000 {
788 compatible = "qcom,gcc-sm6350";
790 #clock-cells = <1>;
791 #reset-cells = <1>;
792 #power-domain-cells = <1>;
793 clock-names = "bi_tcxo",
802 compatible = "qcom,sm6350-ipcc", "qcom,ipcc";
805 interrupt-controller;
806 #interrupt-cells = <3>;
807 #mbox-cells = <2>;
811 compatible = "qcom,sm6350-qfprom", "qcom,qfprom";
813 #address-cells = <1>;
814 #size-cells = <1>;
816 gpu_speed_bin: gpu-speed-bin@2015 {
823 compatible = "qcom,prng-ee";
826 clock-names = "core";
830 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
834 reg-names = "hc", "cqhci", "ice";
838 interrupt-names = "hc_irq", "pwr_irq";
844 clock-names = "iface", "core", "xo";
846 qcom,dll-config = <0x000f642c>;
847 qcom,ddr-config = <0x80040868>;
848 power-domains = <&rpmhpd SM6350_CX>;
849 operating-points-v2 = <&sdhc1_opp_table>;
850 bus-width = <8>;
851 non-removable;
852 supports-cqe;
856 sdhc1_opp_table: opp-table {
857 compatible = "operating-points-v2";
859 opp-19200000 {
860 opp-hz = /bits/ 64 <19200000>;
861 required-opps = <&rpmhpd_opp_min_svs>;
864 opp-100000000 {
865 opp-hz = /bits/ 64 <100000000>;
866 required-opps = <&rpmhpd_opp_low_svs>;
869 opp-384000000 {
870 opp-hz = /bits/ 64 <384000000>;
871 required-opps = <&rpmhpd_opp_svs_l1>;
876 gpi_dma0: dma-controller@800000 {
877 compatible = "qcom,sm6350-gpi-dma";
889 dma-channels = <10>;
890 dma-channel-mask = <0x1f>;
892 #dma-cells = <3>;
897 compatible = "qcom,geni-se-qup";
899 clock-names = "m-ahb", "s-ahb";
902 #address-cells = <2>;
903 #size-cells = <2>;
909 compatible = "qcom,geni-i2c";
911 clock-names = "se";
913 pinctrl-names = "default";
914 pinctrl-0 = <&qup_i2c0_default>;
918 dma-names = "tx", "rx";
919 #address-cells = <1>;
920 #size-cells = <0>;
924 interconnect-names = "qup-core", "qup-config", "qup-memory";
929 compatible = "qcom,geni-uart";
931 clock-names = "se";
933 pinctrl-names = "default";
934 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
936 power-domains = <&rpmhpd SM6350_CX>;
937 operating-points-v2 = <&qup_opp_table>;
940 interconnect-names = "qup-core", "qup-config";
945 compatible = "qcom,geni-i2c";
947 clock-names = "se";
949 pinctrl-names = "default";
950 pinctrl-0 = <&qup_i2c2_default>;
954 dma-names = "tx", "rx";
955 #address-cells = <1>;
956 #size-cells = <0>;
960 interconnect-names = "qup-core", "qup-config", "qup-memory";
965 gpi_dma1: dma-controller@900000 {
966 compatible = "qcom,sm6350-gpi-dma";
978 dma-channels = <10>;
979 dma-channel-mask = <0x3f>;
981 #dma-cells = <3>;
986 compatible = "qcom,geni-se-qup";
988 clock-names = "m-ahb", "s-ahb";
991 #address-cells = <2>;
992 #size-cells = <2>;
998 compatible = "qcom,geni-i2c";
1000 clock-names = "se";
1002 pinctrl-names = "default";
1003 pinctrl-0 = <&qup_i2c6_default>;
1007 dma-names = "tx", "rx";
1008 #address-cells = <1>;
1009 #size-cells = <0>;
1013 interconnect-names = "qup-core", "qup-config", "qup-memory";
1018 compatible = "qcom,geni-i2c";
1020 clock-names = "se";
1022 pinctrl-names = "default";
1023 pinctrl-0 = <&qup_i2c7_default>;
1027 dma-names = "tx", "rx";
1028 #address-cells = <1>;
1029 #size-cells = <0>;
1033 interconnect-names = "qup-core", "qup-config", "qup-memory";
1038 compatible = "qcom,geni-i2c";
1040 clock-names = "se";
1042 pinctrl-names = "default";
1043 pinctrl-0 = <&qup_i2c8_default>;
1047 dma-names = "tx", "rx";
1048 #address-cells = <1>;
1049 #size-cells = <0>;
1053 interconnect-names = "qup-core", "qup-config", "qup-memory";
1058 compatible = "qcom,geni-debug-uart";
1060 clock-names = "se";
1062 pinctrl-names = "default";
1063 pinctrl-0 = <&qup_uart9_default>;
1067 interconnect-names = "qup-core", "qup-config";
1072 compatible = "qcom,geni-i2c";
1074 clock-names = "se";
1076 pinctrl-names = "default";
1077 pinctrl-0 = <&qup_i2c10_default>;
1081 dma-names = "tx", "rx";
1082 #address-cells = <1>;
1083 #size-cells = <0>;
1087 interconnect-names = "qup-core", "qup-config", "qup-memory";
1093 compatible = "qcom,sm6350-config-noc";
1095 #interconnect-cells = <2>;
1096 qcom,bcm-voters = <&apps_bcm_voter>;
1100 compatible = "qcom,sm6350-system-noc";
1102 #interconnect-cells = <2>;
1103 qcom,bcm-voters = <&apps_bcm_voter>;
1105 clk_virt: interconnect-clk-virt {
1106 compatible = "qcom,sm6350-clk-virt";
1107 #interconnect-cells = <2>;
1108 qcom,bcm-voters = <&apps_bcm_voter>;
1113 compatible = "qcom,sm6350-aggre1-noc";
1115 #interconnect-cells = <2>;
1116 qcom,bcm-voters = <&apps_bcm_voter>;
1120 compatible = "qcom,sm6350-aggre2-noc";
1122 #interconnect-cells = <2>;
1123 qcom,bcm-voters = <&apps_bcm_voter>;
1125 compute_noc: interconnect-compute-noc {
1126 compatible = "qcom,sm6350-compute-noc";
1127 #interconnect-cells = <2>;
1128 qcom,bcm-voters = <&apps_bcm_voter>;
1133 compatible = "qcom,sm6350-mmss-noc";
1135 #interconnect-cells = <2>;
1136 qcom,bcm-voters = <&apps_bcm_voter>;
1140 compatible = "qcom,sm6350-ufshc", "qcom,ufshc",
1141 "jedec,ufs-2.0";
1144 reg-names = "std", "ice";
1147 phy-names = "ufsphy";
1148 lanes-per-direction = <2>;
1149 #reset-cells = <1>;
1151 reset-names = "rst";
1153 power-domains = <&gcc UFS_PHY_GDSC>;
1157 clock-names = "core_clk",
1175 freq-table-hz =
1190 compatible = "qcom,sm6350-qmp-ufs-phy";
1196 clock-names = "ref",
1200 power-domains = <&gcc UFS_PHY_GDSC>;
1203 reset-names = "ufsphy";
1205 #phy-cells = <0>;
1210 cryptobam: dma-controller@1dc4000 {
1211 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
1214 #dma-cells = <1>;
1216 qcom,controlled-remotely;
1217 num-channels = <16>;
1218 qcom,num-ees = <4>;
1227 compatible = "qcom,sm6350-qce", "qcom,sm8150-qce", "qcom,qce";
1230 dma-names = "rx", "tx";
1238 interconnect-names = "memory";
1242 compatible = "qcom,sm6350-ipa";
1249 reg-names = "ipa-reg",
1250 "ipa-shared",
1253 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1257 interrupt-names = "ipa",
1259 "ipa-clock-query",
1260 "ipa-setup-ready";
1263 clock-names = "core";
1268 interconnect-names = "memory", "imem", "config";
1270 qcom,smem-states = <&ipa_smp2p_out 0>,
1272 qcom,smem-state-names = "ipa-clock-enabled-valid",
1273 "ipa-clock-enabled";
1279 compatible = "qcom,tcsr-mutex";
1281 #hwlock-cells = <1>;
1285 compatible = "qcom,sm6350-adsp-pas";
1288 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
1293 interrupt-names = "wdog", "fatal", "ready",
1294 "handover", "stop-ack";
1297 clock-names = "xo";
1299 power-domains = <&rpmhpd SM6350_LCX>,
1301 power-domain-names = "lcx", "lmx";
1303 memory-region = <&pil_adsp_mem>;
1307 qcom,smem-states = <&smp2p_adsp_out 0>;
1308 qcom,smem-state-names = "stop";
1312 glink-edge {
1313 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
1320 qcom,remote-pid = <2>;
1324 qcom,glink-channels = "fastrpcglink-apps-dsp";
1326 qcom,non-secure-domain;
1327 #address-cells = <1>;
1328 #size-cells = <0>;
1330 compute-cb@3 {
1331 compatible = "qcom,fastrpc-compute-cb";
1336 compute-cb@4 {
1337 compatible = "qcom,fastrpc-compute-cb";
1342 compute-cb@5 {
1343 compatible = "qcom,fastrpc-compute-cb";
1353 compatible = "qcom,adreno-619.0", "qcom,adreno";
1356 reg-names = "kgsl_3d0_reg_memory",
1361 operating-points-v2 = <&gpu_opp_table>;
1363 nvmem-cells = <&gpu_speed_bin>;
1364 nvmem-cell-names = "speed_bin";
1365 #cooling-cells = <2>;
1369 gpu_zap_shader: zap-shader {
1370 memory-region = <&pil_gpu_mem>;
1373 gpu_opp_table: opp-table {
1374 compatible = "operating-points-v2";
1376 opp-850000000 {
1377 opp-hz = /bits/ 64 <850000000>;
1378 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1379 opp-supported-hw = <0x02>;
1382 opp-800000000 {
1383 opp-hz = /bits/ 64 <800000000>;
1384 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1385 opp-supported-hw = <0x04>;
1388 opp-650000000 {
1389 opp-hz = /bits/ 64 <650000000>;
1390 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1391 opp-supported-hw = <0x08>;
1394 opp-565000000 {
1395 opp-hz = /bits/ 64 <565000000>;
1396 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1397 opp-supported-hw = <0x10>;
1400 opp-430000000 {
1401 opp-hz = /bits/ 64 <430000000>;
1402 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1403 opp-supported-hw = <0xff>;
1406 opp-355000000 {
1407 opp-hz = /bits/ 64 <355000000>;
1408 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1409 opp-supported-hw = <0xff>;
1412 opp-253000000 {
1413 opp-hz = /bits/ 64 <253000000>;
1414 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1415 opp-supported-hw = <0xff>;
1421 compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
1423 #iommu-cells = <1>;
1424 #global-interrupts = <2>;
1439 clock-names = "ahb",
1443 power-domains = <&gpucc GPU_CX_GDSC>;
1447 compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu";
1451 reg-names = "gmu",
1457 interrupt-names = "hfi",
1465 clock-names = "ahb",
1471 power-domains = <&gpucc GPU_CX_GDSC>,
1473 power-domain-names = "cx",
1478 operating-points-v2 = <&gmu_opp_table>;
1480 gmu_opp_table: opp-table {
1481 compatible = "operating-points-v2";
1483 opp-200000000 {
1484 opp-hz = /bits/ 64 <200000000>;
1485 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1490 gpucc: clock-controller@3d90000 {
1491 compatible = "qcom,sm6350-gpucc";
1496 clock-names = "bi_tcxo",
1499 #clock-cells = <1>;
1500 #reset-cells = <1>;
1501 #power-domain-cells = <1>;
1505 compatible = "qcom,sm6350-mpss-pas";
1508 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
1514 interrupt-names = "wdog", "fatal", "ready", "handover",
1515 "stop-ack", "shutdown-ack";
1518 clock-names = "xo";
1520 power-domains = <&rpmhpd SM6350_CX>,
1522 power-domain-names = "cx", "mss";
1524 memory-region = <&pil_modem_mem>;
1528 qcom,smem-states = <&modem_smp2p_out 0>;
1529 qcom,smem-state-names = "stop";
1533 glink-edge {
1534 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
1540 qcom,remote-pid = <1>;
1545 compatible = "qcom,sm6350-cdsp-pas";
1548 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
1553 interrupt-names = "wdog", "fatal", "ready",
1554 "handover", "stop-ack";
1557 clock-names = "xo";
1559 power-domains = <&rpmhpd SM6350_CX>,
1561 power-domain-names = "cx", "mx";
1563 memory-region = <&pil_cdsp_mem>;
1567 qcom,smem-states = <&smp2p_cdsp_out 0>;
1568 qcom,smem-state-names = "stop";
1572 glink-edge {
1573 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
1580 qcom,remote-pid = <5>;
1584 qcom,glink-channels = "fastrpcglink-apps-dsp";
1586 qcom,non-secure-domain;
1587 #address-cells = <1>;
1588 #size-cells = <0>;
1590 compute-cb@1 {
1591 compatible = "qcom,fastrpc-compute-cb";
1596 compute-cb@2 {
1597 compatible = "qcom,fastrpc-compute-cb";
1602 compute-cb@3 {
1603 compatible = "qcom,fastrpc-compute-cb";
1608 compute-cb@4 {
1609 compatible = "qcom,fastrpc-compute-cb";
1614 compute-cb@5 {
1615 compatible = "qcom,fastrpc-compute-cb";
1620 compute-cb@6 {
1621 compatible = "qcom,fastrpc-compute-cb";
1626 compute-cb@7 {
1627 compatible = "qcom,fastrpc-compute-cb";
1632 compute-cb@8 {
1633 compatible = "qcom,fastrpc-compute-cb";
1644 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
1649 interrupt-names = "hc_irq", "pwr_irq";
1655 clock-names = "iface", "core", "xo";
1659 interconnect-names = "sdhc-ddr", "cpu-sdhc";
1661 pinctrl-0 = <&sdc2_on_state>;
1662 pinctrl-1 = <&sdc2_off_state>;
1663 pinctrl-names = "default", "sleep";
1665 qcom,dll-config = <0x0007642c>;
1666 qcom,ddr-config = <0x80040868>;
1667 power-domains = <&rpmhpd SM6350_CX>;
1668 operating-points-v2 = <&sdhc2_opp_table>;
1669 bus-width = <4>;
1673 sdhc2_opp_table: opp-table {
1674 compatible = "operating-points-v2";
1676 opp-100000000 {
1677 opp-hz = /bits/ 64 <100000000>;
1678 required-opps = <&rpmhpd_opp_svs_l1>;
1679 opp-peak-kBps = <790000 131000>;
1680 opp-avg-kBps = <50000 50000>;
1683 opp-202000000 {
1684 opp-hz = /bits/ 64 <202000000>;
1685 required-opps = <&rpmhpd_opp_nom>;
1686 opp-peak-kBps = <3190000 294000>;
1687 opp-avg-kBps = <261438 300000>;
1693 compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy";
1696 #phy-cells = <0>;
1699 clock-names = "cfg_ahb", "ref";
1705 compatible = "qcom,sm6350-qmp-usb3-dp-phy";
1712 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
1714 power-domains = <&gcc USB30_PRIM_GDSC>;
1718 reset-names = "phy", "common";
1720 orientation-switch;
1722 #clock-cells = <1>;
1723 #phy-cells = <1>;
1728 #address-cells = <1>;
1729 #size-cells = <0>;
1742 remote-endpoint = <&usb_1_dwc3_ss_out>;
1756 compatible = "qcom,sm6350-dc-noc";
1758 #interconnect-cells = <2>;
1759 qcom,bcm-voters = <&apps_bcm_voter>;
1762 system-cache-controller@9200000 {
1763 compatible = "qcom,sm6350-llcc";
1765 reg-names = "llcc0_base", "llcc_broadcast_base";
1769 compatible = "qcom,sm6350-gem-noc";
1771 #interconnect-cells = <2>;
1772 qcom,bcm-voters = <&apps_bcm_voter>;
1776 compatible = "qcom,sm6350-npu-noc";
1778 #interconnect-cells = <2>;
1779 qcom,bcm-voters = <&apps_bcm_voter>;
1783 compatible = "qcom,sm6350-llcc-bwmon", "qcom,sdm845-bwmon";
1787 operating-points-v2 = <&llcc_bwmon_opp_table>;
1791 llcc_bwmon_opp_table: opp-table {
1792 compatible = "operating-points-v2";
1794 opp-0 {
1795 opp-peak-kBps = <2288000>;
1798 opp-1 {
1799 opp-peak-kBps = <4577000>;
1802 opp-2 {
1803 opp-peak-kBps = <7110000>;
1806 opp-3 {
1807 opp-peak-kBps = <9155000>;
1810 opp-4 {
1811 opp-peak-kBps = <12298000>;
1814 opp-5 {
1815 opp-peak-kBps = <14236000>;
1822 compatible = "qcom,sm6350-cpu-bwmon", "qcom,sc7280-llcc-bwmon";
1826 operating-points-v2 = <&cpu_bwmon_opp_table>;
1830 cpu_bwmon_opp_table: opp-table {
1831 compatible = "operating-points-v2";
1833 opp-0 {
1834 opp-peak-kBps = <762000>;
1837 opp-1 {
1838 opp-peak-kBps = <1144000>;
1841 opp-2 {
1842 opp-peak-kBps = <1720000>;
1845 opp-3 {
1846 opp-peak-kBps = <2086000>;
1849 opp-4 {
1850 opp-peak-kBps = <2597000>;
1853 opp-5 {
1854 opp-peak-kBps = <2929000>;
1857 opp-6 {
1858 opp-peak-kBps = <3879000>;
1861 opp-7 {
1862 opp-peak-kBps = <5161000>;
1865 opp-8 {
1866 opp-peak-kBps = <5931000>;
1869 opp-9 {
1870 opp-peak-kBps = <6881000>;
1873 opp-10 {
1874 opp-peak-kBps = <7980000>;
1880 compatible = "qcom,sm6350-dwc3", "qcom,dwc3";
1883 #address-cells = <2>;
1884 #size-cells = <2>;
1892 clock-names = "cfg_noc",
1898 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1903 interrupt-names = "pwr_event",
1909 power-domains = <&gcc USB30_PRIM_GDSC>;
1915 interconnect-names = "usb-ddr", "apps-usb";
1924 snps,has-lpm-erratum;
1925 snps,hird-threshold = /bits/ 8 <0x10>;
1926 snps,parkmode-disable-ss-quirk;
1928 phy-names = "usb2-phy", "usb3-phy";
1929 usb-role-switch;
1932 #address-cells = <1>;
1933 #size-cells = <0>;
1946 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
1954 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci";
1957 power-domains = <&camcc TITAN_TOP_GDSC>;
1965 clock-names = "camnoc_axi",
1972 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
1974 assigned-clock-rates = <80000000>, <37500000>;
1976 pinctrl-0 = <&cci0_default &cci1_default>;
1977 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
1978 pinctrl-names = "default", "sleep";
1980 #address-cells = <1>;
1981 #size-cells = <0>;
1985 cci0_i2c0: i2c-bus@0 {
1987 clock-frequency = <1000000>;
1988 #address-cells = <1>;
1989 #size-cells = <0>;
1992 cci0_i2c1: i2c-bus@1 {
1994 clock-frequency = <1000000>;
1995 #address-cells = <1>;
1996 #size-cells = <0>;
2001 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci";
2004 power-domains = <&camcc TITAN_TOP_GDSC>;
2012 clock-names = "camnoc_axi",
2019 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
2021 assigned-clock-rates = <80000000>, <37500000>;
2023 pinctrl-0 = <&cci2_default>;
2024 pinctrl-1 = <&cci2_sleep>;
2025 pinctrl-names = "default", "sleep";
2027 #address-cells = <1>;
2028 #size-cells = <0>;
2032 cci1_i2c0: i2c-bus@0 {
2034 clock-frequency = <1000000>;
2035 #address-cells = <1>;
2036 #size-cells = <0>;
2042 camcc: clock-controller@ad00000 {
2043 compatible = "qcom,sm6350-camcc";
2046 #clock-cells = <1>;
2047 #reset-cells = <1>;
2048 #power-domain-cells = <1>;
2051 mdss: display-subsystem@ae00000 {
2052 compatible = "qcom,sm6350-mdss";
2054 reg-names = "mdss";
2057 interrupt-controller;
2058 #interrupt-cells = <1>;
2064 interconnect-names = "mdp0-mem",
2065 "cpu-cfg";
2070 clock-names = "iface",
2074 power-domains = <&dispcc MDSS_GDSC>;
2077 #address-cells = <2>;
2078 #size-cells = <2>;
2083 mdss_mdp: display-controller@ae01000 {
2084 compatible = "qcom,sm6350-dpu";
2087 reg-names = "mdp", "vbif";
2089 interrupt-parent = <&mdss>;
2098 clock-names = "bus",
2105 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2106 assigned-clock-rates = <19200000>;
2108 operating-points-v2 = <&mdp_opp_table>;
2109 power-domains = <&rpmhpd SM6350_CX>;
2112 #address-cells = <1>;
2113 #size-cells = <0>;
2119 remote-endpoint = <&mdss_dsi0_in>;
2127 remote-endpoint = <&mdss_dp_in>;
2132 mdp_opp_table: opp-table {
2133 compatible = "operating-points-v2";
2135 opp-19200000 {
2136 opp-hz = /bits/ 64 <19200000>;
2137 required-opps = <&rpmhpd_opp_min_svs>;
2140 opp-200000000 {
2141 opp-hz = /bits/ 64 <200000000>;
2142 required-opps = <&rpmhpd_opp_low_svs>;
2145 opp-300000000 {
2146 opp-hz = /bits/ 64 <300000000>;
2147 required-opps = <&rpmhpd_opp_svs>;
2150 opp-373333333 {
2151 opp-hz = /bits/ 64 <373333333>;
2152 required-opps = <&rpmhpd_opp_svs_l1>;
2155 opp-448000000 {
2156 opp-hz = /bits/ 64 <448000000>;
2157 required-opps = <&rpmhpd_opp_nom>;
2160 opp-560000000 {
2161 opp-hz = /bits/ 64 <560000000>;
2162 required-opps = <&rpmhpd_opp_turbo>;
2167 mdss_dp: displayport-controller@ae90000 {
2168 compatible = "qcom,sm6350-dp", "qcom,sm8350-dp";
2174 interrupt-parent = <&mdss>;
2181 clock-names = "core_iface",
2187 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
2189 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2193 phy-names = "dp";
2195 #sound-dai-cells = <0>;
2197 operating-points-v2 = <&dp_opp_table>;
2198 power-domains = <&rpmhpd SM6350_CX>;
2203 #address-cells = <1>;
2204 #size-cells = <0>;
2210 remote-endpoint = <&dpu_intf0_out>;
2222 dp_opp_table: opp-table {
2223 compatible = "operating-points-v2";
2225 opp-160000000 {
2226 opp-hz = /bits/ 64 <160000000>;
2227 required-opps = <&rpmhpd_opp_low_svs>;
2230 opp-270000000 {
2231 opp-hz = /bits/ 64 <270000000>;
2232 required-opps = <&rpmhpd_opp_svs>;
2235 opp-540000000 {
2236 opp-hz = /bits/ 64 <540000000>;
2237 required-opps = <&rpmhpd_opp_svs_l1>;
2240 opp-810000000 {
2241 opp-hz = /bits/ 64 <810000000>;
2242 required-opps = <&rpmhpd_opp_nom>;
2248 compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2250 reg-names = "dsi_ctrl";
2252 interrupt-parent = <&mdss>;
2261 clock-names = "byte",
2268 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2270 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
2272 operating-points-v2 = <&mdss_dsi_opp_table>;
2273 power-domains = <&rpmhpd SM6350_MX>;
2276 phy-names = "dsi";
2278 #address-cells = <1>;
2279 #size-cells = <0>;
2284 #address-cells = <1>;
2285 #size-cells = <0>;
2291 remote-endpoint = <&dpu_intf1_out>;
2303 mdss_dsi_opp_table: opp-table {
2304 compatible = "operating-points-v2";
2306 opp-187500000 {
2307 opp-hz = /bits/ 64 <187500000>;
2308 required-opps = <&rpmhpd_opp_low_svs>;
2311 opp-300000000 {
2312 opp-hz = /bits/ 64 <300000000>;
2313 required-opps = <&rpmhpd_opp_svs>;
2316 opp-358000000 {
2317 opp-hz = /bits/ 64 <358000000>;
2318 required-opps = <&rpmhpd_opp_svs_l1>;
2324 compatible = "qcom,dsi-phy-10nm";
2328 reg-names = "dsi_phy",
2332 #clock-cells = <1>;
2333 #phy-cells = <0>;
2337 clock-names = "iface", "ref";
2343 dispcc: clock-controller@af00000 {
2344 compatible = "qcom,sm6350-dispcc";
2352 clock-names = "bi_tcxo",
2358 #clock-cells = <1>;
2359 #reset-cells = <1>;
2360 #power-domain-cells = <1>;
2363 pdc: interrupt-controller@b220000 {
2364 compatible = "qcom,sm6350-pdc", "qcom,pdc";
2366 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
2368 #interrupt-cells = <2>;
2369 interrupt-parent = <&intc>;
2370 interrupt-controller;
2373 tsens0: thermal-sensor@c263000 {
2374 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2";
2378 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
2380 interrupt-names = "uplow", "critical";
2381 #thermal-sensor-cells = <1>;
2384 tsens1: thermal-sensor@c265000 {
2385 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2";
2389 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
2391 interrupt-names = "uplow", "critical";
2392 #thermal-sensor-cells = <1>;
2395 aoss_qmp: power-management@c300000 {
2396 compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp";
2398 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
2402 #clock-cells = <0>;
2406 compatible = "qcom,spmi-pmic-arb";
2412 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2413 interrupt-names = "periph_irq";
2414 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2417 #address-cells = <2>;
2418 #size-cells = <0>;
2419 interrupt-controller;
2420 #interrupt-cells = <4>;
2424 compatible = "qcom,sm6350-tlmm";
2435 gpio-controller;
2436 #gpio-cells = <2>;
2437 interrupt-controller;
2438 #interrupt-cells = <2>;
2439 gpio-ranges = <&tlmm 0 0 157>;
2440 wakeup-parent = <&pdc>;
2442 cci0_default: cci0-default-state {
2445 drive-strength = <2>;
2446 bias-pull-up;
2449 cci0_sleep: cci0-sleep-state {
2452 drive-strength = <2>;
2453 bias-pull-down;
2456 cci1_default: cci1-default-state {
2459 drive-strength = <2>;
2460 bias-pull-up;
2463 cci1_sleep: cci1-sleep-state {
2466 drive-strength = <2>;
2467 bias-pull-down;
2470 cci2_default: cci2-default-state {
2473 drive-strength = <2>;
2474 bias-pull-up;
2477 cci2_sleep: cci2-sleep-state {
2480 drive-strength = <2>;
2481 bias-pull-down;
2484 sdc2_off_state: sdc2-off-state {
2485 clk-pins {
2487 drive-strength = <2>;
2488 bias-disable;
2491 cmd-pins {
2493 drive-strength = <2>;
2494 bias-pull-up;
2497 data-pins {
2499 drive-strength = <2>;
2500 bias-pull-up;
2504 sdc2_on_state: sdc2-on-state {
2505 clk-pins {
2507 drive-strength = <16>;
2508 bias-disable;
2511 cmd-pins {
2513 drive-strength = <10>;
2514 bias-pull-up;
2517 data-pins {
2519 drive-strength = <10>;
2520 bias-pull-up;
2524 qup_uart9_default: qup-uart9-default-state {
2527 drive-strength = <2>;
2528 bias-disable;
2531 qup_i2c0_default: qup-i2c0-default-state {
2534 drive-strength = <2>;
2535 bias-pull-up;
2538 qup_i2c2_default: qup-i2c2-default-state {
2541 drive-strength = <2>;
2542 bias-pull-up;
2545 qup_i2c6_default: qup-i2c6-default-state {
2548 drive-strength = <2>;
2549 bias-pull-up;
2552 qup_i2c7_default: qup-i2c7-default-state {
2555 drive-strength = <2>;
2556 bias-pull-up;
2559 qup_i2c8_default: qup-i2c8-default-state {
2562 drive-strength = <2>;
2563 bias-pull-up;
2566 qup_i2c10_default: qup-i2c10-default-state {
2569 drive-strength = <2>;
2570 bias-pull-up;
2573 qup_uart1_cts: qup-uart1-cts-default-state {
2576 drive-strength = <2>;
2577 bias-disable;
2580 qup_uart1_rts: qup-uart1-rts-default-state {
2583 drive-strength = <2>;
2584 bias-pull-down;
2587 qup_uart1_rx: qup-uart1-rx-default-state {
2590 drive-strength = <2>;
2591 bias-disable;
2594 qup_uart1_tx: qup-uart1-tx-default-state {
2597 drive-strength = <2>;
2598 bias-pull-up;
2603 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500";
2605 #iommu-cells = <2>;
2606 #global-interrupts = <1>;
2690 intc: interrupt-controller@17a00000 {
2691 compatible = "arm,gic-v3";
2692 #interrupt-cells = <3>;
2693 interrupt-controller;
2700 compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt";
2707 compatible = "arm,armv7-timer-mem";
2709 clock-frequency = <19200000>;
2710 #address-cells = <1>;
2711 #size-cells = <1>;
2715 frame-number = <0>;
2723 frame-number = <1>;
2730 frame-number = <2>;
2737 frame-number = <3>;
2744 frame-number = <4>;
2751 frame-number = <5>;
2758 frame-number = <6>;
2765 apps_rsc: rsc@18200000 {
2766 compatible = "qcom,rpmh-rsc";
2771 reg-names = "drv-0", "drv-1", "drv-2";
2775 qcom,tcs-offset = <0xd00>;
2776 qcom,drv-id = <2>;
2777 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
2779 power-domains = <&CLUSTER_PD>;
2781 rpmhcc: clock-controller {
2782 compatible = "qcom,sm6350-rpmh-clk";
2783 #clock-cells = <1>;
2784 clock-names = "xo";
2788 rpmhpd: power-controller {
2789 compatible = "qcom,sm6350-rpmhpd";
2790 #power-domain-cells = <1>;
2791 operating-points-v2 = <&rpmhpd_opp_table>;
2793 rpmhpd_opp_table: opp-table {
2794 compatible = "operating-points-v2";
2797 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
2801 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2805 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2809 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2813 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2817 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2821 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2825 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
2829 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2833 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2838 apps_bcm_voter: bcm-voter {
2839 compatible = "qcom,bcm-voter";
2844 compatible = "qcom,sm6350-osm-l3", "qcom,osm-l3";
2848 clock-names = "xo", "alternate";
2850 #interconnect-cells = <1>;
2854 compatible = "qcom,sm6350-cpufreq-hw", "qcom,cpufreq-hw";
2856 reg-names = "freq-domain0", "freq-domain1";
2858 clock-names = "xo", "alternate";
2860 #freq-domain-cells = <1>;
2861 #clock-cells = <1>;
2865 compatible = "qcom,wcn3990-wifi";
2867 reg-names = "membase";
2868 memory-region = <&wlan_fw_mem>;
2882 qcom,msa-fixed-perm;
2887 thermal-zones {
2888 aoss0-thermal {
2889 thermal-sensors = <&tsens0 0>;
2892 aoss0-crit {
2900 aoss1-thermal {
2901 thermal-sensors = <&tsens1 0>;
2904 aoss1-crit {
2912 audio-thermal {
2913 thermal-sensors = <&tsens1 2>;
2916 audio-crit {
2924 camera-thermal {
2925 thermal-sensors = <&tsens1 5>;
2928 camera-crit {
2936 cpu0-thermal {
2937 thermal-sensors = <&tsens0 1>;
2940 cpu0_alert0: trip-point0 {
2946 cpu0-crit {
2953 cooling-maps {
2956 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2961 cpu1-thermal {
2962 thermal-sensors = <&tsens0 2>;
2965 cpu1_alert0: trip-point0 {
2971 cpu1-crit {
2978 cooling-maps {
2981 cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2986 cpu2-thermal {
2987 thermal-sensors = <&tsens0 3>;
2990 cpu2_alert0: trip-point0 {
2996 cpu2-crit {
3003 cooling-maps {
3006 cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3011 cpu3-thermal {
3012 thermal-sensors = <&tsens0 4>;
3015 cpu3_alert0: trip-point0 {
3021 cpu3-crit {
3028 cooling-maps {
3031 cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3036 cpu4-thermal {
3037 thermal-sensors = <&tsens0 5>;
3040 cpu4_alert0: trip-point0 {
3046 cpu4-crit {
3053 cooling-maps {
3056 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3061 cpu5-thermal {
3062 thermal-sensors = <&tsens0 6>;
3065 cpu5_alert0: trip-point0 {
3071 cpu5-crit {
3078 cooling-maps {
3081 cooling-device = <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3086 cpu6-left-thermal {
3087 thermal-sensors = <&tsens0 9>;
3090 cpu6_left_alert0: trip-point0 {
3096 cpu6-left-crit {
3103 cooling-maps {
3106 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3111 cpu6-right-thermal {
3112 thermal-sensors = <&tsens0 10>;
3115 cpu6_right_alert0: trip-point0 {
3121 cpu6-right-crit {
3128 cooling-maps {
3131 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3136 cpu7-left-thermal {
3137 thermal-sensors = <&tsens0 11>;
3140 cpu7_left_alert0: trip-point0 {
3146 cpu7-left-crit {
3153 cooling-maps {
3156 cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3161 cpu7-right-thermal {
3162 thermal-sensors = <&tsens0 12>;
3165 cpu7_right_alert0: trip-point0 {
3171 cpu7-right-crit {
3178 cooling-maps {
3181 cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3186 cpuss0-thermal {
3187 thermal-sensors = <&tsens0 7>;
3190 cpuss0-crit {
3198 cpuss1-thermal {
3199 thermal-sensors = <&tsens0 8>;
3202 cpuss1-crit {
3210 cwlan-thermal {
3211 thermal-sensors = <&tsens1 1>;
3214 cwlan-crit {
3222 ddr-thermal {
3223 thermal-sensors = <&tsens1 3>;
3226 ddr-crit {
3234 gpuss0-thermal {
3235 polling-delay-passive = <250>;
3237 thermal-sensors = <&tsens0 13>;
3240 gpuss0_alert0: trip-point0 {
3246 gpuss0-crit {
3253 cooling-maps {
3256 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3261 gpuss1-thermal {
3262 polling-delay-passive = <250>;
3264 thermal-sensors = <&tsens0 14>;
3267 gpuss1_alert0: trip-point0 {
3273 gpuss1-crit {
3280 cooling-maps {
3283 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3288 modem-core0-thermal {
3289 thermal-sensors = <&tsens1 6>;
3292 modem-core0-crit {
3300 modem-core1-thermal {
3301 thermal-sensors = <&tsens1 7>;
3304 modem-core1-crit {
3312 modem-scl-thermal {
3313 thermal-sensors = <&tsens1 9>;
3316 modem-scl-crit {
3324 modem-vec-thermal {
3325 thermal-sensors = <&tsens1 8>;
3328 modem-vec-crit {
3336 npu-thermal {
3337 thermal-sensors = <&tsens1 10>;
3340 npu-crit {
3348 q6-hvx-thermal {
3349 thermal-sensors = <&tsens1 4>;
3352 q6-hvx-crit {
3360 video-thermal {
3361 thermal-sensors = <&tsens1 11>;
3364 video-crit {
3374 compatible = "arm,armv8-timer";
3375 clock-frequency = <19200000>;