Lines Matching +full:pdc +full:- +full:intc
1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,dispcc-sm6350.h>
8 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
9 #include <dt-bindings/clock/qcom,gcc-sm6350.h>
10 #include <dt-bindings/clock/qcom,gpucc-sm6350.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/clock/qcom,sm6350-camcc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interconnect/qcom,icc.h>
16 #include <dt-bindings/interconnect/qcom,osm-l3.h>
17 #include <dt-bindings/interconnect/qcom,sm6350.h>
18 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/mailbox/qcom-ipcc.h>
20 #include <dt-bindings/phy/phy-qcom-qmp.h>
21 #include <dt-bindings/power/qcom-rpmpd.h>
22 #include <dt-bindings/soc/qcom,apr.h>
23 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
24 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
25 #include <dt-bindings/thermal/thermal.h>
28 interrupt-parent = <&intc>;
29 #address-cells = <2>;
30 #size-cells = <2>;
33 xo_board: xo-board {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <76800000>;
37 clock-output-names = "xo_board";
40 sleep_clk: sleep-clk {
41 compatible = "fixed-clock";
42 clock-frequency = <32764>;
43 #clock-cells = <0>;
48 #address-cells = <2>;
49 #size-cells = <0>;
56 enable-method = "psci";
57 capacity-dmips-mhz = <1024>;
58 dynamic-power-coefficient = <100>;
59 next-level-cache = <&l2_0>;
60 qcom,freq-domain = <&cpufreq_hw 0>;
61 operating-points-v2 = <&cpu0_opp_table>;
65 power-domains = <&cpu_pd0>;
66 power-domain-names = "psci";
67 #cooling-cells = <2>;
68 l2_0: l2-cache {
70 cache-level = <2>;
71 cache-unified;
72 next-level-cache = <&l3_0>;
73 l3_0: l3-cache {
75 cache-level = <3>;
76 cache-unified;
86 enable-method = "psci";
87 capacity-dmips-mhz = <1024>;
88 dynamic-power-coefficient = <100>;
89 next-level-cache = <&l2_100>;
90 qcom,freq-domain = <&cpufreq_hw 0>;
91 operating-points-v2 = <&cpu0_opp_table>;
95 power-domains = <&cpu_pd1>;
96 power-domain-names = "psci";
97 #cooling-cells = <2>;
98 l2_100: l2-cache {
100 cache-level = <2>;
101 cache-unified;
102 next-level-cache = <&l3_0>;
111 enable-method = "psci";
112 capacity-dmips-mhz = <1024>;
113 dynamic-power-coefficient = <100>;
114 next-level-cache = <&l2_200>;
115 qcom,freq-domain = <&cpufreq_hw 0>;
116 operating-points-v2 = <&cpu0_opp_table>;
120 power-domains = <&cpu_pd2>;
121 power-domain-names = "psci";
122 #cooling-cells = <2>;
123 l2_200: l2-cache {
125 cache-level = <2>;
126 cache-unified;
127 next-level-cache = <&l3_0>;
136 enable-method = "psci";
137 capacity-dmips-mhz = <1024>;
138 dynamic-power-coefficient = <100>;
139 next-level-cache = <&l2_300>;
140 qcom,freq-domain = <&cpufreq_hw 0>;
141 operating-points-v2 = <&cpu0_opp_table>;
145 power-domains = <&cpu_pd3>;
146 power-domain-names = "psci";
147 #cooling-cells = <2>;
148 l2_300: l2-cache {
150 cache-level = <2>;
151 cache-unified;
152 next-level-cache = <&l3_0>;
161 enable-method = "psci";
162 capacity-dmips-mhz = <1024>;
163 dynamic-power-coefficient = <100>;
164 next-level-cache = <&l2_400>;
165 qcom,freq-domain = <&cpufreq_hw 0>;
166 operating-points-v2 = <&cpu0_opp_table>;
170 power-domains = <&cpu_pd4>;
171 power-domain-names = "psci";
172 #cooling-cells = <2>;
173 l2_400: l2-cache {
175 cache-level = <2>;
176 cache-unified;
177 next-level-cache = <&l3_0>;
186 enable-method = "psci";
187 capacity-dmips-mhz = <1024>;
188 dynamic-power-coefficient = <100>;
189 next-level-cache = <&l2_500>;
190 qcom,freq-domain = <&cpufreq_hw 0>;
191 operating-points-v2 = <&cpu0_opp_table>;
195 power-domains = <&cpu_pd5>;
196 power-domain-names = "psci";
197 #cooling-cells = <2>;
198 l2_500: l2-cache {
200 cache-level = <2>;
201 cache-unified;
202 next-level-cache = <&l3_0>;
211 enable-method = "psci";
212 capacity-dmips-mhz = <1894>;
213 dynamic-power-coefficient = <703>;
214 next-level-cache = <&l2_600>;
215 qcom,freq-domain = <&cpufreq_hw 1>;
216 operating-points-v2 = <&cpu6_opp_table>;
220 power-domains = <&cpu_pd6>;
221 power-domain-names = "psci";
222 #cooling-cells = <2>;
223 l2_600: l2-cache {
225 cache-level = <2>;
226 cache-unified;
227 next-level-cache = <&l3_0>;
236 enable-method = "psci";
237 capacity-dmips-mhz = <1894>;
238 dynamic-power-coefficient = <703>;
239 next-level-cache = <&l2_700>;
240 qcom,freq-domain = <&cpufreq_hw 1>;
241 operating-points-v2 = <&cpu6_opp_table>;
245 power-domains = <&cpu_pd7>;
246 power-domain-names = "psci";
247 #cooling-cells = <2>;
248 l2_700: l2-cache {
250 cache-level = <2>;
251 cache-unified;
252 next-level-cache = <&l3_0>;
256 cpu-map {
292 domain-idle-states {
293 cluster_sleep_pc: cluster-sleep-0 {
294 compatible = "domain-idle-state";
295 arm,psci-suspend-param = <0x41000044>;
296 entry-latency-us = <2752>;
297 exit-latency-us = <3048>;
298 min-residency-us = <6118>;
301 cluster_sleep_cx_ret: cluster-sleep-1 {
302 compatible = "domain-idle-state";
303 arm,psci-suspend-param = <0x41001244>;
304 entry-latency-us = <3638>;
305 exit-latency-us = <4562>;
306 min-residency-us = <8467>;
309 cluster_aoss_sleep: cluster-sleep-2 {
310 compatible = "domain-idle-state";
311 arm,psci-suspend-param = <0x4100b244>;
312 entry-latency-us = <3263>;
313 exit-latency-us = <6562>;
314 min-residency-us = <9987>;
318 cpu_idle_states: idle-states {
319 entry-method = "psci";
321 little_cpu_sleep_0: cpu-sleep-0-0 {
322 compatible = "arm,idle-state";
323 idle-state-name = "little-power-collapse";
324 arm,psci-suspend-param = <0x40000003>;
325 entry-latency-us = <549>;
326 exit-latency-us = <901>;
327 min-residency-us = <1774>;
328 local-timer-stop;
331 little_cpu_sleep_1: cpu-sleep-0-1 {
332 compatible = "arm,idle-state";
333 idle-state-name = "little-rail-power-collapse";
334 arm,psci-suspend-param = <0x40000004>;
335 entry-latency-us = <702>;
336 exit-latency-us = <915>;
337 min-residency-us = <4001>;
338 local-timer-stop;
341 big_cpu_sleep_0: cpu-sleep-1-0 {
342 compatible = "arm,idle-state";
343 idle-state-name = "big-power-collapse";
344 arm,psci-suspend-param = <0x40000003>;
345 entry-latency-us = <523>;
346 exit-latency-us = <1244>;
347 min-residency-us = <2207>;
348 local-timer-stop;
351 big_cpu_sleep_1: cpu-sleep-1-1 {
352 compatible = "arm,idle-state";
353 idle-state-name = "big-rail-power-collapse";
354 arm,psci-suspend-param = <0x40000004>;
355 entry-latency-us = <526>;
356 exit-latency-us = <1854>;
357 min-residency-us = <5555>;
358 local-timer-stop;
365 compatible = "qcom,scm-sm6350", "qcom,scm";
366 #reset-cells = <1>;
376 cpu0_opp_table: opp-table-cpu0 {
377 compatible = "operating-points-v2";
378 opp-shared;
380 opp-300000000 {
381 opp-hz = /bits/ 64 <300000000>;
382 /* DDR: 4-wide, 2 channels, double data rate, L3: 16-wide, 2 channels */
383 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>;
386 opp-576000000 {
387 opp-hz = /bits/ 64 <576000000>;
388 opp-peak-kBps = <(547000 * 4 * 2 * 2) (556800 * 16 * 2)>;
391 opp-768000000 {
392 opp-hz = /bits/ 64 <768000000>;
393 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>;
396 opp-1017600000 {
397 opp-hz = /bits/ 64 <1017600000>;
398 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>;
401 opp-1248000000 {
402 opp-hz = /bits/ 64 <1248000000>;
403 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>;
406 opp-1324800000 {
407 opp-hz = /bits/ 64 <1324800000>;
408 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1286400 * 16 * 2)>;
411 opp-1516800000 {
412 opp-hz = /bits/ 64 <1516800000>;
413 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
416 opp-1612800000 {
417 opp-hz = /bits/ 64 <1612800000>;
418 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
421 opp-1708800000 {
422 opp-hz = /bits/ 64 <1708800000>;
423 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
427 cpu6_opp_table: opp-table-cpu6 {
428 compatible = "operating-points-v2";
429 opp-shared;
431 opp-300000000 {
432 opp-hz = /bits/ 64 <300000000>;
433 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>;
436 opp-787200000 {
437 opp-hz = /bits/ 64 <787200000>;
438 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>;
441 opp-979200000 {
442 opp-hz = /bits/ 64 <979200000>;
443 opp-peak-kBps = <(768000 * 4 * 2 * 2) (940800 * 16 * 2)>;
446 opp-1036800000 {
447 opp-hz = /bits/ 64 <1036800000>;
448 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>;
451 opp-1248000000 {
452 opp-hz = /bits/ 64 <1248000000>;
453 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>;
456 opp-1401600000 {
457 opp-hz = /bits/ 64 <1401600000>;
458 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1401600 * 16 * 2)>;
461 opp-1555200000 {
462 opp-hz = /bits/ 64 <1555200000>;
463 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
466 opp-1766400000 {
467 opp-hz = /bits/ 64 <1766400000>;
468 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
471 opp-1900800000 {
472 opp-hz = /bits/ 64 <1900800000>;
473 opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
476 opp-2073600000 {
477 opp-hz = /bits/ 64 <2073600000>;
478 opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
482 qup_opp_table: opp-table-qup {
483 compatible = "operating-points-v2";
485 opp-75000000 {
486 opp-hz = /bits/ 64 <75000000>;
487 required-opps = <&rpmhpd_opp_low_svs>;
490 opp-100000000 {
491 opp-hz = /bits/ 64 <100000000>;
492 required-opps = <&rpmhpd_opp_svs>;
495 opp-128000000 {
496 opp-hz = /bits/ 64 <128000000>;
497 required-opps = <&rpmhpd_opp_nom>;
502 compatible = "arm,armv8-pmuv3";
507 compatible = "arm,psci-1.0";
510 cpu_pd0: power-domain-cpu0 {
511 #power-domain-cells = <0>;
512 power-domains = <&cluster_pd>;
513 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
516 cpu_pd1: power-domain-cpu1 {
517 #power-domain-cells = <0>;
518 power-domains = <&cluster_pd>;
519 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
522 cpu_pd2: power-domain-cpu2 {
523 #power-domain-cells = <0>;
524 power-domains = <&cluster_pd>;
525 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
528 cpu_pd3: power-domain-cpu3 {
529 #power-domain-cells = <0>;
530 power-domains = <&cluster_pd>;
531 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
534 cpu_pd4: power-domain-cpu4 {
535 #power-domain-cells = <0>;
536 power-domains = <&cluster_pd>;
537 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
540 cpu_pd5: power-domain-cpu5 {
541 #power-domain-cells = <0>;
542 power-domains = <&cluster_pd>;
543 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
546 cpu_pd6: power-domain-cpu6 {
547 #power-domain-cells = <0>;
548 power-domains = <&cluster_pd>;
549 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
552 cpu_pd7: power-domain-cpu7 {
553 #power-domain-cells = <0>;
554 power-domains = <&cluster_pd>;
555 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
558 cluster_pd: power-domain-cpu-cluster0 {
559 #power-domain-cells = <0>;
560 domain-idle-states = <&cluster_sleep_pc
566 reserved_memory: reserved-memory {
567 #address-cells = <2>;
568 #size-cells = <2>;
573 no-map;
578 no-map;
582 compatible = "qcom,cmd-db";
584 no-map;
589 no-map;
594 no-map;
599 no-map;
604 no-map;
609 no-map;
614 no-map;
619 no-map;
624 no-map;
629 no-map;
634 no-map;
639 no-map;
644 no-map;
649 no-map;
654 no-map;
659 no-map;
664 no-map;
669 no-map;
674 no-map;
680 record-size = <0x1000>;
681 console-size = <0x40000>;
682 pmsg-size = <0x20000>;
683 ecc-size = <16>;
684 no-map;
689 no-map;
695 memory-region = <&smem_mem>;
699 smp2p-adsp {
702 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
708 qcom,local-pid = <0>;
709 qcom,remote-pid = <2>;
711 smp2p_adsp_out: master-kernel {
712 qcom,entry-name = "master-kernel";
713 #qcom,smem-state-cells = <1>;
716 smp2p_adsp_in: slave-kernel {
717 qcom,entry-name = "slave-kernel";
718 interrupt-controller;
719 #interrupt-cells = <2>;
723 smp2p-cdsp {
726 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
732 qcom,local-pid = <0>;
733 qcom,remote-pid = <5>;
735 smp2p_cdsp_out: master-kernel {
736 qcom,entry-name = "master-kernel";
737 #qcom,smem-state-cells = <1>;
740 smp2p_cdsp_in: slave-kernel {
741 qcom,entry-name = "slave-kernel";
742 interrupt-controller;
743 #interrupt-cells = <2>;
747 smp2p-mpss {
751 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
757 qcom,local-pid = <0>;
758 qcom,remote-pid = <1>;
760 modem_smp2p_out: master-kernel {
761 qcom,entry-name = "master-kernel";
762 #qcom,smem-state-cells = <1>;
765 modem_smp2p_in: slave-kernel {
766 qcom,entry-name = "slave-kernel";
767 interrupt-controller;
768 #interrupt-cells = <2>;
771 ipa_smp2p_out: ipa-ap-to-modem {
772 qcom,entry-name = "ipa";
773 #qcom,smem-state-cells = <1>;
776 ipa_smp2p_in: ipa-modem-to-ap {
777 qcom,entry-name = "ipa";
778 interrupt-controller;
779 #interrupt-cells = <2>;
784 #address-cells = <2>;
785 #size-cells = <2>;
787 dma-ranges = <0 0 0 0 0x10 0>;
788 compatible = "simple-bus";
790 gcc: clock-controller@100000 {
791 compatible = "qcom,gcc-sm6350";
793 #clock-cells = <1>;
794 #reset-cells = <1>;
795 #power-domain-cells = <1>;
796 clock-names = "bi_tcxo",
805 compatible = "qcom,sm6350-ipcc", "qcom,ipcc";
808 interrupt-controller;
809 #interrupt-cells = <3>;
810 #mbox-cells = <2>;
814 compatible = "qcom,sm6350-qfprom", "qcom,qfprom";
816 #address-cells = <1>;
817 #size-cells = <1>;
819 gpu_speed_bin: gpu-speed-bin@2015 {
826 compatible = "qcom,prng-ee";
829 clock-names = "core";
833 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
837 reg-names = "hc", "cqhci", "ice";
841 interrupt-names = "hc_irq", "pwr_irq";
847 clock-names = "iface", "core", "xo";
849 qcom,dll-config = <0x000f642c>;
850 qcom,ddr-config = <0x80040868>;
851 power-domains = <&rpmhpd SM6350_CX>;
852 operating-points-v2 = <&sdhc1_opp_table>;
853 bus-width = <8>;
854 non-removable;
855 supports-cqe;
859 sdhc1_opp_table: opp-table {
860 compatible = "operating-points-v2";
862 opp-19200000 {
863 opp-hz = /bits/ 64 <19200000>;
864 required-opps = <&rpmhpd_opp_min_svs>;
867 opp-100000000 {
868 opp-hz = /bits/ 64 <100000000>;
869 required-opps = <&rpmhpd_opp_low_svs>;
872 opp-384000000 {
873 opp-hz = /bits/ 64 <384000000>;
874 required-opps = <&rpmhpd_opp_svs_l1>;
879 gpi_dma0: dma-controller@800000 {
880 compatible = "qcom,sm6350-gpi-dma";
892 dma-channels = <10>;
893 dma-channel-mask = <0x1f>;
895 #dma-cells = <3>;
900 compatible = "qcom,geni-se-qup";
902 clock-names = "m-ahb", "s-ahb";
905 #address-cells = <2>;
906 #size-cells = <2>;
912 compatible = "qcom,geni-i2c";
914 clock-names = "se";
916 pinctrl-names = "default";
917 pinctrl-0 = <&qup_i2c0_default>;
921 dma-names = "tx", "rx";
922 #address-cells = <1>;
923 #size-cells = <0>;
927 interconnect-names = "qup-core", "qup-config", "qup-memory";
932 compatible = "qcom,geni-uart";
934 clock-names = "se";
936 pinctrl-names = "default";
937 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
939 power-domains = <&rpmhpd SM6350_CX>;
940 operating-points-v2 = <&qup_opp_table>;
943 interconnect-names = "qup-core", "qup-config";
948 compatible = "qcom,geni-i2c";
950 clock-names = "se";
952 pinctrl-names = "default";
953 pinctrl-0 = <&qup_i2c2_default>;
957 dma-names = "tx", "rx";
958 #address-cells = <1>;
959 #size-cells = <0>;
963 interconnect-names = "qup-core", "qup-config", "qup-memory";
968 gpi_dma1: dma-controller@900000 {
969 compatible = "qcom,sm6350-gpi-dma";
981 dma-channels = <10>;
982 dma-channel-mask = <0x3f>;
984 #dma-cells = <3>;
989 compatible = "qcom,geni-se-qup";
991 clock-names = "m-ahb", "s-ahb";
994 #address-cells = <2>;
995 #size-cells = <2>;
1001 compatible = "qcom,geni-i2c";
1003 clock-names = "se";
1005 pinctrl-names = "default";
1006 pinctrl-0 = <&qup_i2c6_default>;
1010 dma-names = "tx", "rx";
1011 #address-cells = <1>;
1012 #size-cells = <0>;
1016 interconnect-names = "qup-core", "qup-config", "qup-memory";
1021 compatible = "qcom,geni-i2c";
1023 clock-names = "se";
1025 pinctrl-names = "default";
1026 pinctrl-0 = <&qup_i2c7_default>;
1030 dma-names = "tx", "rx";
1031 #address-cells = <1>;
1032 #size-cells = <0>;
1036 interconnect-names = "qup-core", "qup-config", "qup-memory";
1041 compatible = "qcom,geni-i2c";
1043 clock-names = "se";
1045 pinctrl-names = "default";
1046 pinctrl-0 = <&qup_i2c8_default>;
1050 dma-names = "tx", "rx";
1051 #address-cells = <1>;
1052 #size-cells = <0>;
1056 interconnect-names = "qup-core", "qup-config", "qup-memory";
1061 compatible = "qcom,geni-debug-uart";
1063 clock-names = "se";
1065 pinctrl-names = "default";
1066 pinctrl-0 = <&qup_uart9_default>;
1070 interconnect-names = "qup-core", "qup-config";
1075 compatible = "qcom,geni-i2c";
1077 clock-names = "se";
1079 pinctrl-names = "default";
1080 pinctrl-0 = <&qup_i2c10_default>;
1084 dma-names = "tx", "rx";
1085 #address-cells = <1>;
1086 #size-cells = <0>;
1090 interconnect-names = "qup-core", "qup-config", "qup-memory";
1096 compatible = "qcom,sm6350-config-noc";
1098 #interconnect-cells = <2>;
1099 qcom,bcm-voters = <&apps_bcm_voter>;
1103 compatible = "qcom,sm6350-system-noc";
1105 #interconnect-cells = <2>;
1106 qcom,bcm-voters = <&apps_bcm_voter>;
1108 clk_virt: interconnect-clk-virt {
1109 compatible = "qcom,sm6350-clk-virt";
1110 #interconnect-cells = <2>;
1111 qcom,bcm-voters = <&apps_bcm_voter>;
1116 compatible = "qcom,sm6350-aggre1-noc";
1118 #interconnect-cells = <2>;
1119 qcom,bcm-voters = <&apps_bcm_voter>;
1123 compatible = "qcom,sm6350-aggre2-noc";
1125 #interconnect-cells = <2>;
1126 qcom,bcm-voters = <&apps_bcm_voter>;
1128 compute_noc: interconnect-compute-noc {
1129 compatible = "qcom,sm6350-compute-noc";
1130 #interconnect-cells = <2>;
1131 qcom,bcm-voters = <&apps_bcm_voter>;
1136 compatible = "qcom,sm6350-mmss-noc";
1138 #interconnect-cells = <2>;
1139 qcom,bcm-voters = <&apps_bcm_voter>;
1143 compatible = "qcom,sm6350-ufshc", "qcom,ufshc",
1144 "jedec,ufs-2.0";
1147 reg-names = "std", "ice";
1150 phy-names = "ufsphy";
1151 lanes-per-direction = <2>;
1152 #reset-cells = <1>;
1154 reset-names = "rst";
1156 power-domains = <&gcc UFS_PHY_GDSC>;
1160 clock-names = "core_clk",
1179 operating-points-v2 = <&ufs_opp_table>;
1185 interconnect-names = "ufs-ddr",
1186 "cpu-ufs";
1190 ufs_opp_table: opp-table {
1191 compatible = "operating-points-v2";
1193 opp-50000000 {
1194 opp-hz = /bits/ 64 <50000000>,
1203 required-opps = <&rpmhpd_opp_low_svs>;
1206 opp-200000000 {
1207 opp-hz = /bits/ 64 <200000000>,
1216 required-opps = <&rpmhpd_opp_nom>;
1222 compatible = "qcom,sm6350-qmp-ufs-phy";
1228 clock-names = "ref",
1232 power-domains = <&gcc UFS_PHY_GDSC>;
1235 reset-names = "ufsphy";
1237 #phy-cells = <0>;
1242 cryptobam: dma-controller@1dc4000 {
1243 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
1246 #dma-cells = <1>;
1248 qcom,controlled-remotely;
1249 num-channels = <16>;
1250 qcom,num-ees = <4>;
1259 compatible = "qcom,sm6350-qce", "qcom,sm8150-qce", "qcom,qce";
1262 dma-names = "rx", "tx";
1270 interconnect-names = "memory";
1274 compatible = "qcom,sm6350-ipa";
1281 reg-names = "ipa-reg",
1282 "ipa-shared",
1285 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1286 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1289 interrupt-names = "ipa",
1291 "ipa-clock-query",
1292 "ipa-setup-ready";
1295 clock-names = "core";
1300 interconnect-names = "memory", "imem", "config";
1302 qcom,smem-states = <&ipa_smp2p_out 0>,
1304 qcom,smem-state-names = "ipa-clock-enabled-valid",
1305 "ipa-clock-enabled";
1311 compatible = "qcom,tcsr-mutex";
1313 #hwlock-cells = <1>;
1317 compatible = "qcom,sm6350-adsp-pas";
1320 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
1325 interrupt-names = "wdog", "fatal", "ready",
1326 "handover", "stop-ack";
1329 clock-names = "xo";
1331 power-domains = <&rpmhpd SM6350_LCX>,
1333 power-domain-names = "lcx", "lmx";
1335 memory-region = <&pil_adsp_mem>;
1339 qcom,smem-states = <&smp2p_adsp_out 0>;
1340 qcom,smem-state-names = "stop";
1344 glink-edge {
1345 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
1352 qcom,remote-pid = <2>;
1355 compatible = "qcom,apr-v2";
1356 qcom,glink-channels = "apr_audio_svc";
1358 #address-cells = <1>;
1359 #size-cells = <0>;
1364 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
1370 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
1373 compatible = "qcom,q6afe-dais";
1374 #address-cells = <1>;
1375 #size-cells = <0>;
1376 #sound-dai-cells = <1>;
1379 q6afecc: clock-controller {
1380 compatible = "qcom,q6afe-clocks";
1381 #clock-cells = <2>;
1387 #sound-dai-cells = <1>;
1388 qcom,usb-audio-intr-idx = /bits/ 16 <2>;
1395 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
1398 compatible = "qcom,q6asm-dais";
1399 #address-cells = <1>;
1400 #size-cells = <0>;
1401 #sound-dai-cells = <1>;
1409 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
1412 compatible = "qcom,q6adm-routing";
1413 #sound-dai-cells = <0>;
1420 qcom,glink-channels = "fastrpcglink-apps-dsp";
1422 qcom,non-secure-domain;
1423 #address-cells = <1>;
1424 #size-cells = <0>;
1426 compute-cb@3 {
1427 compatible = "qcom,fastrpc-compute-cb";
1432 compute-cb@4 {
1433 compatible = "qcom,fastrpc-compute-cb";
1438 compute-cb@5 {
1439 compatible = "qcom,fastrpc-compute-cb";
1449 compatible = "qcom,adreno-619.0", "qcom,adreno";
1452 reg-names = "kgsl_3d0_reg_memory",
1457 operating-points-v2 = <&gpu_opp_table>;
1459 nvmem-cells = <&gpu_speed_bin>;
1460 nvmem-cell-names = "speed_bin";
1461 #cooling-cells = <2>;
1465 gpu_zap_shader: zap-shader {
1466 memory-region = <&pil_gpu_mem>;
1469 gpu_opp_table: opp-table {
1470 compatible = "operating-points-v2";
1472 opp-850000000 {
1473 opp-hz = /bits/ 64 <850000000>;
1474 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1475 opp-supported-hw = <0x03>;
1478 opp-800000000 {
1479 opp-hz = /bits/ 64 <800000000>;
1480 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1481 opp-supported-hw = <0x07>;
1484 opp-650000000 {
1485 opp-hz = /bits/ 64 <650000000>;
1486 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1487 opp-supported-hw = <0x0f>;
1490 opp-565000000 {
1491 opp-hz = /bits/ 64 <565000000>;
1492 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1493 opp-supported-hw = <0x1f>;
1496 opp-430000000 {
1497 opp-hz = /bits/ 64 <430000000>;
1498 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1499 opp-supported-hw = <0x1f>;
1502 opp-355000000 {
1503 opp-hz = /bits/ 64 <355000000>;
1504 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1505 opp-supported-hw = <0x1f>;
1508 opp-253000000 {
1509 opp-hz = /bits/ 64 <253000000>;
1510 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1511 opp-supported-hw = <0x1f>;
1517 compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
1519 #iommu-cells = <1>;
1520 #global-interrupts = <2>;
1535 clock-names = "ahb",
1539 power-domains = <&gpucc GPU_CX_GDSC>;
1543 compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu";
1547 reg-names = "gmu",
1553 interrupt-names = "hfi",
1561 clock-names = "ahb",
1567 power-domains = <&gpucc GPU_CX_GDSC>,
1569 power-domain-names = "cx",
1574 operating-points-v2 = <&gmu_opp_table>;
1576 gmu_opp_table: opp-table {
1577 compatible = "operating-points-v2";
1579 opp-200000000 {
1580 opp-hz = /bits/ 64 <200000000>;
1581 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1586 gpucc: clock-controller@3d90000 {
1587 compatible = "qcom,sm6350-gpucc";
1592 clock-names = "bi_tcxo",
1595 #clock-cells = <1>;
1596 #reset-cells = <1>;
1597 #power-domain-cells = <1>;
1601 compatible = "qcom,sm6350-mpss-pas";
1604 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
1610 interrupt-names = "wdog", "fatal", "ready", "handover",
1611 "stop-ack", "shutdown-ack";
1614 clock-names = "xo";
1616 power-domains = <&rpmhpd SM6350_CX>,
1618 power-domain-names = "cx", "mss";
1620 memory-region = <&pil_modem_mem>;
1624 qcom,smem-states = <&modem_smp2p_out 0>;
1625 qcom,smem-state-names = "stop";
1629 glink-edge {
1630 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
1636 qcom,remote-pid = <1>;
1641 compatible = "qcom,sm6350-cdsp-pas";
1644 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
1649 interrupt-names = "wdog", "fatal", "ready",
1650 "handover", "stop-ack";
1653 clock-names = "xo";
1655 power-domains = <&rpmhpd SM6350_CX>,
1657 power-domain-names = "cx", "mx";
1659 memory-region = <&pil_cdsp_mem>;
1663 qcom,smem-states = <&smp2p_cdsp_out 0>;
1664 qcom,smem-state-names = "stop";
1668 glink-edge {
1669 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
1676 qcom,remote-pid = <5>;
1680 qcom,glink-channels = "fastrpcglink-apps-dsp";
1682 qcom,non-secure-domain;
1683 #address-cells = <1>;
1684 #size-cells = <0>;
1686 compute-cb@1 {
1687 compatible = "qcom,fastrpc-compute-cb";
1692 compute-cb@2 {
1693 compatible = "qcom,fastrpc-compute-cb";
1698 compute-cb@3 {
1699 compatible = "qcom,fastrpc-compute-cb";
1704 compute-cb@4 {
1705 compatible = "qcom,fastrpc-compute-cb";
1710 compute-cb@5 {
1711 compatible = "qcom,fastrpc-compute-cb";
1716 compute-cb@6 {
1717 compatible = "qcom,fastrpc-compute-cb";
1722 compute-cb@7 {
1723 compatible = "qcom,fastrpc-compute-cb";
1728 compute-cb@8 {
1729 compatible = "qcom,fastrpc-compute-cb";
1740 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
1745 interrupt-names = "hc_irq", "pwr_irq";
1751 clock-names = "iface", "core", "xo";
1755 interconnect-names = "sdhc-ddr", "cpu-sdhc";
1757 pinctrl-0 = <&sdc2_on_state>;
1758 pinctrl-1 = <&sdc2_off_state>;
1759 pinctrl-names = "default", "sleep";
1761 qcom,dll-config = <0x0007642c>;
1762 qcom,ddr-config = <0x80040868>;
1763 power-domains = <&rpmhpd SM6350_CX>;
1764 operating-points-v2 = <&sdhc2_opp_table>;
1765 bus-width = <4>;
1769 sdhc2_opp_table: opp-table {
1770 compatible = "operating-points-v2";
1772 opp-100000000 {
1773 opp-hz = /bits/ 64 <100000000>;
1774 required-opps = <&rpmhpd_opp_svs_l1>;
1775 opp-peak-kBps = <790000 131000>;
1776 opp-avg-kBps = <50000 50000>;
1779 opp-202000000 {
1780 opp-hz = /bits/ 64 <202000000>;
1781 required-opps = <&rpmhpd_opp_nom>;
1782 opp-peak-kBps = <3190000 294000>;
1783 opp-avg-kBps = <261438 300000>;
1789 compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy";
1792 #phy-cells = <0>;
1795 clock-names = "cfg_ahb", "ref";
1801 compatible = "qcom,sm6350-refgen-regulator",
1802 "qcom,sm8250-refgen-regulator";
1807 compatible = "qcom,sm6350-qmp-usb3-dp-phy";
1814 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
1816 power-domains = <&gcc USB30_PRIM_GDSC>;
1820 reset-names = "phy", "common";
1822 orientation-switch;
1824 #clock-cells = <1>;
1825 #phy-cells = <1>;
1830 #address-cells = <1>;
1831 #size-cells = <0>;
1844 remote-endpoint = <&usb_1_dwc3_ss_out>;
1858 compatible = "qcom,sm6350-dc-noc";
1860 #interconnect-cells = <2>;
1861 qcom,bcm-voters = <&apps_bcm_voter>;
1864 system-cache-controller@9200000 {
1865 compatible = "qcom,sm6350-llcc";
1867 reg-names = "llcc0_base", "llcc_broadcast_base";
1871 compatible = "qcom,sm6350-gem-noc";
1873 #interconnect-cells = <2>;
1874 qcom,bcm-voters = <&apps_bcm_voter>;
1878 compatible = "qcom,sm6350-npu-noc";
1880 #interconnect-cells = <2>;
1881 qcom,bcm-voters = <&apps_bcm_voter>;
1885 compatible = "qcom,sm6350-llcc-bwmon", "qcom,sdm845-bwmon";
1889 operating-points-v2 = <&llcc_bwmon_opp_table>;
1893 llcc_bwmon_opp_table: opp-table {
1894 compatible = "operating-points-v2";
1896 opp-0 {
1897 opp-peak-kBps = <2288000>;
1900 opp-1 {
1901 opp-peak-kBps = <4577000>;
1904 opp-2 {
1905 opp-peak-kBps = <7110000>;
1908 opp-3 {
1909 opp-peak-kBps = <9155000>;
1912 opp-4 {
1913 opp-peak-kBps = <12298000>;
1916 opp-5 {
1917 opp-peak-kBps = <14236000>;
1924 compatible = "qcom,sm6350-cpu-bwmon", "qcom,sc7280-llcc-bwmon";
1928 operating-points-v2 = <&cpu_bwmon_opp_table>;
1932 cpu_bwmon_opp_table: opp-table {
1933 compatible = "operating-points-v2";
1935 opp-0 {
1936 opp-peak-kBps = <762000>;
1939 opp-1 {
1940 opp-peak-kBps = <1144000>;
1943 opp-2 {
1944 opp-peak-kBps = <1720000>;
1947 opp-3 {
1948 opp-peak-kBps = <2086000>;
1951 opp-4 {
1952 opp-peak-kBps = <2597000>;
1955 opp-5 {
1956 opp-peak-kBps = <2929000>;
1959 opp-6 {
1960 opp-peak-kBps = <3879000>;
1963 opp-7 {
1964 opp-peak-kBps = <5161000>;
1967 opp-8 {
1968 opp-peak-kBps = <5931000>;
1971 opp-9 {
1972 opp-peak-kBps = <6881000>;
1975 opp-10 {
1976 opp-peak-kBps = <7980000>;
1982 compatible = "qcom,sm6350-dwc3", "qcom,dwc3";
1985 #address-cells = <2>;
1986 #size-cells = <2>;
1994 clock-names = "cfg_noc",
2000 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
2001 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2002 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
2003 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
2004 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
2005 interrupt-names = "pwr_event",
2011 power-domains = <&gcc USB30_PRIM_GDSC>;
2017 interconnect-names = "usb-ddr", "apps-usb";
2024 num-hc-interrupters = /bits/ 16 <3>;
2027 snps,has-lpm-erratum;
2028 snps,hird-threshold = /bits/ 8 <0x10>;
2029 snps,parkmode-disable-ss-quirk;
2030 snps,dis-u1-entry-quirk;
2031 snps,dis-u2-entry-quirk;
2033 phy-names = "usb2-phy", "usb3-phy";
2034 usb-role-switch;
2037 #address-cells = <1>;
2038 #size-cells = <0>;
2051 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
2058 videocc: clock-controller@aaf0000 {
2059 compatible = "qcom,sm6350-videocc";
2064 clock-names = "iface",
2067 #clock-cells = <1>;
2068 #reset-cells = <1>;
2069 #power-domain-cells = <1>;
2073 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci";
2076 power-domains = <&camcc TITAN_TOP_GDSC>;
2084 clock-names = "camnoc_axi",
2091 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
2093 assigned-clock-rates = <80000000>, <37500000>;
2095 pinctrl-0 = <&cci0_default &cci1_default>;
2096 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
2097 pinctrl-names = "default", "sleep";
2099 #address-cells = <1>;
2100 #size-cells = <0>;
2104 cci0_i2c0: i2c-bus@0 {
2106 clock-frequency = <1000000>;
2107 #address-cells = <1>;
2108 #size-cells = <0>;
2111 cci0_i2c1: i2c-bus@1 {
2113 clock-frequency = <1000000>;
2114 #address-cells = <1>;
2115 #size-cells = <0>;
2120 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci";
2123 power-domains = <&camcc TITAN_TOP_GDSC>;
2131 clock-names = "camnoc_axi",
2138 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
2140 assigned-clock-rates = <80000000>, <37500000>;
2142 pinctrl-0 = <&cci2_default>;
2143 pinctrl-1 = <&cci2_sleep>;
2144 pinctrl-names = "default", "sleep";
2146 #address-cells = <1>;
2147 #size-cells = <0>;
2151 cci1_i2c0: i2c-bus@0 {
2153 clock-frequency = <1000000>;
2154 #address-cells = <1>;
2155 #size-cells = <0>;
2161 camcc: clock-controller@ad00000 {
2162 compatible = "qcom,sm6350-camcc";
2165 #clock-cells = <1>;
2166 #reset-cells = <1>;
2167 #power-domain-cells = <1>;
2170 mdss: display-subsystem@ae00000 {
2171 compatible = "qcom,sm6350-mdss";
2173 reg-names = "mdss";
2176 interrupt-controller;
2177 #interrupt-cells = <1>;
2183 interconnect-names = "mdp0-mem",
2184 "cpu-cfg";
2189 clock-names = "iface",
2193 power-domains = <&dispcc MDSS_GDSC>;
2198 #address-cells = <2>;
2199 #size-cells = <2>;
2204 mdss_mdp: display-controller@ae01000 {
2205 compatible = "qcom,sm6350-dpu";
2208 reg-names = "mdp", "vbif";
2210 interrupt-parent = <&mdss>;
2219 clock-names = "bus",
2226 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2227 assigned-clock-rates = <19200000>;
2229 operating-points-v2 = <&mdp_opp_table>;
2230 power-domains = <&rpmhpd SM6350_CX>;
2233 #address-cells = <1>;
2234 #size-cells = <0>;
2240 remote-endpoint = <&mdss_dsi0_in>;
2248 remote-endpoint = <&mdss_dp_in>;
2253 mdp_opp_table: opp-table {
2254 compatible = "operating-points-v2";
2256 opp-19200000 {
2257 opp-hz = /bits/ 64 <19200000>;
2258 required-opps = <&rpmhpd_opp_min_svs>;
2261 opp-200000000 {
2262 opp-hz = /bits/ 64 <200000000>;
2263 required-opps = <&rpmhpd_opp_low_svs>;
2266 opp-300000000 {
2267 opp-hz = /bits/ 64 <300000000>;
2268 required-opps = <&rpmhpd_opp_svs>;
2271 opp-373333333 {
2272 opp-hz = /bits/ 64 <373333333>;
2273 required-opps = <&rpmhpd_opp_svs_l1>;
2276 opp-448000000 {
2277 opp-hz = /bits/ 64 <448000000>;
2278 required-opps = <&rpmhpd_opp_nom>;
2281 opp-560000000 {
2282 opp-hz = /bits/ 64 <560000000>;
2283 required-opps = <&rpmhpd_opp_turbo>;
2288 mdss_dp: displayport-controller@ae90000 {
2289 compatible = "qcom,sm6350-dp", "qcom,sc7180-dp";
2295 interrupt-parent = <&mdss>;
2302 clock-names = "core_iface",
2308 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
2310 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2314 phy-names = "dp";
2316 #sound-dai-cells = <0>;
2318 operating-points-v2 = <&dp_opp_table>;
2319 power-domains = <&rpmhpd SM6350_CX>;
2324 #address-cells = <1>;
2325 #size-cells = <0>;
2331 remote-endpoint = <&dpu_intf0_out>;
2343 dp_opp_table: opp-table {
2344 compatible = "operating-points-v2";
2346 opp-160000000 {
2347 opp-hz = /bits/ 64 <160000000>;
2348 required-opps = <&rpmhpd_opp_low_svs>;
2351 opp-270000000 {
2352 opp-hz = /bits/ 64 <270000000>;
2353 required-opps = <&rpmhpd_opp_svs>;
2356 opp-540000000 {
2357 opp-hz = /bits/ 64 <540000000>;
2358 required-opps = <&rpmhpd_opp_svs_l1>;
2361 opp-810000000 {
2362 opp-hz = /bits/ 64 <810000000>;
2363 required-opps = <&rpmhpd_opp_nom>;
2369 compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2371 reg-names = "dsi_ctrl";
2373 interrupt-parent = <&mdss>;
2382 clock-names = "byte",
2389 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2391 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
2394 operating-points-v2 = <&mdss_dsi_opp_table>;
2395 power-domains = <&rpmhpd SM6350_MX>;
2398 phy-names = "dsi";
2400 refgen-supply = <&refgen>;
2402 #address-cells = <1>;
2403 #size-cells = <0>;
2408 #address-cells = <1>;
2409 #size-cells = <0>;
2415 remote-endpoint = <&dpu_intf1_out>;
2427 mdss_dsi_opp_table: opp-table {
2428 compatible = "operating-points-v2";
2430 opp-187500000 {
2431 opp-hz = /bits/ 64 <187500000>;
2432 required-opps = <&rpmhpd_opp_low_svs>;
2435 opp-300000000 {
2436 opp-hz = /bits/ 64 <300000000>;
2437 required-opps = <&rpmhpd_opp_svs>;
2440 opp-358000000 {
2441 opp-hz = /bits/ 64 <358000000>;
2442 required-opps = <&rpmhpd_opp_svs_l1>;
2448 compatible = "qcom,dsi-phy-10nm";
2452 reg-names = "dsi_phy",
2456 #clock-cells = <1>;
2457 #phy-cells = <0>;
2461 clock-names = "iface", "ref";
2467 dispcc: clock-controller@af00000 {
2468 compatible = "qcom,sm6350-dispcc";
2476 clock-names = "bi_tcxo",
2482 #clock-cells = <1>;
2483 #reset-cells = <1>;
2484 #power-domain-cells = <1>;
2487 pdc: interrupt-controller@b220000 { label
2488 compatible = "qcom,sm6350-pdc", "qcom,pdc";
2490 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
2492 #interrupt-cells = <2>;
2493 interrupt-parent = <&intc>;
2494 interrupt-controller;
2497 tsens0: thermal-sensor@c263000 {
2498 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2";
2502 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
2503 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
2504 interrupt-names = "uplow", "critical";
2505 #thermal-sensor-cells = <1>;
2508 tsens1: thermal-sensor@c265000 {
2509 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2";
2513 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
2514 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
2515 interrupt-names = "uplow", "critical";
2516 #thermal-sensor-cells = <1>;
2519 aoss_qmp: power-management@c300000 {
2520 compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp";
2522 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
2526 #clock-cells = <0>;
2530 compatible = "qcom,rpmh-stats";
2535 compatible = "qcom,spmi-pmic-arb";
2541 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2542 interrupt-names = "periph_irq";
2543 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2546 #address-cells = <2>;
2547 #size-cells = <0>;
2548 interrupt-controller;
2549 #interrupt-cells = <4>;
2553 compatible = "qcom,sm6350-tlmm";
2564 gpio-controller;
2565 #gpio-cells = <2>;
2566 interrupt-controller;
2567 #interrupt-cells = <2>;
2568 gpio-ranges = <&tlmm 0 0 157>;
2569 wakeup-parent = <&pdc>;
2571 cci0_default: cci0-default-state {
2574 drive-strength = <2>;
2575 bias-pull-up;
2578 cci0_sleep: cci0-sleep-state {
2581 drive-strength = <2>;
2582 bias-pull-down;
2585 cci1_default: cci1-default-state {
2588 drive-strength = <2>;
2589 bias-pull-up;
2592 cci1_sleep: cci1-sleep-state {
2595 drive-strength = <2>;
2596 bias-pull-down;
2599 cci2_default: cci2-default-state {
2602 drive-strength = <2>;
2603 bias-pull-up;
2606 cci2_sleep: cci2-sleep-state {
2609 drive-strength = <2>;
2610 bias-pull-down;
2613 sdc2_off_state: sdc2-off-state {
2614 clk-pins {
2616 drive-strength = <2>;
2617 bias-disable;
2620 cmd-pins {
2622 drive-strength = <2>;
2623 bias-pull-up;
2626 data-pins {
2628 drive-strength = <2>;
2629 bias-pull-up;
2633 sdc2_on_state: sdc2-on-state {
2634 clk-pins {
2636 drive-strength = <16>;
2637 bias-disable;
2640 cmd-pins {
2642 drive-strength = <10>;
2643 bias-pull-up;
2646 data-pins {
2648 drive-strength = <10>;
2649 bias-pull-up;
2653 qup_uart9_default: qup-uart9-default-state {
2656 drive-strength = <2>;
2657 bias-disable;
2660 qup_i2c0_default: qup-i2c0-default-state {
2663 drive-strength = <2>;
2664 bias-pull-up;
2667 qup_i2c2_default: qup-i2c2-default-state {
2670 drive-strength = <2>;
2671 bias-pull-up;
2674 qup_i2c6_default: qup-i2c6-default-state {
2677 drive-strength = <2>;
2678 bias-pull-up;
2681 qup_i2c7_default: qup-i2c7-default-state {
2684 drive-strength = <2>;
2685 bias-pull-up;
2688 qup_i2c8_default: qup-i2c8-default-state {
2691 drive-strength = <2>;
2692 bias-pull-up;
2695 qup_i2c10_default: qup-i2c10-default-state {
2698 drive-strength = <2>;
2699 bias-pull-up;
2702 qup_uart1_cts: qup-uart1-cts-default-state {
2705 drive-strength = <2>;
2706 bias-disable;
2709 qup_uart1_rts: qup-uart1-rts-default-state {
2712 drive-strength = <2>;
2713 bias-pull-down;
2716 qup_uart1_rx: qup-uart1-rx-default-state {
2719 drive-strength = <2>;
2720 bias-disable;
2723 qup_uart1_tx: qup-uart1-tx-default-state {
2726 drive-strength = <2>;
2727 bias-pull-up;
2732 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500";
2734 #iommu-cells = <2>;
2735 #global-interrupts = <1>;
2817 dma-coherent;
2820 intc: interrupt-controller@17a00000 { label
2821 compatible = "arm,gic-v3";
2822 #interrupt-cells = <3>;
2823 interrupt-controller;
2830 compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt";
2837 compatible = "arm,armv7-timer-mem";
2839 clock-frequency = <19200000>;
2840 #address-cells = <1>;
2841 #size-cells = <1>;
2845 frame-number = <0>;
2853 frame-number = <1>;
2860 frame-number = <2>;
2867 frame-number = <3>;
2874 frame-number = <4>;
2881 frame-number = <5>;
2888 frame-number = <6>;
2896 compatible = "qcom,rpmh-rsc";
2901 reg-names = "drv-0", "drv-1", "drv-2";
2905 qcom,tcs-offset = <0xd00>;
2906 qcom,drv-id = <2>;
2907 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
2909 power-domains = <&cluster_pd>;
2911 rpmhcc: clock-controller {
2912 compatible = "qcom,sm6350-rpmh-clk";
2913 #clock-cells = <1>;
2914 clock-names = "xo";
2918 rpmhpd: power-controller {
2919 compatible = "qcom,sm6350-rpmhpd";
2920 #power-domain-cells = <1>;
2921 operating-points-v2 = <&rpmhpd_opp_table>;
2923 rpmhpd_opp_table: opp-table {
2924 compatible = "operating-points-v2";
2927 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
2931 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2935 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2939 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2943 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2947 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2951 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2955 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
2959 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2963 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2968 apps_bcm_voter: bcm-voter {
2969 compatible = "qcom,bcm-voter";
2974 compatible = "qcom,sm6350-osm-l3", "qcom,osm-l3";
2978 clock-names = "xo", "alternate";
2980 #interconnect-cells = <1>;
2984 compatible = "qcom,sm6350-cpufreq-hw", "qcom,cpufreq-hw";
2986 reg-names = "freq-domain0", "freq-domain1";
2988 clock-names = "xo", "alternate";
2990 #freq-domain-cells = <1>;
2991 #clock-cells = <1>;
2995 compatible = "qcom,wcn3990-wifi";
2997 reg-names = "membase";
2998 memory-region = <&wlan_fw_mem>;
3012 qcom,msa-fixed-perm;
3020 thermal-zones {
3021 aoss0-thermal {
3022 thermal-sensors = <&tsens0 0>;
3025 aoss0-crit {
3033 aoss1-thermal {
3034 thermal-sensors = <&tsens1 0>;
3037 aoss1-crit {
3045 audio-thermal {
3046 thermal-sensors = <&tsens1 2>;
3049 audio-crit {
3057 camera-thermal {
3058 thermal-sensors = <&tsens1 5>;
3061 camera-crit {
3069 cpu0-thermal {
3070 thermal-sensors = <&tsens0 1>;
3073 cpu0_alert0: trip-point0 {
3079 cpu0-crit {
3086 cooling-maps {
3089 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3094 cpu1-thermal {
3095 thermal-sensors = <&tsens0 2>;
3098 cpu1_alert0: trip-point0 {
3104 cpu1-crit {
3111 cooling-maps {
3114 cooling-device = <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3119 cpu2-thermal {
3120 thermal-sensors = <&tsens0 3>;
3123 cpu2_alert0: trip-point0 {
3129 cpu2-crit {
3136 cooling-maps {
3139 cooling-device = <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3144 cpu3-thermal {
3145 thermal-sensors = <&tsens0 4>;
3148 cpu3_alert0: trip-point0 {
3154 cpu3-crit {
3161 cooling-maps {
3164 cooling-device = <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3169 cpu4-thermal {
3170 thermal-sensors = <&tsens0 5>;
3173 cpu4_alert0: trip-point0 {
3179 cpu4-crit {
3186 cooling-maps {
3189 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3194 cpu5-thermal {
3195 thermal-sensors = <&tsens0 6>;
3198 cpu5_alert0: trip-point0 {
3204 cpu5-crit {
3211 cooling-maps {
3214 cooling-device = <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3219 cpu6-left-thermal {
3220 thermal-sensors = <&tsens0 9>;
3223 cpu6_left_alert0: trip-point0 {
3229 cpu6-left-crit {
3236 cooling-maps {
3239 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3244 cpu6-right-thermal {
3245 thermal-sensors = <&tsens0 10>;
3248 cpu6_right_alert0: trip-point0 {
3254 cpu6-right-crit {
3261 cooling-maps {
3264 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3269 cpu7-left-thermal {
3270 thermal-sensors = <&tsens0 11>;
3273 cpu7_left_alert0: trip-point0 {
3279 cpu7-left-crit {
3286 cooling-maps {
3289 cooling-device = <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3294 cpu7-right-thermal {
3295 thermal-sensors = <&tsens0 12>;
3298 cpu7_right_alert0: trip-point0 {
3304 cpu7-right-crit {
3311 cooling-maps {
3314 cooling-device = <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3319 cpuss0-thermal {
3320 thermal-sensors = <&tsens0 7>;
3323 cpuss0-crit {
3331 cpuss1-thermal {
3332 thermal-sensors = <&tsens0 8>;
3335 cpuss1-crit {
3343 cwlan-thermal {
3344 thermal-sensors = <&tsens1 1>;
3347 cwlan-crit {
3355 ddr-thermal {
3356 thermal-sensors = <&tsens1 3>;
3359 ddr-crit {
3367 gpuss0-thermal {
3368 polling-delay-passive = <250>;
3370 thermal-sensors = <&tsens0 13>;
3373 gpuss0_alert0: trip-point0 {
3379 gpuss0-crit {
3386 cooling-maps {
3389 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3394 gpuss1-thermal {
3395 polling-delay-passive = <250>;
3397 thermal-sensors = <&tsens0 14>;
3400 gpuss1_alert0: trip-point0 {
3406 gpuss1-crit {
3413 cooling-maps {
3416 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3421 modem-core0-thermal {
3422 thermal-sensors = <&tsens1 6>;
3425 modem-core0-crit {
3433 modem-core1-thermal {
3434 thermal-sensors = <&tsens1 7>;
3437 modem-core1-crit {
3445 modem-scl-thermal {
3446 thermal-sensors = <&tsens1 9>;
3449 modem-scl-crit {
3457 modem-vec-thermal {
3458 thermal-sensors = <&tsens1 8>;
3461 modem-vec-crit {
3469 npu-thermal {
3470 thermal-sensors = <&tsens1 10>;
3473 npu-crit {
3481 q6-hvx-thermal {
3482 thermal-sensors = <&tsens1 4>;
3485 q6-hvx-crit {
3493 video-thermal {
3494 thermal-sensors = <&tsens1 11>;
3497 video-crit {
3507 compatible = "arm,armv8-timer";
3508 clock-frequency = <19200000>;