Lines Matching +full:ipa +full:- +full:clock +full:- +full:enabled
1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,dispcc-sm6350.h>
8 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
9 #include <dt-bindings/clock/qcom,gcc-sm6350.h>
10 #include <dt-bindings/clock/qcom,gpucc-sm6350.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/clock/qcom,sm6350-camcc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interconnect/qcom,icc.h>
16 #include <dt-bindings/interconnect/qcom,osm-l3.h>
17 #include <dt-bindings/interconnect/qcom,sm6350.h>
18 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/mailbox/qcom-ipcc.h>
20 #include <dt-bindings/phy/phy-qcom-qmp.h>
21 #include <dt-bindings/power/qcom-rpmpd.h>
22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
23 #include <dt-bindings/thermal/thermal.h>
26 interrupt-parent = <&intc>;
27 #address-cells = <2>;
28 #size-cells = <2>;
31 xo_board: xo-board {
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <76800000>;
35 clock-output-names = "xo_board";
38 sleep_clk: sleep-clk {
39 compatible = "fixed-clock";
40 clock-frequency = <32764>;
41 #clock-cells = <0>;
46 #address-cells = <2>;
47 #size-cells = <0>;
54 enable-method = "psci";
55 capacity-dmips-mhz = <1024>;
56 dynamic-power-coefficient = <100>;
57 next-level-cache = <&l2_0>;
58 qcom,freq-domain = <&cpufreq_hw 0>;
59 operating-points-v2 = <&cpu0_opp_table>;
63 power-domains = <&cpu_pd0>;
64 power-domain-names = "psci";
65 #cooling-cells = <2>;
66 l2_0: l2-cache {
68 cache-level = <2>;
69 cache-unified;
70 next-level-cache = <&l3_0>;
71 l3_0: l3-cache {
73 cache-level = <3>;
74 cache-unified;
84 enable-method = "psci";
85 capacity-dmips-mhz = <1024>;
86 dynamic-power-coefficient = <100>;
87 next-level-cache = <&l2_100>;
88 qcom,freq-domain = <&cpufreq_hw 0>;
89 operating-points-v2 = <&cpu0_opp_table>;
93 power-domains = <&cpu_pd1>;
94 power-domain-names = "psci";
95 #cooling-cells = <2>;
96 l2_100: l2-cache {
98 cache-level = <2>;
99 cache-unified;
100 next-level-cache = <&l3_0>;
109 enable-method = "psci";
110 capacity-dmips-mhz = <1024>;
111 dynamic-power-coefficient = <100>;
112 next-level-cache = <&l2_200>;
113 qcom,freq-domain = <&cpufreq_hw 0>;
114 operating-points-v2 = <&cpu0_opp_table>;
118 power-domains = <&cpu_pd2>;
119 power-domain-names = "psci";
120 #cooling-cells = <2>;
121 l2_200: l2-cache {
123 cache-level = <2>;
124 cache-unified;
125 next-level-cache = <&l3_0>;
134 enable-method = "psci";
135 capacity-dmips-mhz = <1024>;
136 dynamic-power-coefficient = <100>;
137 next-level-cache = <&l2_300>;
138 qcom,freq-domain = <&cpufreq_hw 0>;
139 operating-points-v2 = <&cpu0_opp_table>;
143 power-domains = <&cpu_pd3>;
144 power-domain-names = "psci";
145 #cooling-cells = <2>;
146 l2_300: l2-cache {
148 cache-level = <2>;
149 cache-unified;
150 next-level-cache = <&l3_0>;
159 enable-method = "psci";
160 capacity-dmips-mhz = <1024>;
161 dynamic-power-coefficient = <100>;
162 next-level-cache = <&l2_400>;
163 qcom,freq-domain = <&cpufreq_hw 0>;
164 operating-points-v2 = <&cpu0_opp_table>;
168 power-domains = <&cpu_pd4>;
169 power-domain-names = "psci";
170 #cooling-cells = <2>;
171 l2_400: l2-cache {
173 cache-level = <2>;
174 cache-unified;
175 next-level-cache = <&l3_0>;
184 enable-method = "psci";
185 capacity-dmips-mhz = <1024>;
186 dynamic-power-coefficient = <100>;
187 next-level-cache = <&l2_500>;
188 qcom,freq-domain = <&cpufreq_hw 0>;
189 operating-points-v2 = <&cpu0_opp_table>;
193 power-domains = <&cpu_pd5>;
194 power-domain-names = "psci";
195 #cooling-cells = <2>;
196 l2_500: l2-cache {
198 cache-level = <2>;
199 cache-unified;
200 next-level-cache = <&l3_0>;
209 enable-method = "psci";
210 capacity-dmips-mhz = <1894>;
211 dynamic-power-coefficient = <703>;
212 next-level-cache = <&l2_600>;
213 qcom,freq-domain = <&cpufreq_hw 1>;
214 operating-points-v2 = <&cpu6_opp_table>;
218 power-domains = <&cpu_pd6>;
219 power-domain-names = "psci";
220 #cooling-cells = <2>;
221 l2_600: l2-cache {
223 cache-level = <2>;
224 cache-unified;
225 next-level-cache = <&l3_0>;
234 enable-method = "psci";
235 capacity-dmips-mhz = <1894>;
236 dynamic-power-coefficient = <703>;
237 next-level-cache = <&l2_700>;
238 qcom,freq-domain = <&cpufreq_hw 1>;
239 operating-points-v2 = <&cpu6_opp_table>;
243 power-domains = <&cpu_pd7>;
244 power-domain-names = "psci";
245 #cooling-cells = <2>;
246 l2_700: l2-cache {
248 cache-level = <2>;
249 cache-unified;
250 next-level-cache = <&l3_0>;
254 cpu-map {
290 domain-idle-states {
291 cluster_sleep_pc: cluster-sleep-0 {
292 compatible = "domain-idle-state";
293 arm,psci-suspend-param = <0x41000044>;
294 entry-latency-us = <2752>;
295 exit-latency-us = <3048>;
296 min-residency-us = <6118>;
299 cluster_sleep_cx_ret: cluster-sleep-1 {
300 compatible = "domain-idle-state";
301 arm,psci-suspend-param = <0x41001244>;
302 entry-latency-us = <3638>;
303 exit-latency-us = <4562>;
304 min-residency-us = <8467>;
307 cluster_aoss_sleep: cluster-sleep-2 {
308 compatible = "domain-idle-state";
309 arm,psci-suspend-param = <0x4100b244>;
310 entry-latency-us = <3263>;
311 exit-latency-us = <6562>;
312 min-residency-us = <9987>;
316 cpu_idle_states: idle-states {
317 entry-method = "psci";
319 little_cpu_sleep_0: cpu-sleep-0-0 {
320 compatible = "arm,idle-state";
321 idle-state-name = "little-power-collapse";
322 arm,psci-suspend-param = <0x40000003>;
323 entry-latency-us = <549>;
324 exit-latency-us = <901>;
325 min-residency-us = <1774>;
326 local-timer-stop;
329 little_cpu_sleep_1: cpu-sleep-0-1 {
330 compatible = "arm,idle-state";
331 idle-state-name = "little-rail-power-collapse";
332 arm,psci-suspend-param = <0x40000004>;
333 entry-latency-us = <702>;
334 exit-latency-us = <915>;
335 min-residency-us = <4001>;
336 local-timer-stop;
339 big_cpu_sleep_0: cpu-sleep-1-0 {
340 compatible = "arm,idle-state";
341 idle-state-name = "big-power-collapse";
342 arm,psci-suspend-param = <0x40000003>;
343 entry-latency-us = <523>;
344 exit-latency-us = <1244>;
345 min-residency-us = <2207>;
346 local-timer-stop;
349 big_cpu_sleep_1: cpu-sleep-1-1 {
350 compatible = "arm,idle-state";
351 idle-state-name = "big-rail-power-collapse";
352 arm,psci-suspend-param = <0x40000004>;
353 entry-latency-us = <526>;
354 exit-latency-us = <1854>;
355 min-residency-us = <5555>;
356 local-timer-stop;
363 compatible = "qcom,scm-sm6350", "qcom,scm";
364 #reset-cells = <1>;
374 cpu0_opp_table: opp-table-cpu0 {
375 compatible = "operating-points-v2";
376 opp-shared;
378 opp-300000000 {
379 opp-hz = /bits/ 64 <300000000>;
380 /* DDR: 4-wide, 2 channels, double data rate, L3: 16-wide, 2 channels */
381 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>;
384 opp-576000000 {
385 opp-hz = /bits/ 64 <576000000>;
386 opp-peak-kBps = <(547000 * 4 * 2 * 2) (556800 * 16 * 2)>;
389 opp-768000000 {
390 opp-hz = /bits/ 64 <768000000>;
391 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>;
394 opp-1017600000 {
395 opp-hz = /bits/ 64 <1017600000>;
396 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>;
399 opp-1248000000 {
400 opp-hz = /bits/ 64 <1248000000>;
401 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>;
404 opp-1324800000 {
405 opp-hz = /bits/ 64 <1324800000>;
406 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1286400 * 16 * 2)>;
409 opp-1516800000 {
410 opp-hz = /bits/ 64 <1516800000>;
411 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
414 opp-1612800000 {
415 opp-hz = /bits/ 64 <1612800000>;
416 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
419 opp-1708800000 {
420 opp-hz = /bits/ 64 <1708800000>;
421 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
425 cpu6_opp_table: opp-table-cpu6 {
426 compatible = "operating-points-v2";
427 opp-shared;
429 opp-300000000 {
430 opp-hz = /bits/ 64 <300000000>;
431 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>;
434 opp-787200000 {
435 opp-hz = /bits/ 64 <787200000>;
436 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>;
439 opp-979200000 {
440 opp-hz = /bits/ 64 <979200000>;
441 opp-peak-kBps = <(768000 * 4 * 2 * 2) (940800 * 16 * 2)>;
444 opp-1036800000 {
445 opp-hz = /bits/ 64 <1036800000>;
446 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>;
449 opp-1248000000 {
450 opp-hz = /bits/ 64 <1248000000>;
451 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>;
454 opp-1401600000 {
455 opp-hz = /bits/ 64 <1401600000>;
456 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1401600 * 16 * 2)>;
459 opp-1555200000 {
460 opp-hz = /bits/ 64 <1555200000>;
461 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
464 opp-1766400000 {
465 opp-hz = /bits/ 64 <1766400000>;
466 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
469 opp-1900800000 {
470 opp-hz = /bits/ 64 <1900800000>;
471 opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
474 opp-2073600000 {
475 opp-hz = /bits/ 64 <2073600000>;
476 opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
480 qup_opp_table: opp-table-qup {
481 compatible = "operating-points-v2";
483 opp-75000000 {
484 opp-hz = /bits/ 64 <75000000>;
485 required-opps = <&rpmhpd_opp_low_svs>;
488 opp-100000000 {
489 opp-hz = /bits/ 64 <100000000>;
490 required-opps = <&rpmhpd_opp_svs>;
493 opp-128000000 {
494 opp-hz = /bits/ 64 <128000000>;
495 required-opps = <&rpmhpd_opp_nom>;
500 compatible = "arm,armv8-pmuv3";
505 compatible = "arm,psci-1.0";
508 cpu_pd0: power-domain-cpu0 {
509 #power-domain-cells = <0>;
510 power-domains = <&cluster_pd>;
511 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
514 cpu_pd1: power-domain-cpu1 {
515 #power-domain-cells = <0>;
516 power-domains = <&cluster_pd>;
517 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
520 cpu_pd2: power-domain-cpu2 {
521 #power-domain-cells = <0>;
522 power-domains = <&cluster_pd>;
523 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
526 cpu_pd3: power-domain-cpu3 {
527 #power-domain-cells = <0>;
528 power-domains = <&cluster_pd>;
529 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
532 cpu_pd4: power-domain-cpu4 {
533 #power-domain-cells = <0>;
534 power-domains = <&cluster_pd>;
535 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
538 cpu_pd5: power-domain-cpu5 {
539 #power-domain-cells = <0>;
540 power-domains = <&cluster_pd>;
541 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
544 cpu_pd6: power-domain-cpu6 {
545 #power-domain-cells = <0>;
546 power-domains = <&cluster_pd>;
547 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
550 cpu_pd7: power-domain-cpu7 {
551 #power-domain-cells = <0>;
552 power-domains = <&cluster_pd>;
553 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
556 cluster_pd: power-domain-cpu-cluster0 {
557 #power-domain-cells = <0>;
558 domain-idle-states = <&cluster_sleep_pc
564 reserved_memory: reserved-memory {
565 #address-cells = <2>;
566 #size-cells = <2>;
571 no-map;
576 no-map;
580 compatible = "qcom,cmd-db";
582 no-map;
587 no-map;
592 no-map;
597 no-map;
602 no-map;
607 no-map;
612 no-map;
617 no-map;
622 no-map;
627 no-map;
632 no-map;
637 no-map;
642 no-map;
647 no-map;
652 no-map;
657 no-map;
662 no-map;
667 no-map;
672 no-map;
678 record-size = <0x1000>;
679 console-size = <0x40000>;
680 pmsg-size = <0x20000>;
681 ecc-size = <16>;
682 no-map;
687 no-map;
693 memory-region = <&smem_mem>;
697 smp2p-adsp {
700 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
706 qcom,local-pid = <0>;
707 qcom,remote-pid = <2>;
709 smp2p_adsp_out: master-kernel {
710 qcom,entry-name = "master-kernel";
711 #qcom,smem-state-cells = <1>;
714 smp2p_adsp_in: slave-kernel {
715 qcom,entry-name = "slave-kernel";
716 interrupt-controller;
717 #interrupt-cells = <2>;
721 smp2p-cdsp {
724 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
730 qcom,local-pid = <0>;
731 qcom,remote-pid = <5>;
733 smp2p_cdsp_out: master-kernel {
734 qcom,entry-name = "master-kernel";
735 #qcom,smem-state-cells = <1>;
738 smp2p_cdsp_in: slave-kernel {
739 qcom,entry-name = "slave-kernel";
740 interrupt-controller;
741 #interrupt-cells = <2>;
745 smp2p-mpss {
749 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
755 qcom,local-pid = <0>;
756 qcom,remote-pid = <1>;
758 modem_smp2p_out: master-kernel {
759 qcom,entry-name = "master-kernel";
760 #qcom,smem-state-cells = <1>;
763 modem_smp2p_in: slave-kernel {
764 qcom,entry-name = "slave-kernel";
765 interrupt-controller;
766 #interrupt-cells = <2>;
769 ipa_smp2p_out: ipa-ap-to-modem {
770 qcom,entry-name = "ipa";
771 #qcom,smem-state-cells = <1>;
774 ipa_smp2p_in: ipa-modem-to-ap {
775 qcom,entry-name = "ipa";
776 interrupt-controller;
777 #interrupt-cells = <2>;
782 #address-cells = <2>;
783 #size-cells = <2>;
785 dma-ranges = <0 0 0 0 0x10 0>;
786 compatible = "simple-bus";
788 gcc: clock-controller@100000 {
789 compatible = "qcom,gcc-sm6350";
791 #clock-cells = <1>;
792 #reset-cells = <1>;
793 #power-domain-cells = <1>;
794 clock-names = "bi_tcxo",
803 compatible = "qcom,sm6350-ipcc", "qcom,ipcc";
806 interrupt-controller;
807 #interrupt-cells = <3>;
808 #mbox-cells = <2>;
812 compatible = "qcom,sm6350-qfprom", "qcom,qfprom";
814 #address-cells = <1>;
815 #size-cells = <1>;
817 gpu_speed_bin: gpu-speed-bin@2015 {
824 compatible = "qcom,prng-ee";
827 clock-names = "core";
831 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
835 reg-names = "hc", "cqhci", "ice";
839 interrupt-names = "hc_irq", "pwr_irq";
845 clock-names = "iface", "core", "xo";
847 qcom,dll-config = <0x000f642c>;
848 qcom,ddr-config = <0x80040868>;
849 power-domains = <&rpmhpd SM6350_CX>;
850 operating-points-v2 = <&sdhc1_opp_table>;
851 bus-width = <8>;
852 non-removable;
853 supports-cqe;
857 sdhc1_opp_table: opp-table {
858 compatible = "operating-points-v2";
860 opp-19200000 {
861 opp-hz = /bits/ 64 <19200000>;
862 required-opps = <&rpmhpd_opp_min_svs>;
865 opp-100000000 {
866 opp-hz = /bits/ 64 <100000000>;
867 required-opps = <&rpmhpd_opp_low_svs>;
870 opp-384000000 {
871 opp-hz = /bits/ 64 <384000000>;
872 required-opps = <&rpmhpd_opp_svs_l1>;
877 gpi_dma0: dma-controller@800000 {
878 compatible = "qcom,sm6350-gpi-dma";
890 dma-channels = <10>;
891 dma-channel-mask = <0x1f>;
893 #dma-cells = <3>;
898 compatible = "qcom,geni-se-qup";
900 clock-names = "m-ahb", "s-ahb";
903 #address-cells = <2>;
904 #size-cells = <2>;
910 compatible = "qcom,geni-i2c";
912 clock-names = "se";
914 pinctrl-names = "default";
915 pinctrl-0 = <&qup_i2c0_default>;
919 dma-names = "tx", "rx";
920 #address-cells = <1>;
921 #size-cells = <0>;
925 interconnect-names = "qup-core", "qup-config", "qup-memory";
930 compatible = "qcom,geni-uart";
932 clock-names = "se";
934 pinctrl-names = "default";
935 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
937 power-domains = <&rpmhpd SM6350_CX>;
938 operating-points-v2 = <&qup_opp_table>;
941 interconnect-names = "qup-core", "qup-config";
946 compatible = "qcom,geni-i2c";
948 clock-names = "se";
950 pinctrl-names = "default";
951 pinctrl-0 = <&qup_i2c2_default>;
955 dma-names = "tx", "rx";
956 #address-cells = <1>;
957 #size-cells = <0>;
961 interconnect-names = "qup-core", "qup-config", "qup-memory";
966 gpi_dma1: dma-controller@900000 {
967 compatible = "qcom,sm6350-gpi-dma";
979 dma-channels = <10>;
980 dma-channel-mask = <0x3f>;
982 #dma-cells = <3>;
987 compatible = "qcom,geni-se-qup";
989 clock-names = "m-ahb", "s-ahb";
992 #address-cells = <2>;
993 #size-cells = <2>;
999 compatible = "qcom,geni-i2c";
1001 clock-names = "se";
1003 pinctrl-names = "default";
1004 pinctrl-0 = <&qup_i2c6_default>;
1008 dma-names = "tx", "rx";
1009 #address-cells = <1>;
1010 #size-cells = <0>;
1014 interconnect-names = "qup-core", "qup-config", "qup-memory";
1019 compatible = "qcom,geni-i2c";
1021 clock-names = "se";
1023 pinctrl-names = "default";
1024 pinctrl-0 = <&qup_i2c7_default>;
1028 dma-names = "tx", "rx";
1029 #address-cells = <1>;
1030 #size-cells = <0>;
1034 interconnect-names = "qup-core", "qup-config", "qup-memory";
1039 compatible = "qcom,geni-i2c";
1041 clock-names = "se";
1043 pinctrl-names = "default";
1044 pinctrl-0 = <&qup_i2c8_default>;
1048 dma-names = "tx", "rx";
1049 #address-cells = <1>;
1050 #size-cells = <0>;
1054 interconnect-names = "qup-core", "qup-config", "qup-memory";
1059 compatible = "qcom,geni-debug-uart";
1061 clock-names = "se";
1063 pinctrl-names = "default";
1064 pinctrl-0 = <&qup_uart9_default>;
1068 interconnect-names = "qup-core", "qup-config";
1073 compatible = "qcom,geni-i2c";
1075 clock-names = "se";
1077 pinctrl-names = "default";
1078 pinctrl-0 = <&qup_i2c10_default>;
1082 dma-names = "tx", "rx";
1083 #address-cells = <1>;
1084 #size-cells = <0>;
1088 interconnect-names = "qup-core", "qup-config", "qup-memory";
1094 compatible = "qcom,sm6350-config-noc";
1096 #interconnect-cells = <2>;
1097 qcom,bcm-voters = <&apps_bcm_voter>;
1101 compatible = "qcom,sm6350-system-noc";
1103 #interconnect-cells = <2>;
1104 qcom,bcm-voters = <&apps_bcm_voter>;
1106 clk_virt: interconnect-clk-virt {
1107 compatible = "qcom,sm6350-clk-virt";
1108 #interconnect-cells = <2>;
1109 qcom,bcm-voters = <&apps_bcm_voter>;
1114 compatible = "qcom,sm6350-aggre1-noc";
1116 #interconnect-cells = <2>;
1117 qcom,bcm-voters = <&apps_bcm_voter>;
1121 compatible = "qcom,sm6350-aggre2-noc";
1123 #interconnect-cells = <2>;
1124 qcom,bcm-voters = <&apps_bcm_voter>;
1126 compute_noc: interconnect-compute-noc {
1127 compatible = "qcom,sm6350-compute-noc";
1128 #interconnect-cells = <2>;
1129 qcom,bcm-voters = <&apps_bcm_voter>;
1134 compatible = "qcom,sm6350-mmss-noc";
1136 #interconnect-cells = <2>;
1137 qcom,bcm-voters = <&apps_bcm_voter>;
1141 compatible = "qcom,sm6350-ufshc", "qcom,ufshc",
1142 "jedec,ufs-2.0";
1145 reg-names = "std", "ice";
1148 phy-names = "ufsphy";
1149 lanes-per-direction = <2>;
1150 #reset-cells = <1>;
1152 reset-names = "rst";
1154 power-domains = <&gcc UFS_PHY_GDSC>;
1158 clock-names = "core_clk",
1176 freq-table-hz =
1191 compatible = "qcom,sm6350-qmp-ufs-phy";
1197 clock-names = "ref",
1201 power-domains = <&gcc UFS_PHY_GDSC>;
1204 reset-names = "ufsphy";
1206 #phy-cells = <0>;
1211 cryptobam: dma-controller@1dc4000 {
1212 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
1215 #dma-cells = <1>;
1217 qcom,controlled-remotely;
1218 num-channels = <16>;
1219 qcom,num-ees = <4>;
1228 compatible = "qcom,sm6350-qce", "qcom,sm8150-qce", "qcom,qce";
1231 dma-names = "rx", "tx";
1239 interconnect-names = "memory";
1242 ipa: ipa@1e40000 { label
1243 compatible = "qcom,sm6350-ipa";
1250 reg-names = "ipa-reg",
1251 "ipa-shared",
1254 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1258 interrupt-names = "ipa",
1260 "ipa-clock-query",
1261 "ipa-setup-ready";
1264 clock-names = "core";
1269 interconnect-names = "memory", "imem", "config";
1271 qcom,smem-states = <&ipa_smp2p_out 0>,
1273 qcom,smem-state-names = "ipa-clock-enabled-valid",
1274 "ipa-clock-enabled";
1280 compatible = "qcom,tcsr-mutex";
1282 #hwlock-cells = <1>;
1286 compatible = "qcom,sm6350-adsp-pas";
1289 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
1294 interrupt-names = "wdog", "fatal", "ready",
1295 "handover", "stop-ack";
1298 clock-names = "xo";
1300 power-domains = <&rpmhpd SM6350_LCX>,
1302 power-domain-names = "lcx", "lmx";
1304 memory-region = <&pil_adsp_mem>;
1308 qcom,smem-states = <&smp2p_adsp_out 0>;
1309 qcom,smem-state-names = "stop";
1313 glink-edge {
1314 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
1321 qcom,remote-pid = <2>;
1325 qcom,glink-channels = "fastrpcglink-apps-dsp";
1327 qcom,non-secure-domain;
1328 #address-cells = <1>;
1329 #size-cells = <0>;
1331 compute-cb@3 {
1332 compatible = "qcom,fastrpc-compute-cb";
1337 compute-cb@4 {
1338 compatible = "qcom,fastrpc-compute-cb";
1343 compute-cb@5 {
1344 compatible = "qcom,fastrpc-compute-cb";
1354 compatible = "qcom,adreno-619.0", "qcom,adreno";
1357 reg-names = "kgsl_3d0_reg_memory",
1362 operating-points-v2 = <&gpu_opp_table>;
1364 nvmem-cells = <&gpu_speed_bin>;
1365 nvmem-cell-names = "speed_bin";
1366 #cooling-cells = <2>;
1370 gpu_zap_shader: zap-shader {
1371 memory-region = <&pil_gpu_mem>;
1374 gpu_opp_table: opp-table {
1375 compatible = "operating-points-v2";
1377 opp-850000000 {
1378 opp-hz = /bits/ 64 <850000000>;
1379 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1380 opp-supported-hw = <0x03>;
1383 opp-800000000 {
1384 opp-hz = /bits/ 64 <800000000>;
1385 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1386 opp-supported-hw = <0x07>;
1389 opp-650000000 {
1390 opp-hz = /bits/ 64 <650000000>;
1391 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1392 opp-supported-hw = <0x0f>;
1395 opp-565000000 {
1396 opp-hz = /bits/ 64 <565000000>;
1397 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1398 opp-supported-hw = <0x1f>;
1401 opp-430000000 {
1402 opp-hz = /bits/ 64 <430000000>;
1403 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1404 opp-supported-hw = <0x1f>;
1407 opp-355000000 {
1408 opp-hz = /bits/ 64 <355000000>;
1409 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1410 opp-supported-hw = <0x1f>;
1413 opp-253000000 {
1414 opp-hz = /bits/ 64 <253000000>;
1415 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1416 opp-supported-hw = <0x1f>;
1422 compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
1424 #iommu-cells = <1>;
1425 #global-interrupts = <2>;
1440 clock-names = "ahb",
1444 power-domains = <&gpucc GPU_CX_GDSC>;
1448 compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu";
1452 reg-names = "gmu",
1458 interrupt-names = "hfi",
1466 clock-names = "ahb",
1472 power-domains = <&gpucc GPU_CX_GDSC>,
1474 power-domain-names = "cx",
1479 operating-points-v2 = <&gmu_opp_table>;
1481 gmu_opp_table: opp-table {
1482 compatible = "operating-points-v2";
1484 opp-200000000 {
1485 opp-hz = /bits/ 64 <200000000>;
1486 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1491 gpucc: clock-controller@3d90000 {
1492 compatible = "qcom,sm6350-gpucc";
1497 clock-names = "bi_tcxo",
1500 #clock-cells = <1>;
1501 #reset-cells = <1>;
1502 #power-domain-cells = <1>;
1506 compatible = "qcom,sm6350-mpss-pas";
1509 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
1515 interrupt-names = "wdog", "fatal", "ready", "handover",
1516 "stop-ack", "shutdown-ack";
1519 clock-names = "xo";
1521 power-domains = <&rpmhpd SM6350_CX>,
1523 power-domain-names = "cx", "mss";
1525 memory-region = <&pil_modem_mem>;
1529 qcom,smem-states = <&modem_smp2p_out 0>;
1530 qcom,smem-state-names = "stop";
1534 glink-edge {
1535 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
1541 qcom,remote-pid = <1>;
1546 compatible = "qcom,sm6350-cdsp-pas";
1549 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
1554 interrupt-names = "wdog", "fatal", "ready",
1555 "handover", "stop-ack";
1558 clock-names = "xo";
1560 power-domains = <&rpmhpd SM6350_CX>,
1562 power-domain-names = "cx", "mx";
1564 memory-region = <&pil_cdsp_mem>;
1568 qcom,smem-states = <&smp2p_cdsp_out 0>;
1569 qcom,smem-state-names = "stop";
1573 glink-edge {
1574 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
1581 qcom,remote-pid = <5>;
1585 qcom,glink-channels = "fastrpcglink-apps-dsp";
1587 qcom,non-secure-domain;
1588 #address-cells = <1>;
1589 #size-cells = <0>;
1591 compute-cb@1 {
1592 compatible = "qcom,fastrpc-compute-cb";
1597 compute-cb@2 {
1598 compatible = "qcom,fastrpc-compute-cb";
1603 compute-cb@3 {
1604 compatible = "qcom,fastrpc-compute-cb";
1609 compute-cb@4 {
1610 compatible = "qcom,fastrpc-compute-cb";
1615 compute-cb@5 {
1616 compatible = "qcom,fastrpc-compute-cb";
1621 compute-cb@6 {
1622 compatible = "qcom,fastrpc-compute-cb";
1627 compute-cb@7 {
1628 compatible = "qcom,fastrpc-compute-cb";
1633 compute-cb@8 {
1634 compatible = "qcom,fastrpc-compute-cb";
1645 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
1650 interrupt-names = "hc_irq", "pwr_irq";
1656 clock-names = "iface", "core", "xo";
1660 interconnect-names = "sdhc-ddr", "cpu-sdhc";
1662 pinctrl-0 = <&sdc2_on_state>;
1663 pinctrl-1 = <&sdc2_off_state>;
1664 pinctrl-names = "default", "sleep";
1666 qcom,dll-config = <0x0007642c>;
1667 qcom,ddr-config = <0x80040868>;
1668 power-domains = <&rpmhpd SM6350_CX>;
1669 operating-points-v2 = <&sdhc2_opp_table>;
1670 bus-width = <4>;
1674 sdhc2_opp_table: opp-table {
1675 compatible = "operating-points-v2";
1677 opp-100000000 {
1678 opp-hz = /bits/ 64 <100000000>;
1679 required-opps = <&rpmhpd_opp_svs_l1>;
1680 opp-peak-kBps = <790000 131000>;
1681 opp-avg-kBps = <50000 50000>;
1684 opp-202000000 {
1685 opp-hz = /bits/ 64 <202000000>;
1686 required-opps = <&rpmhpd_opp_nom>;
1687 opp-peak-kBps = <3190000 294000>;
1688 opp-avg-kBps = <261438 300000>;
1694 compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy";
1697 #phy-cells = <0>;
1700 clock-names = "cfg_ahb", "ref";
1706 compatible = "qcom,sm6350-qmp-usb3-dp-phy";
1713 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
1715 power-domains = <&gcc USB30_PRIM_GDSC>;
1719 reset-names = "phy", "common";
1721 orientation-switch;
1723 #clock-cells = <1>;
1724 #phy-cells = <1>;
1729 #address-cells = <1>;
1730 #size-cells = <0>;
1743 remote-endpoint = <&usb_1_dwc3_ss_out>;
1757 compatible = "qcom,sm6350-dc-noc";
1759 #interconnect-cells = <2>;
1760 qcom,bcm-voters = <&apps_bcm_voter>;
1763 system-cache-controller@9200000 {
1764 compatible = "qcom,sm6350-llcc";
1766 reg-names = "llcc0_base", "llcc_broadcast_base";
1770 compatible = "qcom,sm6350-gem-noc";
1772 #interconnect-cells = <2>;
1773 qcom,bcm-voters = <&apps_bcm_voter>;
1777 compatible = "qcom,sm6350-npu-noc";
1779 #interconnect-cells = <2>;
1780 qcom,bcm-voters = <&apps_bcm_voter>;
1784 compatible = "qcom,sm6350-llcc-bwmon", "qcom,sdm845-bwmon";
1788 operating-points-v2 = <&llcc_bwmon_opp_table>;
1792 llcc_bwmon_opp_table: opp-table {
1793 compatible = "operating-points-v2";
1795 opp-0 {
1796 opp-peak-kBps = <2288000>;
1799 opp-1 {
1800 opp-peak-kBps = <4577000>;
1803 opp-2 {
1804 opp-peak-kBps = <7110000>;
1807 opp-3 {
1808 opp-peak-kBps = <9155000>;
1811 opp-4 {
1812 opp-peak-kBps = <12298000>;
1815 opp-5 {
1816 opp-peak-kBps = <14236000>;
1823 compatible = "qcom,sm6350-cpu-bwmon", "qcom,sc7280-llcc-bwmon";
1827 operating-points-v2 = <&cpu_bwmon_opp_table>;
1831 cpu_bwmon_opp_table: opp-table {
1832 compatible = "operating-points-v2";
1834 opp-0 {
1835 opp-peak-kBps = <762000>;
1838 opp-1 {
1839 opp-peak-kBps = <1144000>;
1842 opp-2 {
1843 opp-peak-kBps = <1720000>;
1846 opp-3 {
1847 opp-peak-kBps = <2086000>;
1850 opp-4 {
1851 opp-peak-kBps = <2597000>;
1854 opp-5 {
1855 opp-peak-kBps = <2929000>;
1858 opp-6 {
1859 opp-peak-kBps = <3879000>;
1862 opp-7 {
1863 opp-peak-kBps = <5161000>;
1866 opp-8 {
1867 opp-peak-kBps = <5931000>;
1870 opp-9 {
1871 opp-peak-kBps = <6881000>;
1874 opp-10 {
1875 opp-peak-kBps = <7980000>;
1881 compatible = "qcom,sm6350-dwc3", "qcom,dwc3";
1884 #address-cells = <2>;
1885 #size-cells = <2>;
1893 clock-names = "cfg_noc",
1899 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1904 interrupt-names = "pwr_event",
1910 power-domains = <&gcc USB30_PRIM_GDSC>;
1916 interconnect-names = "usb-ddr", "apps-usb";
1925 snps,has-lpm-erratum;
1926 snps,hird-threshold = /bits/ 8 <0x10>;
1927 snps,parkmode-disable-ss-quirk;
1928 snps,dis-u1-entry-quirk;
1929 snps,dis-u2-entry-quirk;
1931 phy-names = "usb2-phy", "usb3-phy";
1932 usb-role-switch;
1935 #address-cells = <1>;
1936 #size-cells = <0>;
1949 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
1957 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci";
1960 power-domains = <&camcc TITAN_TOP_GDSC>;
1968 clock-names = "camnoc_axi",
1975 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
1977 assigned-clock-rates = <80000000>, <37500000>;
1979 pinctrl-0 = <&cci0_default &cci1_default>;
1980 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
1981 pinctrl-names = "default", "sleep";
1983 #address-cells = <1>;
1984 #size-cells = <0>;
1988 cci0_i2c0: i2c-bus@0 {
1990 clock-frequency = <1000000>;
1991 #address-cells = <1>;
1992 #size-cells = <0>;
1995 cci0_i2c1: i2c-bus@1 {
1997 clock-frequency = <1000000>;
1998 #address-cells = <1>;
1999 #size-cells = <0>;
2004 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci";
2007 power-domains = <&camcc TITAN_TOP_GDSC>;
2015 clock-names = "camnoc_axi",
2022 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
2024 assigned-clock-rates = <80000000>, <37500000>;
2026 pinctrl-0 = <&cci2_default>;
2027 pinctrl-1 = <&cci2_sleep>;
2028 pinctrl-names = "default", "sleep";
2030 #address-cells = <1>;
2031 #size-cells = <0>;
2035 cci1_i2c0: i2c-bus@0 {
2037 clock-frequency = <1000000>;
2038 #address-cells = <1>;
2039 #size-cells = <0>;
2045 camcc: clock-controller@ad00000 {
2046 compatible = "qcom,sm6350-camcc";
2049 #clock-cells = <1>;
2050 #reset-cells = <1>;
2051 #power-domain-cells = <1>;
2054 mdss: display-subsystem@ae00000 {
2055 compatible = "qcom,sm6350-mdss";
2057 reg-names = "mdss";
2060 interrupt-controller;
2061 #interrupt-cells = <1>;
2067 interconnect-names = "mdp0-mem",
2068 "cpu-cfg";
2073 clock-names = "iface",
2077 power-domains = <&dispcc MDSS_GDSC>;
2080 #address-cells = <2>;
2081 #size-cells = <2>;
2086 mdss_mdp: display-controller@ae01000 {
2087 compatible = "qcom,sm6350-dpu";
2090 reg-names = "mdp", "vbif";
2092 interrupt-parent = <&mdss>;
2101 clock-names = "bus",
2108 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2109 assigned-clock-rates = <19200000>;
2111 operating-points-v2 = <&mdp_opp_table>;
2112 power-domains = <&rpmhpd SM6350_CX>;
2115 #address-cells = <1>;
2116 #size-cells = <0>;
2122 remote-endpoint = <&mdss_dsi0_in>;
2130 remote-endpoint = <&mdss_dp_in>;
2135 mdp_opp_table: opp-table {
2136 compatible = "operating-points-v2";
2138 opp-19200000 {
2139 opp-hz = /bits/ 64 <19200000>;
2140 required-opps = <&rpmhpd_opp_min_svs>;
2143 opp-200000000 {
2144 opp-hz = /bits/ 64 <200000000>;
2145 required-opps = <&rpmhpd_opp_low_svs>;
2148 opp-300000000 {
2149 opp-hz = /bits/ 64 <300000000>;
2150 required-opps = <&rpmhpd_opp_svs>;
2153 opp-373333333 {
2154 opp-hz = /bits/ 64 <373333333>;
2155 required-opps = <&rpmhpd_opp_svs_l1>;
2158 opp-448000000 {
2159 opp-hz = /bits/ 64 <448000000>;
2160 required-opps = <&rpmhpd_opp_nom>;
2163 opp-560000000 {
2164 opp-hz = /bits/ 64 <560000000>;
2165 required-opps = <&rpmhpd_opp_turbo>;
2170 mdss_dp: displayport-controller@ae90000 {
2171 compatible = "qcom,sm6350-dp", "qcom,sm8350-dp";
2177 interrupt-parent = <&mdss>;
2184 clock-names = "core_iface",
2190 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
2192 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2196 phy-names = "dp";
2198 #sound-dai-cells = <0>;
2200 operating-points-v2 = <&dp_opp_table>;
2201 power-domains = <&rpmhpd SM6350_CX>;
2206 #address-cells = <1>;
2207 #size-cells = <0>;
2213 remote-endpoint = <&dpu_intf0_out>;
2225 dp_opp_table: opp-table {
2226 compatible = "operating-points-v2";
2228 opp-160000000 {
2229 opp-hz = /bits/ 64 <160000000>;
2230 required-opps = <&rpmhpd_opp_low_svs>;
2233 opp-270000000 {
2234 opp-hz = /bits/ 64 <270000000>;
2235 required-opps = <&rpmhpd_opp_svs>;
2238 opp-540000000 {
2239 opp-hz = /bits/ 64 <540000000>;
2240 required-opps = <&rpmhpd_opp_svs_l1>;
2243 opp-810000000 {
2244 opp-hz = /bits/ 64 <810000000>;
2245 required-opps = <&rpmhpd_opp_nom>;
2251 compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2253 reg-names = "dsi_ctrl";
2255 interrupt-parent = <&mdss>;
2264 clock-names = "byte",
2271 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2273 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
2276 operating-points-v2 = <&mdss_dsi_opp_table>;
2277 power-domains = <&rpmhpd SM6350_MX>;
2280 phy-names = "dsi";
2282 #address-cells = <1>;
2283 #size-cells = <0>;
2288 #address-cells = <1>;
2289 #size-cells = <0>;
2295 remote-endpoint = <&dpu_intf1_out>;
2307 mdss_dsi_opp_table: opp-table {
2308 compatible = "operating-points-v2";
2310 opp-187500000 {
2311 opp-hz = /bits/ 64 <187500000>;
2312 required-opps = <&rpmhpd_opp_low_svs>;
2315 opp-300000000 {
2316 opp-hz = /bits/ 64 <300000000>;
2317 required-opps = <&rpmhpd_opp_svs>;
2320 opp-358000000 {
2321 opp-hz = /bits/ 64 <358000000>;
2322 required-opps = <&rpmhpd_opp_svs_l1>;
2328 compatible = "qcom,dsi-phy-10nm";
2332 reg-names = "dsi_phy",
2336 #clock-cells = <1>;
2337 #phy-cells = <0>;
2341 clock-names = "iface", "ref";
2347 dispcc: clock-controller@af00000 {
2348 compatible = "qcom,sm6350-dispcc";
2356 clock-names = "bi_tcxo",
2362 #clock-cells = <1>;
2363 #reset-cells = <1>;
2364 #power-domain-cells = <1>;
2367 pdc: interrupt-controller@b220000 {
2368 compatible = "qcom,sm6350-pdc", "qcom,pdc";
2370 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
2372 #interrupt-cells = <2>;
2373 interrupt-parent = <&intc>;
2374 interrupt-controller;
2377 tsens0: thermal-sensor@c263000 {
2378 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2";
2382 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
2384 interrupt-names = "uplow", "critical";
2385 #thermal-sensor-cells = <1>;
2388 tsens1: thermal-sensor@c265000 {
2389 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2";
2393 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
2395 interrupt-names = "uplow", "critical";
2396 #thermal-sensor-cells = <1>;
2399 aoss_qmp: power-management@c300000 {
2400 compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp";
2402 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
2406 #clock-cells = <0>;
2410 compatible = "qcom,spmi-pmic-arb";
2416 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2417 interrupt-names = "periph_irq";
2418 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2421 #address-cells = <2>;
2422 #size-cells = <0>;
2423 interrupt-controller;
2424 #interrupt-cells = <4>;
2428 compatible = "qcom,sm6350-tlmm";
2439 gpio-controller;
2440 #gpio-cells = <2>;
2441 interrupt-controller;
2442 #interrupt-cells = <2>;
2443 gpio-ranges = <&tlmm 0 0 157>;
2444 wakeup-parent = <&pdc>;
2446 cci0_default: cci0-default-state {
2449 drive-strength = <2>;
2450 bias-pull-up;
2453 cci0_sleep: cci0-sleep-state {
2456 drive-strength = <2>;
2457 bias-pull-down;
2460 cci1_default: cci1-default-state {
2463 drive-strength = <2>;
2464 bias-pull-up;
2467 cci1_sleep: cci1-sleep-state {
2470 drive-strength = <2>;
2471 bias-pull-down;
2474 cci2_default: cci2-default-state {
2477 drive-strength = <2>;
2478 bias-pull-up;
2481 cci2_sleep: cci2-sleep-state {
2484 drive-strength = <2>;
2485 bias-pull-down;
2488 sdc2_off_state: sdc2-off-state {
2489 clk-pins {
2491 drive-strength = <2>;
2492 bias-disable;
2495 cmd-pins {
2497 drive-strength = <2>;
2498 bias-pull-up;
2501 data-pins {
2503 drive-strength = <2>;
2504 bias-pull-up;
2508 sdc2_on_state: sdc2-on-state {
2509 clk-pins {
2511 drive-strength = <16>;
2512 bias-disable;
2515 cmd-pins {
2517 drive-strength = <10>;
2518 bias-pull-up;
2521 data-pins {
2523 drive-strength = <10>;
2524 bias-pull-up;
2528 qup_uart9_default: qup-uart9-default-state {
2531 drive-strength = <2>;
2532 bias-disable;
2535 qup_i2c0_default: qup-i2c0-default-state {
2538 drive-strength = <2>;
2539 bias-pull-up;
2542 qup_i2c2_default: qup-i2c2-default-state {
2545 drive-strength = <2>;
2546 bias-pull-up;
2549 qup_i2c6_default: qup-i2c6-default-state {
2552 drive-strength = <2>;
2553 bias-pull-up;
2556 qup_i2c7_default: qup-i2c7-default-state {
2559 drive-strength = <2>;
2560 bias-pull-up;
2563 qup_i2c8_default: qup-i2c8-default-state {
2566 drive-strength = <2>;
2567 bias-pull-up;
2570 qup_i2c10_default: qup-i2c10-default-state {
2573 drive-strength = <2>;
2574 bias-pull-up;
2577 qup_uart1_cts: qup-uart1-cts-default-state {
2580 drive-strength = <2>;
2581 bias-disable;
2584 qup_uart1_rts: qup-uart1-rts-default-state {
2587 drive-strength = <2>;
2588 bias-pull-down;
2591 qup_uart1_rx: qup-uart1-rx-default-state {
2594 drive-strength = <2>;
2595 bias-disable;
2598 qup_uart1_tx: qup-uart1-tx-default-state {
2601 drive-strength = <2>;
2602 bias-pull-up;
2607 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500";
2609 #iommu-cells = <2>;
2610 #global-interrupts = <1>;
2692 dma-coherent;
2695 intc: interrupt-controller@17a00000 {
2696 compatible = "arm,gic-v3";
2697 #interrupt-cells = <3>;
2698 interrupt-controller;
2705 compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt";
2712 compatible = "arm,armv7-timer-mem";
2714 clock-frequency = <19200000>;
2715 #address-cells = <1>;
2716 #size-cells = <1>;
2720 frame-number = <0>;
2728 frame-number = <1>;
2735 frame-number = <2>;
2742 frame-number = <3>;
2749 frame-number = <4>;
2756 frame-number = <5>;
2763 frame-number = <6>;
2771 compatible = "qcom,rpmh-rsc";
2776 reg-names = "drv-0", "drv-1", "drv-2";
2780 qcom,tcs-offset = <0xd00>;
2781 qcom,drv-id = <2>;
2782 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
2784 power-domains = <&cluster_pd>;
2786 rpmhcc: clock-controller {
2787 compatible = "qcom,sm6350-rpmh-clk";
2788 #clock-cells = <1>;
2789 clock-names = "xo";
2793 rpmhpd: power-controller {
2794 compatible = "qcom,sm6350-rpmhpd";
2795 #power-domain-cells = <1>;
2796 operating-points-v2 = <&rpmhpd_opp_table>;
2798 rpmhpd_opp_table: opp-table {
2799 compatible = "operating-points-v2";
2802 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
2806 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2810 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2814 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2818 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2822 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2826 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2830 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
2834 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2838 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2843 apps_bcm_voter: bcm-voter {
2844 compatible = "qcom,bcm-voter";
2849 compatible = "qcom,sm6350-osm-l3", "qcom,osm-l3";
2853 clock-names = "xo", "alternate";
2855 #interconnect-cells = <1>;
2859 compatible = "qcom,sm6350-cpufreq-hw", "qcom,cpufreq-hw";
2861 reg-names = "freq-domain0", "freq-domain1";
2863 clock-names = "xo", "alternate";
2865 #freq-domain-cells = <1>;
2866 #clock-cells = <1>;
2870 compatible = "qcom,wcn3990-wifi";
2872 reg-names = "membase";
2873 memory-region = <&wlan_fw_mem>;
2887 qcom,msa-fixed-perm;
2892 thermal-zones {
2893 aoss0-thermal {
2894 thermal-sensors = <&tsens0 0>;
2897 aoss0-crit {
2905 aoss1-thermal {
2906 thermal-sensors = <&tsens1 0>;
2909 aoss1-crit {
2917 audio-thermal {
2918 thermal-sensors = <&tsens1 2>;
2921 audio-crit {
2929 camera-thermal {
2930 thermal-sensors = <&tsens1 5>;
2933 camera-crit {
2941 cpu0-thermal {
2942 thermal-sensors = <&tsens0 1>;
2945 cpu0_alert0: trip-point0 {
2951 cpu0-crit {
2958 cooling-maps {
2961 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2966 cpu1-thermal {
2967 thermal-sensors = <&tsens0 2>;
2970 cpu1_alert0: trip-point0 {
2976 cpu1-crit {
2983 cooling-maps {
2986 cooling-device = <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2991 cpu2-thermal {
2992 thermal-sensors = <&tsens0 3>;
2995 cpu2_alert0: trip-point0 {
3001 cpu2-crit {
3008 cooling-maps {
3011 cooling-device = <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3016 cpu3-thermal {
3017 thermal-sensors = <&tsens0 4>;
3020 cpu3_alert0: trip-point0 {
3026 cpu3-crit {
3033 cooling-maps {
3036 cooling-device = <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3041 cpu4-thermal {
3042 thermal-sensors = <&tsens0 5>;
3045 cpu4_alert0: trip-point0 {
3051 cpu4-crit {
3058 cooling-maps {
3061 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3066 cpu5-thermal {
3067 thermal-sensors = <&tsens0 6>;
3070 cpu5_alert0: trip-point0 {
3076 cpu5-crit {
3083 cooling-maps {
3086 cooling-device = <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3091 cpu6-left-thermal {
3092 thermal-sensors = <&tsens0 9>;
3095 cpu6_left_alert0: trip-point0 {
3101 cpu6-left-crit {
3108 cooling-maps {
3111 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3116 cpu6-right-thermal {
3117 thermal-sensors = <&tsens0 10>;
3120 cpu6_right_alert0: trip-point0 {
3126 cpu6-right-crit {
3133 cooling-maps {
3136 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3141 cpu7-left-thermal {
3142 thermal-sensors = <&tsens0 11>;
3145 cpu7_left_alert0: trip-point0 {
3151 cpu7-left-crit {
3158 cooling-maps {
3161 cooling-device = <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3166 cpu7-right-thermal {
3167 thermal-sensors = <&tsens0 12>;
3170 cpu7_right_alert0: trip-point0 {
3176 cpu7-right-crit {
3183 cooling-maps {
3186 cooling-device = <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3191 cpuss0-thermal {
3192 thermal-sensors = <&tsens0 7>;
3195 cpuss0-crit {
3203 cpuss1-thermal {
3204 thermal-sensors = <&tsens0 8>;
3207 cpuss1-crit {
3215 cwlan-thermal {
3216 thermal-sensors = <&tsens1 1>;
3219 cwlan-crit {
3227 ddr-thermal {
3228 thermal-sensors = <&tsens1 3>;
3231 ddr-crit {
3239 gpuss0-thermal {
3240 polling-delay-passive = <250>;
3242 thermal-sensors = <&tsens0 13>;
3245 gpuss0_alert0: trip-point0 {
3251 gpuss0-crit {
3258 cooling-maps {
3261 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3266 gpuss1-thermal {
3267 polling-delay-passive = <250>;
3269 thermal-sensors = <&tsens0 14>;
3272 gpuss1_alert0: trip-point0 {
3278 gpuss1-crit {
3285 cooling-maps {
3288 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3293 modem-core0-thermal {
3294 thermal-sensors = <&tsens1 6>;
3297 modem-core0-crit {
3305 modem-core1-thermal {
3306 thermal-sensors = <&tsens1 7>;
3309 modem-core1-crit {
3317 modem-scl-thermal {
3318 thermal-sensors = <&tsens1 9>;
3321 modem-scl-crit {
3329 modem-vec-thermal {
3330 thermal-sensors = <&tsens1 8>;
3333 modem-vec-crit {
3341 npu-thermal {
3342 thermal-sensors = <&tsens1 10>;
3345 npu-crit {
3353 q6-hvx-thermal {
3354 thermal-sensors = <&tsens1 4>;
3357 q6-hvx-crit {
3365 video-thermal {
3366 thermal-sensors = <&tsens1 11>;
3369 video-crit {
3379 compatible = "arm,armv8-timer";
3380 clock-frequency = <19200000>;