Lines Matching +full:0 +full:x18220000
32 #clock-cells = <0>;
40 #clock-cells = <0>;
46 #size-cells = <0>;
48 CPU0: cpu@0 {
51 reg = <0x0 0x0>;
52 clocks = <&cpufreq_hw 0>;
57 qcom,freq-domain = <&cpufreq_hw 0>;
81 reg = <0x0 0x100>;
82 clocks = <&cpufreq_hw 0>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
106 reg = <0x0 0x200>;
107 clocks = <&cpufreq_hw 0>;
112 qcom,freq-domain = <&cpufreq_hw 0>;
131 reg = <0x0 0x300>;
132 clocks = <&cpufreq_hw 0>;
137 qcom,freq-domain = <&cpufreq_hw 0>;
156 reg = <0x0 0x400>;
157 clocks = <&cpufreq_hw 0>;
162 qcom,freq-domain = <&cpufreq_hw 0>;
181 reg = <0x0 0x500>;
182 clocks = <&cpufreq_hw 0>;
187 qcom,freq-domain = <&cpufreq_hw 0>;
206 reg = <0x0 0x600>;
231 reg = <0x0 0x700>;
290 CLUSTER_SLEEP_PC: cluster-sleep-0 {
292 arm,psci-suspend-param = <0x41000044>;
300 arm,psci-suspend-param = <0x41001244>;
308 arm,psci-suspend-param = <0x4100b244>;
318 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
321 arm,psci-suspend-param = <0x40000003>;
328 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
331 arm,psci-suspend-param = <0x40000004>;
338 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
341 arm,psci-suspend-param = <0x40000003>;
351 arm,psci-suspend-param = <0x40000004>;
370 reg = <0x0 0x80000000 0x0 0x0>;
508 #power-domain-cells = <0>;
514 #power-domain-cells = <0>;
520 #power-domain-cells = <0>;
526 #power-domain-cells = <0>;
532 #power-domain-cells = <0>;
538 #power-domain-cells = <0>;
544 #power-domain-cells = <0>;
550 #power-domain-cells = <0>;
556 #power-domain-cells = <0>;
569 reg = <0 0x80000000 0 0x600000>;
574 reg = <0 0x80700000 0 0x160000>;
580 reg = <0 0x80860000 0 0x20000>;
585 reg = <0 0x808ff000 0 0x1000>;
590 reg = <0 0x80900000 0 0x200000>;
595 reg = <0 0x80b00000 0 0x1e00000>;
600 reg = <0 0x86000000 0 0x500000>;
605 reg = <0 0x86500000 0 0x500000>;
610 reg = <0 0x86a00000 0 0x500000>;
615 reg = <0 0x86f00000 0 0x1e00000>;
620 reg = <0 0x88d00000 0 0x2800000>;
625 reg = <0 0x8b500000 0 0x200000>;
630 reg = <0 0x8b700000 0 0x10000>;
635 reg = <0 0x8b710000 0 0x5400>;
640 reg = <0 0x8b800000 0 0xf800000>;
645 reg = <0 0xa0000000 0 0x2300000>;
650 reg = <0 0xa2300000 0 0x100000>;
655 reg = <0 0xc0000000 0 0x3900000>;
660 reg = <0 0xf0d00000 0 0x1000>;
665 reg = <0 0xffb00000 0 0xc0000>;
670 reg = <0 0xffbc0000 0 0x40000>;
676 reg = <0 0xffc00000 0 0x100000>;
677 record-size = <0x1000>;
678 console-size = <0x40000>;
679 pmsg-size = <0x20000>;
685 reg = <0 0xffd00000 0 0x1000>;
705 qcom,local-pid = <0>;
729 qcom,local-pid = <0>;
754 qcom,local-pid = <0>;
780 soc: soc@0 {
783 ranges = <0 0 0 0 0x10 0>;
784 dma-ranges = <0 0 0 0 0x10 0>;
789 reg = <0 0x00100000 0 0x1f0000>;
803 reg = <0 0x00408000 0 0x1000>;
812 reg = <0 0x00784000 0 0x3000>;
817 reg = <0x2015 0x1>;
818 bits = <0 8>;
824 reg = <0 0x00793000 0 0x1000>;
831 reg = <0 0x007c4000 0 0x1000>,
832 <0 0x007c5000 0 0x1000>,
833 <0 0x007c8000 0 0x8000>;
839 iommus = <&apps_smmu 0x60 0x0>;
846 qcom,dll-config = <0x000f642c>;
847 qcom,ddr-config = <0x80040868>;
878 reg = <0 0x00800000 0 0x60000>;
890 dma-channel-mask = <0x1f>;
891 iommus = <&apps_smmu 0x56 0x0>;
898 reg = <0x0 0x008c0000 0x0 0x2000>;
904 iommus = <&apps_smmu 0x43 0x0>;
910 reg = <0 0x00880000 0 0x4000>;
914 pinctrl-0 = <&qup_i2c0_default>;
916 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
917 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
920 #size-cells = <0>;
921 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
922 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
923 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
930 reg = <0 0x00884000 0 0x4000>;
934 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
938 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
939 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
946 reg = <0 0x00888000 0 0x4000>;
950 pinctrl-0 = <&qup_i2c2_default>;
952 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
956 #size-cells = <0>;
957 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
958 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
959 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
967 reg = <0 0x00900000 0 0x60000>;
979 dma-channel-mask = <0x3f>;
980 iommus = <&apps_smmu 0x4d6 0x0>;
987 reg = <0x0 0x009c0000 0x0 0x2000>;
993 iommus = <&apps_smmu 0x4c3 0x0>;
999 reg = <0 0x00980000 0 0x4000>;
1003 pinctrl-0 = <&qup_i2c6_default>;
1005 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1006 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1009 #size-cells = <0>;
1010 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1011 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1012 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
1019 reg = <0 0x00984000 0 0x4000>;
1023 pinctrl-0 = <&qup_i2c7_default>;
1025 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1029 #size-cells = <0>;
1030 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1031 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1032 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
1039 reg = <0 0x00988000 0 0x4000>;
1043 pinctrl-0 = <&qup_i2c8_default>;
1045 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1049 #size-cells = <0>;
1050 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1051 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1052 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
1059 reg = <0 0x0098c000 0 0x4000>;
1063 pinctrl-0 = <&qup_uart9_default>;
1065 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1066 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1073 reg = <0 0x00990000 0 0x4000>;
1077 pinctrl-0 = <&qup_i2c10_default>;
1079 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1083 #size-cells = <0>;
1084 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1085 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1086 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
1094 reg = <0 0x01500000 0 0x28000>;
1101 reg = <0 0x01620000 0 0x17080>;
1114 reg = <0 0x016e0000 0 0x15080>;
1121 reg = <0 0x01700000 0 0x1f880>;
1134 reg = <0 0x01740000 0 0x1c100>;
1142 reg = <0 0x01d84000 0 0x3000>,
1143 <0 0x01d90000 0 0x8000>;
1155 iommus = <&apps_smmu 0x80 0x0>;
1177 <0 0>,
1178 <0 0>,
1181 <0 0>,
1182 <0 0>,
1183 <0 0>,
1184 <0 0>;
1191 reg = <0 0x01d87000 0 0x1000>;
1202 resets = <&ufs_mem_hc 0>;
1205 #phy-cells = <0>;
1212 reg = <0 0x01dc4000 0 0x24000>;
1215 qcom,ee = <0>;
1219 iommus = <&apps_smmu 0x426 0x11>,
1220 <&apps_smmu 0x432 0x0>,
1221 <&apps_smmu 0x436 0x11>,
1222 <&apps_smmu 0x438 0x1>,
1223 <&apps_smmu 0x43f 0x0>;
1228 reg = <0 0x01dfa000 0 0x6000>;
1231 iommus = <&apps_smmu 0x426 0x11>,
1232 <&apps_smmu 0x432 0x0>,
1233 <&apps_smmu 0x436 0x11>,
1234 <&apps_smmu 0x438 0x1>,
1235 <&apps_smmu 0x43f 0x0>;
1244 iommus = <&apps_smmu 0x440 0x0>,
1245 <&apps_smmu 0x442 0x0>;
1246 reg = <0 0x01e40000 0 0x8000>,
1247 <0 0x01e50000 0 0x3000>,
1248 <0 0x01e04000 0 0x23000>;
1255 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1265 interconnects = <&aggre2_noc MASTER_IPA 0 &clk_virt SLAVE_EBI_CH0 0>,
1266 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_OCIMEM 0>,
1267 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_IPA_CFG 0>;
1270 qcom,smem-states = <&ipa_smp2p_out 0>,
1280 reg = <0x0 0x01f40000 0x0 0x40000>;
1286 reg = <0 0x03000000 0 0x100>;
1289 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1307 qcom,smem-states = <&smp2p_adsp_out 0>;
1328 #size-cells = <0>;
1333 iommus = <&apps_smmu 0x1003 0x0>;
1339 iommus = <&apps_smmu 0x1004 0x0>;
1345 iommus = <&apps_smmu 0x1005 0x0>;
1354 reg = <0 0x03d00000 0 0x40000>,
1355 <0 0x03d9e000 0 0x1000>;
1360 iommus = <&adreno_smmu 0>;
1379 opp-supported-hw = <0x02>;
1385 opp-supported-hw = <0x04>;
1391 opp-supported-hw = <0x08>;
1397 opp-supported-hw = <0x10>;
1403 opp-supported-hw = <0xff>;
1409 opp-supported-hw = <0xff>;
1415 opp-supported-hw = <0xff>;
1422 reg = <0 0x03d40000 0 0x10000>;
1448 reg = <0 0x03d6a000 0 0x31000>,
1449 <0 0x0b290000 0 0x10000>,
1450 <0 0x0b490000 0 0x10000>;
1492 reg = <0 0x03d90000 0 0x9000>;
1506 reg = <0x0 0x04080000 0x0 0x4040>;
1509 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1528 qcom,smem-states = <&modem_smp2p_out 0>;
1546 reg = <0 0x08300000 0 0x10000>;
1549 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
1567 qcom,smem-states = <&smp2p_cdsp_out 0>;
1588 #size-cells = <0>;
1593 iommus = <&apps_smmu 0x1401 0x20>;
1599 iommus = <&apps_smmu 0x1402 0x20>;
1605 iommus = <&apps_smmu 0x1403 0x20>;
1611 iommus = <&apps_smmu 0x1404 0x20>;
1617 iommus = <&apps_smmu 0x1405 0x20>;
1623 iommus = <&apps_smmu 0x1406 0x20>;
1629 iommus = <&apps_smmu 0x1407 0x20>;
1635 iommus = <&apps_smmu 0x1408 0x20>;
1645 reg = <0 0x08804000 0 0x1000>;
1650 iommus = <&apps_smmu 0x560 0x0>;
1657 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>,
1658 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>;
1661 pinctrl-0 = <&sdc2_on_state>;
1665 qcom,dll-config = <0x0007642c>;
1666 qcom,ddr-config = <0x80040868>;
1694 reg = <0 0x088e3000 0 0x400>;
1696 #phy-cells = <0>;
1706 reg = <0 0x088e8000 0 0x3000>;
1729 #size-cells = <0>;
1731 port@0 {
1732 reg = <0>;
1757 reg = <0 0x09160000 0 0x3200>;
1764 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
1770 reg = <0 0x09680000 0 0x3e200>;
1777 reg = <0 0x09990000 0 0x1600>;
1784 reg = <0x0 0x090b6300 0x0 0x600>;
1794 opp-0 {
1823 reg = <0x0 0x090cd000 0x0 0x1000>;
1833 opp-0 {
1881 reg = <0 0x0a6f8800 0 0x400>;
1913 interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>,
1914 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
1919 reg = <0 0x0a600000 0 0xcd00>;
1921 iommus = <&apps_smmu 0x540 0x0>;
1925 snps,hird-threshold = /bits/ 8 <0x10>;
1933 #size-cells = <0>;
1935 port@0 {
1936 reg = <0>;
1955 reg = <0 0x0ac4a000 0 0x1000>;
1976 pinctrl-0 = <&cci0_default &cci1_default>;
1981 #size-cells = <0>;
1985 cci0_i2c0: i2c-bus@0 {
1986 reg = <0>;
1989 #size-cells = <0>;
1996 #size-cells = <0>;
2002 reg = <0 0x0ac4b000 0 0x1000>;
2023 pinctrl-0 = <&cci2_default>;
2028 #size-cells = <0>;
2032 cci1_i2c0: i2c-bus@0 {
2033 reg = <0>;
2036 #size-cells = <0>;
2044 reg = <0 0x0ad00000 0 0x16000>;
2053 reg = <0 0x0ae00000 0 0x1000>;
2075 iommus = <&apps_smmu 0x800 0x2>;
2085 reg = <0 0x0ae01000 0 0x8f000>,
2086 <0 0x0aeb0000 0 0x2008>;
2090 interrupts = <0>;
2113 #size-cells = <0>;
2115 port@0 {
2116 reg = <0>;
2169 reg = <0 0xae90000 0 0x200>,
2170 <0 0xae90200 0 0x200>,
2171 <0 0xae90400 0 0x600>,
2172 <0 0xae91000 0 0x400>,
2173 <0 0xae91400 0 0x400>;
2195 #sound-dai-cells = <0>;
2204 #size-cells = <0>;
2206 port@0 {
2207 reg = <0>;
2249 reg = <0 0x0ae94000 0 0x400>;
2270 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
2279 #size-cells = <0>;
2285 #size-cells = <0>;
2287 port@0 {
2288 reg = <0>;
2325 reg = <0 0x0ae94400 0 0x200>,
2326 <0 0x0ae94600 0 0x280>,
2327 <0 0x0ae94a00 0 0x1e0>;
2333 #phy-cells = <0>;
2345 reg = <0 0x0af00000 0 0x20000>;
2348 <&mdss_dsi0_phy 0>,
2365 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>;
2366 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
2375 reg = <0 0x0c263000 0 0x1ff>, /* TM */
2376 <0 0x0c222000 0 0x8>; /* SROT */
2386 reg = <0 0x0c265000 0 0x1ff>, /* TM */
2387 <0 0x0c223000 0 0x8>; /* SROT */
2397 reg = <0 0x0c300000 0 0x1000>;
2402 #clock-cells = <0>;
2407 reg = <0 0x0c440000 0 0x1100>,
2408 <0 0x0c600000 0 0x2000000>,
2409 <0 0x0e600000 0 0x100000>,
2410 <0 0x0e700000 0 0xa0000>,
2411 <0 0x0c40a000 0 0x26000>;
2415 qcom,ee = <0>;
2416 qcom,channel = <0>;
2418 #size-cells = <0>;
2425 reg = <0 0x0f100000 0 0x300000>;
2439 gpio-ranges = <&tlmm 0 0 157>;
2604 reg = <0 0x15000000 0 0x100000>;
2694 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
2695 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
2701 reg = <0 0x17c10000 0 0x1000>;
2703 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
2708 reg = <0x0 0x17c20000 0x0 0x1000>;
2712 ranges = <0 0 0 0x20000000>;
2715 frame-number = <0>;
2718 reg = <0x17c21000 0x1000>,
2719 <0x17c22000 0x1000>;
2725 reg = <0x17c23000 0x1000>;
2732 reg = <0x17c25000 0x1000>;
2739 reg = <0x17c27000 0x1000>;
2746 reg = <0x17c29000 0x1000>;
2753 reg = <0x17c2b000 0x1000>;
2760 reg = <0x17c2d000 0x1000>;
2768 reg = <0x0 0x18200000 0x0 0x10000>,
2769 <0x0 0x18210000 0x0 0x10000>,
2770 <0x0 0x18220000 0x0 0x10000>;
2771 reg-names = "drv-0", "drv-1", "drv-2";
2775 qcom,tcs-offset = <0xd00>;
2845 reg = <0x0 0x18321000 0x0 0x1000>;
2855 reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>;
2866 reg = <0 0x18800000 0 0x800000>;
2881 iommus = <&apps_smmu 0x20 0x1>;
2889 thermal-sensors = <&tsens0 0>;
2894 hysteresis = <0>;
2901 thermal-sensors = <&tsens1 0>;
2906 hysteresis = <0>;
2918 hysteresis = <0>;
2930 hysteresis = <0>;
2948 hysteresis = <0>;
2973 hysteresis = <0>;
2998 hysteresis = <0>;
3023 hysteresis = <0>;
3048 hysteresis = <0>;
3073 hysteresis = <0>;
3098 hysteresis = <0>;
3123 hysteresis = <0>;
3148 hysteresis = <0>;
3173 hysteresis = <0>;
3192 hysteresis = <0>;
3204 hysteresis = <0>;
3216 hysteresis = <0>;
3228 hysteresis = <0>;
3294 hysteresis = <0>;
3306 hysteresis = <0>;
3318 hysteresis = <0>;
3330 hysteresis = <0>;
3342 hysteresis = <0>;
3354 hysteresis = <0>;
3366 hysteresis = <0>;
3379 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;