Lines Matching +full:ufs +full:- +full:ddr
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,dispcc-sm6125.h>
7 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
8 #include <dt-bindings/clock/qcom,gcc-sm6125.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/dma/qcom-gpi.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
16 interrupt-parent = <&intc>;
17 #address-cells = <2>;
18 #size-cells = <2>;
23 xo_board: xo-board {
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <19200000>;
29 sleep_clk: sleep-clk {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <32764>;
33 clock-output-names = "sleep_clk";
38 #address-cells = <2>;
39 #size-cells = <0>;
45 enable-method = "psci";
46 capacity-dmips-mhz = <1024>;
47 next-level-cache = <&l2_0>;
48 l2_0: l2-cache {
50 cache-level = <2>;
51 cache-unified;
59 enable-method = "psci";
60 capacity-dmips-mhz = <1024>;
61 next-level-cache = <&l2_0>;
68 enable-method = "psci";
69 capacity-dmips-mhz = <1024>;
70 next-level-cache = <&l2_0>;
77 enable-method = "psci";
78 capacity-dmips-mhz = <1024>;
79 next-level-cache = <&l2_0>;
86 enable-method = "psci";
87 capacity-dmips-mhz = <1638>;
88 next-level-cache = <&l2_1>;
89 l2_1: l2-cache {
91 cache-level = <2>;
92 cache-unified;
100 enable-method = "psci";
101 capacity-dmips-mhz = <1638>;
102 next-level-cache = <&l2_1>;
109 enable-method = "psci";
110 capacity-dmips-mhz = <1638>;
111 next-level-cache = <&l2_1>;
118 enable-method = "psci";
119 capacity-dmips-mhz = <1638>;
120 next-level-cache = <&l2_1>;
123 cpu-map {
164 compatible = "qcom,scm-sm6125", "qcom,scm";
165 #reset-cells = <1>;
176 compatible = "arm,armv8-pmuv3";
181 compatible = "arm,psci-1.0";
186 compatible = "qcom,sm6125-rpm-proc", "qcom,rpm-proc";
188 glink-edge {
189 compatible = "qcom,glink-rpm";
192 qcom,rpm-msg-ram = <&rpm_msg_ram>;
195 rpm_requests: rpm-requests {
196 compatible = "qcom,rpm-sm6125", "qcom,glink-smd-rpm";
197 qcom,glink-channels = "rpm_requests";
199 rpmcc: clock-controller {
200 compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc";
201 #clock-cells = <1>;
203 clock-names = "xo";
206 rpmpd: power-controller {
207 compatible = "qcom,sm6125-rpmpd";
208 #power-domain-cells = <1>;
209 operating-points-v2 = <&rpmpd_opp_table>;
211 rpmpd_opp_table: opp-table {
212 compatible = "operating-points-v2";
215 opp-level = <RPM_SMD_LEVEL_RETENTION>;
219 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
223 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
227 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
231 opp-level = <RPM_SMD_LEVEL_SVS>;
235 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
239 opp-level = <RPM_SMD_LEVEL_NOM>;
243 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
247 opp-level = <RPM_SMD_LEVEL_TURBO>;
251 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
259 reserved_memory: reserved-memory {
260 #address-cells = <2>;
261 #size-cells = <2>;
266 no-map;
271 no-map;
276 no-map;
281 no-map;
286 no-map;
291 no-map;
296 no-map;
301 no-map;
306 no-map;
311 no-map;
316 no-map;
321 no-map;
326 no-map;
331 no-map;
336 no-map;
341 no-map;
346 no-map;
351 no-map;
356 no-map;
361 no-map;
366 no-map;
372 memory-region = <&smem_mem>;
377 #address-cells = <1>;
378 #size-cells = <1>;
380 compatible = "simple-bus";
383 compatible = "qcom,tcsr-mutex";
385 #hwlock-cells = <1>;
389 compatible = "qcom,sm6125-tlmm";
393 reg-names = "west", "south", "east";
395 gpio-controller;
396 gpio-ranges = <&tlmm 0 0 134>;
397 #gpio-cells = <2>;
398 interrupt-controller;
399 #interrupt-cells = <2>;
401 sdc2_off_state: sdc2-off-state {
402 clk-pins {
404 drive-strength = <2>;
405 bias-disable;
408 cmd-pins {
410 drive-strength = <2>;
411 bias-pull-up;
414 data-pins {
416 drive-strength = <2>;
417 bias-pull-up;
421 sdc2_on_state: sdc2-on-state {
422 clk-pins {
424 drive-strength = <16>;
425 bias-disable;
428 cmd-pins {
430 drive-strength = <10>;
431 bias-pull-up;
434 data-pins {
436 drive-strength = <10>;
437 bias-pull-up;
441 qup_i2c0_default: qup-i2c0-default-state {
444 drive-strength = <2>;
445 bias-disable;
448 qup_i2c0_sleep: qup-i2c0-sleep-state {
451 drive-strength = <2>;
452 bias-pull-up;
455 qup_i2c1_default: qup-i2c1-default-state {
458 drive-strength = <2>;
459 bias-disable;
462 qup_i2c1_sleep: qup-i2c1-sleep-state {
465 drive-strength = <2>;
466 bias-pull-up;
469 qup_i2c2_default: qup-i2c2-default-state {
472 drive-strength = <2>;
473 bias-disable;
476 qup_i2c2_sleep: qup-i2c2-sleep-state {
479 drive-strength = <2>;
480 bias-pull-up;
483 qup_i2c3_default: qup-i2c3-default-state {
486 drive-strength = <2>;
487 bias-disable;
490 qup_i2c3_sleep: qup-i2c3-sleep-state {
493 drive-strength = <2>;
494 bias-pull-up;
497 qup_i2c4_default: qup-i2c4-default-state {
500 drive-strength = <2>;
501 bias-disable;
504 qup_i2c4_sleep: qup-i2c4-sleep-state {
507 drive-strength = <2>;
508 bias-pull-up;
511 qup_i2c5_default: qup-i2c5-default-state {
514 drive-strength = <2>;
515 bias-disable;
518 qup_i2c5_sleep: qup-i2c5-sleep-state {
521 drive-strength = <2>;
522 bias-pull-up;
525 qup_i2c6_default: qup-i2c6-default-state {
528 drive-strength = <2>;
529 bias-disable;
532 qup_i2c6_sleep: qup-i2c6-sleep-state {
535 drive-strength = <2>;
536 bias-pull-up;
539 qup_i2c7_default: qup-i2c7-default-state {
542 drive-strength = <2>;
543 bias-disable;
546 qup_i2c7_sleep: qup-i2c7-sleep-state {
549 drive-strength = <2>;
550 bias-pull-up;
553 qup_i2c8_default: qup-i2c8-default-state {
556 drive-strength = <2>;
557 bias-disable;
560 qup_i2c8_sleep: qup-i2c8-sleep-state {
563 drive-strength = <2>;
564 bias-pull-up;
567 qup_i2c9_default: qup-i2c9-default-state {
570 drive-strength = <2>;
571 bias-disable;
574 qup_i2c9_sleep: qup-i2c9-sleep-state {
577 drive-strength = <2>;
578 bias-pull-up;
581 qup_spi0_default: qup-spi0-default-state {
584 drive-strength = <6>;
585 bias-disable;
588 qup_spi0_sleep: qup-spi0-sleep-state {
591 drive-strength = <6>;
592 bias-disable;
595 qup_spi2_default: qup-spi2-default-state {
598 drive-strength = <6>;
599 bias-disable;
602 qup_spi2_sleep: qup-spi2-sleep-state {
605 drive-strength = <6>;
606 bias-disable;
609 qup_spi5_default: qup-spi5-default-state {
612 drive-strength = <6>;
613 bias-disable;
616 qup_spi5_sleep: qup-spi5-sleep-state {
619 drive-strength = <6>;
620 bias-disable;
623 qup_spi6_default: qup-spi6-default-state {
626 drive-strength = <6>;
627 bias-disable;
630 qup_spi6_sleep: qup-spi6-sleep-state {
633 drive-strength = <6>;
634 bias-disable;
637 qup_spi8_default: qup-spi8-default-state {
640 drive-strength = <6>;
641 bias-disable;
644 qup_spi8_sleep: qup-spi8-sleep-state {
647 drive-strength = <6>;
648 bias-disable;
651 qup_spi9_default: qup-spi9-default-state {
654 drive-strength = <6>;
655 bias-disable;
658 qup_spi9_sleep: qup-spi9-sleep-state {
661 drive-strength = <6>;
662 bias-disable;
666 gcc: clock-controller@1400000 {
667 compatible = "qcom,gcc-sm6125";
669 #clock-cells = <1>;
670 #reset-cells = <1>;
671 #power-domain-cells = <1>;
672 clock-names = "bi_tcxo", "sleep_clk";
677 compatible = "qcom,msm8996-qusb2-phy";
679 #phy-cells = <0>;
683 clock-names = "cfg_ahb", "ref";
690 compatible = "qcom,spmi-pmic-arb";
696 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
697 interrupt-names = "periph_irq";
701 #address-cells = <2>;
702 #size-cells = <0>;
703 interrupt-controller;
704 #interrupt-cells = <4>;
708 compatible = "qcom,rpm-msg-ram";
713 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
715 reg-names = "hc", "cqhci";
719 interrupt-names = "hc_irq", "pwr_irq";
724 clock-names = "iface", "core", "xo";
727 power-domains = <&rpmpd SM6125_VDDCX>;
729 qcom,dll-config = <0x000f642c>;
730 qcom,ddr-config = <0x80040873>;
732 bus-width = <8>;
733 non-removable;
734 supports-cqe;
740 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
742 reg-names = "hc";
746 interrupt-names = "hc_irq", "pwr_irq";
751 clock-names = "iface", "core", "xo";
754 pinctrl-0 = <&sdc2_on_state>;
755 pinctrl-1 = <&sdc2_off_state>;
756 pinctrl-names = "default", "sleep";
758 power-domains = <&rpmpd SM6125_VDDCX>;
760 qcom,dll-config = <0x0007642c>;
761 qcom,ddr-config = <0x80040873>;
763 bus-width = <4>;
768 compatible = "qcom,sm6125-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
770 reg-names = "std", "ice";
781 clock-names = "core_clk",
789 freq-table-hz = <50000000 240000000>,
799 reset-names = "rst";
800 #reset-cells = <1>;
803 phy-names = "ufsphy";
805 lanes-per-direction = <1>;
813 compatible = "qcom,sm6125-qmp-ufs-phy";
819 clock-names = "ref",
824 reset-names = "ufsphy";
826 power-domains = <&gcc UFS_PHY_GDSC>;
828 #phy-cells = <0>;
833 gpi_dma0: dma-controller@4a00000 {
834 compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma";
844 dma-channels = <8>;
845 dma-channel-mask = <0x1f>;
847 #dma-cells = <3>;
852 compatible = "qcom,geni-se-qup";
856 clock-names = "m-ahb", "s-ahb";
858 #address-cells = <1>;
859 #size-cells = <1>;
864 compatible = "qcom,geni-i2c";
867 clock-names = "se";
869 pinctrl-0 = <&qup_i2c0_default>;
870 pinctrl-1 = <&qup_i2c0_sleep>;
871 pinctrl-names = "default", "sleep";
874 dma-names = "tx", "rx";
875 #address-cells = <1>;
876 #size-cells = <0>;
881 compatible = "qcom,geni-spi";
884 clock-names = "se";
886 pinctrl-0 = <&qup_spi0_default>;
887 pinctrl-1 = <&qup_spi0_sleep>;
888 pinctrl-names = "default", "sleep";
891 dma-names = "tx", "rx";
892 #address-cells = <1>;
893 #size-cells = <0>;
898 compatible = "qcom,geni-i2c";
901 clock-names = "se";
903 pinctrl-0 = <&qup_i2c1_default>;
904 pinctrl-1 = <&qup_i2c1_sleep>;
905 pinctrl-names = "default", "sleep";
908 dma-names = "tx", "rx";
909 #address-cells = <1>;
910 #size-cells = <0>;
915 compatible = "qcom,geni-i2c";
918 clock-names = "se";
920 pinctrl-0 = <&qup_i2c2_default>;
921 pinctrl-1 = <&qup_i2c2_sleep>;
922 pinctrl-names = "default", "sleep";
925 dma-names = "tx", "rx";
926 #address-cells = <1>;
927 #size-cells = <0>;
932 compatible = "qcom,geni-spi";
935 clock-names = "se";
937 pinctrl-0 = <&qup_spi2_default>;
938 pinctrl-1 = <&qup_spi2_sleep>;
939 pinctrl-names = "default", "sleep";
942 dma-names = "tx", "rx";
943 #address-cells = <1>;
944 #size-cells = <0>;
949 compatible = "qcom,geni-i2c";
952 clock-names = "se";
954 pinctrl-0 = <&qup_i2c3_default>;
955 pinctrl-1 = <&qup_i2c3_sleep>;
956 pinctrl-names = "default", "sleep";
959 dma-names = "tx", "rx";
960 #address-cells = <1>;
961 #size-cells = <0>;
966 compatible = "qcom,geni-i2c";
969 clock-names = "se";
971 pinctrl-0 = <&qup_i2c4_default>;
972 pinctrl-1 = <&qup_i2c4_sleep>;
973 pinctrl-names = "default", "sleep";
976 dma-names = "tx", "rx";
977 #address-cells = <1>;
978 #size-cells = <0>;
983 gpi_dma1: dma-controller@4c00000 {
984 compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma";
994 dma-channels = <8>;
995 dma-channel-mask = <0x0f>;
997 #dma-cells = <3>;
1002 compatible = "qcom,geni-se-qup";
1006 clock-names = "m-ahb", "s-ahb";
1008 #address-cells = <1>;
1009 #size-cells = <1>;
1014 compatible = "qcom,geni-i2c";
1017 clock-names = "se";
1019 pinctrl-0 = <&qup_i2c5_default>;
1020 pinctrl-1 = <&qup_i2c5_sleep>;
1021 pinctrl-names = "default", "sleep";
1024 dma-names = "tx", "rx";
1025 #address-cells = <1>;
1026 #size-cells = <0>;
1031 compatible = "qcom,geni-spi";
1034 clock-names = "se";
1036 pinctrl-0 = <&qup_spi5_default>;
1037 pinctrl-1 = <&qup_spi5_sleep>;
1038 pinctrl-names = "default", "sleep";
1041 dma-names = "tx", "rx";
1042 #address-cells = <1>;
1043 #size-cells = <0>;
1048 compatible = "qcom,geni-i2c";
1051 clock-names = "se";
1053 pinctrl-0 = <&qup_i2c6_default>;
1054 pinctrl-1 = <&qup_i2c6_sleep>;
1055 pinctrl-names = "default", "sleep";
1058 dma-names = "tx", "rx";
1059 #address-cells = <1>;
1060 #size-cells = <0>;
1065 compatible = "qcom,geni-spi";
1068 clock-names = "se";
1070 pinctrl-0 = <&qup_spi6_default>;
1071 pinctrl-1 = <&qup_spi6_sleep>;
1072 pinctrl-names = "default", "sleep";
1075 dma-names = "tx", "rx";
1076 #address-cells = <1>;
1077 #size-cells = <0>;
1082 compatible = "qcom,geni-i2c";
1085 clock-names = "se";
1087 pinctrl-0 = <&qup_i2c7_default>;
1088 pinctrl-1 = <&qup_i2c7_sleep>;
1089 pinctrl-names = "default", "sleep";
1092 dma-names = "tx", "rx";
1093 #address-cells = <1>;
1094 #size-cells = <0>;
1099 compatible = "qcom,geni-i2c";
1102 clock-names = "se";
1104 pinctrl-0 = <&qup_i2c8_default>;
1105 pinctrl-1 = <&qup_i2c8_sleep>;
1106 pinctrl-names = "default", "sleep";
1109 dma-names = "tx", "rx";
1110 #address-cells = <1>;
1111 #size-cells = <0>;
1116 compatible = "qcom,geni-spi";
1119 clock-names = "se";
1121 pinctrl-0 = <&qup_spi8_default>;
1122 pinctrl-1 = <&qup_spi8_sleep>;
1123 pinctrl-names = "default", "sleep";
1126 dma-names = "tx", "rx";
1127 #address-cells = <1>;
1128 #size-cells = <0>;
1133 compatible = "qcom,geni-i2c";
1136 clock-names = "se";
1138 pinctrl-0 = <&qup_i2c9_default>;
1139 pinctrl-1 = <&qup_i2c9_sleep>;
1140 pinctrl-names = "default", "sleep";
1143 dma-names = "tx", "rx";
1144 #address-cells = <1>;
1145 #size-cells = <0>;
1150 compatible = "qcom,geni-spi";
1153 clock-names = "se";
1155 pinctrl-0 = <&qup_spi9_default>;
1156 pinctrl-1 = <&qup_spi9_sleep>;
1157 pinctrl-names = "default", "sleep";
1160 dma-names = "tx", "rx";
1161 #address-cells = <1>;
1162 #size-cells = <0>;
1168 compatible = "qcom,sm6125-dwc3", "qcom,dwc3";
1170 #address-cells = <1>;
1171 #size-cells = <1>;
1180 clock-names = "cfg_noc",
1187 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1189 assigned-clock-rates = <19200000>, <66666667>;
1195 interrupt-names = "pwr_event",
1200 power-domains = <&gcc USB30_PRIM_GDSC>;
1201 qcom,select-utmi-as-pipe-clk;
1210 phy-names = "usb2-phy";
1213 snps,dis-u1-entry-quirk;
1214 snps,dis-u2-entry-quirk;
1215 maximum-speed = "high-speed";
1221 compatible = "qcom,rpm-stats";
1225 mdss: display-subsystem@5e00000 {
1226 compatible = "qcom,sm6125-mdss";
1228 reg-names = "mdss";
1231 interrupt-controller;
1232 #interrupt-cells = <1>;
1237 clock-names = "iface",
1241 power-domains = <&dispcc MDSS_GDSC>;
1245 #address-cells = <1>;
1246 #size-cells = <1>;
1251 mdss_mdp: display-controller@5e01000 {
1252 compatible = "qcom,sm6125-dpu";
1255 reg-names = "mdp", "vbif";
1257 interrupt-parent = <&mdss>;
1267 clock-names = "bus",
1274 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
1275 assigned-clock-rates = <19200000>;
1277 operating-points-v2 = <&mdp_opp_table>;
1278 power-domains = <&rpmpd SM6125_VDDCX>;
1281 #address-cells = <1>;
1282 #size-cells = <0>;
1287 remote-endpoint = <&mdss_dsi0_in>;
1292 mdp_opp_table: opp-table {
1293 compatible = "operating-points-v2";
1295 opp-192000000 {
1296 opp-hz = /bits/ 64 <192000000>;
1297 required-opps = <&rpmpd_opp_low_svs>;
1300 opp-256000000 {
1301 opp-hz = /bits/ 64 <256000000>;
1302 required-opps = <&rpmpd_opp_svs>;
1305 opp-307200000 {
1306 opp-hz = /bits/ 64 <307200000>;
1307 required-opps = <&rpmpd_opp_svs_plus>;
1310 opp-384000000 {
1311 opp-hz = /bits/ 64 <384000000>;
1312 required-opps = <&rpmpd_opp_nom>;
1315 opp-400000000 {
1316 opp-hz = /bits/ 64 <400000000>;
1317 required-opps = <&rpmpd_opp_turbo>;
1323 compatible = "qcom,sm6125-dsi-ctrl", "qcom,mdss-dsi-ctrl";
1325 reg-names = "dsi_ctrl";
1327 interrupt-parent = <&mdss>;
1336 clock-names = "byte",
1342 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
1344 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
1347 operating-points-v2 = <&dsi_opp_table>;
1348 power-domains = <&rpmpd SM6125_VDDCX>;
1351 phy-names = "dsi";
1353 #address-cells = <1>;
1354 #size-cells = <0>;
1359 #address-cells = <1>;
1360 #size-cells = <0>;
1365 remote-endpoint = <&dpu_intf1_out>;
1376 dsi_opp_table: opp-table {
1377 compatible = "operating-points-v2";
1379 opp-164000000 {
1380 opp-hz = /bits/ 64 <164000000>;
1381 required-opps = <&rpmpd_opp_low_svs>;
1384 opp-187500000 {
1385 opp-hz = /bits/ 64 <187500000>;
1386 required-opps = <&rpmpd_opp_svs>;
1392 compatible = "qcom,sm6125-dsi-phy-14nm";
1396 reg-names = "dsi_phy",
1400 #clock-cells = <1>;
1401 #phy-cells = <0>;
1405 clock-names = "iface",
1408 required-opps = <&rpmpd_opp_nom>;
1409 power-domains = <&rpmpd SM6125_VDDMX>;
1415 dispcc: clock-controller@5f00000 {
1416 compatible = "qcom,sm6125-dispcc";
1427 clock-names = "bi_tcxo",
1436 required-opps = <&rpmpd_opp_ret>;
1437 power-domains = <&rpmpd SM6125_VDDCX>;
1439 #clock-cells = <1>;
1440 #power-domain-cells = <1>;
1444 compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1512 #global-interrupts = <1>;
1513 #iommu-cells = <2>;
1517 compatible = "qcom,sm6125-apcs-hmss-global",
1518 "qcom,msm8994-apcs-kpss-global";
1521 #mbox-cells = <1>;
1525 compatible = "arm,armv7-timer-mem";
1526 #address-cells = <1>;
1527 #size-cells = <1>;
1530 clock-frequency = <19200000>;
1533 frame-number = <0>;
1541 frame-number = <1>;
1548 frame-number = <2>;
1555 frame-number = <3>;
1562 frame-number = <4>;
1569 frame-number = <5>;
1576 frame-number = <6>;
1583 intc: interrupt-controller@f200000 {
1584 compatible = "arm,gic-v3";
1587 #interrupt-cells = <3>;
1588 interrupt-controller;
1594 compatible = "arm,armv8-timer";
1599 clock-frequency = <19200000>;